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Linux 2.6.36-rc5
[linux-2.6/next.git] / drivers / atm / fore200e.h
blob7f97c09aaea5ec068d83c37e2ed2222af601f43a
1 #ifndef _FORE200E_H
2 #define _FORE200E_H
3
4 #ifdef __KERNEL__
5
6 /* rx buffer sizes */
7
8 #define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
9 #define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
10
11
12 #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */
13
14
15 #define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */
16
17
18 #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */
19 #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */
20
21 #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */
22 #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */
23
24 #define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)
25 #define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)
26
27 #define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)
28 #define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)
29
30
31 #define QUEUE_SIZE_CMD 16 /* command queue capacity */
32 #define QUEUE_SIZE_RX 64 /* receive queue capacity */
33 #define QUEUE_SIZE_TX 256 /* transmit queue capacity */
34 #define QUEUE_SIZE_BS 32 /* buffer supply queue capacity */
35
36 #define FORE200E_VPI_BITS 0
37 #define FORE200E_VCI_BITS 10
38 #define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */
39
40
41 #define TSD_FIXED 2
42 #define TSD_EXTENSION 0
43 #define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
44
45
46 /* the cp starts putting a received PDU into one *small* buffer,
47 then it uses a number of *large* buffers for the trailing data.
48 we compute here the total number of receive segment descriptors
49 required to hold the largest possible PDU */
50
51 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
52
53 #define RSD_FIXED 3
54
55 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
56 but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
57 so we add one extra RSD to RSD_EXTENSION
58 (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */
59
60 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
61 #define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
62
63
64 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
65 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
66
67 /* bitfields endian games */
68
69 #if defined(__LITTLE_ENDIAN_BITFIELD)
70 #define BITFIELD2(b1, b2) b1; b2;
71 #define BITFIELD3(b1, b2, b3) b1; b2; b3;
72 #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
73 #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
74 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
75 #elif defined(__BIG_ENDIAN_BITFIELD)
76 #define BITFIELD2(b1, b2) b2; b1;
77 #define BITFIELD3(b1, b2, b3) b3; b2; b1;
78 #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
79 #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
80 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
81 #else
82 #error unknown bitfield endianess
83 #endif
84
85
86 /* ATM cell header (minus HEC byte) */
87
88 typedef struct atm_header {
89 BITFIELD5(
90 u32 clp : 1, /* cell loss priority */
91 u32 plt : 3, /* payload type */
92 u32 vci : 16, /* virtual channel identifier */
93 u32 vpi : 8, /* virtual path identifier */
94 u32 gfc : 4 /* generic flow control */
95 )
96 } atm_header_t;
97
98
99 /* ATM adaptation layer id */
100
101 typedef enum fore200e_aal {
102 FORE200E_AAL0 = 0,
103 FORE200E_AAL34 = 4,
104 FORE200E_AAL5 = 5,
105 } fore200e_aal_t;
106
107
108 /* transmit PDU descriptor specification */
109
110 typedef struct tpd_spec {
111 BITFIELD4(
112 u32 length : 16, /* total PDU length */
113 u32 nseg : 8, /* number of transmit segments */
114 enum fore200e_aal aal : 4, /* adaptation layer */
115 u32 intr : 4 /* interrupt requested */
116 )
117 } tpd_spec_t;
118
119
120 /* transmit PDU rate control */
121
122 typedef struct tpd_rate
123 {
124 BITFIELD2(
125 u32 idle_cells : 16, /* number of idle cells to insert */
126 u32 data_cells : 16 /* number of data cells to transmit */
127 )
128 } tpd_rate_t;
129
130
131 /* transmit segment descriptor */
132
133 typedef struct tsd {
134 u32 buffer; /* transmit buffer DMA address */
135 u32 length; /* number of bytes in buffer */
136 } tsd_t;
137
138
139 /* transmit PDU descriptor */
140
141 typedef struct tpd {
142 struct atm_header atm_header; /* ATM header minus HEC byte */
143 struct tpd_spec spec; /* tpd specification */
144 struct tpd_rate rate; /* tpd rate control */
145 u32 pad; /* reserved */
146 struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */
147 } tpd_t;
148
149
150 /* receive segment descriptor */
151
152 typedef struct rsd {
153 u32 handle; /* host supplied receive buffer handle */
154 u32 length; /* number of bytes in buffer */
155 } rsd_t;
156
157
158 /* receive PDU descriptor */
159
160 typedef struct rpd {
161 struct atm_header atm_header; /* ATM header minus HEC byte */
162 u32 nseg; /* number of receive segments */
163 struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */
164 } rpd_t;
165
166
167 /* buffer scheme */
168
169 typedef enum buffer_scheme {
170 BUFFER_SCHEME_ONE,
171 BUFFER_SCHEME_TWO,
172 BUFFER_SCHEME_NBR /* always last */
173 } buffer_scheme_t;
174
175
176 /* buffer magnitude */
177
178 typedef enum buffer_magn {
179 BUFFER_MAGN_SMALL,
180 BUFFER_MAGN_LARGE,
181 BUFFER_MAGN_NBR /* always last */
182 } buffer_magn_t;
183
184
185 /* receive buffer descriptor */
186
187 typedef struct rbd {
188 u32 handle; /* host supplied handle */
189 u32 buffer_haddr; /* host DMA address of host buffer */
190 } rbd_t;
191
192
193 /* receive buffer descriptor block */
194
195 typedef struct rbd_block {
196 struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */
197 } rbd_block_t;
198
199
200 /* tpd DMA address */
201
202 typedef struct tpd_haddr {
203 BITFIELD3(
204 u32 size : 4, /* tpd size expressed in 32 byte blocks */
205 u32 pad : 1, /* reserved */
206 u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
207 )
208 } tpd_haddr_t;
209
210 #define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */
211
212 /* cp resident transmit queue entry */
213
214 typedef struct cp_txq_entry {
215 struct tpd_haddr tpd_haddr; /* host DMA address of tpd */
216 u32 status_haddr; /* host DMA address of completion status */
217 } cp_txq_entry_t;
218
219
220 /* cp resident receive queue entry */
221
222 typedef struct cp_rxq_entry {
223 u32 rpd_haddr; /* host DMA address of rpd */
224 u32 status_haddr; /* host DMA address of completion status */
225 } cp_rxq_entry_t;
226
227
228 /* cp resident buffer supply queue entry */
229
230 typedef struct cp_bsq_entry {
231 u32 rbd_block_haddr; /* host DMA address of rbd block */
232 u32 status_haddr; /* host DMA address of completion status */
233 } cp_bsq_entry_t;
234
235
236 /* completion status */
237
238 typedef volatile enum status {
239 STATUS_PENDING = (1<<0), /* initial status (written by host) */
240 STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */
241 STATUS_FREE = (1<<2), /* initial status (written by host) */
242 STATUS_ERROR = (1<<3) /* completion status (written by cp) */
243 } status_t;
244
245
246 /* cp operation code */
247
248 typedef enum opcode {
249 OPCODE_INITIALIZE = 1, /* initialize board */
250 OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */
251 OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */
252 OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */
253 OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */
254 OPCODE_GET_STATS, /* get board statistics */
255 OPCODE_SET_OC3, /* set OC-3 registers */
256 OPCODE_GET_OC3, /* get OC-3 registers */
257 OPCODE_RESET_STATS, /* reset board statistics */
258 OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */
259 OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the
260 firmware to be low order bits from
261 the VPI field of the ATM cell header */
262 OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */
263 } opcode_t;
264
265
266 /* virtual path / virtual channel identifers */
267
268 typedef struct vpvc {
269 BITFIELD3(
270 u32 vci : 16, /* virtual channel identifier */
271 u32 vpi : 8, /* virtual path identifier */
272 u32 pad : 8 /* reserved */
273 )
274 } vpvc_t;
275
276
277 /* activate VC command opcode */
278
279 typedef struct activate_opcode {
280 BITFIELD4(
281 enum opcode opcode : 8, /* cp opcode */
282 enum fore200e_aal aal : 8, /* adaptation layer */
283 enum buffer_scheme scheme : 8, /* buffer scheme */
284 u32 pad : 8 /* reserved */
285 )
286 } activate_opcode_t;
287
288
289 /* activate VC command block */
290
291 typedef struct activate_block {
292 struct activate_opcode opcode; /* activate VC command opcode */
293 struct vpvc vpvc; /* VPI/VCI */
294 u32 mtu; /* for AAL0 only */
295
296 } activate_block_t;
297
298
299 /* deactivate VC command opcode */
300
301 typedef struct deactivate_opcode {
302 BITFIELD2(
303 enum opcode opcode : 8, /* cp opcode */
304 u32 pad : 24 /* reserved */
305 )
306 } deactivate_opcode_t;
307
308
309 /* deactivate VC command block */
310
311 typedef struct deactivate_block {
312 struct deactivate_opcode opcode; /* deactivate VC command opcode */
313 struct vpvc vpvc; /* VPI/VCI */
314 } deactivate_block_t;
315
316
317 /* OC-3 registers */
318
319 typedef struct oc3_regs {
320 u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
321 Saturn User Network Interface documentation
322 for a description of the OC-3 chip registers */
323 } oc3_regs_t;
324
325
326 /* set/get OC-3 regs command opcode */
327
328 typedef struct oc3_opcode {
329 BITFIELD4(
330 enum opcode opcode : 8, /* cp opcode */
331 u32 reg : 8, /* register index */
332 u32 value : 8, /* register value */
333 u32 mask : 8 /* register mask that specifies which
334 bits of the register value field
335 are significant */
336 )
337 } oc3_opcode_t;
338
339
340 /* set/get OC-3 regs command block */
341
342 typedef struct oc3_block {
343 struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */
344 u32 regs_haddr; /* host DMA address of OC-3 regs buffer */
345 } oc3_block_t;
346
347
348 /* physical encoding statistics */
349
350 typedef struct stats_phy {
351 __be32 crc_header_errors; /* cells received with bad header CRC */
352 __be32 framing_errors; /* cells received with bad framing */
353 __be32 pad[ 2 ]; /* i960 padding */
354 } stats_phy_t;
355
356
357 /* OC-3 statistics */
358
359 typedef struct stats_oc3 {
360 __be32 section_bip8_errors; /* section 8 bit interleaved parity */
361 __be32 path_bip8_errors; /* path 8 bit interleaved parity */
362 __be32 line_bip24_errors; /* line 24 bit interleaved parity */
363 __be32 line_febe_errors; /* line far end block errors */
364 __be32 path_febe_errors; /* path far end block errors */
365 __be32 corr_hcs_errors; /* correctable header check sequence */
366 __be32 ucorr_hcs_errors; /* uncorrectable header check sequence */
367 __be32 pad[ 1 ]; /* i960 padding */
368 } stats_oc3_t;
369
370
371 /* ATM statistics */
372
373 typedef struct stats_atm {
374 __be32 cells_transmitted; /* cells transmitted */
375 __be32 cells_received; /* cells received */
376 __be32 vpi_bad_range; /* cell drops: VPI out of range */
377 __be32 vpi_no_conn; /* cell drops: no connection for VPI */
378 __be32 vci_bad_range; /* cell drops: VCI out of range */
379 __be32 vci_no_conn; /* cell drops: no connection for VCI */
380 __be32 pad[ 2 ]; /* i960 padding */
381 } stats_atm_t;
382
383 /* AAL0 statistics */
384
385 typedef struct stats_aal0 {
386 __be32 cells_transmitted; /* cells transmitted */
387 __be32 cells_received; /* cells received */
388 __be32 cells_dropped; /* cells dropped */
389 __be32 pad[ 1 ]; /* i960 padding */
390 } stats_aal0_t;
391
392
393 /* AAL3/4 statistics */
394
395 typedef struct stats_aal34 {
396 __be32 cells_transmitted; /* cells transmitted from segmented PDUs */
397 __be32 cells_received; /* cells reassembled into PDUs */
398 __be32 cells_crc_errors; /* payload CRC error count */
399 __be32 cells_protocol_errors; /* SAR or CS layer protocol errors */
400 __be32 cells_dropped; /* cells dropped: partial reassembly */
401 __be32 cspdus_transmitted; /* CS PDUs transmitted */
402 __be32 cspdus_received; /* CS PDUs received */
403 __be32 cspdus_protocol_errors; /* CS layer protocol errors */
404 __be32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */
405 __be32 pad[ 3 ]; /* i960 padding */
406 } stats_aal34_t;
407
408
409 /* AAL5 statistics */
410
411 typedef struct stats_aal5 {
412 __be32 cells_transmitted; /* cells transmitted from segmented SDUs */
413 __be32 cells_received; /* cells reassembled into SDUs */
414 __be32 cells_dropped; /* reassembled PDUs dropped (in cells) */
415 __be32 congestion_experienced; /* CRC error and length wrong */
416 __be32 cspdus_transmitted; /* CS PDUs transmitted */
417 __be32 cspdus_received; /* CS PDUs received */
418 __be32 cspdus_crc_errors; /* CS PDUs CRC errors */
419 __be32 cspdus_protocol_errors; /* CS layer protocol errors */
420 __be32 cspdus_dropped; /* reassembled PDUs dropped */
421 __be32 pad[ 3 ]; /* i960 padding */
422 } stats_aal5_t;
423
424
425 /* auxiliary statistics */
426
427 typedef struct stats_aux {
428 __be32 small_b1_failed; /* receive BD allocation failures */
429 __be32 large_b1_failed; /* receive BD allocation failures */
430 __be32 small_b2_failed; /* receive BD allocation failures */
431 __be32 large_b2_failed; /* receive BD allocation failures */
432 __be32 rpd_alloc_failed; /* receive PDU allocation failures */
433 __be32 receive_carrier; /* no carrier = 0, carrier = 1 */
434 __be32 pad[ 2 ]; /* i960 padding */
435 } stats_aux_t;
436
437
438 /* whole statistics buffer */
439
440 typedef struct stats {
441 struct stats_phy phy; /* physical encoding statistics */
442 struct stats_oc3 oc3; /* OC-3 statistics */
443 struct stats_atm atm; /* ATM statistics */
444 struct stats_aal0 aal0; /* AAL0 statistics */
445 struct stats_aal34 aal34; /* AAL3/4 statistics */
446 struct stats_aal5 aal5; /* AAL5 statistics */
447 struct stats_aux aux; /* auxiliary statistics */
448 } stats_t;
449
450
451 /* get statistics command opcode */
452
453 typedef struct stats_opcode {
454 BITFIELD2(
455 enum opcode opcode : 8, /* cp opcode */
456 u32 pad : 24 /* reserved */
457 )
458 } stats_opcode_t;
459
460
461 /* get statistics command block */
462
463 typedef struct stats_block {
464 struct stats_opcode opcode; /* get statistics command opcode */
465 u32 stats_haddr; /* host DMA address of stats buffer */
466 } stats_block_t;
467
468
469 /* expansion PROM data (PCI specific) */
470
471 typedef struct prom_data {
472 u32 hw_revision; /* hardware revision */
473 u32 serial_number; /* board serial number */
474 u8 mac_addr[ 8 ]; /* board MAC address */
475 } prom_data_t;
476
477
478 /* get expansion PROM data command opcode */
479
480 typedef struct prom_opcode {
481 BITFIELD2(
482 enum opcode opcode : 8, /* cp opcode */
483 u32 pad : 24 /* reserved */
484 )
485 } prom_opcode_t;
486
487
488 /* get expansion PROM data command block */
489
490 typedef struct prom_block {
491 struct prom_opcode opcode; /* get PROM data command opcode */
492 u32 prom_haddr; /* host DMA address of PROM buffer */
493 } prom_block_t;
494
495
496 /* cp command */
497
498 typedef union cmd {
499 enum opcode opcode; /* operation code */
500 struct activate_block activate_block; /* activate VC */
501 struct deactivate_block deactivate_block; /* deactivate VC */
502 struct stats_block stats_block; /* get statistics */
503 struct prom_block prom_block; /* get expansion PROM data */
504 struct oc3_block oc3_block; /* get/set OC-3 registers */
505 u32 pad[ 4 ]; /* i960 padding */
506 } cmd_t;
507
508
509 /* cp resident command queue */
510
511 typedef struct cp_cmdq_entry {
512 union cmd cmd; /* command */
513 u32 status_haddr; /* host DMA address of completion status */
514 u32 pad[ 3 ]; /* i960 padding */
515 } cp_cmdq_entry_t;
516
517
518 /* host resident transmit queue entry */
519
520 typedef struct host_txq_entry {
521 struct cp_txq_entry __iomem *cp_entry; /* addr of cp resident tx queue entry */
522 enum status* status; /* addr of host resident status */
523 struct tpd* tpd; /* addr of transmit PDU descriptor */
524 u32 tpd_dma; /* DMA address of tpd */
525 struct sk_buff* skb; /* related skb */
526 void* data; /* copy of misaligned data */
527 unsigned long incarn; /* vc_map incarnation when submitted for tx */
528 struct fore200e_vc_map* vc_map;
529
530 } host_txq_entry_t;
531
532
533 /* host resident receive queue entry */
534
535 typedef struct host_rxq_entry {
536 struct cp_rxq_entry __iomem *cp_entry; /* addr of cp resident rx queue entry */
537 enum status* status; /* addr of host resident status */
538 struct rpd* rpd; /* addr of receive PDU descriptor */
539 u32 rpd_dma; /* DMA address of rpd */
540 } host_rxq_entry_t;
541
542
543 /* host resident buffer supply queue entry */
544
545 typedef struct host_bsq_entry {
546 struct cp_bsq_entry __iomem *cp_entry; /* addr of cp resident buffer supply queue entry */
547 enum status* status; /* addr of host resident status */
548 struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */
549 u32 rbd_block_dma; /* DMA address od rdb */
550 } host_bsq_entry_t;
551
552
553 /* host resident command queue entry */
554
555 typedef struct host_cmdq_entry {
556 struct cp_cmdq_entry __iomem *cp_entry; /* addr of cp resident cmd queue entry */
557 enum status *status; /* addr of host resident status */
558 } host_cmdq_entry_t;
559
560
561 /* chunk of memory */
562
563 typedef struct chunk {
564 void* alloc_addr; /* base address of allocated chunk */
565 void* align_addr; /* base address of aligned chunk */
566 dma_addr_t dma_addr; /* DMA address of aligned chunk */
567 int direction; /* direction of DMA mapping */
568 u32 alloc_size; /* length of allocated chunk */
569 u32 align_size; /* length of aligned chunk */
570 } chunk_t;
571
572 #define dma_size align_size /* DMA useable size */
573
574
575 /* host resident receive buffer */
576
577 typedef struct buffer {
578 struct buffer* next; /* next receive buffer */
579 enum buffer_scheme scheme; /* buffer scheme */
580 enum buffer_magn magn; /* buffer magnitude */
581 struct chunk data; /* data buffer */
582 #ifdef FORE200E_BSQ_DEBUG
583 unsigned long index; /* buffer # in queue */
584 int supplied; /* 'buffer supplied' flag */
585 #endif
586 } buffer_t;
587
588
589 #if (BITS_PER_LONG == 32)
590 #define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
591 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
592 #else /* deal with 64 bit pointers */
593 #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
594 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
595 #endif
596
597
598 /* host resident command queue */
599
600 typedef struct host_cmdq {
601 struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */
602 int head; /* head of cmd queue */
603 struct chunk status; /* array of completion status */
604 } host_cmdq_t;
605
606
607 /* host resident transmit queue */
608
609 typedef struct host_txq {
610 struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */
611 int head; /* head of tx queue */
612 int tail; /* tail of tx queue */
613 struct chunk tpd; /* array of tpds */
614 struct chunk status; /* arry of completion status */
615 int txing; /* number of pending PDUs in tx queue */
616 } host_txq_t;
617
618
619 /* host resident receive queue */
620
621 typedef struct host_rxq {
622 struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */
623 int head; /* head of rx queue */
624 struct chunk rpd; /* array of rpds */
625 struct chunk status; /* array of completion status */
626 } host_rxq_t;
627
628
629 /* host resident buffer supply queues */
630
631 typedef struct host_bsq {
632 struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */
633 int head; /* head of buffer supply queue */
634 struct chunk rbd_block; /* array of rbds */
635 struct chunk status; /* array of completion status */
636 struct buffer* buffer; /* array of rx buffers */
637 struct buffer* freebuf; /* list of free rx buffers */
638 volatile int freebuf_count; /* count of free rx buffers */
639 } host_bsq_t;
640
641
642 /* header of the firmware image */
643
644 typedef struct fw_header {
645 __le32 magic; /* magic number */
646 __le32 version; /* firmware version id */
647 __le32 load_offset; /* fw load offset in board memory */
648 __le32 start_offset; /* fw execution start address in board memory */
649 } fw_header_t;
650
651 #define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */
652
653
654 /* receive buffer supply queues scheme specification */
655
656 typedef struct bs_spec {
657 u32 queue_length; /* queue capacity */
658 u32 buffer_size; /* host buffer size */
659 u32 pool_size; /* number of rbds */
660 u32 supply_blksize; /* num of rbds in I/O block (multiple
661 of 4 between 4 and 124 inclusive) */
662 } bs_spec_t;
663
664
665 /* initialization command block (one-time command, not in cmd queue) */
666
667 typedef struct init_block {
668 enum opcode opcode; /* initialize command */
669 enum status status; /* related status word */
670 u32 receive_threshold; /* not used */
671 u32 num_connect; /* ATM connections */
672 u32 cmd_queue_len; /* length of command queue */
673 u32 tx_queue_len; /* length of transmit queue */
674 u32 rx_queue_len; /* length of receive queue */
675 u32 rsd_extension; /* number of extra 32 byte blocks */
676 u32 tsd_extension; /* number of extra 32 byte blocks */
677 u32 conless_vpvc; /* not used */
678 u32 pad[ 2 ]; /* force quad alignment */
679 struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */
680 } init_block_t;
681
682
683 typedef enum media_type {
684 MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */
685 MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */
686 MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */
687 MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */
688 MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */
689 } media_type_t;
690
691 #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
692
693
694 /* cp resident queues */
695
696 typedef struct cp_queues {
697 u32 cp_cmdq; /* command queue */
698 u32 cp_txq; /* transmit queue */
699 u32 cp_rxq; /* receive queue */
700 u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */
701 u32 imask; /* 1 enables cp to host interrupts */
702 u32 istat; /* 1 for interrupt posted */
703 u32 heap_base; /* offset form beginning of ram */
704 u32 heap_size; /* space available for queues */
705 u32 hlogger; /* non zero for host logging */
706 u32 heartbeat; /* cp heartbeat */
707 u32 fw_release; /* firmware version */
708 u32 mon960_release; /* i960 monitor version */
709 u32 tq_plen; /* transmit throughput measurements */
710 /* make sure the init block remains on a quad word boundary */
711 struct init_block init; /* one time cmd, not in cmd queue */
712 enum media_type media_type; /* media type id */
713 u32 oc3_revision; /* OC-3 revision number */
714 } cp_queues_t;
715
716
717 /* boot status */
718
719 typedef enum boot_status {
720 BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */
721 BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */
722 BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */
723 BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */
724 BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */
725 } boot_status_t;
726
727
728 /* software UART */
729
730 typedef struct soft_uart {
731 u32 send; /* write register */
732 u32 recv; /* read register */
733 } soft_uart_t;
734
735 #define FORE200E_CP_MONITOR_UART_FREE 0x00000000
736 #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
737
738
739 /* i960 monitor */
740
741 typedef struct cp_monitor {
742 struct soft_uart soft_uart; /* software UART */
743 enum boot_status bstat; /* boot status */
744 u32 app_base; /* application base offset */
745 u32 mon_version; /* i960 monitor version */
746 } cp_monitor_t;
747
748
749 /* device state */
750
751 typedef enum fore200e_state {
752 FORE200E_STATE_BLANK, /* initial state */
753 FORE200E_STATE_REGISTER, /* device registered */
754 FORE200E_STATE_CONFIGURE, /* bus interface configured */
755 FORE200E_STATE_MAP, /* board space mapped in host memory */
756 FORE200E_STATE_RESET, /* board resetted */
757 FORE200E_STATE_START_FW, /* firmware started */
758 FORE200E_STATE_INITIALIZE, /* initialize command successful */
759 FORE200E_STATE_INIT_CMDQ, /* command queue initialized */
760 FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */
761 FORE200E_STATE_INIT_RXQ, /* receive queue initialized */
762 FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */
763 FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */
764 FORE200E_STATE_IRQ, /* host interrupt requested */
765 FORE200E_STATE_COMPLETE /* initialization completed */
766 } fore200e_state;
767
768
769 /* PCA-200E registers */
770
771 typedef struct fore200e_pca_regs {
772 volatile u32 __iomem * hcr; /* address of host control register */
773 volatile u32 __iomem * imr; /* address of host interrupt mask register */
774 volatile u32 __iomem * psr; /* address of PCI specific register */
775 } fore200e_pca_regs_t;
776
777
778 /* SBA-200E registers */
779
780 typedef struct fore200e_sba_regs {
781 u32 __iomem *hcr; /* address of host control register */
782 u32 __iomem *bsr; /* address of burst transfer size register */
783 u32 __iomem *isr; /* address of interrupt level selection register */
784 } fore200e_sba_regs_t;
785
786
787 /* model-specific registers */
788
789 typedef union fore200e_regs {
790 struct fore200e_pca_regs pca; /* PCA-200E registers */
791 struct fore200e_sba_regs sba; /* SBA-200E registers */
792 } fore200e_regs;
793
794
795 struct fore200e;
796
797 /* bus-dependent data */
798
799 typedef struct fore200e_bus {
800 char* model_name; /* board model name */
801 char* proc_name; /* board name under /proc/atm */
802 int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */
803 int buffer_alignment; /* rx buffers DMA alignment requirement */
804 int status_alignment; /* status words DMA alignment requirement */
805 u32 (*read)(volatile u32 __iomem *);
806 void (*write)(u32, volatile u32 __iomem *);
807 u32 (*dma_map)(struct fore200e*, void*, int, int);
808 void (*dma_unmap)(struct fore200e*, u32, int, int);
809 void (*dma_sync_for_cpu)(struct fore200e*, u32, int, int);
810 void (*dma_sync_for_device)(struct fore200e*, u32, int, int);
811 int (*dma_chunk_alloc)(struct fore200e*, struct chunk*, int, int, int);
812 void (*dma_chunk_free)(struct fore200e*, struct chunk*);
813 int (*configure)(struct fore200e*);
814 int (*map)(struct fore200e*);
815 void (*reset)(struct fore200e*);
816 int (*prom_read)(struct fore200e*, struct prom_data*);
817 void (*unmap)(struct fore200e*);
818 void (*irq_enable)(struct fore200e*);
819 int (*irq_check)(struct fore200e*);
820 void (*irq_ack)(struct fore200e*);
821 int (*proc_read)(struct fore200e*, char*);
822 } fore200e_bus_t;
823
824 /* vc mapping */
825
826 typedef struct fore200e_vc_map {
827 struct atm_vcc* vcc; /* vcc entry */
828 unsigned long incarn; /* vcc incarnation number */
829 } fore200e_vc_map_t;
830
831 #define FORE200E_VC_MAP(fore200e, vpi, vci) \
832 (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
833
834
835 /* per-device data */
836
837 typedef struct fore200e {
838 struct list_head entry; /* next device */
839 const struct fore200e_bus* bus; /* bus-dependent code and data */
840 union fore200e_regs regs; /* bus-dependent registers */
841 struct atm_dev* atm_dev; /* ATM device */
842
843 enum fore200e_state state; /* device state */
844
845 char name[16]; /* device name */
846 void* bus_dev; /* bus-specific kernel data */
847 int irq; /* irq number */
848 unsigned long phys_base; /* physical base address */
849 void __iomem * virt_base; /* virtual base address */
850
851 unsigned char esi[ ESI_LEN ]; /* end system identifier */
852
853 struct cp_monitor __iomem * cp_monitor; /* i960 monitor address */
854 struct cp_queues __iomem * cp_queues; /* cp resident queues */
855 struct host_cmdq host_cmdq; /* host resident cmd queue */
856 struct host_txq host_txq; /* host resident tx queue */
857 struct host_rxq host_rxq; /* host resident rx queue */
858 /* host resident buffer supply queues */
859 struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
860
861 u32 available_cell_rate; /* remaining pseudo-CBR bw on link */
862
863 int loop_mode; /* S/UNI loopback mode */
864
865 struct stats* stats; /* last snapshot of the stats */
866
867 struct mutex rate_mtx; /* protects rate reservation ops */
868 spinlock_t q_lock; /* protects queue ops */
869 #ifdef FORE200E_USE_TASKLET
870 struct tasklet_struct tx_tasklet; /* performs tx interrupt work */
871 struct tasklet_struct rx_tasklet; /* performs rx interrupt work */
872 #endif
873 unsigned long tx_sat; /* tx queue saturation count */
874
875 unsigned long incarn_count;
876 struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */
877 } fore200e_t;
878
879
880 /* per-vcc data */
881
882 typedef struct fore200e_vcc {
883 enum buffer_scheme scheme; /* rx buffer scheme */
884 struct tpd_rate rate; /* tx rate control data */
885 int rx_min_pdu; /* size of smallest PDU received */
886 int rx_max_pdu; /* size of largest PDU received */
887 int tx_min_pdu; /* size of smallest PDU transmitted */
888 int tx_max_pdu; /* size of largest PDU transmitted */
889 unsigned long tx_pdu; /* nbr of tx pdus */
890 unsigned long rx_pdu; /* nbr of rx pdus */
891 } fore200e_vcc_t;
892
893
894
895 /* 200E-series common memory layout */
896
897 #define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */
898 #define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */
899
900
901 /* PCA-200E memory layout */
902
903 #define PCA200E_IOSPACE_LENGTH 0x00200000
904
905 #define PCA200E_HCR_OFFSET 0x00100000 /* board control register */
906 #define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */
907 #define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */
908
909
910 /* PCA-200E host control register */
911
912 #define PCA200E_HCR_RESET (1<<0) /* read / write */
913 #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */
914 #define PCA200E_HCR_I960FAIL (1<<2) /* read */
915 #define PCA200E_HCR_INTRB (1<<2) /* write */
916 #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */
917 #define PCA200E_HCR_INTRA (1<<3) /* write */
918 #define PCA200E_HCR_OUTFULL (1<<4) /* read */
919 #define PCA200E_HCR_CLRINTR (1<<4) /* write */
920 #define PCA200E_HCR_ESPHOLD (1<<5) /* read */
921 #define PCA200E_HCR_INFULL (1<<6) /* read */
922 #define PCA200E_HCR_TESTMODE (1<<7) /* read */
923
924
925 /* PCA-200E PCI bus interface regs (offsets in PCI config space) */
926
927 #define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */
928 #define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */
929 #define PCA200E_PCI_THRESHOLD 0x42 /* burst / continous req threshold */
930
931 /* PBI master control register */
932
933 #define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */
934 #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */
935 #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */
936 #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */
937 #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */
938 #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */
939 #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */
940
941
942
943 #define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */
944
945
946 /* size of SBA-200E registers */
947
948 #define SBA200E_HCR_LENGTH 4
949 #define SBA200E_BSR_LENGTH 4
950 #define SBA200E_ISR_LENGTH 4
951 #define SBA200E_RAM_LENGTH 0x40000
952
953
954 /* SBA-200E SBUS burst transfer size register */
955
956 #define SBA200E_BSR_BURST4 0x04
957 #define SBA200E_BSR_BURST8 0x08
958 #define SBA200E_BSR_BURST16 0x10
959
960
961 /* SBA-200E host control register */
962
963 #define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */
964 #define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */
965 #define SBA200E_HCR_I960FAIL (1<<2) /* read */
966 #define SBA200E_HCR_I960SETINTR (1<<2) /* write */
967 #define SBA200E_HCR_OUTFULL (1<<3) /* read */
968 #define SBA200E_HCR_INTR_CLR (1<<3) /* write */
969 #define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */
970 #define SBA200E_HCR_ESPHOLD (1<<5) /* read */
971 #define SBA200E_HCR_INFULL (1<<6) /* read */
972 #define SBA200E_HCR_TESTMODE (1<<7) /* read */
973 #define SBA200E_HCR_INTR_REQ (1<<8) /* read */
974
975 #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
976
977
978 #endif /* __KERNEL__ */
979 #endif /* _FORE200E_H */
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