?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'cleancache/linux-next'
[linux-2.6/next.git] / drivers / mmc / host / tmio_mmc_pio.c
blob710339a85c84676d9c72e2105f24108344248da2
1 /*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/highmem.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/irq.h>
36 #include <linux/mfd/tmio.h>
37 #include <linux/mmc/host.h>
38 #include <linux/mmc/tmio.h>
39 #include <linux/module.h>
40 #include <linux/pagemap.h>
41 #include <linux/platform_device.h>
42 #include <linux/scatterlist.h>
43 #include <linux/workqueue.h>
44 #include <linux/spinlock.h>
45
46 #include "tmio_mmc.h"
47
48 static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
49 {
50 return readw(host->ctl + (addr << host->bus_shift));
51 }
52
53 static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
54 u16 *buf, int count)
55 {
56 readsw(host->ctl + (addr << host->bus_shift), buf, count);
57 }
58
59 static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
60 {
61 return readw(host->ctl + (addr << host->bus_shift)) |
62 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
63 }
64
65 static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
66 {
67 writew(val, host->ctl + (addr << host->bus_shift));
68 }
69
70 static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
71 u16 *buf, int count)
72 {
73 writesw(host->ctl + (addr << host->bus_shift), buf, count);
74 }
75
76 static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
77 {
78 writew(val, host->ctl + (addr << host->bus_shift));
79 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
80 }
81
82 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
83 {
84 u32 mask = sd_ctrl_read32(host, CTL_IRQ_MASK) & ~(i & TMIO_MASK_IRQ);
85 sd_ctrl_write32(host, CTL_IRQ_MASK, mask);
86 }
87
88 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
89 {
90 u32 mask = sd_ctrl_read32(host, CTL_IRQ_MASK) | (i & TMIO_MASK_IRQ);
91 sd_ctrl_write32(host, CTL_IRQ_MASK, mask);
92 }
93
94 static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
95 {
96 sd_ctrl_write32(host, CTL_STATUS, ~i);
97 }
98
99 static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
100 {
101 host->sg_len = data->sg_len;
102 host->sg_ptr = data->sg;
103 host->sg_orig = data->sg;
104 host->sg_off = 0;
105 }
106
107 static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
108 {
109 host->sg_ptr = sg_next(host->sg_ptr);
110 host->sg_off = 0;
111 return --host->sg_len;
112 }
113
114 #ifdef CONFIG_MMC_DEBUG
115
116 #define STATUS_TO_TEXT(a, status, i) \
117 do { \
118 if (status & TMIO_STAT_##a) { \
119 if (i++) \
120 printk(" | "); \
121 printk(#a); \
122 } \
123 } while (0)
124
125 static void pr_debug_status(u32 status)
126 {
127 int i = 0;
128 printk(KERN_DEBUG "status: %08x = ", status);
129 STATUS_TO_TEXT(CARD_REMOVE, status, i);
130 STATUS_TO_TEXT(CARD_INSERT, status, i);
131 STATUS_TO_TEXT(SIGSTATE, status, i);
132 STATUS_TO_TEXT(WRPROTECT, status, i);
133 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
134 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
135 STATUS_TO_TEXT(SIGSTATE_A, status, i);
136 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
137 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
138 STATUS_TO_TEXT(ILL_FUNC, status, i);
139 STATUS_TO_TEXT(CMD_BUSY, status, i);
140 STATUS_TO_TEXT(CMDRESPEND, status, i);
141 STATUS_TO_TEXT(DATAEND, status, i);
142 STATUS_TO_TEXT(CRCFAIL, status, i);
143 STATUS_TO_TEXT(DATATIMEOUT, status, i);
144 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
145 STATUS_TO_TEXT(RXOVERFLOW, status, i);
146 STATUS_TO_TEXT(TXUNDERRUN, status, i);
147 STATUS_TO_TEXT(RXRDY, status, i);
148 STATUS_TO_TEXT(TXRQ, status, i);
149 STATUS_TO_TEXT(ILL_ACCESS, status, i);
150 printk("\n");
151 }
152
153 #else
154 #define pr_debug_status(s) do { } while (0)
155 #endif
156
157 static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
158 {
159 struct tmio_mmc_host *host = mmc_priv(mmc);
160
161 if (enable) {
162 host->sdio_irq_enabled = 1;
163 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
164 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
165 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
166 } else {
167 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
168 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
169 host->sdio_irq_enabled = 0;
170 }
171 }
172
173 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
174 {
175 u32 clk = 0, clock;
176
177 if (new_clock) {
178 for (clock = host->mmc->f_min, clk = 0x80000080;
179 new_clock >= (clock<<1); clk >>= 1)
180 clock <<= 1;
181 clk |= 0x100;
182 }
183
184 if (host->set_clk_div)
185 host->set_clk_div(host->pdev, (clk>>22) & 1);
186
187 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
188 }
189
190 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
191 {
192 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
193
194 /* implicit BUG_ON(!res) */
195 if (resource_size(res) > 0x100) {
196 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
197 msleep(10);
198 }
199
200 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
201 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
202 msleep(10);
203 }
204
205 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
206 {
207 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
208
209 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
210 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
211 msleep(10);
212
213 /* implicit BUG_ON(!res) */
214 if (resource_size(res) > 0x100) {
215 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
216 msleep(10);
217 }
218 }
219
220 static void tmio_mmc_reset(struct tmio_mmc_host *host)
221 {
222 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
223
224 /* FIXME - should we set stop clock reg here */
225 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
226 /* implicit BUG_ON(!res) */
227 if (resource_size(res) > 0x100)
228 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
229 msleep(10);
230 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
231 if (resource_size(res) > 0x100)
232 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
233 msleep(10);
234 }
235
236 static void tmio_mmc_reset_work(struct work_struct *work)
237 {
238 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
239 delayed_reset_work.work);
240 struct mmc_request *mrq;
241 unsigned long flags;
242
243 spin_lock_irqsave(&host->lock, flags);
244 mrq = host->mrq;
245
246 /* request already finished */
247 if (!mrq
248 || time_is_after_jiffies(host->last_req_ts +
249 msecs_to_jiffies(2000))) {
250 spin_unlock_irqrestore(&host->lock, flags);
251 return;
252 }
253
254 dev_warn(&host->pdev->dev,
255 "timeout waiting for hardware interrupt (CMD%u)\n",
256 mrq->cmd->opcode);
257
258 if (host->data)
259 host->data->error = -ETIMEDOUT;
260 else if (host->cmd)
261 host->cmd->error = -ETIMEDOUT;
262 else
263 mrq->cmd->error = -ETIMEDOUT;
264
265 host->cmd = NULL;
266 host->data = NULL;
267 host->mrq = NULL;
268 host->force_pio = false;
269
270 spin_unlock_irqrestore(&host->lock, flags);
271
272 tmio_mmc_reset(host);
273
274 mmc_request_done(host->mmc, mrq);
275 }
276
277 static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
278 {
279 struct mmc_request *mrq = host->mrq;
280
281 if (!mrq)
282 return;
283
284 host->mrq = NULL;
285 host->cmd = NULL;
286 host->data = NULL;
287 host->force_pio = false;
288
289 cancel_delayed_work(&host->delayed_reset_work);
290
291 mmc_request_done(host->mmc, mrq);
292 }
293
294 /* These are the bitmasks the tmio chip requires to implement the MMC response
295 * types. Note that R1 and R6 are the same in this scheme. */
296 #define APP_CMD 0x0040
297 #define RESP_NONE 0x0300
298 #define RESP_R1 0x0400
299 #define RESP_R1B 0x0500
300 #define RESP_R2 0x0600
301 #define RESP_R3 0x0700
302 #define DATA_PRESENT 0x0800
303 #define TRANSFER_READ 0x1000
304 #define TRANSFER_MULTI 0x2000
305 #define SECURITY_CMD 0x4000
306
307 static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
308 {
309 struct mmc_data *data = host->data;
310 int c = cmd->opcode;
311
312 /* Command 12 is handled by hardware */
313 if (cmd->opcode == 12 && !cmd->arg) {
314 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
315 return 0;
316 }
317
318 switch (mmc_resp_type(cmd)) {
319 case MMC_RSP_NONE: c |= RESP_NONE; break;
320 case MMC_RSP_R1: c |= RESP_R1; break;
321 case MMC_RSP_R1B: c |= RESP_R1B; break;
322 case MMC_RSP_R2: c |= RESP_R2; break;
323 case MMC_RSP_R3: c |= RESP_R3; break;
324 default:
325 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
326 return -EINVAL;
327 }
328
329 host->cmd = cmd;
330
331 /* FIXME - this seems to be ok commented out but the spec suggest this bit
332 * should be set when issuing app commands.
333 * if(cmd->flags & MMC_FLAG_ACMD)
334 * c |= APP_CMD;
335 */
336 if (data) {
337 c |= DATA_PRESENT;
338 if (data->blocks > 1) {
339 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
340 c |= TRANSFER_MULTI;
341 }
342 if (data->flags & MMC_DATA_READ)
343 c |= TRANSFER_READ;
344 }
345
346 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_CMD);
347
348 /* Fire off the command */
349 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
350 sd_ctrl_write16(host, CTL_SD_CMD, c);
351
352 return 0;
353 }
354
355 /*
356 * This chip always returns (at least?) as much data as you ask for.
357 * I'm unsure what happens if you ask for less than a block. This should be
358 * looked into to ensure that a funny length read doesn't hose the controller.
359 */
360 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
361 {
362 struct mmc_data *data = host->data;
363 void *sg_virt;
364 unsigned short *buf;
365 unsigned int count;
366 unsigned long flags;
367
368 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
369 pr_err("PIO IRQ in DMA mode!\n");
370 return;
371 } else if (!data) {
372 pr_debug("Spurious PIO IRQ\n");
373 return;
374 }
375
376 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
377 buf = (unsigned short *)(sg_virt + host->sg_off);
378
379 count = host->sg_ptr->length - host->sg_off;
380 if (count > data->blksz)
381 count = data->blksz;
382
383 pr_debug("count: %08x offset: %08x flags %08x\n",
384 count, host->sg_off, data->flags);
385
386 /* Transfer the data */
387 if (data->flags & MMC_DATA_READ)
388 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
389 else
390 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
391
392 host->sg_off += count;
393
394 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
395
396 if (host->sg_off == host->sg_ptr->length)
397 tmio_mmc_next_sg(host);
398
399 return;
400 }
401
402 static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
403 {
404 if (host->sg_ptr == &host->bounce_sg) {
405 unsigned long flags;
406 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
407 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
408 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
409 }
410 }
411
412 /* needs to be called with host->lock held */
413 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
414 {
415 struct mmc_data *data = host->data;
416 struct mmc_command *stop;
417
418 host->data = NULL;
419
420 if (!data) {
421 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
422 return;
423 }
424 stop = data->stop;
425
426 /* FIXME - return correct transfer count on errors */
427 if (!data->error)
428 data->bytes_xfered = data->blocks * data->blksz;
429 else
430 data->bytes_xfered = 0;
431
432 pr_debug("Completed data request\n");
433
434 /*
435 * FIXME: other drivers allow an optional stop command of any given type
436 * which we dont do, as the chip can auto generate them.
437 * Perhaps we can be smarter about when to use auto CMD12 and
438 * only issue the auto request when we know this is the desired
439 * stop command, allowing fallback to the stop command the
440 * upper layers expect. For now, we do what works.
441 */
442
443 if (data->flags & MMC_DATA_READ) {
444 if (host->chan_rx && !host->force_pio)
445 tmio_mmc_check_bounce_buffer(host);
446 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
447 host->mrq);
448 } else {
449 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
450 host->mrq);
451 }
452
453 if (stop) {
454 if (stop->opcode == 12 && !stop->arg)
455 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
456 else
457 BUG();
458 }
459
460 tmio_mmc_finish_request(host);
461 }
462
463 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
464 {
465 struct mmc_data *data;
466 spin_lock(&host->lock);
467 data = host->data;
468
469 if (!data)
470 goto out;
471
472 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
473 /*
474 * Has all data been written out yet? Testing on SuperH showed,
475 * that in most cases the first interrupt comes already with the
476 * BUSY status bit clear, but on some operations, like mount or
477 * in the beginning of a write / sync / umount, there is one
478 * DATAEND interrupt with the BUSY bit set, in this cases
479 * waiting for one more interrupt fixes the problem.
480 */
481 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
482 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
483 tasklet_schedule(&host->dma_complete);
484 }
485 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
486 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
487 tasklet_schedule(&host->dma_complete);
488 } else {
489 tmio_mmc_do_data_irq(host);
490 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
491 }
492 out:
493 spin_unlock(&host->lock);
494 }
495
496 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
497 unsigned int stat)
498 {
499 struct mmc_command *cmd = host->cmd;
500 int i, addr;
501
502 spin_lock(&host->lock);
503
504 if (!host->cmd) {
505 pr_debug("Spurious CMD irq\n");
506 goto out;
507 }
508
509 host->cmd = NULL;
510
511 /* This controller is sicker than the PXA one. Not only do we need to
512 * drop the top 8 bits of the first response word, we also need to
513 * modify the order of the response for short response command types.
514 */
515
516 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
517 cmd->resp[i] = sd_ctrl_read32(host, addr);
518
519 if (cmd->flags & MMC_RSP_136) {
520 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
521 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
522 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
523 cmd->resp[3] <<= 8;
524 } else if (cmd->flags & MMC_RSP_R3) {
525 cmd->resp[0] = cmd->resp[3];
526 }
527
528 if (stat & TMIO_STAT_CMDTIMEOUT)
529 cmd->error = -ETIMEDOUT;
530 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
531 cmd->error = -EILSEQ;
532
533 /* If there is data to handle we enable data IRQs here, and
534 * we will ultimatley finish the request in the data_end handler.
535 * If theres no data or we encountered an error, finish now.
536 */
537 if (host->data && !cmd->error) {
538 if (host->data->flags & MMC_DATA_READ) {
539 if (host->force_pio || !host->chan_rx)
540 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
541 else
542 tasklet_schedule(&host->dma_issue);
543 } else {
544 if (host->force_pio || !host->chan_tx)
545 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
546 else
547 tasklet_schedule(&host->dma_issue);
548 }
549 } else {
550 tmio_mmc_finish_request(host);
551 }
552
553 out:
554 spin_unlock(&host->lock);
555 }
556
557 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
558 {
559 struct tmio_mmc_host *host = devid;
560 struct tmio_mmc_data *pdata = host->pdata;
561 unsigned int ireg, irq_mask, status;
562 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
563
564 pr_debug("MMC IRQ begin\n");
565
566 status = sd_ctrl_read32(host, CTL_STATUS);
567 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
568 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
569
570 sdio_ireg = 0;
571 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
572 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
573 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
574 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
575
576 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
577
578 if (sdio_ireg && !host->sdio_irq_enabled) {
579 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
580 sdio_status, sdio_irq_mask, sdio_ireg);
581 tmio_mmc_enable_sdio_irq(host->mmc, 0);
582 goto out;
583 }
584
585 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
586 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
587 mmc_signal_sdio_irq(host->mmc);
588
589 if (sdio_ireg)
590 goto out;
591 }
592
593 pr_debug_status(status);
594 pr_debug_status(ireg);
595
596 if (!ireg) {
597 tmio_mmc_disable_mmc_irqs(host, status & ~irq_mask);
598
599 pr_warning("tmio_mmc: Spurious irq, disabling! "
600 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
601 pr_debug_status(status);
602
603 goto out;
604 }
605
606 while (ireg) {
607 /* Card insert / remove attempts */
608 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
609 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
610 TMIO_STAT_CARD_REMOVE);
611 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
612 }
613
614 /* CRC and other errors */
615 /* if (ireg & TMIO_STAT_ERR_IRQ)
616 * handled |= tmio_error_irq(host, irq, stat);
617 */
618
619 /* Command completion */
620 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
621 tmio_mmc_ack_mmc_irqs(host,
622 TMIO_STAT_CMDRESPEND |
623 TMIO_STAT_CMDTIMEOUT);
624 tmio_mmc_cmd_irq(host, status);
625 }
626
627 /* Data transfer */
628 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
629 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
630 tmio_mmc_pio_irq(host);
631 }
632
633 /* Data transfer completion */
634 if (ireg & TMIO_STAT_DATAEND) {
635 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
636 tmio_mmc_data_irq(host);
637 }
638
639 /* Check status - keep going until we've handled it all */
640 status = sd_ctrl_read32(host, CTL_STATUS);
641 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
642 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
643
644 pr_debug("Status at end of loop: %08x\n", status);
645 pr_debug_status(status);
646 }
647 pr_debug("MMC IRQ end\n");
648
649 out:
650 return IRQ_HANDLED;
651 }
652
653 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
654 struct mmc_data *data)
655 {
656 struct tmio_mmc_data *pdata = host->pdata;
657
658 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
659 data->blksz, data->blocks);
660
661 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
662 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
663 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
664
665 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
666 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
667 mmc_hostname(host->mmc), data->blksz);
668 return -EINVAL;
669 }
670 }
671
672 tmio_mmc_init_sg(host, data);
673 host->data = data;
674
675 /* Set transfer length / blocksize */
676 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
677 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
678
679 tmio_mmc_start_dma(host, data);
680
681 return 0;
682 }
683
684 /* Process requests from the MMC layer */
685 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
686 {
687 struct tmio_mmc_host *host = mmc_priv(mmc);
688 int ret;
689
690 if (host->mrq)
691 pr_debug("request not null\n");
692
693 host->last_req_ts = jiffies;
694 wmb();
695 host->mrq = mrq;
696
697 if (mrq->data) {
698 ret = tmio_mmc_start_data(host, mrq->data);
699 if (ret)
700 goto fail;
701 }
702
703 ret = tmio_mmc_start_command(host, mrq->cmd);
704 if (!ret) {
705 schedule_delayed_work(&host->delayed_reset_work,
706 msecs_to_jiffies(2000));
707 return;
708 }
709
710 fail:
711 host->mrq = NULL;
712 host->force_pio = false;
713 mrq->cmd->error = ret;
714 mmc_request_done(mmc, mrq);
715 }
716
717 /* Set MMC clock / power.
718 * Note: This controller uses a simple divider scheme therefore it cannot
719 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
720 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
721 * slowest setting.
722 */
723 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
724 {
725 struct tmio_mmc_host *host = mmc_priv(mmc);
726
727 if (ios->clock)
728 tmio_mmc_set_clock(host, ios->clock);
729
730 /* Power sequence - OFF -> UP -> ON */
731 if (ios->power_mode == MMC_POWER_UP) {
732 /* power up SD bus */
733 if (host->set_pwr)
734 host->set_pwr(host->pdev, 1);
735 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
736 /* power down SD bus */
737 if (ios->power_mode == MMC_POWER_OFF && host->set_pwr)
738 host->set_pwr(host->pdev, 0);
739 tmio_mmc_clk_stop(host);
740 } else {
741 /* start bus clock */
742 tmio_mmc_clk_start(host);
743 }
744
745 switch (ios->bus_width) {
746 case MMC_BUS_WIDTH_1:
747 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
748 break;
749 case MMC_BUS_WIDTH_4:
750 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
751 break;
752 }
753
754 /* Let things settle. delay taken from winCE driver */
755 udelay(140);
756 }
757
758 static int tmio_mmc_get_ro(struct mmc_host *mmc)
759 {
760 struct tmio_mmc_host *host = mmc_priv(mmc);
761 struct tmio_mmc_data *pdata = host->pdata;
762
763 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
764 !(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
765 }
766
767 static int tmio_mmc_get_cd(struct mmc_host *mmc)
768 {
769 struct tmio_mmc_host *host = mmc_priv(mmc);
770 struct tmio_mmc_data *pdata = host->pdata;
771
772 if (!pdata->get_cd)
773 return -ENOSYS;
774 else
775 return pdata->get_cd(host->pdev);
776 }
777
778 static const struct mmc_host_ops tmio_mmc_ops = {
779 .request = tmio_mmc_request,
780 .set_ios = tmio_mmc_set_ios,
781 .get_ro = tmio_mmc_get_ro,
782 .get_cd = tmio_mmc_get_cd,
783 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
784 };
785
786 int __devinit tmio_mmc_host_probe(struct tmio_mmc_host **host,
787 struct platform_device *pdev,
788 struct tmio_mmc_data *pdata)
789 {
790 struct tmio_mmc_host *_host;
791 struct mmc_host *mmc;
792 struct resource *res_ctl;
793 int ret;
794 u32 irq_mask = TMIO_MASK_CMD;
795
796 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
797 if (!res_ctl)
798 return -EINVAL;
799
800 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
801 if (!mmc)
802 return -ENOMEM;
803
804 _host = mmc_priv(mmc);
805 _host->pdata = pdata;
806 _host->mmc = mmc;
807 _host->pdev = pdev;
808 platform_set_drvdata(pdev, mmc);
809
810 _host->set_pwr = pdata->set_pwr;
811 _host->set_clk_div = pdata->set_clk_div;
812
813 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
814 _host->bus_shift = resource_size(res_ctl) >> 10;
815
816 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
817 if (!_host->ctl) {
818 ret = -ENOMEM;
819 goto host_free;
820 }
821
822 mmc->ops = &tmio_mmc_ops;
823 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
824 mmc->f_max = pdata->hclk;
825 mmc->f_min = mmc->f_max / 512;
826 mmc->max_segs = 32;
827 mmc->max_blk_size = 512;
828 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
829 mmc->max_segs;
830 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
831 mmc->max_seg_size = mmc->max_req_size;
832 if (pdata->ocr_mask)
833 mmc->ocr_avail = pdata->ocr_mask;
834 else
835 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
836
837 tmio_mmc_clk_stop(_host);
838 tmio_mmc_reset(_host);
839
840 ret = platform_get_irq(pdev, 0);
841 if (ret < 0)
842 goto unmap_ctl;
843
844 _host->irq = ret;
845
846 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
847 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
848 tmio_mmc_enable_sdio_irq(mmc, 0);
849
850 ret = request_irq(_host->irq, tmio_mmc_irq, IRQF_DISABLED |
851 IRQF_TRIGGER_FALLING, dev_name(&pdev->dev), _host);
852 if (ret)
853 goto unmap_ctl;
854
855 spin_lock_init(&_host->lock);
856
857 /* Init delayed work for request timeouts */
858 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
859
860 /* See if we also get DMA */
861 tmio_mmc_request_dma(_host, pdata);
862
863 mmc_add_host(mmc);
864
865 /* Unmask the IRQs we want to know about */
866 if (!_host->chan_rx)
867 irq_mask |= TMIO_MASK_READOP;
868 if (!_host->chan_tx)
869 irq_mask |= TMIO_MASK_WRITEOP;
870
871 tmio_mmc_enable_mmc_irqs(_host, irq_mask);
872
873 *host = _host;
874
875 return 0;
876
877 unmap_ctl:
878 iounmap(_host->ctl);
879 host_free:
880 mmc_free_host(mmc);
881
882 return ret;
883 }
884 EXPORT_SYMBOL(tmio_mmc_host_probe);
885
886 void tmio_mmc_host_remove(struct tmio_mmc_host *host)
887 {
888 mmc_remove_host(host->mmc);
889 cancel_delayed_work_sync(&host->delayed_reset_work);
890 tmio_mmc_release_dma(host);
891 free_irq(host->irq, host);
892 iounmap(host->ctl);
893 mmc_free_host(host->mmc);
894 }
895 EXPORT_SYMBOL(tmio_mmc_host_remove);
896
897 MODULE_LICENSE("GPL v2");
linux-next