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Merge remote-tracking branch 'cleancache/linux-next'
[linux-2.6/next.git] / drivers / net / forcedeth.c
blobd09e8b0add0105cd94489faac70f34ddc01d8bce
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/io.h>
68
69 #include <asm/irq.h>
70 #include <asm/system.h>
71
72 #define TX_WORK_PER_LOOP 64
73 #define RX_WORK_PER_LOOP 64
74
75 /*
76 * Hardware access:
77 */
78
79 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
80 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
81 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
82 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
83 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
84 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
85 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
86 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
87 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
88 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
89 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
90 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
91 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
92 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
93 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
94 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
95 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
96 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
97 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
98 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
99 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
100 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
101 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
102 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
103 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
104 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
105 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
106
107 enum {
108 NvRegIrqStatus = 0x000,
109 #define NVREG_IRQSTAT_MIIEVENT 0x040
110 #define NVREG_IRQSTAT_MASK 0x83ff
111 NvRegIrqMask = 0x004,
112 #define NVREG_IRQ_RX_ERROR 0x0001
113 #define NVREG_IRQ_RX 0x0002
114 #define NVREG_IRQ_RX_NOBUF 0x0004
115 #define NVREG_IRQ_TX_ERR 0x0008
116 #define NVREG_IRQ_TX_OK 0x0010
117 #define NVREG_IRQ_TIMER 0x0020
118 #define NVREG_IRQ_LINK 0x0040
119 #define NVREG_IRQ_RX_FORCED 0x0080
120 #define NVREG_IRQ_TX_FORCED 0x0100
121 #define NVREG_IRQ_RECOVER_ERROR 0x8200
122 #define NVREG_IRQMASK_THROUGHPUT 0x00df
123 #define NVREG_IRQMASK_CPU 0x0060
124 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
125 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
126 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
127
128 NvRegUnknownSetupReg6 = 0x008,
129 #define NVREG_UNKSETUP6_VAL 3
130
131 /*
132 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
133 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
134 */
135 NvRegPollingInterval = 0x00c,
136 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
137 #define NVREG_POLL_DEFAULT_CPU 13
138 NvRegMSIMap0 = 0x020,
139 NvRegMSIMap1 = 0x024,
140 NvRegMSIIrqMask = 0x030,
141 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
142 NvRegMisc1 = 0x080,
143 #define NVREG_MISC1_PAUSE_TX 0x01
144 #define NVREG_MISC1_HD 0x02
145 #define NVREG_MISC1_FORCE 0x3b0f3c
146
147 NvRegMacReset = 0x34,
148 #define NVREG_MAC_RESET_ASSERT 0x0F3
149 NvRegTransmitterControl = 0x084,
150 #define NVREG_XMITCTL_START 0x01
151 #define NVREG_XMITCTL_MGMT_ST 0x40000000
152 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
153 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
154 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
155 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
156 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
157 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
158 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
159 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
160 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
161 #define NVREG_XMITCTL_DATA_START 0x00100000
162 #define NVREG_XMITCTL_DATA_READY 0x00010000
163 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
164 NvRegTransmitterStatus = 0x088,
165 #define NVREG_XMITSTAT_BUSY 0x01
166
167 NvRegPacketFilterFlags = 0x8c,
168 #define NVREG_PFF_PAUSE_RX 0x08
169 #define NVREG_PFF_ALWAYS 0x7F0000
170 #define NVREG_PFF_PROMISC 0x80
171 #define NVREG_PFF_MYADDR 0x20
172 #define NVREG_PFF_LOOPBACK 0x10
173
174 NvRegOffloadConfig = 0x90,
175 #define NVREG_OFFLOAD_HOMEPHY 0x601
176 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
177 NvRegReceiverControl = 0x094,
178 #define NVREG_RCVCTL_START 0x01
179 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
180 NvRegReceiverStatus = 0x98,
181 #define NVREG_RCVSTAT_BUSY 0x01
182
183 NvRegSlotTime = 0x9c,
184 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
185 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
186 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
187 #define NVREG_SLOTTIME_HALF 0x0000ff00
188 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
189 #define NVREG_SLOTTIME_MASK 0x000000ff
190
191 NvRegTxDeferral = 0xA0,
192 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
193 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
194 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
197 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
198 NvRegRxDeferral = 0xA4,
199 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
200 NvRegMacAddrA = 0xA8,
201 NvRegMacAddrB = 0xAC,
202 NvRegMulticastAddrA = 0xB0,
203 #define NVREG_MCASTADDRA_FORCE 0x01
204 NvRegMulticastAddrB = 0xB4,
205 NvRegMulticastMaskA = 0xB8,
206 #define NVREG_MCASTMASKA_NONE 0xffffffff
207 NvRegMulticastMaskB = 0xBC,
208 #define NVREG_MCASTMASKB_NONE 0xffff
209
210 NvRegPhyInterface = 0xC0,
211 #define PHY_RGMII 0x10000000
212 NvRegBackOffControl = 0xC4,
213 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
214 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
215 #define NVREG_BKOFFCTRL_SELECT 24
216 #define NVREG_BKOFFCTRL_GEAR 12
217
218 NvRegTxRingPhysAddr = 0x100,
219 NvRegRxRingPhysAddr = 0x104,
220 NvRegRingSizes = 0x108,
221 #define NVREG_RINGSZ_TXSHIFT 0
222 #define NVREG_RINGSZ_RXSHIFT 16
223 NvRegTransmitPoll = 0x10c,
224 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
225 NvRegLinkSpeed = 0x110,
226 #define NVREG_LINKSPEED_FORCE 0x10000
227 #define NVREG_LINKSPEED_10 1000
228 #define NVREG_LINKSPEED_100 100
229 #define NVREG_LINKSPEED_1000 50
230 #define NVREG_LINKSPEED_MASK (0xFFF)
231 NvRegUnknownSetupReg5 = 0x130,
232 #define NVREG_UNKSETUP5_BIT31 (1<<31)
233 NvRegTxWatermark = 0x13c,
234 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
235 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
236 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
237 NvRegTxRxControl = 0x144,
238 #define NVREG_TXRXCTL_KICK 0x0001
239 #define NVREG_TXRXCTL_BIT1 0x0002
240 #define NVREG_TXRXCTL_BIT2 0x0004
241 #define NVREG_TXRXCTL_IDLE 0x0008
242 #define NVREG_TXRXCTL_RESET 0x0010
243 #define NVREG_TXRXCTL_RXCHECK 0x0400
244 #define NVREG_TXRXCTL_DESC_1 0
245 #define NVREG_TXRXCTL_DESC_2 0x002100
246 #define NVREG_TXRXCTL_DESC_3 0xc02200
247 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
248 #define NVREG_TXRXCTL_VLANINS 0x00080
249 NvRegTxRingPhysAddrHigh = 0x148,
250 NvRegRxRingPhysAddrHigh = 0x14C,
251 NvRegTxPauseFrame = 0x170,
252 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
253 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
256 NvRegTxPauseFrameLimit = 0x174,
257 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
258 NvRegMIIStatus = 0x180,
259 #define NVREG_MIISTAT_ERROR 0x0001
260 #define NVREG_MIISTAT_LINKCHANGE 0x0008
261 #define NVREG_MIISTAT_MASK_RW 0x0007
262 #define NVREG_MIISTAT_MASK_ALL 0x000f
263 NvRegMIIMask = 0x184,
264 #define NVREG_MII_LINKCHANGE 0x0008
265
266 NvRegAdapterControl = 0x188,
267 #define NVREG_ADAPTCTL_START 0x02
268 #define NVREG_ADAPTCTL_LINKUP 0x04
269 #define NVREG_ADAPTCTL_PHYVALID 0x40000
270 #define NVREG_ADAPTCTL_RUNNING 0x100000
271 #define NVREG_ADAPTCTL_PHYSHIFT 24
272 NvRegMIISpeed = 0x18c,
273 #define NVREG_MIISPEED_BIT8 (1<<8)
274 #define NVREG_MIIDELAY 5
275 NvRegMIIControl = 0x190,
276 #define NVREG_MIICTL_INUSE 0x08000
277 #define NVREG_MIICTL_WRITE 0x00400
278 #define NVREG_MIICTL_ADDRSHIFT 5
279 NvRegMIIData = 0x194,
280 NvRegTxUnicast = 0x1a0,
281 NvRegTxMulticast = 0x1a4,
282 NvRegTxBroadcast = 0x1a8,
283 NvRegWakeUpFlags = 0x200,
284 #define NVREG_WAKEUPFLAGS_VAL 0x7770
285 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
286 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
287 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
288 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
289 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
290 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
291 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
292 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
293 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
294 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
295
296 NvRegMgmtUnitGetVersion = 0x204,
297 #define NVREG_MGMTUNITGETVERSION 0x01
298 NvRegMgmtUnitVersion = 0x208,
299 #define NVREG_MGMTUNITVERSION 0x08
300 NvRegPowerCap = 0x268,
301 #define NVREG_POWERCAP_D3SUPP (1<<30)
302 #define NVREG_POWERCAP_D2SUPP (1<<26)
303 #define NVREG_POWERCAP_D1SUPP (1<<25)
304 NvRegPowerState = 0x26c,
305 #define NVREG_POWERSTATE_POWEREDUP 0x8000
306 #define NVREG_POWERSTATE_VALID 0x0100
307 #define NVREG_POWERSTATE_MASK 0x0003
308 #define NVREG_POWERSTATE_D0 0x0000
309 #define NVREG_POWERSTATE_D1 0x0001
310 #define NVREG_POWERSTATE_D2 0x0002
311 #define NVREG_POWERSTATE_D3 0x0003
312 NvRegMgmtUnitControl = 0x278,
313 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
314 NvRegTxCnt = 0x280,
315 NvRegTxZeroReXmt = 0x284,
316 NvRegTxOneReXmt = 0x288,
317 NvRegTxManyReXmt = 0x28c,
318 NvRegTxLateCol = 0x290,
319 NvRegTxUnderflow = 0x294,
320 NvRegTxLossCarrier = 0x298,
321 NvRegTxExcessDef = 0x29c,
322 NvRegTxRetryErr = 0x2a0,
323 NvRegRxFrameErr = 0x2a4,
324 NvRegRxExtraByte = 0x2a8,
325 NvRegRxLateCol = 0x2ac,
326 NvRegRxRunt = 0x2b0,
327 NvRegRxFrameTooLong = 0x2b4,
328 NvRegRxOverflow = 0x2b8,
329 NvRegRxFCSErr = 0x2bc,
330 NvRegRxFrameAlignErr = 0x2c0,
331 NvRegRxLenErr = 0x2c4,
332 NvRegRxUnicast = 0x2c8,
333 NvRegRxMulticast = 0x2cc,
334 NvRegRxBroadcast = 0x2d0,
335 NvRegTxDef = 0x2d4,
336 NvRegTxFrame = 0x2d8,
337 NvRegRxCnt = 0x2dc,
338 NvRegTxPause = 0x2e0,
339 NvRegRxPause = 0x2e4,
340 NvRegRxDropFrame = 0x2e8,
341 NvRegVlanControl = 0x300,
342 #define NVREG_VLANCONTROL_ENABLE 0x2000
343 NvRegMSIXMap0 = 0x3e0,
344 NvRegMSIXMap1 = 0x3e4,
345 NvRegMSIXIrqStatus = 0x3f0,
346
347 NvRegPowerState2 = 0x600,
348 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
349 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
350 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
351 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
352 };
353
354 /* Big endian: should work, but is untested */
355 struct ring_desc {
356 __le32 buf;
357 __le32 flaglen;
358 };
359
360 struct ring_desc_ex {
361 __le32 bufhigh;
362 __le32 buflow;
363 __le32 txvlan;
364 __le32 flaglen;
365 };
366
367 union ring_type {
368 struct ring_desc *orig;
369 struct ring_desc_ex *ex;
370 };
371
372 #define FLAG_MASK_V1 0xffff0000
373 #define FLAG_MASK_V2 0xffffc000
374 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
375 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
376
377 #define NV_TX_LASTPACKET (1<<16)
378 #define NV_TX_RETRYERROR (1<<19)
379 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
380 #define NV_TX_FORCED_INTERRUPT (1<<24)
381 #define NV_TX_DEFERRED (1<<26)
382 #define NV_TX_CARRIERLOST (1<<27)
383 #define NV_TX_LATECOLLISION (1<<28)
384 #define NV_TX_UNDERFLOW (1<<29)
385 #define NV_TX_ERROR (1<<30)
386 #define NV_TX_VALID (1<<31)
387
388 #define NV_TX2_LASTPACKET (1<<29)
389 #define NV_TX2_RETRYERROR (1<<18)
390 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
391 #define NV_TX2_FORCED_INTERRUPT (1<<30)
392 #define NV_TX2_DEFERRED (1<<25)
393 #define NV_TX2_CARRIERLOST (1<<26)
394 #define NV_TX2_LATECOLLISION (1<<27)
395 #define NV_TX2_UNDERFLOW (1<<28)
396 /* error and valid are the same for both */
397 #define NV_TX2_ERROR (1<<30)
398 #define NV_TX2_VALID (1<<31)
399 #define NV_TX2_TSO (1<<28)
400 #define NV_TX2_TSO_SHIFT 14
401 #define NV_TX2_TSO_MAX_SHIFT 14
402 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
403 #define NV_TX2_CHECKSUM_L3 (1<<27)
404 #define NV_TX2_CHECKSUM_L4 (1<<26)
405
406 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
407
408 #define NV_RX_DESCRIPTORVALID (1<<16)
409 #define NV_RX_MISSEDFRAME (1<<17)
410 #define NV_RX_SUBSTRACT1 (1<<18)
411 #define NV_RX_ERROR1 (1<<23)
412 #define NV_RX_ERROR2 (1<<24)
413 #define NV_RX_ERROR3 (1<<25)
414 #define NV_RX_ERROR4 (1<<26)
415 #define NV_RX_CRCERR (1<<27)
416 #define NV_RX_OVERFLOW (1<<28)
417 #define NV_RX_FRAMINGERR (1<<29)
418 #define NV_RX_ERROR (1<<30)
419 #define NV_RX_AVAIL (1<<31)
420 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
421
422 #define NV_RX2_CHECKSUMMASK (0x1C000000)
423 #define NV_RX2_CHECKSUM_IP (0x10000000)
424 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
425 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
426 #define NV_RX2_DESCRIPTORVALID (1<<29)
427 #define NV_RX2_SUBSTRACT1 (1<<25)
428 #define NV_RX2_ERROR1 (1<<18)
429 #define NV_RX2_ERROR2 (1<<19)
430 #define NV_RX2_ERROR3 (1<<20)
431 #define NV_RX2_ERROR4 (1<<21)
432 #define NV_RX2_CRCERR (1<<22)
433 #define NV_RX2_OVERFLOW (1<<23)
434 #define NV_RX2_FRAMINGERR (1<<24)
435 /* error and avail are the same for both */
436 #define NV_RX2_ERROR (1<<30)
437 #define NV_RX2_AVAIL (1<<31)
438 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
439
440 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
441 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
442
443 /* Miscellaneous hardware related defines: */
444 #define NV_PCI_REGSZ_VER1 0x270
445 #define NV_PCI_REGSZ_VER2 0x2d4
446 #define NV_PCI_REGSZ_VER3 0x604
447 #define NV_PCI_REGSZ_MAX 0x604
448
449 /* various timeout delays: all in usec */
450 #define NV_TXRX_RESET_DELAY 4
451 #define NV_TXSTOP_DELAY1 10
452 #define NV_TXSTOP_DELAY1MAX 500000
453 #define NV_TXSTOP_DELAY2 100
454 #define NV_RXSTOP_DELAY1 10
455 #define NV_RXSTOP_DELAY1MAX 500000
456 #define NV_RXSTOP_DELAY2 100
457 #define NV_SETUP5_DELAY 5
458 #define NV_SETUP5_DELAYMAX 50000
459 #define NV_POWERUP_DELAY 5
460 #define NV_POWERUP_DELAYMAX 5000
461 #define NV_MIIBUSY_DELAY 50
462 #define NV_MIIPHY_DELAY 10
463 #define NV_MIIPHY_DELAYMAX 10000
464 #define NV_MAC_RESET_DELAY 64
465
466 #define NV_WAKEUPPATTERNS 5
467 #define NV_WAKEUPMASKENTRIES 4
468
469 /* General driver defaults */
470 #define NV_WATCHDOG_TIMEO (5*HZ)
471
472 #define RX_RING_DEFAULT 512
473 #define TX_RING_DEFAULT 256
474 #define RX_RING_MIN 128
475 #define TX_RING_MIN 64
476 #define RING_MAX_DESC_VER_1 1024
477 #define RING_MAX_DESC_VER_2_3 16384
478
479 /* rx/tx mac addr + type + vlan + align + slack*/
480 #define NV_RX_HEADERS (64)
481 /* even more slack. */
482 #define NV_RX_ALLOC_PAD (64)
483
484 /* maximum mtu size */
485 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
486 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
487
488 #define OOM_REFILL (1+HZ/20)
489 #define POLL_WAIT (1+HZ/100)
490 #define LINK_TIMEOUT (3*HZ)
491 #define STATS_INTERVAL (10*HZ)
492
493 /*
494 * desc_ver values:
495 * The nic supports three different descriptor types:
496 * - DESC_VER_1: Original
497 * - DESC_VER_2: support for jumbo frames.
498 * - DESC_VER_3: 64-bit format.
499 */
500 #define DESC_VER_1 1
501 #define DESC_VER_2 2
502 #define DESC_VER_3 3
503
504 /* PHY defines */
505 #define PHY_OUI_MARVELL 0x5043
506 #define PHY_OUI_CICADA 0x03f1
507 #define PHY_OUI_VITESSE 0x01c1
508 #define PHY_OUI_REALTEK 0x0732
509 #define PHY_OUI_REALTEK2 0x0020
510 #define PHYID1_OUI_MASK 0x03ff
511 #define PHYID1_OUI_SHFT 6
512 #define PHYID2_OUI_MASK 0xfc00
513 #define PHYID2_OUI_SHFT 10
514 #define PHYID2_MODEL_MASK 0x03f0
515 #define PHY_MODEL_REALTEK_8211 0x0110
516 #define PHY_REV_MASK 0x0001
517 #define PHY_REV_REALTEK_8211B 0x0000
518 #define PHY_REV_REALTEK_8211C 0x0001
519 #define PHY_MODEL_REALTEK_8201 0x0200
520 #define PHY_MODEL_MARVELL_E3016 0x0220
521 #define PHY_MARVELL_E3016_INITMASK 0x0300
522 #define PHY_CICADA_INIT1 0x0f000
523 #define PHY_CICADA_INIT2 0x0e00
524 #define PHY_CICADA_INIT3 0x01000
525 #define PHY_CICADA_INIT4 0x0200
526 #define PHY_CICADA_INIT5 0x0004
527 #define PHY_CICADA_INIT6 0x02000
528 #define PHY_VITESSE_INIT_REG1 0x1f
529 #define PHY_VITESSE_INIT_REG2 0x10
530 #define PHY_VITESSE_INIT_REG3 0x11
531 #define PHY_VITESSE_INIT_REG4 0x12
532 #define PHY_VITESSE_INIT_MSK1 0xc
533 #define PHY_VITESSE_INIT_MSK2 0x0180
534 #define PHY_VITESSE_INIT1 0x52b5
535 #define PHY_VITESSE_INIT2 0xaf8a
536 #define PHY_VITESSE_INIT3 0x8
537 #define PHY_VITESSE_INIT4 0x8f8a
538 #define PHY_VITESSE_INIT5 0xaf86
539 #define PHY_VITESSE_INIT6 0x8f86
540 #define PHY_VITESSE_INIT7 0xaf82
541 #define PHY_VITESSE_INIT8 0x0100
542 #define PHY_VITESSE_INIT9 0x8f82
543 #define PHY_VITESSE_INIT10 0x0
544 #define PHY_REALTEK_INIT_REG1 0x1f
545 #define PHY_REALTEK_INIT_REG2 0x19
546 #define PHY_REALTEK_INIT_REG3 0x13
547 #define PHY_REALTEK_INIT_REG4 0x14
548 #define PHY_REALTEK_INIT_REG5 0x18
549 #define PHY_REALTEK_INIT_REG6 0x11
550 #define PHY_REALTEK_INIT_REG7 0x01
551 #define PHY_REALTEK_INIT1 0x0000
552 #define PHY_REALTEK_INIT2 0x8e00
553 #define PHY_REALTEK_INIT3 0x0001
554 #define PHY_REALTEK_INIT4 0xad17
555 #define PHY_REALTEK_INIT5 0xfb54
556 #define PHY_REALTEK_INIT6 0xf5c7
557 #define PHY_REALTEK_INIT7 0x1000
558 #define PHY_REALTEK_INIT8 0x0003
559 #define PHY_REALTEK_INIT9 0x0008
560 #define PHY_REALTEK_INIT10 0x0005
561 #define PHY_REALTEK_INIT11 0x0200
562 #define PHY_REALTEK_INIT_MSK1 0x0003
563
564 #define PHY_GIGABIT 0x0100
565
566 #define PHY_TIMEOUT 0x1
567 #define PHY_ERROR 0x2
568
569 #define PHY_100 0x1
570 #define PHY_1000 0x2
571 #define PHY_HALF 0x100
572
573 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
574 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
575 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
576 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
577 #define NV_PAUSEFRAME_RX_REQ 0x0010
578 #define NV_PAUSEFRAME_TX_REQ 0x0020
579 #define NV_PAUSEFRAME_AUTONEG 0x0040
580
581 /* MSI/MSI-X defines */
582 #define NV_MSI_X_MAX_VECTORS 8
583 #define NV_MSI_X_VECTORS_MASK 0x000f
584 #define NV_MSI_CAPABLE 0x0010
585 #define NV_MSI_X_CAPABLE 0x0020
586 #define NV_MSI_ENABLED 0x0040
587 #define NV_MSI_X_ENABLED 0x0080
588
589 #define NV_MSI_X_VECTOR_ALL 0x0
590 #define NV_MSI_X_VECTOR_RX 0x0
591 #define NV_MSI_X_VECTOR_TX 0x1
592 #define NV_MSI_X_VECTOR_OTHER 0x2
593
594 #define NV_MSI_PRIV_OFFSET 0x68
595 #define NV_MSI_PRIV_VALUE 0xffffffff
596
597 #define NV_RESTART_TX 0x1
598 #define NV_RESTART_RX 0x2
599
600 #define NV_TX_LIMIT_COUNT 16
601
602 #define NV_DYNAMIC_THRESHOLD 4
603 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
604
605 /* statistics */
606 struct nv_ethtool_str {
607 char name[ETH_GSTRING_LEN];
608 };
609
610 static const struct nv_ethtool_str nv_estats_str[] = {
611 { "tx_bytes" },
612 { "tx_zero_rexmt" },
613 { "tx_one_rexmt" },
614 { "tx_many_rexmt" },
615 { "tx_late_collision" },
616 { "tx_fifo_errors" },
617 { "tx_carrier_errors" },
618 { "tx_excess_deferral" },
619 { "tx_retry_error" },
620 { "rx_frame_error" },
621 { "rx_extra_byte" },
622 { "rx_late_collision" },
623 { "rx_runt" },
624 { "rx_frame_too_long" },
625 { "rx_over_errors" },
626 { "rx_crc_errors" },
627 { "rx_frame_align_error" },
628 { "rx_length_error" },
629 { "rx_unicast" },
630 { "rx_multicast" },
631 { "rx_broadcast" },
632 { "rx_packets" },
633 { "rx_errors_total" },
634 { "tx_errors_total" },
635
636 /* version 2 stats */
637 { "tx_deferral" },
638 { "tx_packets" },
639 { "rx_bytes" },
640 { "tx_pause" },
641 { "rx_pause" },
642 { "rx_drop_frame" },
643
644 /* version 3 stats */
645 { "tx_unicast" },
646 { "tx_multicast" },
647 { "tx_broadcast" }
648 };
649
650 struct nv_ethtool_stats {
651 u64 tx_bytes;
652 u64 tx_zero_rexmt;
653 u64 tx_one_rexmt;
654 u64 tx_many_rexmt;
655 u64 tx_late_collision;
656 u64 tx_fifo_errors;
657 u64 tx_carrier_errors;
658 u64 tx_excess_deferral;
659 u64 tx_retry_error;
660 u64 rx_frame_error;
661 u64 rx_extra_byte;
662 u64 rx_late_collision;
663 u64 rx_runt;
664 u64 rx_frame_too_long;
665 u64 rx_over_errors;
666 u64 rx_crc_errors;
667 u64 rx_frame_align_error;
668 u64 rx_length_error;
669 u64 rx_unicast;
670 u64 rx_multicast;
671 u64 rx_broadcast;
672 u64 rx_packets;
673 u64 rx_errors_total;
674 u64 tx_errors_total;
675
676 /* version 2 stats */
677 u64 tx_deferral;
678 u64 tx_packets;
679 u64 rx_bytes;
680 u64 tx_pause;
681 u64 rx_pause;
682 u64 rx_drop_frame;
683
684 /* version 3 stats */
685 u64 tx_unicast;
686 u64 tx_multicast;
687 u64 tx_broadcast;
688 };
689
690 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
691 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
692 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
693
694 /* diagnostics */
695 #define NV_TEST_COUNT_BASE 3
696 #define NV_TEST_COUNT_EXTENDED 4
697
698 static const struct nv_ethtool_str nv_etests_str[] = {
699 { "link (online/offline)" },
700 { "register (offline) " },
701 { "interrupt (offline) " },
702 { "loopback (offline) " }
703 };
704
705 struct register_test {
706 __u32 reg;
707 __u32 mask;
708 };
709
710 static const struct register_test nv_registers_test[] = {
711 { NvRegUnknownSetupReg6, 0x01 },
712 { NvRegMisc1, 0x03c },
713 { NvRegOffloadConfig, 0x03ff },
714 { NvRegMulticastAddrA, 0xffffffff },
715 { NvRegTxWatermark, 0x0ff },
716 { NvRegWakeUpFlags, 0x07777 },
717 { 0, 0 }
718 };
719
720 struct nv_skb_map {
721 struct sk_buff *skb;
722 dma_addr_t dma;
723 unsigned int dma_len:31;
724 unsigned int dma_single:1;
725 struct ring_desc_ex *first_tx_desc;
726 struct nv_skb_map *next_tx_ctx;
727 };
728
729 /*
730 * SMP locking:
731 * All hardware access under netdev_priv(dev)->lock, except the performance
732 * critical parts:
733 * - rx is (pseudo-) lockless: it relies on the single-threading provided
734 * by the arch code for interrupts.
735 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
736 * needs netdev_priv(dev)->lock :-(
737 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
738 */
739
740 /* in dev: base, irq */
741 struct fe_priv {
742 spinlock_t lock;
743
744 struct net_device *dev;
745 struct napi_struct napi;
746
747 /* General data:
748 * Locking: spin_lock(&np->lock); */
749 struct nv_ethtool_stats estats;
750 int in_shutdown;
751 u32 linkspeed;
752 int duplex;
753 int autoneg;
754 int fixed_mode;
755 int phyaddr;
756 int wolenabled;
757 unsigned int phy_oui;
758 unsigned int phy_model;
759 unsigned int phy_rev;
760 u16 gigabit;
761 int intr_test;
762 int recover_error;
763 int quiet_count;
764
765 /* General data: RO fields */
766 dma_addr_t ring_addr;
767 struct pci_dev *pci_dev;
768 u32 orig_mac[2];
769 u32 events;
770 u32 irqmask;
771 u32 desc_ver;
772 u32 txrxctl_bits;
773 u32 vlanctl_bits;
774 u32 driver_data;
775 u32 device_id;
776 u32 register_size;
777 u32 mac_in_use;
778 int mgmt_version;
779 int mgmt_sema;
780
781 void __iomem *base;
782
783 /* rx specific fields.
784 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
785 */
786 union ring_type get_rx, put_rx, first_rx, last_rx;
787 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
788 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
789 struct nv_skb_map *rx_skb;
790
791 union ring_type rx_ring;
792 unsigned int rx_buf_sz;
793 unsigned int pkt_limit;
794 struct timer_list oom_kick;
795 struct timer_list nic_poll;
796 struct timer_list stats_poll;
797 u32 nic_poll_irq;
798 int rx_ring_size;
799
800 /* media detection workaround.
801 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
802 */
803 int need_linktimer;
804 unsigned long link_timeout;
805 /*
806 * tx specific fields.
807 */
808 union ring_type get_tx, put_tx, first_tx, last_tx;
809 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
810 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
811 struct nv_skb_map *tx_skb;
812
813 union ring_type tx_ring;
814 u32 tx_flags;
815 int tx_ring_size;
816 int tx_limit;
817 u32 tx_pkts_in_progress;
818 struct nv_skb_map *tx_change_owner;
819 struct nv_skb_map *tx_end_flip;
820 int tx_stop;
821
822 /* vlan fields */
823 struct vlan_group *vlangrp;
824
825 /* msi/msi-x fields */
826 u32 msi_flags;
827 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
828
829 /* flow control */
830 u32 pause_flags;
831
832 /* power saved state */
833 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
834
835 /* for different msi-x irq type */
836 char name_rx[IFNAMSIZ + 3]; /* -rx */
837 char name_tx[IFNAMSIZ + 3]; /* -tx */
838 char name_other[IFNAMSIZ + 6]; /* -other */
839 };
840
841 /*
842 * Maximum number of loops until we assume that a bit in the irq mask
843 * is stuck. Overridable with module param.
844 */
845 static int max_interrupt_work = 4;
846
847 /*
848 * Optimization can be either throuput mode or cpu mode
849 *
850 * Throughput Mode: Every tx and rx packet will generate an interrupt.
851 * CPU Mode: Interrupts are controlled by a timer.
852 */
853 enum {
854 NV_OPTIMIZATION_MODE_THROUGHPUT,
855 NV_OPTIMIZATION_MODE_CPU,
856 NV_OPTIMIZATION_MODE_DYNAMIC
857 };
858 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
859
860 /*
861 * Poll interval for timer irq
862 *
863 * This interval determines how frequent an interrupt is generated.
864 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
865 * Min = 0, and Max = 65535
866 */
867 static int poll_interval = -1;
868
869 /*
870 * MSI interrupts
871 */
872 enum {
873 NV_MSI_INT_DISABLED,
874 NV_MSI_INT_ENABLED
875 };
876 static int msi = NV_MSI_INT_ENABLED;
877
878 /*
879 * MSIX interrupts
880 */
881 enum {
882 NV_MSIX_INT_DISABLED,
883 NV_MSIX_INT_ENABLED
884 };
885 static int msix = NV_MSIX_INT_ENABLED;
886
887 /*
888 * DMA 64bit
889 */
890 enum {
891 NV_DMA_64BIT_DISABLED,
892 NV_DMA_64BIT_ENABLED
893 };
894 static int dma_64bit = NV_DMA_64BIT_ENABLED;
895
896 /*
897 * Crossover Detection
898 * Realtek 8201 phy + some OEM boards do not work properly.
899 */
900 enum {
901 NV_CROSSOVER_DETECTION_DISABLED,
902 NV_CROSSOVER_DETECTION_ENABLED
903 };
904 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
905
906 /*
907 * Power down phy when interface is down (persists through reboot;
908 * older Linux and other OSes may not power it up again)
909 */
910 static int phy_power_down;
911
912 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
913 {
914 return netdev_priv(dev);
915 }
916
917 static inline u8 __iomem *get_hwbase(struct net_device *dev)
918 {
919 return ((struct fe_priv *)netdev_priv(dev))->base;
920 }
921
922 static inline void pci_push(u8 __iomem *base)
923 {
924 /* force out pending posted writes */
925 readl(base);
926 }
927
928 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
929 {
930 return le32_to_cpu(prd->flaglen)
931 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
932 }
933
934 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
935 {
936 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
937 }
938
939 static bool nv_optimized(struct fe_priv *np)
940 {
941 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
942 return false;
943 return true;
944 }
945
946 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
947 int delay, int delaymax)
948 {
949 u8 __iomem *base = get_hwbase(dev);
950
951 pci_push(base);
952 do {
953 udelay(delay);
954 delaymax -= delay;
955 if (delaymax < 0)
956 return 1;
957 } while ((readl(base + offset) & mask) != target);
958 return 0;
959 }
960
961 #define NV_SETUP_RX_RING 0x01
962 #define NV_SETUP_TX_RING 0x02
963
964 static inline u32 dma_low(dma_addr_t addr)
965 {
966 return addr;
967 }
968
969 static inline u32 dma_high(dma_addr_t addr)
970 {
971 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
972 }
973
974 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
975 {
976 struct fe_priv *np = get_nvpriv(dev);
977 u8 __iomem *base = get_hwbase(dev);
978
979 if (!nv_optimized(np)) {
980 if (rxtx_flags & NV_SETUP_RX_RING)
981 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
982 if (rxtx_flags & NV_SETUP_TX_RING)
983 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
984 } else {
985 if (rxtx_flags & NV_SETUP_RX_RING) {
986 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
987 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
988 }
989 if (rxtx_flags & NV_SETUP_TX_RING) {
990 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
991 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
992 }
993 }
994 }
995
996 static void free_rings(struct net_device *dev)
997 {
998 struct fe_priv *np = get_nvpriv(dev);
999
1000 if (!nv_optimized(np)) {
1001 if (np->rx_ring.orig)
1002 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1003 np->rx_ring.orig, np->ring_addr);
1004 } else {
1005 if (np->rx_ring.ex)
1006 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1007 np->rx_ring.ex, np->ring_addr);
1008 }
1009 kfree(np->rx_skb);
1010 kfree(np->tx_skb);
1011 }
1012
1013 static int using_multi_irqs(struct net_device *dev)
1014 {
1015 struct fe_priv *np = get_nvpriv(dev);
1016
1017 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1018 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1019 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1020 return 0;
1021 else
1022 return 1;
1023 }
1024
1025 static void nv_txrx_gate(struct net_device *dev, bool gate)
1026 {
1027 struct fe_priv *np = get_nvpriv(dev);
1028 u8 __iomem *base = get_hwbase(dev);
1029 u32 powerstate;
1030
1031 if (!np->mac_in_use &&
1032 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1033 powerstate = readl(base + NvRegPowerState2);
1034 if (gate)
1035 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1036 else
1037 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1038 writel(powerstate, base + NvRegPowerState2);
1039 }
1040 }
1041
1042 static void nv_enable_irq(struct net_device *dev)
1043 {
1044 struct fe_priv *np = get_nvpriv(dev);
1045
1046 if (!using_multi_irqs(dev)) {
1047 if (np->msi_flags & NV_MSI_X_ENABLED)
1048 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1049 else
1050 enable_irq(np->pci_dev->irq);
1051 } else {
1052 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1053 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1054 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1055 }
1056 }
1057
1058 static void nv_disable_irq(struct net_device *dev)
1059 {
1060 struct fe_priv *np = get_nvpriv(dev);
1061
1062 if (!using_multi_irqs(dev)) {
1063 if (np->msi_flags & NV_MSI_X_ENABLED)
1064 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1065 else
1066 disable_irq(np->pci_dev->irq);
1067 } else {
1068 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1069 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1070 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1071 }
1072 }
1073
1074 /* In MSIX mode, a write to irqmask behaves as XOR */
1075 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1076 {
1077 u8 __iomem *base = get_hwbase(dev);
1078
1079 writel(mask, base + NvRegIrqMask);
1080 }
1081
1082 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1083 {
1084 struct fe_priv *np = get_nvpriv(dev);
1085 u8 __iomem *base = get_hwbase(dev);
1086
1087 if (np->msi_flags & NV_MSI_X_ENABLED) {
1088 writel(mask, base + NvRegIrqMask);
1089 } else {
1090 if (np->msi_flags & NV_MSI_ENABLED)
1091 writel(0, base + NvRegMSIIrqMask);
1092 writel(0, base + NvRegIrqMask);
1093 }
1094 }
1095
1096 static void nv_napi_enable(struct net_device *dev)
1097 {
1098 struct fe_priv *np = get_nvpriv(dev);
1099
1100 napi_enable(&np->napi);
1101 }
1102
1103 static void nv_napi_disable(struct net_device *dev)
1104 {
1105 struct fe_priv *np = get_nvpriv(dev);
1106
1107 napi_disable(&np->napi);
1108 }
1109
1110 #define MII_READ (-1)
1111 /* mii_rw: read/write a register on the PHY.
1112 *
1113 * Caller must guarantee serialization
1114 */
1115 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1116 {
1117 u8 __iomem *base = get_hwbase(dev);
1118 u32 reg;
1119 int retval;
1120
1121 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1122
1123 reg = readl(base + NvRegMIIControl);
1124 if (reg & NVREG_MIICTL_INUSE) {
1125 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1126 udelay(NV_MIIBUSY_DELAY);
1127 }
1128
1129 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1130 if (value != MII_READ) {
1131 writel(value, base + NvRegMIIData);
1132 reg |= NVREG_MIICTL_WRITE;
1133 }
1134 writel(reg, base + NvRegMIIControl);
1135
1136 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1137 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1138 retval = -1;
1139 } else if (value != MII_READ) {
1140 /* it was a write operation - fewer failures are detectable */
1141 retval = 0;
1142 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1143 retval = -1;
1144 } else {
1145 retval = readl(base + NvRegMIIData);
1146 }
1147
1148 return retval;
1149 }
1150
1151 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1152 {
1153 struct fe_priv *np = netdev_priv(dev);
1154 u32 miicontrol;
1155 unsigned int tries = 0;
1156
1157 miicontrol = BMCR_RESET | bmcr_setup;
1158 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1159 return -1;
1160
1161 /* wait for 500ms */
1162 msleep(500);
1163
1164 /* must wait till reset is deasserted */
1165 while (miicontrol & BMCR_RESET) {
1166 usleep_range(10000, 20000);
1167 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1168 /* FIXME: 100 tries seem excessive */
1169 if (tries++ > 100)
1170 return -1;
1171 }
1172 return 0;
1173 }
1174
1175 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1176 {
1177 static const struct {
1178 int reg;
1179 int init;
1180 } ri[] = {
1181 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1182 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1183 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1184 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1185 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1186 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1187 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1188 };
1189 int i;
1190
1191 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1192 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1193 return PHY_ERROR;
1194 }
1195
1196 return 0;
1197 }
1198
1199 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1200 {
1201 u32 reg;
1202 u8 __iomem *base = get_hwbase(dev);
1203 u32 powerstate = readl(base + NvRegPowerState2);
1204
1205 /* need to perform hw phy reset */
1206 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1207 writel(powerstate, base + NvRegPowerState2);
1208 msleep(25);
1209
1210 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1211 writel(powerstate, base + NvRegPowerState2);
1212 msleep(25);
1213
1214 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1215 reg |= PHY_REALTEK_INIT9;
1216 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1217 return PHY_ERROR;
1218 if (mii_rw(dev, np->phyaddr,
1219 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1220 return PHY_ERROR;
1221 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1222 if (!(reg & PHY_REALTEK_INIT11)) {
1223 reg |= PHY_REALTEK_INIT11;
1224 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1225 return PHY_ERROR;
1226 }
1227 if (mii_rw(dev, np->phyaddr,
1228 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1229 return PHY_ERROR;
1230
1231 return 0;
1232 }
1233
1234 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1235 {
1236 u32 phy_reserved;
1237
1238 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1239 phy_reserved = mii_rw(dev, np->phyaddr,
1240 PHY_REALTEK_INIT_REG6, MII_READ);
1241 phy_reserved |= PHY_REALTEK_INIT7;
1242 if (mii_rw(dev, np->phyaddr,
1243 PHY_REALTEK_INIT_REG6, phy_reserved))
1244 return PHY_ERROR;
1245 }
1246
1247 return 0;
1248 }
1249
1250 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1251 {
1252 u32 phy_reserved;
1253
1254 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1255 if (mii_rw(dev, np->phyaddr,
1256 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1257 return PHY_ERROR;
1258 phy_reserved = mii_rw(dev, np->phyaddr,
1259 PHY_REALTEK_INIT_REG2, MII_READ);
1260 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1261 phy_reserved |= PHY_REALTEK_INIT3;
1262 if (mii_rw(dev, np->phyaddr,
1263 PHY_REALTEK_INIT_REG2, phy_reserved))
1264 return PHY_ERROR;
1265 if (mii_rw(dev, np->phyaddr,
1266 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1267 return PHY_ERROR;
1268 }
1269
1270 return 0;
1271 }
1272
1273 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1274 u32 phyinterface)
1275 {
1276 u32 phy_reserved;
1277
1278 if (phyinterface & PHY_RGMII) {
1279 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1280 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1281 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1282 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1283 return PHY_ERROR;
1284 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1285 phy_reserved |= PHY_CICADA_INIT5;
1286 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1287 return PHY_ERROR;
1288 }
1289 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1290 phy_reserved |= PHY_CICADA_INIT6;
1291 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1292 return PHY_ERROR;
1293
1294 return 0;
1295 }
1296
1297 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1298 {
1299 u32 phy_reserved;
1300
1301 if (mii_rw(dev, np->phyaddr,
1302 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1303 return PHY_ERROR;
1304 if (mii_rw(dev, np->phyaddr,
1305 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1306 return PHY_ERROR;
1307 phy_reserved = mii_rw(dev, np->phyaddr,
1308 PHY_VITESSE_INIT_REG4, MII_READ);
1309 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1310 return PHY_ERROR;
1311 phy_reserved = mii_rw(dev, np->phyaddr,
1312 PHY_VITESSE_INIT_REG3, MII_READ);
1313 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1314 phy_reserved |= PHY_VITESSE_INIT3;
1315 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1316 return PHY_ERROR;
1317 if (mii_rw(dev, np->phyaddr,
1318 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1319 return PHY_ERROR;
1320 if (mii_rw(dev, np->phyaddr,
1321 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1322 return PHY_ERROR;
1323 phy_reserved = mii_rw(dev, np->phyaddr,
1324 PHY_VITESSE_INIT_REG4, MII_READ);
1325 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1326 phy_reserved |= PHY_VITESSE_INIT3;
1327 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1328 return PHY_ERROR;
1329 phy_reserved = mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG3, MII_READ);
1331 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1332 return PHY_ERROR;
1333 if (mii_rw(dev, np->phyaddr,
1334 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1335 return PHY_ERROR;
1336 if (mii_rw(dev, np->phyaddr,
1337 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1338 return PHY_ERROR;
1339 phy_reserved = mii_rw(dev, np->phyaddr,
1340 PHY_VITESSE_INIT_REG4, MII_READ);
1341 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1342 return PHY_ERROR;
1343 phy_reserved = mii_rw(dev, np->phyaddr,
1344 PHY_VITESSE_INIT_REG3, MII_READ);
1345 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1346 phy_reserved |= PHY_VITESSE_INIT8;
1347 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1348 return PHY_ERROR;
1349 if (mii_rw(dev, np->phyaddr,
1350 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1351 return PHY_ERROR;
1352 if (mii_rw(dev, np->phyaddr,
1353 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1354 return PHY_ERROR;
1355
1356 return 0;
1357 }
1358
1359 static int phy_init(struct net_device *dev)
1360 {
1361 struct fe_priv *np = get_nvpriv(dev);
1362 u8 __iomem *base = get_hwbase(dev);
1363 u32 phyinterface;
1364 u32 mii_status, mii_control, mii_control_1000, reg;
1365
1366 /* phy errata for E3016 phy */
1367 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1368 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1369 reg &= ~PHY_MARVELL_E3016_INITMASK;
1370 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1371 netdev_info(dev, "%s: phy write to errata reg failed\n",
1372 pci_name(np->pci_dev));
1373 return PHY_ERROR;
1374 }
1375 }
1376 if (np->phy_oui == PHY_OUI_REALTEK) {
1377 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1378 np->phy_rev == PHY_REV_REALTEK_8211B) {
1379 if (init_realtek_8211b(dev, np)) {
1380 netdev_info(dev, "%s: phy init failed\n",
1381 pci_name(np->pci_dev));
1382 return PHY_ERROR;
1383 }
1384 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1385 np->phy_rev == PHY_REV_REALTEK_8211C) {
1386 if (init_realtek_8211c(dev, np)) {
1387 netdev_info(dev, "%s: phy init failed\n",
1388 pci_name(np->pci_dev));
1389 return PHY_ERROR;
1390 }
1391 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1392 if (init_realtek_8201(dev, np)) {
1393 netdev_info(dev, "%s: phy init failed\n",
1394 pci_name(np->pci_dev));
1395 return PHY_ERROR;
1396 }
1397 }
1398 }
1399
1400 /* set advertise register */
1401 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1402 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1403 ADVERTISE_100HALF | ADVERTISE_100FULL |
1404 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1405 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1406 netdev_info(dev, "%s: phy write to advertise failed\n",
1407 pci_name(np->pci_dev));
1408 return PHY_ERROR;
1409 }
1410
1411 /* get phy interface type */
1412 phyinterface = readl(base + NvRegPhyInterface);
1413
1414 /* see if gigabit phy */
1415 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1416 if (mii_status & PHY_GIGABIT) {
1417 np->gigabit = PHY_GIGABIT;
1418 mii_control_1000 = mii_rw(dev, np->phyaddr,
1419 MII_CTRL1000, MII_READ);
1420 mii_control_1000 &= ~ADVERTISE_1000HALF;
1421 if (phyinterface & PHY_RGMII)
1422 mii_control_1000 |= ADVERTISE_1000FULL;
1423 else
1424 mii_control_1000 &= ~ADVERTISE_1000FULL;
1425
1426 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1427 netdev_info(dev, "%s: phy init failed\n",
1428 pci_name(np->pci_dev));
1429 return PHY_ERROR;
1430 }
1431 } else
1432 np->gigabit = 0;
1433
1434 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1435 mii_control |= BMCR_ANENABLE;
1436
1437 if (np->phy_oui == PHY_OUI_REALTEK &&
1438 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1439 np->phy_rev == PHY_REV_REALTEK_8211C) {
1440 /* start autoneg since we already performed hw reset above */
1441 mii_control |= BMCR_ANRESTART;
1442 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1443 netdev_info(dev, "%s: phy init failed\n",
1444 pci_name(np->pci_dev));
1445 return PHY_ERROR;
1446 }
1447 } else {
1448 /* reset the phy
1449 * (certain phys need bmcr to be setup with reset)
1450 */
1451 if (phy_reset(dev, mii_control)) {
1452 netdev_info(dev, "%s: phy reset failed\n",
1453 pci_name(np->pci_dev));
1454 return PHY_ERROR;
1455 }
1456 }
1457
1458 /* phy vendor specific configuration */
1459 if ((np->phy_oui == PHY_OUI_CICADA)) {
1460 if (init_cicada(dev, np, phyinterface)) {
1461 netdev_info(dev, "%s: phy init failed\n",
1462 pci_name(np->pci_dev));
1463 return PHY_ERROR;
1464 }
1465 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1466 if (init_vitesse(dev, np)) {
1467 netdev_info(dev, "%s: phy init failed\n",
1468 pci_name(np->pci_dev));
1469 return PHY_ERROR;
1470 }
1471 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1472 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1473 np->phy_rev == PHY_REV_REALTEK_8211B) {
1474 /* reset could have cleared these out, set them back */
1475 if (init_realtek_8211b(dev, np)) {
1476 netdev_info(dev, "%s: phy init failed\n",
1477 pci_name(np->pci_dev));
1478 return PHY_ERROR;
1479 }
1480 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1481 if (init_realtek_8201(dev, np) ||
1482 init_realtek_8201_cross(dev, np)) {
1483 netdev_info(dev, "%s: phy init failed\n",
1484 pci_name(np->pci_dev));
1485 return PHY_ERROR;
1486 }
1487 }
1488 }
1489
1490 /* some phys clear out pause advertisement on reset, set it back */
1491 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1492
1493 /* restart auto negotiation, power down phy */
1494 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1495 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1496 if (phy_power_down)
1497 mii_control |= BMCR_PDOWN;
1498 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1499 return PHY_ERROR;
1500
1501 return 0;
1502 }
1503
1504 static void nv_start_rx(struct net_device *dev)
1505 {
1506 struct fe_priv *np = netdev_priv(dev);
1507 u8 __iomem *base = get_hwbase(dev);
1508 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1509
1510 /* Already running? Stop it. */
1511 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1512 rx_ctrl &= ~NVREG_RCVCTL_START;
1513 writel(rx_ctrl, base + NvRegReceiverControl);
1514 pci_push(base);
1515 }
1516 writel(np->linkspeed, base + NvRegLinkSpeed);
1517 pci_push(base);
1518 rx_ctrl |= NVREG_RCVCTL_START;
1519 if (np->mac_in_use)
1520 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1521 writel(rx_ctrl, base + NvRegReceiverControl);
1522 pci_push(base);
1523 }
1524
1525 static void nv_stop_rx(struct net_device *dev)
1526 {
1527 struct fe_priv *np = netdev_priv(dev);
1528 u8 __iomem *base = get_hwbase(dev);
1529 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1530
1531 if (!np->mac_in_use)
1532 rx_ctrl &= ~NVREG_RCVCTL_START;
1533 else
1534 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1535 writel(rx_ctrl, base + NvRegReceiverControl);
1536 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1537 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1538 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1539 __func__);
1540
1541 udelay(NV_RXSTOP_DELAY2);
1542 if (!np->mac_in_use)
1543 writel(0, base + NvRegLinkSpeed);
1544 }
1545
1546 static void nv_start_tx(struct net_device *dev)
1547 {
1548 struct fe_priv *np = netdev_priv(dev);
1549 u8 __iomem *base = get_hwbase(dev);
1550 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1551
1552 tx_ctrl |= NVREG_XMITCTL_START;
1553 if (np->mac_in_use)
1554 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1555 writel(tx_ctrl, base + NvRegTransmitterControl);
1556 pci_push(base);
1557 }
1558
1559 static void nv_stop_tx(struct net_device *dev)
1560 {
1561 struct fe_priv *np = netdev_priv(dev);
1562 u8 __iomem *base = get_hwbase(dev);
1563 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564
1565 if (!np->mac_in_use)
1566 tx_ctrl &= ~NVREG_XMITCTL_START;
1567 else
1568 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1569 writel(tx_ctrl, base + NvRegTransmitterControl);
1570 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1571 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1572 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1573 __func__);
1574
1575 udelay(NV_TXSTOP_DELAY2);
1576 if (!np->mac_in_use)
1577 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1578 base + NvRegTransmitPoll);
1579 }
1580
1581 static void nv_start_rxtx(struct net_device *dev)
1582 {
1583 nv_start_rx(dev);
1584 nv_start_tx(dev);
1585 }
1586
1587 static void nv_stop_rxtx(struct net_device *dev)
1588 {
1589 nv_stop_rx(dev);
1590 nv_stop_tx(dev);
1591 }
1592
1593 static void nv_txrx_reset(struct net_device *dev)
1594 {
1595 struct fe_priv *np = netdev_priv(dev);
1596 u8 __iomem *base = get_hwbase(dev);
1597
1598 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1599 pci_push(base);
1600 udelay(NV_TXRX_RESET_DELAY);
1601 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1602 pci_push(base);
1603 }
1604
1605 static void nv_mac_reset(struct net_device *dev)
1606 {
1607 struct fe_priv *np = netdev_priv(dev);
1608 u8 __iomem *base = get_hwbase(dev);
1609 u32 temp1, temp2, temp3;
1610
1611 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1612 pci_push(base);
1613
1614 /* save registers since they will be cleared on reset */
1615 temp1 = readl(base + NvRegMacAddrA);
1616 temp2 = readl(base + NvRegMacAddrB);
1617 temp3 = readl(base + NvRegTransmitPoll);
1618
1619 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1620 pci_push(base);
1621 udelay(NV_MAC_RESET_DELAY);
1622 writel(0, base + NvRegMacReset);
1623 pci_push(base);
1624 udelay(NV_MAC_RESET_DELAY);
1625
1626 /* restore saved registers */
1627 writel(temp1, base + NvRegMacAddrA);
1628 writel(temp2, base + NvRegMacAddrB);
1629 writel(temp3, base + NvRegTransmitPoll);
1630
1631 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1632 pci_push(base);
1633 }
1634
1635 static void nv_get_hw_stats(struct net_device *dev)
1636 {
1637 struct fe_priv *np = netdev_priv(dev);
1638 u8 __iomem *base = get_hwbase(dev);
1639
1640 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1641 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1642 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1643 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1644 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1645 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1646 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1647 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1648 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1649 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1650 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1651 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1652 np->estats.rx_runt += readl(base + NvRegRxRunt);
1653 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1654 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1655 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1656 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1657 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1658 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1659 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1660 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1661 np->estats.rx_packets =
1662 np->estats.rx_unicast +
1663 np->estats.rx_multicast +
1664 np->estats.rx_broadcast;
1665 np->estats.rx_errors_total =
1666 np->estats.rx_crc_errors +
1667 np->estats.rx_over_errors +
1668 np->estats.rx_frame_error +
1669 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1670 np->estats.rx_late_collision +
1671 np->estats.rx_runt +
1672 np->estats.rx_frame_too_long;
1673 np->estats.tx_errors_total =
1674 np->estats.tx_late_collision +
1675 np->estats.tx_fifo_errors +
1676 np->estats.tx_carrier_errors +
1677 np->estats.tx_excess_deferral +
1678 np->estats.tx_retry_error;
1679
1680 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1681 np->estats.tx_deferral += readl(base + NvRegTxDef);
1682 np->estats.tx_packets += readl(base + NvRegTxFrame);
1683 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1684 np->estats.tx_pause += readl(base + NvRegTxPause);
1685 np->estats.rx_pause += readl(base + NvRegRxPause);
1686 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1687 }
1688
1689 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1690 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1691 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1692 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1693 }
1694 }
1695
1696 /*
1697 * nv_get_stats: dev->get_stats function
1698 * Get latest stats value from the nic.
1699 * Called with read_lock(&dev_base_lock) held for read -
1700 * only synchronized against unregister_netdevice.
1701 */
1702 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1703 {
1704 struct fe_priv *np = netdev_priv(dev);
1705
1706 /* If the nic supports hw counters then retrieve latest values */
1707 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1708 nv_get_hw_stats(dev);
1709
1710 /* copy to net_device stats */
1711 dev->stats.tx_bytes = np->estats.tx_bytes;
1712 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1713 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1714 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1715 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1716 dev->stats.rx_errors = np->estats.rx_errors_total;
1717 dev->stats.tx_errors = np->estats.tx_errors_total;
1718 }
1719
1720 return &dev->stats;
1721 }
1722
1723 /*
1724 * nv_alloc_rx: fill rx ring entries.
1725 * Return 1 if the allocations for the skbs failed and the
1726 * rx engine is without Available descriptors
1727 */
1728 static int nv_alloc_rx(struct net_device *dev)
1729 {
1730 struct fe_priv *np = netdev_priv(dev);
1731 struct ring_desc *less_rx;
1732
1733 less_rx = np->get_rx.orig;
1734 if (less_rx-- == np->first_rx.orig)
1735 less_rx = np->last_rx.orig;
1736
1737 while (np->put_rx.orig != less_rx) {
1738 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1739 if (skb) {
1740 np->put_rx_ctx->skb = skb;
1741 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1742 skb->data,
1743 skb_tailroom(skb),
1744 PCI_DMA_FROMDEVICE);
1745 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1746 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1747 wmb();
1748 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1749 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1750 np->put_rx.orig = np->first_rx.orig;
1751 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1752 np->put_rx_ctx = np->first_rx_ctx;
1753 } else
1754 return 1;
1755 }
1756 return 0;
1757 }
1758
1759 static int nv_alloc_rx_optimized(struct net_device *dev)
1760 {
1761 struct fe_priv *np = netdev_priv(dev);
1762 struct ring_desc_ex *less_rx;
1763
1764 less_rx = np->get_rx.ex;
1765 if (less_rx-- == np->first_rx.ex)
1766 less_rx = np->last_rx.ex;
1767
1768 while (np->put_rx.ex != less_rx) {
1769 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1770 if (skb) {
1771 np->put_rx_ctx->skb = skb;
1772 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1773 skb->data,
1774 skb_tailroom(skb),
1775 PCI_DMA_FROMDEVICE);
1776 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1777 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1778 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1779 wmb();
1780 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1781 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1782 np->put_rx.ex = np->first_rx.ex;
1783 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1784 np->put_rx_ctx = np->first_rx_ctx;
1785 } else
1786 return 1;
1787 }
1788 return 0;
1789 }
1790
1791 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1792 static void nv_do_rx_refill(unsigned long data)
1793 {
1794 struct net_device *dev = (struct net_device *) data;
1795 struct fe_priv *np = netdev_priv(dev);
1796
1797 /* Just reschedule NAPI rx processing */
1798 napi_schedule(&np->napi);
1799 }
1800
1801 static void nv_init_rx(struct net_device *dev)
1802 {
1803 struct fe_priv *np = netdev_priv(dev);
1804 int i;
1805
1806 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1807
1808 if (!nv_optimized(np))
1809 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1810 else
1811 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1812 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1813 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1814
1815 for (i = 0; i < np->rx_ring_size; i++) {
1816 if (!nv_optimized(np)) {
1817 np->rx_ring.orig[i].flaglen = 0;
1818 np->rx_ring.orig[i].buf = 0;
1819 } else {
1820 np->rx_ring.ex[i].flaglen = 0;
1821 np->rx_ring.ex[i].txvlan = 0;
1822 np->rx_ring.ex[i].bufhigh = 0;
1823 np->rx_ring.ex[i].buflow = 0;
1824 }
1825 np->rx_skb[i].skb = NULL;
1826 np->rx_skb[i].dma = 0;
1827 }
1828 }
1829
1830 static void nv_init_tx(struct net_device *dev)
1831 {
1832 struct fe_priv *np = netdev_priv(dev);
1833 int i;
1834
1835 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1836
1837 if (!nv_optimized(np))
1838 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1839 else
1840 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1841 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1842 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1843 np->tx_pkts_in_progress = 0;
1844 np->tx_change_owner = NULL;
1845 np->tx_end_flip = NULL;
1846 np->tx_stop = 0;
1847
1848 for (i = 0; i < np->tx_ring_size; i++) {
1849 if (!nv_optimized(np)) {
1850 np->tx_ring.orig[i].flaglen = 0;
1851 np->tx_ring.orig[i].buf = 0;
1852 } else {
1853 np->tx_ring.ex[i].flaglen = 0;
1854 np->tx_ring.ex[i].txvlan = 0;
1855 np->tx_ring.ex[i].bufhigh = 0;
1856 np->tx_ring.ex[i].buflow = 0;
1857 }
1858 np->tx_skb[i].skb = NULL;
1859 np->tx_skb[i].dma = 0;
1860 np->tx_skb[i].dma_len = 0;
1861 np->tx_skb[i].dma_single = 0;
1862 np->tx_skb[i].first_tx_desc = NULL;
1863 np->tx_skb[i].next_tx_ctx = NULL;
1864 }
1865 }
1866
1867 static int nv_init_ring(struct net_device *dev)
1868 {
1869 struct fe_priv *np = netdev_priv(dev);
1870
1871 nv_init_tx(dev);
1872 nv_init_rx(dev);
1873
1874 if (!nv_optimized(np))
1875 return nv_alloc_rx(dev);
1876 else
1877 return nv_alloc_rx_optimized(dev);
1878 }
1879
1880 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1881 {
1882 if (tx_skb->dma) {
1883 if (tx_skb->dma_single)
1884 pci_unmap_single(np->pci_dev, tx_skb->dma,
1885 tx_skb->dma_len,
1886 PCI_DMA_TODEVICE);
1887 else
1888 pci_unmap_page(np->pci_dev, tx_skb->dma,
1889 tx_skb->dma_len,
1890 PCI_DMA_TODEVICE);
1891 tx_skb->dma = 0;
1892 }
1893 }
1894
1895 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1896 {
1897 nv_unmap_txskb(np, tx_skb);
1898 if (tx_skb->skb) {
1899 dev_kfree_skb_any(tx_skb->skb);
1900 tx_skb->skb = NULL;
1901 return 1;
1902 }
1903 return 0;
1904 }
1905
1906 static void nv_drain_tx(struct net_device *dev)
1907 {
1908 struct fe_priv *np = netdev_priv(dev);
1909 unsigned int i;
1910
1911 for (i = 0; i < np->tx_ring_size; i++) {
1912 if (!nv_optimized(np)) {
1913 np->tx_ring.orig[i].flaglen = 0;
1914 np->tx_ring.orig[i].buf = 0;
1915 } else {
1916 np->tx_ring.ex[i].flaglen = 0;
1917 np->tx_ring.ex[i].txvlan = 0;
1918 np->tx_ring.ex[i].bufhigh = 0;
1919 np->tx_ring.ex[i].buflow = 0;
1920 }
1921 if (nv_release_txskb(np, &np->tx_skb[i]))
1922 dev->stats.tx_dropped++;
1923 np->tx_skb[i].dma = 0;
1924 np->tx_skb[i].dma_len = 0;
1925 np->tx_skb[i].dma_single = 0;
1926 np->tx_skb[i].first_tx_desc = NULL;
1927 np->tx_skb[i].next_tx_ctx = NULL;
1928 }
1929 np->tx_pkts_in_progress = 0;
1930 np->tx_change_owner = NULL;
1931 np->tx_end_flip = NULL;
1932 }
1933
1934 static void nv_drain_rx(struct net_device *dev)
1935 {
1936 struct fe_priv *np = netdev_priv(dev);
1937 int i;
1938
1939 for (i = 0; i < np->rx_ring_size; i++) {
1940 if (!nv_optimized(np)) {
1941 np->rx_ring.orig[i].flaglen = 0;
1942 np->rx_ring.orig[i].buf = 0;
1943 } else {
1944 np->rx_ring.ex[i].flaglen = 0;
1945 np->rx_ring.ex[i].txvlan = 0;
1946 np->rx_ring.ex[i].bufhigh = 0;
1947 np->rx_ring.ex[i].buflow = 0;
1948 }
1949 wmb();
1950 if (np->rx_skb[i].skb) {
1951 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1952 (skb_end_pointer(np->rx_skb[i].skb) -
1953 np->rx_skb[i].skb->data),
1954 PCI_DMA_FROMDEVICE);
1955 dev_kfree_skb(np->rx_skb[i].skb);
1956 np->rx_skb[i].skb = NULL;
1957 }
1958 }
1959 }
1960
1961 static void nv_drain_rxtx(struct net_device *dev)
1962 {
1963 nv_drain_tx(dev);
1964 nv_drain_rx(dev);
1965 }
1966
1967 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1968 {
1969 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1970 }
1971
1972 static void nv_legacybackoff_reseed(struct net_device *dev)
1973 {
1974 u8 __iomem *base = get_hwbase(dev);
1975 u32 reg;
1976 u32 low;
1977 int tx_status = 0;
1978
1979 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1980 get_random_bytes(&low, sizeof(low));
1981 reg |= low & NVREG_SLOTTIME_MASK;
1982
1983 /* Need to stop tx before change takes effect.
1984 * Caller has already gained np->lock.
1985 */
1986 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1987 if (tx_status)
1988 nv_stop_tx(dev);
1989 nv_stop_rx(dev);
1990 writel(reg, base + NvRegSlotTime);
1991 if (tx_status)
1992 nv_start_tx(dev);
1993 nv_start_rx(dev);
1994 }
1995
1996 /* Gear Backoff Seeds */
1997 #define BACKOFF_SEEDSET_ROWS 8
1998 #define BACKOFF_SEEDSET_LFSRS 15
1999
2000 /* Known Good seed sets */
2001 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2002 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2003 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2004 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2005 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2006 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2007 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2008 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2009 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2010
2011 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2012 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2013 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2014 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2015 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2016 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2017 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2018 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2019 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2020
2021 static void nv_gear_backoff_reseed(struct net_device *dev)
2022 {
2023 u8 __iomem *base = get_hwbase(dev);
2024 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2025 u32 temp, seedset, combinedSeed;
2026 int i;
2027
2028 /* Setup seed for free running LFSR */
2029 /* We are going to read the time stamp counter 3 times
2030 and swizzle bits around to increase randomness */
2031 get_random_bytes(&miniseed1, sizeof(miniseed1));
2032 miniseed1 &= 0x0fff;
2033 if (miniseed1 == 0)
2034 miniseed1 = 0xabc;
2035
2036 get_random_bytes(&miniseed2, sizeof(miniseed2));
2037 miniseed2 &= 0x0fff;
2038 if (miniseed2 == 0)
2039 miniseed2 = 0xabc;
2040 miniseed2_reversed =
2041 ((miniseed2 & 0xF00) >> 8) |
2042 (miniseed2 & 0x0F0) |
2043 ((miniseed2 & 0x00F) << 8);
2044
2045 get_random_bytes(&miniseed3, sizeof(miniseed3));
2046 miniseed3 &= 0x0fff;
2047 if (miniseed3 == 0)
2048 miniseed3 = 0xabc;
2049 miniseed3_reversed =
2050 ((miniseed3 & 0xF00) >> 8) |
2051 (miniseed3 & 0x0F0) |
2052 ((miniseed3 & 0x00F) << 8);
2053
2054 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2055 (miniseed2 ^ miniseed3_reversed);
2056
2057 /* Seeds can not be zero */
2058 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2059 combinedSeed |= 0x08;
2060 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2061 combinedSeed |= 0x8000;
2062
2063 /* No need to disable tx here */
2064 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2065 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2066 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2067 writel(temp, base + NvRegBackOffControl);
2068
2069 /* Setup seeds for all gear LFSRs. */
2070 get_random_bytes(&seedset, sizeof(seedset));
2071 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2072 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2073 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2074 temp |= main_seedset[seedset][i-1] & 0x3ff;
2075 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2076 writel(temp, base + NvRegBackOffControl);
2077 }
2078 }
2079
2080 /*
2081 * nv_start_xmit: dev->hard_start_xmit function
2082 * Called with netif_tx_lock held.
2083 */
2084 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2085 {
2086 struct fe_priv *np = netdev_priv(dev);
2087 u32 tx_flags = 0;
2088 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2089 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2090 unsigned int i;
2091 u32 offset = 0;
2092 u32 bcnt;
2093 u32 size = skb_headlen(skb);
2094 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2095 u32 empty_slots;
2096 struct ring_desc *put_tx;
2097 struct ring_desc *start_tx;
2098 struct ring_desc *prev_tx;
2099 struct nv_skb_map *prev_tx_ctx;
2100 unsigned long flags;
2101
2102 /* add fragments to entries count */
2103 for (i = 0; i < fragments; i++) {
2104 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2105 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2106 }
2107
2108 spin_lock_irqsave(&np->lock, flags);
2109 empty_slots = nv_get_empty_tx_slots(np);
2110 if (unlikely(empty_slots <= entries)) {
2111 netif_stop_queue(dev);
2112 np->tx_stop = 1;
2113 spin_unlock_irqrestore(&np->lock, flags);
2114 return NETDEV_TX_BUSY;
2115 }
2116 spin_unlock_irqrestore(&np->lock, flags);
2117
2118 start_tx = put_tx = np->put_tx.orig;
2119
2120 /* setup the header buffer */
2121 do {
2122 prev_tx = put_tx;
2123 prev_tx_ctx = np->put_tx_ctx;
2124 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2125 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2126 PCI_DMA_TODEVICE);
2127 np->put_tx_ctx->dma_len = bcnt;
2128 np->put_tx_ctx->dma_single = 1;
2129 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2130 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2131
2132 tx_flags = np->tx_flags;
2133 offset += bcnt;
2134 size -= bcnt;
2135 if (unlikely(put_tx++ == np->last_tx.orig))
2136 put_tx = np->first_tx.orig;
2137 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2138 np->put_tx_ctx = np->first_tx_ctx;
2139 } while (size);
2140
2141 /* setup the fragments */
2142 for (i = 0; i < fragments; i++) {
2143 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2144 u32 size = frag->size;
2145 offset = 0;
2146
2147 do {
2148 prev_tx = put_tx;
2149 prev_tx_ctx = np->put_tx_ctx;
2150 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2151 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2152 PCI_DMA_TODEVICE);
2153 np->put_tx_ctx->dma_len = bcnt;
2154 np->put_tx_ctx->dma_single = 0;
2155 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2156 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2157
2158 offset += bcnt;
2159 size -= bcnt;
2160 if (unlikely(put_tx++ == np->last_tx.orig))
2161 put_tx = np->first_tx.orig;
2162 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2163 np->put_tx_ctx = np->first_tx_ctx;
2164 } while (size);
2165 }
2166
2167 /* set last fragment flag */
2168 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2169
2170 /* save skb in this slot's context area */
2171 prev_tx_ctx->skb = skb;
2172
2173 if (skb_is_gso(skb))
2174 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2175 else
2176 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2177 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2178
2179 spin_lock_irqsave(&np->lock, flags);
2180
2181 /* set tx flags */
2182 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2183 np->put_tx.orig = put_tx;
2184
2185 spin_unlock_irqrestore(&np->lock, flags);
2186
2187 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2188 return NETDEV_TX_OK;
2189 }
2190
2191 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2192 struct net_device *dev)
2193 {
2194 struct fe_priv *np = netdev_priv(dev);
2195 u32 tx_flags = 0;
2196 u32 tx_flags_extra;
2197 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2198 unsigned int i;
2199 u32 offset = 0;
2200 u32 bcnt;
2201 u32 size = skb_headlen(skb);
2202 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2203 u32 empty_slots;
2204 struct ring_desc_ex *put_tx;
2205 struct ring_desc_ex *start_tx;
2206 struct ring_desc_ex *prev_tx;
2207 struct nv_skb_map *prev_tx_ctx;
2208 struct nv_skb_map *start_tx_ctx;
2209 unsigned long flags;
2210
2211 /* add fragments to entries count */
2212 for (i = 0; i < fragments; i++) {
2213 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2214 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2215 }
2216
2217 spin_lock_irqsave(&np->lock, flags);
2218 empty_slots = nv_get_empty_tx_slots(np);
2219 if (unlikely(empty_slots <= entries)) {
2220 netif_stop_queue(dev);
2221 np->tx_stop = 1;
2222 spin_unlock_irqrestore(&np->lock, flags);
2223 return NETDEV_TX_BUSY;
2224 }
2225 spin_unlock_irqrestore(&np->lock, flags);
2226
2227 start_tx = put_tx = np->put_tx.ex;
2228 start_tx_ctx = np->put_tx_ctx;
2229
2230 /* setup the header buffer */
2231 do {
2232 prev_tx = put_tx;
2233 prev_tx_ctx = np->put_tx_ctx;
2234 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2235 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2236 PCI_DMA_TODEVICE);
2237 np->put_tx_ctx->dma_len = bcnt;
2238 np->put_tx_ctx->dma_single = 1;
2239 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2240 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2241 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2242
2243 tx_flags = NV_TX2_VALID;
2244 offset += bcnt;
2245 size -= bcnt;
2246 if (unlikely(put_tx++ == np->last_tx.ex))
2247 put_tx = np->first_tx.ex;
2248 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2249 np->put_tx_ctx = np->first_tx_ctx;
2250 } while (size);
2251
2252 /* setup the fragments */
2253 for (i = 0; i < fragments; i++) {
2254 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2255 u32 size = frag->size;
2256 offset = 0;
2257
2258 do {
2259 prev_tx = put_tx;
2260 prev_tx_ctx = np->put_tx_ctx;
2261 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2262 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2263 PCI_DMA_TODEVICE);
2264 np->put_tx_ctx->dma_len = bcnt;
2265 np->put_tx_ctx->dma_single = 0;
2266 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2267 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2268 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2269
2270 offset += bcnt;
2271 size -= bcnt;
2272 if (unlikely(put_tx++ == np->last_tx.ex))
2273 put_tx = np->first_tx.ex;
2274 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2275 np->put_tx_ctx = np->first_tx_ctx;
2276 } while (size);
2277 }
2278
2279 /* set last fragment flag */
2280 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2281
2282 /* save skb in this slot's context area */
2283 prev_tx_ctx->skb = skb;
2284
2285 if (skb_is_gso(skb))
2286 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2287 else
2288 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2289 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2290
2291 /* vlan tag */
2292 if (vlan_tx_tag_present(skb))
2293 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2294 vlan_tx_tag_get(skb));
2295 else
2296 start_tx->txvlan = 0;
2297
2298 spin_lock_irqsave(&np->lock, flags);
2299
2300 if (np->tx_limit) {
2301 /* Limit the number of outstanding tx. Setup all fragments, but
2302 * do not set the VALID bit on the first descriptor. Save a pointer
2303 * to that descriptor and also for next skb_map element.
2304 */
2305
2306 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2307 if (!np->tx_change_owner)
2308 np->tx_change_owner = start_tx_ctx;
2309
2310 /* remove VALID bit */
2311 tx_flags &= ~NV_TX2_VALID;
2312 start_tx_ctx->first_tx_desc = start_tx;
2313 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2314 np->tx_end_flip = np->put_tx_ctx;
2315 } else {
2316 np->tx_pkts_in_progress++;
2317 }
2318 }
2319
2320 /* set tx flags */
2321 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2322 np->put_tx.ex = put_tx;
2323
2324 spin_unlock_irqrestore(&np->lock, flags);
2325
2326 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2327 return NETDEV_TX_OK;
2328 }
2329
2330 static inline void nv_tx_flip_ownership(struct net_device *dev)
2331 {
2332 struct fe_priv *np = netdev_priv(dev);
2333
2334 np->tx_pkts_in_progress--;
2335 if (np->tx_change_owner) {
2336 np->tx_change_owner->first_tx_desc->flaglen |=
2337 cpu_to_le32(NV_TX2_VALID);
2338 np->tx_pkts_in_progress++;
2339
2340 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2341 if (np->tx_change_owner == np->tx_end_flip)
2342 np->tx_change_owner = NULL;
2343
2344 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2345 }
2346 }
2347
2348 /*
2349 * nv_tx_done: check for completed packets, release the skbs.
2350 *
2351 * Caller must own np->lock.
2352 */
2353 static int nv_tx_done(struct net_device *dev, int limit)
2354 {
2355 struct fe_priv *np = netdev_priv(dev);
2356 u32 flags;
2357 int tx_work = 0;
2358 struct ring_desc *orig_get_tx = np->get_tx.orig;
2359
2360 while ((np->get_tx.orig != np->put_tx.orig) &&
2361 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2362 (tx_work < limit)) {
2363
2364 nv_unmap_txskb(np, np->get_tx_ctx);
2365
2366 if (np->desc_ver == DESC_VER_1) {
2367 if (flags & NV_TX_LASTPACKET) {
2368 if (flags & NV_TX_ERROR) {
2369 if (flags & NV_TX_UNDERFLOW)
2370 dev->stats.tx_fifo_errors++;
2371 if (flags & NV_TX_CARRIERLOST)
2372 dev->stats.tx_carrier_errors++;
2373 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2374 nv_legacybackoff_reseed(dev);
2375 dev->stats.tx_errors++;
2376 } else {
2377 dev->stats.tx_packets++;
2378 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2379 }
2380 dev_kfree_skb_any(np->get_tx_ctx->skb);
2381 np->get_tx_ctx->skb = NULL;
2382 tx_work++;
2383 }
2384 } else {
2385 if (flags & NV_TX2_LASTPACKET) {
2386 if (flags & NV_TX2_ERROR) {
2387 if (flags & NV_TX2_UNDERFLOW)
2388 dev->stats.tx_fifo_errors++;
2389 if (flags & NV_TX2_CARRIERLOST)
2390 dev->stats.tx_carrier_errors++;
2391 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2392 nv_legacybackoff_reseed(dev);
2393 dev->stats.tx_errors++;
2394 } else {
2395 dev->stats.tx_packets++;
2396 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2397 }
2398 dev_kfree_skb_any(np->get_tx_ctx->skb);
2399 np->get_tx_ctx->skb = NULL;
2400 tx_work++;
2401 }
2402 }
2403 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2404 np->get_tx.orig = np->first_tx.orig;
2405 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2406 np->get_tx_ctx = np->first_tx_ctx;
2407 }
2408 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2409 np->tx_stop = 0;
2410 netif_wake_queue(dev);
2411 }
2412 return tx_work;
2413 }
2414
2415 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2416 {
2417 struct fe_priv *np = netdev_priv(dev);
2418 u32 flags;
2419 int tx_work = 0;
2420 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2421
2422 while ((np->get_tx.ex != np->put_tx.ex) &&
2423 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2424 (tx_work < limit)) {
2425
2426 nv_unmap_txskb(np, np->get_tx_ctx);
2427
2428 if (flags & NV_TX2_LASTPACKET) {
2429 if (!(flags & NV_TX2_ERROR))
2430 dev->stats.tx_packets++;
2431 else {
2432 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2433 if (np->driver_data & DEV_HAS_GEAR_MODE)
2434 nv_gear_backoff_reseed(dev);
2435 else
2436 nv_legacybackoff_reseed(dev);
2437 }
2438 }
2439
2440 dev_kfree_skb_any(np->get_tx_ctx->skb);
2441 np->get_tx_ctx->skb = NULL;
2442 tx_work++;
2443
2444 if (np->tx_limit)
2445 nv_tx_flip_ownership(dev);
2446 }
2447 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2448 np->get_tx.ex = np->first_tx.ex;
2449 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2450 np->get_tx_ctx = np->first_tx_ctx;
2451 }
2452 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2453 np->tx_stop = 0;
2454 netif_wake_queue(dev);
2455 }
2456 return tx_work;
2457 }
2458
2459 /*
2460 * nv_tx_timeout: dev->tx_timeout function
2461 * Called with netif_tx_lock held.
2462 */
2463 static void nv_tx_timeout(struct net_device *dev)
2464 {
2465 struct fe_priv *np = netdev_priv(dev);
2466 u8 __iomem *base = get_hwbase(dev);
2467 u32 status;
2468 union ring_type put_tx;
2469 int saved_tx_limit;
2470 int i;
2471
2472 if (np->msi_flags & NV_MSI_X_ENABLED)
2473 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2474 else
2475 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2476
2477 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2478
2479 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2480 netdev_info(dev, "Dumping tx registers\n");
2481 for (i = 0; i <= np->register_size; i += 32) {
2482 netdev_info(dev,
2483 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2484 i,
2485 readl(base + i + 0), readl(base + i + 4),
2486 readl(base + i + 8), readl(base + i + 12),
2487 readl(base + i + 16), readl(base + i + 20),
2488 readl(base + i + 24), readl(base + i + 28));
2489 }
2490 netdev_info(dev, "Dumping tx ring\n");
2491 for (i = 0; i < np->tx_ring_size; i += 4) {
2492 if (!nv_optimized(np)) {
2493 netdev_info(dev,
2494 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2495 i,
2496 le32_to_cpu(np->tx_ring.orig[i].buf),
2497 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2498 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2499 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2500 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2501 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2502 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2503 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2504 } else {
2505 netdev_info(dev,
2506 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2507 i,
2508 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2509 le32_to_cpu(np->tx_ring.ex[i].buflow),
2510 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2511 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2512 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2513 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2514 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2515 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2516 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2517 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2518 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2519 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2520 }
2521 }
2522
2523 spin_lock_irq(&np->lock);
2524
2525 /* 1) stop tx engine */
2526 nv_stop_tx(dev);
2527
2528 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2529 saved_tx_limit = np->tx_limit;
2530 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2531 np->tx_stop = 0; /* prevent waking tx queue */
2532 if (!nv_optimized(np))
2533 nv_tx_done(dev, np->tx_ring_size);
2534 else
2535 nv_tx_done_optimized(dev, np->tx_ring_size);
2536
2537 /* save current HW position */
2538 if (np->tx_change_owner)
2539 put_tx.ex = np->tx_change_owner->first_tx_desc;
2540 else
2541 put_tx = np->put_tx;
2542
2543 /* 3) clear all tx state */
2544 nv_drain_tx(dev);
2545 nv_init_tx(dev);
2546
2547 /* 4) restore state to current HW position */
2548 np->get_tx = np->put_tx = put_tx;
2549 np->tx_limit = saved_tx_limit;
2550
2551 /* 5) restart tx engine */
2552 nv_start_tx(dev);
2553 netif_wake_queue(dev);
2554 spin_unlock_irq(&np->lock);
2555 }
2556
2557 /*
2558 * Called when the nic notices a mismatch between the actual data len on the
2559 * wire and the len indicated in the 802 header
2560 */
2561 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2562 {
2563 int hdrlen; /* length of the 802 header */
2564 int protolen; /* length as stored in the proto field */
2565
2566 /* 1) calculate len according to header */
2567 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2568 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2569 hdrlen = VLAN_HLEN;
2570 } else {
2571 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2572 hdrlen = ETH_HLEN;
2573 }
2574 if (protolen > ETH_DATA_LEN)
2575 return datalen; /* Value in proto field not a len, no checks possible */
2576
2577 protolen += hdrlen;
2578 /* consistency checks: */
2579 if (datalen > ETH_ZLEN) {
2580 if (datalen >= protolen) {
2581 /* more data on wire than in 802 header, trim of
2582 * additional data.
2583 */
2584 return protolen;
2585 } else {
2586 /* less data on wire than mentioned in header.
2587 * Discard the packet.
2588 */
2589 return -1;
2590 }
2591 } else {
2592 /* short packet. Accept only if 802 values are also short */
2593 if (protolen > ETH_ZLEN) {
2594 return -1;
2595 }
2596 return datalen;
2597 }
2598 }
2599
2600 static int nv_rx_process(struct net_device *dev, int limit)
2601 {
2602 struct fe_priv *np = netdev_priv(dev);
2603 u32 flags;
2604 int rx_work = 0;
2605 struct sk_buff *skb;
2606 int len;
2607
2608 while ((np->get_rx.orig != np->put_rx.orig) &&
2609 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2610 (rx_work < limit)) {
2611
2612 /*
2613 * the packet is for us - immediately tear down the pci mapping.
2614 * TODO: check if a prefetch of the first cacheline improves
2615 * the performance.
2616 */
2617 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2618 np->get_rx_ctx->dma_len,
2619 PCI_DMA_FROMDEVICE);
2620 skb = np->get_rx_ctx->skb;
2621 np->get_rx_ctx->skb = NULL;
2622
2623 /* look at what we actually got: */
2624 if (np->desc_ver == DESC_VER_1) {
2625 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2626 len = flags & LEN_MASK_V1;
2627 if (unlikely(flags & NV_RX_ERROR)) {
2628 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2629 len = nv_getlen(dev, skb->data, len);
2630 if (len < 0) {
2631 dev->stats.rx_errors++;
2632 dev_kfree_skb(skb);
2633 goto next_pkt;
2634 }
2635 }
2636 /* framing errors are soft errors */
2637 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2638 if (flags & NV_RX_SUBSTRACT1)
2639 len--;
2640 }
2641 /* the rest are hard errors */
2642 else {
2643 if (flags & NV_RX_MISSEDFRAME)
2644 dev->stats.rx_missed_errors++;
2645 if (flags & NV_RX_CRCERR)
2646 dev->stats.rx_crc_errors++;
2647 if (flags & NV_RX_OVERFLOW)
2648 dev->stats.rx_over_errors++;
2649 dev->stats.rx_errors++;
2650 dev_kfree_skb(skb);
2651 goto next_pkt;
2652 }
2653 }
2654 } else {
2655 dev_kfree_skb(skb);
2656 goto next_pkt;
2657 }
2658 } else {
2659 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2660 len = flags & LEN_MASK_V2;
2661 if (unlikely(flags & NV_RX2_ERROR)) {
2662 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2663 len = nv_getlen(dev, skb->data, len);
2664 if (len < 0) {
2665 dev->stats.rx_errors++;
2666 dev_kfree_skb(skb);
2667 goto next_pkt;
2668 }
2669 }
2670 /* framing errors are soft errors */
2671 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2672 if (flags & NV_RX2_SUBSTRACT1)
2673 len--;
2674 }
2675 /* the rest are hard errors */
2676 else {
2677 if (flags & NV_RX2_CRCERR)
2678 dev->stats.rx_crc_errors++;
2679 if (flags & NV_RX2_OVERFLOW)
2680 dev->stats.rx_over_errors++;
2681 dev->stats.rx_errors++;
2682 dev_kfree_skb(skb);
2683 goto next_pkt;
2684 }
2685 }
2686 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2687 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2688 skb->ip_summed = CHECKSUM_UNNECESSARY;
2689 } else {
2690 dev_kfree_skb(skb);
2691 goto next_pkt;
2692 }
2693 }
2694 /* got a valid packet - forward it to the network core */
2695 skb_put(skb, len);
2696 skb->protocol = eth_type_trans(skb, dev);
2697 napi_gro_receive(&np->napi, skb);
2698 dev->stats.rx_packets++;
2699 dev->stats.rx_bytes += len;
2700 next_pkt:
2701 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2702 np->get_rx.orig = np->first_rx.orig;
2703 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2704 np->get_rx_ctx = np->first_rx_ctx;
2705
2706 rx_work++;
2707 }
2708
2709 return rx_work;
2710 }
2711
2712 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2713 {
2714 struct fe_priv *np = netdev_priv(dev);
2715 u32 flags;
2716 u32 vlanflags = 0;
2717 int rx_work = 0;
2718 struct sk_buff *skb;
2719 int len;
2720
2721 while ((np->get_rx.ex != np->put_rx.ex) &&
2722 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2723 (rx_work < limit)) {
2724
2725 /*
2726 * the packet is for us - immediately tear down the pci mapping.
2727 * TODO: check if a prefetch of the first cacheline improves
2728 * the performance.
2729 */
2730 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2731 np->get_rx_ctx->dma_len,
2732 PCI_DMA_FROMDEVICE);
2733 skb = np->get_rx_ctx->skb;
2734 np->get_rx_ctx->skb = NULL;
2735
2736 /* look at what we actually got: */
2737 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2738 len = flags & LEN_MASK_V2;
2739 if (unlikely(flags & NV_RX2_ERROR)) {
2740 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2741 len = nv_getlen(dev, skb->data, len);
2742 if (len < 0) {
2743 dev_kfree_skb(skb);
2744 goto next_pkt;
2745 }
2746 }
2747 /* framing errors are soft errors */
2748 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2749 if (flags & NV_RX2_SUBSTRACT1)
2750 len--;
2751 }
2752 /* the rest are hard errors */
2753 else {
2754 dev_kfree_skb(skb);
2755 goto next_pkt;
2756 }
2757 }
2758
2759 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2760 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2761 skb->ip_summed = CHECKSUM_UNNECESSARY;
2762
2763 /* got a valid packet - forward it to the network core */
2764 skb_put(skb, len);
2765 skb->protocol = eth_type_trans(skb, dev);
2766 prefetch(skb->data);
2767
2768 if (likely(!np->vlangrp)) {
2769 napi_gro_receive(&np->napi, skb);
2770 } else {
2771 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2772 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2773 vlan_gro_receive(&np->napi, np->vlangrp,
2774 vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
2775 } else {
2776 napi_gro_receive(&np->napi, skb);
2777 }
2778 }
2779
2780 dev->stats.rx_packets++;
2781 dev->stats.rx_bytes += len;
2782 } else {
2783 dev_kfree_skb(skb);
2784 }
2785 next_pkt:
2786 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2787 np->get_rx.ex = np->first_rx.ex;
2788 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2789 np->get_rx_ctx = np->first_rx_ctx;
2790
2791 rx_work++;
2792 }
2793
2794 return rx_work;
2795 }
2796
2797 static void set_bufsize(struct net_device *dev)
2798 {
2799 struct fe_priv *np = netdev_priv(dev);
2800
2801 if (dev->mtu <= ETH_DATA_LEN)
2802 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2803 else
2804 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2805 }
2806
2807 /*
2808 * nv_change_mtu: dev->change_mtu function
2809 * Called with dev_base_lock held for read.
2810 */
2811 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2812 {
2813 struct fe_priv *np = netdev_priv(dev);
2814 int old_mtu;
2815
2816 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2817 return -EINVAL;
2818
2819 old_mtu = dev->mtu;
2820 dev->mtu = new_mtu;
2821
2822 /* return early if the buffer sizes will not change */
2823 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2824 return 0;
2825 if (old_mtu == new_mtu)
2826 return 0;
2827
2828 /* synchronized against open : rtnl_lock() held by caller */
2829 if (netif_running(dev)) {
2830 u8 __iomem *base = get_hwbase(dev);
2831 /*
2832 * It seems that the nic preloads valid ring entries into an
2833 * internal buffer. The procedure for flushing everything is
2834 * guessed, there is probably a simpler approach.
2835 * Changing the MTU is a rare event, it shouldn't matter.
2836 */
2837 nv_disable_irq(dev);
2838 nv_napi_disable(dev);
2839 netif_tx_lock_bh(dev);
2840 netif_addr_lock(dev);
2841 spin_lock(&np->lock);
2842 /* stop engines */
2843 nv_stop_rxtx(dev);
2844 nv_txrx_reset(dev);
2845 /* drain rx queue */
2846 nv_drain_rxtx(dev);
2847 /* reinit driver view of the rx queue */
2848 set_bufsize(dev);
2849 if (nv_init_ring(dev)) {
2850 if (!np->in_shutdown)
2851 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2852 }
2853 /* reinit nic view of the rx queue */
2854 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2855 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2856 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2857 base + NvRegRingSizes);
2858 pci_push(base);
2859 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2860 pci_push(base);
2861
2862 /* restart rx engine */
2863 nv_start_rxtx(dev);
2864 spin_unlock(&np->lock);
2865 netif_addr_unlock(dev);
2866 netif_tx_unlock_bh(dev);
2867 nv_napi_enable(dev);
2868 nv_enable_irq(dev);
2869 }
2870 return 0;
2871 }
2872
2873 static void nv_copy_mac_to_hw(struct net_device *dev)
2874 {
2875 u8 __iomem *base = get_hwbase(dev);
2876 u32 mac[2];
2877
2878 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2879 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2880 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2881
2882 writel(mac[0], base + NvRegMacAddrA);
2883 writel(mac[1], base + NvRegMacAddrB);
2884 }
2885
2886 /*
2887 * nv_set_mac_address: dev->set_mac_address function
2888 * Called with rtnl_lock() held.
2889 */
2890 static int nv_set_mac_address(struct net_device *dev, void *addr)
2891 {
2892 struct fe_priv *np = netdev_priv(dev);
2893 struct sockaddr *macaddr = (struct sockaddr *)addr;
2894
2895 if (!is_valid_ether_addr(macaddr->sa_data))
2896 return -EADDRNOTAVAIL;
2897
2898 /* synchronized against open : rtnl_lock() held by caller */
2899 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2900
2901 if (netif_running(dev)) {
2902 netif_tx_lock_bh(dev);
2903 netif_addr_lock(dev);
2904 spin_lock_irq(&np->lock);
2905
2906 /* stop rx engine */
2907 nv_stop_rx(dev);
2908
2909 /* set mac address */
2910 nv_copy_mac_to_hw(dev);
2911
2912 /* restart rx engine */
2913 nv_start_rx(dev);
2914 spin_unlock_irq(&np->lock);
2915 netif_addr_unlock(dev);
2916 netif_tx_unlock_bh(dev);
2917 } else {
2918 nv_copy_mac_to_hw(dev);
2919 }
2920 return 0;
2921 }
2922
2923 /*
2924 * nv_set_multicast: dev->set_multicast function
2925 * Called with netif_tx_lock held.
2926 */
2927 static void nv_set_multicast(struct net_device *dev)
2928 {
2929 struct fe_priv *np = netdev_priv(dev);
2930 u8 __iomem *base = get_hwbase(dev);
2931 u32 addr[2];
2932 u32 mask[2];
2933 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2934
2935 memset(addr, 0, sizeof(addr));
2936 memset(mask, 0, sizeof(mask));
2937
2938 if (dev->flags & IFF_PROMISC) {
2939 pff |= NVREG_PFF_PROMISC;
2940 } else {
2941 pff |= NVREG_PFF_MYADDR;
2942
2943 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2944 u32 alwaysOff[2];
2945 u32 alwaysOn[2];
2946
2947 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2948 if (dev->flags & IFF_ALLMULTI) {
2949 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2950 } else {
2951 struct netdev_hw_addr *ha;
2952
2953 netdev_for_each_mc_addr(ha, dev) {
2954 unsigned char *addr = ha->addr;
2955 u32 a, b;
2956
2957 a = le32_to_cpu(*(__le32 *) addr);
2958 b = le16_to_cpu(*(__le16 *) (&addr[4]));
2959 alwaysOn[0] &= a;
2960 alwaysOff[0] &= ~a;
2961 alwaysOn[1] &= b;
2962 alwaysOff[1] &= ~b;
2963 }
2964 }
2965 addr[0] = alwaysOn[0];
2966 addr[1] = alwaysOn[1];
2967 mask[0] = alwaysOn[0] | alwaysOff[0];
2968 mask[1] = alwaysOn[1] | alwaysOff[1];
2969 } else {
2970 mask[0] = NVREG_MCASTMASKA_NONE;
2971 mask[1] = NVREG_MCASTMASKB_NONE;
2972 }
2973 }
2974 addr[0] |= NVREG_MCASTADDRA_FORCE;
2975 pff |= NVREG_PFF_ALWAYS;
2976 spin_lock_irq(&np->lock);
2977 nv_stop_rx(dev);
2978 writel(addr[0], base + NvRegMulticastAddrA);
2979 writel(addr[1], base + NvRegMulticastAddrB);
2980 writel(mask[0], base + NvRegMulticastMaskA);
2981 writel(mask[1], base + NvRegMulticastMaskB);
2982 writel(pff, base + NvRegPacketFilterFlags);
2983 nv_start_rx(dev);
2984 spin_unlock_irq(&np->lock);
2985 }
2986
2987 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2988 {
2989 struct fe_priv *np = netdev_priv(dev);
2990 u8 __iomem *base = get_hwbase(dev);
2991
2992 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2993
2994 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2995 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2996 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2997 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2998 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2999 } else {
3000 writel(pff, base + NvRegPacketFilterFlags);
3001 }
3002 }
3003 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3004 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3005 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3006 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3007 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3008 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3009 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3010 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3011 /* limit the number of tx pause frames to a default of 8 */
3012 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3013 }
3014 writel(pause_enable, base + NvRegTxPauseFrame);
3015 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3016 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3017 } else {
3018 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3019 writel(regmisc, base + NvRegMisc1);
3020 }
3021 }
3022 }
3023
3024 /**
3025 * nv_update_linkspeed: Setup the MAC according to the link partner
3026 * @dev: Network device to be configured
3027 *
3028 * The function queries the PHY and checks if there is a link partner.
3029 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3030 * set to 10 MBit HD.
3031 *
3032 * The function returns 0 if there is no link partner and 1 if there is
3033 * a good link partner.
3034 */
3035 static int nv_update_linkspeed(struct net_device *dev)
3036 {
3037 struct fe_priv *np = netdev_priv(dev);
3038 u8 __iomem *base = get_hwbase(dev);
3039 int adv = 0;
3040 int lpa = 0;
3041 int adv_lpa, adv_pause, lpa_pause;
3042 int newls = np->linkspeed;
3043 int newdup = np->duplex;
3044 int mii_status;
3045 int retval = 0;
3046 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3047 u32 txrxFlags = 0;
3048 u32 phy_exp;
3049
3050 /* BMSR_LSTATUS is latched, read it twice:
3051 * we want the current value.
3052 */
3053 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3054 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3055
3056 if (!(mii_status & BMSR_LSTATUS)) {
3057 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3058 newdup = 0;
3059 retval = 0;
3060 goto set_speed;
3061 }
3062
3063 if (np->autoneg == 0) {
3064 if (np->fixed_mode & LPA_100FULL) {
3065 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3066 newdup = 1;
3067 } else if (np->fixed_mode & LPA_100HALF) {
3068 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3069 newdup = 0;
3070 } else if (np->fixed_mode & LPA_10FULL) {
3071 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3072 newdup = 1;
3073 } else {
3074 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3075 newdup = 0;
3076 }
3077 retval = 1;
3078 goto set_speed;
3079 }
3080 /* check auto negotiation is complete */
3081 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3082 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3083 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3084 newdup = 0;
3085 retval = 0;
3086 goto set_speed;
3087 }
3088
3089 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3090 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3091
3092 retval = 1;
3093 if (np->gigabit == PHY_GIGABIT) {
3094 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3095 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3096
3097 if ((control_1000 & ADVERTISE_1000FULL) &&
3098 (status_1000 & LPA_1000FULL)) {
3099 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3100 newdup = 1;
3101 goto set_speed;
3102 }
3103 }
3104
3105 /* FIXME: handle parallel detection properly */
3106 adv_lpa = lpa & adv;
3107 if (adv_lpa & LPA_100FULL) {
3108 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3109 newdup = 1;
3110 } else if (adv_lpa & LPA_100HALF) {
3111 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3112 newdup = 0;
3113 } else if (adv_lpa & LPA_10FULL) {
3114 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3115 newdup = 1;
3116 } else if (adv_lpa & LPA_10HALF) {
3117 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3118 newdup = 0;
3119 } else {
3120 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3121 newdup = 0;
3122 }
3123
3124 set_speed:
3125 if (np->duplex == newdup && np->linkspeed == newls)
3126 return retval;
3127
3128 np->duplex = newdup;
3129 np->linkspeed = newls;
3130
3131 /* The transmitter and receiver must be restarted for safe update */
3132 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3133 txrxFlags |= NV_RESTART_TX;
3134 nv_stop_tx(dev);
3135 }
3136 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3137 txrxFlags |= NV_RESTART_RX;
3138 nv_stop_rx(dev);
3139 }
3140
3141 if (np->gigabit == PHY_GIGABIT) {
3142 phyreg = readl(base + NvRegSlotTime);
3143 phyreg &= ~(0x3FF00);
3144 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3145 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3146 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3147 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3148 phyreg |= NVREG_SLOTTIME_1000_FULL;
3149 writel(phyreg, base + NvRegSlotTime);
3150 }
3151
3152 phyreg = readl(base + NvRegPhyInterface);
3153 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3154 if (np->duplex == 0)
3155 phyreg |= PHY_HALF;
3156 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3157 phyreg |= PHY_100;
3158 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3159 phyreg |= PHY_1000;
3160 writel(phyreg, base + NvRegPhyInterface);
3161
3162 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3163 if (phyreg & PHY_RGMII) {
3164 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3165 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3166 } else {
3167 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3168 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3169 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3170 else
3171 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3172 } else {
3173 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3174 }
3175 }
3176 } else {
3177 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3178 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3179 else
3180 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3181 }
3182 writel(txreg, base + NvRegTxDeferral);
3183
3184 if (np->desc_ver == DESC_VER_1) {
3185 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3186 } else {
3187 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3188 txreg = NVREG_TX_WM_DESC2_3_1000;
3189 else
3190 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3191 }
3192 writel(txreg, base + NvRegTxWatermark);
3193
3194 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3195 base + NvRegMisc1);
3196 pci_push(base);
3197 writel(np->linkspeed, base + NvRegLinkSpeed);
3198 pci_push(base);
3199
3200 pause_flags = 0;
3201 /* setup pause frame */
3202 if (np->duplex != 0) {
3203 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3204 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3205 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3206
3207 switch (adv_pause) {
3208 case ADVERTISE_PAUSE_CAP:
3209 if (lpa_pause & LPA_PAUSE_CAP) {
3210 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3211 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3212 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3213 }
3214 break;
3215 case ADVERTISE_PAUSE_ASYM:
3216 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3217 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3218 break;
3219 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3220 if (lpa_pause & LPA_PAUSE_CAP) {
3221 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3222 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3223 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3224 }
3225 if (lpa_pause == LPA_PAUSE_ASYM)
3226 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3227 break;
3228 }
3229 } else {
3230 pause_flags = np->pause_flags;
3231 }
3232 }
3233 nv_update_pause(dev, pause_flags);
3234
3235 if (txrxFlags & NV_RESTART_TX)
3236 nv_start_tx(dev);
3237 if (txrxFlags & NV_RESTART_RX)
3238 nv_start_rx(dev);
3239
3240 return retval;
3241 }
3242
3243 static void nv_linkchange(struct net_device *dev)
3244 {
3245 if (nv_update_linkspeed(dev)) {
3246 if (!netif_carrier_ok(dev)) {
3247 netif_carrier_on(dev);
3248 netdev_info(dev, "link up\n");
3249 nv_txrx_gate(dev, false);
3250 nv_start_rx(dev);
3251 }
3252 } else {
3253 if (netif_carrier_ok(dev)) {
3254 netif_carrier_off(dev);
3255 netdev_info(dev, "link down\n");
3256 nv_txrx_gate(dev, true);
3257 nv_stop_rx(dev);
3258 }
3259 }
3260 }
3261
3262 static void nv_link_irq(struct net_device *dev)
3263 {
3264 u8 __iomem *base = get_hwbase(dev);
3265 u32 miistat;
3266
3267 miistat = readl(base + NvRegMIIStatus);
3268 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3269
3270 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3271 nv_linkchange(dev);
3272 }
3273
3274 static void nv_msi_workaround(struct fe_priv *np)
3275 {
3276
3277 /* Need to toggle the msi irq mask within the ethernet device,
3278 * otherwise, future interrupts will not be detected.
3279 */
3280 if (np->msi_flags & NV_MSI_ENABLED) {
3281 u8 __iomem *base = np->base;
3282
3283 writel(0, base + NvRegMSIIrqMask);
3284 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3285 }
3286 }
3287
3288 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3289 {
3290 struct fe_priv *np = netdev_priv(dev);
3291
3292 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3293 if (total_work > NV_DYNAMIC_THRESHOLD) {
3294 /* transition to poll based interrupts */
3295 np->quiet_count = 0;
3296 if (np->irqmask != NVREG_IRQMASK_CPU) {
3297 np->irqmask = NVREG_IRQMASK_CPU;
3298 return 1;
3299 }
3300 } else {
3301 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3302 np->quiet_count++;
3303 } else {
3304 /* reached a period of low activity, switch
3305 to per tx/rx packet interrupts */
3306 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3307 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3308 return 1;
3309 }
3310 }
3311 }
3312 }
3313 return 0;
3314 }
3315
3316 static irqreturn_t nv_nic_irq(int foo, void *data)
3317 {
3318 struct net_device *dev = (struct net_device *) data;
3319 struct fe_priv *np = netdev_priv(dev);
3320 u8 __iomem *base = get_hwbase(dev);
3321
3322 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3323 np->events = readl(base + NvRegIrqStatus);
3324 writel(np->events, base + NvRegIrqStatus);
3325 } else {
3326 np->events = readl(base + NvRegMSIXIrqStatus);
3327 writel(np->events, base + NvRegMSIXIrqStatus);
3328 }
3329 if (!(np->events & np->irqmask))
3330 return IRQ_NONE;
3331
3332 nv_msi_workaround(np);
3333
3334 if (napi_schedule_prep(&np->napi)) {
3335 /*
3336 * Disable further irq's (msix not enabled with napi)
3337 */
3338 writel(0, base + NvRegIrqMask);
3339 __napi_schedule(&np->napi);
3340 }
3341
3342 return IRQ_HANDLED;
3343 }
3344
3345 /**
3346 * All _optimized functions are used to help increase performance
3347 * (reduce CPU and increase throughput). They use descripter version 3,
3348 * compiler directives, and reduce memory accesses.
3349 */
3350 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3351 {
3352 struct net_device *dev = (struct net_device *) data;
3353 struct fe_priv *np = netdev_priv(dev);
3354 u8 __iomem *base = get_hwbase(dev);
3355
3356 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3357 np->events = readl(base + NvRegIrqStatus);
3358 writel(np->events, base + NvRegIrqStatus);
3359 } else {
3360 np->events = readl(base + NvRegMSIXIrqStatus);
3361 writel(np->events, base + NvRegMSIXIrqStatus);
3362 }
3363 if (!(np->events & np->irqmask))
3364 return IRQ_NONE;
3365
3366 nv_msi_workaround(np);
3367
3368 if (napi_schedule_prep(&np->napi)) {
3369 /*
3370 * Disable further irq's (msix not enabled with napi)
3371 */
3372 writel(0, base + NvRegIrqMask);
3373 __napi_schedule(&np->napi);
3374 }
3375
3376 return IRQ_HANDLED;
3377 }
3378
3379 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3380 {
3381 struct net_device *dev = (struct net_device *) data;
3382 struct fe_priv *np = netdev_priv(dev);
3383 u8 __iomem *base = get_hwbase(dev);
3384 u32 events;
3385 int i;
3386 unsigned long flags;
3387
3388 for (i = 0;; i++) {
3389 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3390 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3391 if (!(events & np->irqmask))
3392 break;
3393
3394 spin_lock_irqsave(&np->lock, flags);
3395 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3396 spin_unlock_irqrestore(&np->lock, flags);
3397
3398 if (unlikely(i > max_interrupt_work)) {
3399 spin_lock_irqsave(&np->lock, flags);
3400 /* disable interrupts on the nic */
3401 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3402 pci_push(base);
3403
3404 if (!np->in_shutdown) {
3405 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3406 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3407 }
3408 spin_unlock_irqrestore(&np->lock, flags);
3409 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3410 __func__, i);
3411 break;
3412 }
3413
3414 }
3415
3416 return IRQ_RETVAL(i);
3417 }
3418
3419 static int nv_napi_poll(struct napi_struct *napi, int budget)
3420 {
3421 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3422 struct net_device *dev = np->dev;
3423 u8 __iomem *base = get_hwbase(dev);
3424 unsigned long flags;
3425 int retcode;
3426 int rx_count, tx_work = 0, rx_work = 0;
3427
3428 do {
3429 if (!nv_optimized(np)) {
3430 spin_lock_irqsave(&np->lock, flags);
3431 tx_work += nv_tx_done(dev, np->tx_ring_size);
3432 spin_unlock_irqrestore(&np->lock, flags);
3433
3434 rx_count = nv_rx_process(dev, budget - rx_work);
3435 retcode = nv_alloc_rx(dev);
3436 } else {
3437 spin_lock_irqsave(&np->lock, flags);
3438 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3439 spin_unlock_irqrestore(&np->lock, flags);
3440
3441 rx_count = nv_rx_process_optimized(dev,
3442 budget - rx_work);
3443 retcode = nv_alloc_rx_optimized(dev);
3444 }
3445 } while (retcode == 0 &&
3446 rx_count > 0 && (rx_work += rx_count) < budget);
3447
3448 if (retcode) {
3449 spin_lock_irqsave(&np->lock, flags);
3450 if (!np->in_shutdown)
3451 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3452 spin_unlock_irqrestore(&np->lock, flags);
3453 }
3454
3455 nv_change_interrupt_mode(dev, tx_work + rx_work);
3456
3457 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3458 spin_lock_irqsave(&np->lock, flags);
3459 nv_link_irq(dev);
3460 spin_unlock_irqrestore(&np->lock, flags);
3461 }
3462 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3463 spin_lock_irqsave(&np->lock, flags);
3464 nv_linkchange(dev);
3465 spin_unlock_irqrestore(&np->lock, flags);
3466 np->link_timeout = jiffies + LINK_TIMEOUT;
3467 }
3468 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3469 spin_lock_irqsave(&np->lock, flags);
3470 if (!np->in_shutdown) {
3471 np->nic_poll_irq = np->irqmask;
3472 np->recover_error = 1;
3473 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3474 }
3475 spin_unlock_irqrestore(&np->lock, flags);
3476 napi_complete(napi);
3477 return rx_work;
3478 }
3479
3480 if (rx_work < budget) {
3481 /* re-enable interrupts
3482 (msix not enabled in napi) */
3483 napi_complete(napi);
3484
3485 writel(np->irqmask, base + NvRegIrqMask);
3486 }
3487 return rx_work;
3488 }
3489
3490 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3491 {
3492 struct net_device *dev = (struct net_device *) data;
3493 struct fe_priv *np = netdev_priv(dev);
3494 u8 __iomem *base = get_hwbase(dev);
3495 u32 events;
3496 int i;
3497 unsigned long flags;
3498
3499 for (i = 0;; i++) {
3500 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3501 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3502 if (!(events & np->irqmask))
3503 break;
3504
3505 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3506 if (unlikely(nv_alloc_rx_optimized(dev))) {
3507 spin_lock_irqsave(&np->lock, flags);
3508 if (!np->in_shutdown)
3509 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3510 spin_unlock_irqrestore(&np->lock, flags);
3511 }
3512 }
3513
3514 if (unlikely(i > max_interrupt_work)) {
3515 spin_lock_irqsave(&np->lock, flags);
3516 /* disable interrupts on the nic */
3517 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3518 pci_push(base);
3519
3520 if (!np->in_shutdown) {
3521 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3522 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3523 }
3524 spin_unlock_irqrestore(&np->lock, flags);
3525 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3526 __func__, i);
3527 break;
3528 }
3529 }
3530
3531 return IRQ_RETVAL(i);
3532 }
3533
3534 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3535 {
3536 struct net_device *dev = (struct net_device *) data;
3537 struct fe_priv *np = netdev_priv(dev);
3538 u8 __iomem *base = get_hwbase(dev);
3539 u32 events;
3540 int i;
3541 unsigned long flags;
3542
3543 for (i = 0;; i++) {
3544 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3545 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3546 if (!(events & np->irqmask))
3547 break;
3548
3549 /* check tx in case we reached max loop limit in tx isr */
3550 spin_lock_irqsave(&np->lock, flags);
3551 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3552 spin_unlock_irqrestore(&np->lock, flags);
3553
3554 if (events & NVREG_IRQ_LINK) {
3555 spin_lock_irqsave(&np->lock, flags);
3556 nv_link_irq(dev);
3557 spin_unlock_irqrestore(&np->lock, flags);
3558 }
3559 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3560 spin_lock_irqsave(&np->lock, flags);
3561 nv_linkchange(dev);
3562 spin_unlock_irqrestore(&np->lock, flags);
3563 np->link_timeout = jiffies + LINK_TIMEOUT;
3564 }
3565 if (events & NVREG_IRQ_RECOVER_ERROR) {
3566 spin_lock_irq(&np->lock);
3567 /* disable interrupts on the nic */
3568 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3569 pci_push(base);
3570
3571 if (!np->in_shutdown) {
3572 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3573 np->recover_error = 1;
3574 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3575 }
3576 spin_unlock_irq(&np->lock);
3577 break;
3578 }
3579 if (unlikely(i > max_interrupt_work)) {
3580 spin_lock_irqsave(&np->lock, flags);
3581 /* disable interrupts on the nic */
3582 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3583 pci_push(base);
3584
3585 if (!np->in_shutdown) {
3586 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3587 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3588 }
3589 spin_unlock_irqrestore(&np->lock, flags);
3590 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3591 __func__, i);
3592 break;
3593 }
3594
3595 }
3596
3597 return IRQ_RETVAL(i);
3598 }
3599
3600 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3601 {
3602 struct net_device *dev = (struct net_device *) data;
3603 struct fe_priv *np = netdev_priv(dev);
3604 u8 __iomem *base = get_hwbase(dev);
3605 u32 events;
3606
3607 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3608 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3609 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3610 } else {
3611 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3612 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3613 }
3614 pci_push(base);
3615 if (!(events & NVREG_IRQ_TIMER))
3616 return IRQ_RETVAL(0);
3617
3618 nv_msi_workaround(np);
3619
3620 spin_lock(&np->lock);
3621 np->intr_test = 1;
3622 spin_unlock(&np->lock);
3623
3624 return IRQ_RETVAL(1);
3625 }
3626
3627 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3628 {
3629 u8 __iomem *base = get_hwbase(dev);
3630 int i;
3631 u32 msixmap = 0;
3632
3633 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3634 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3635 * the remaining 8 interrupts.
3636 */
3637 for (i = 0; i < 8; i++) {
3638 if ((irqmask >> i) & 0x1)
3639 msixmap |= vector << (i << 2);
3640 }
3641 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3642
3643 msixmap = 0;
3644 for (i = 0; i < 8; i++) {
3645 if ((irqmask >> (i + 8)) & 0x1)
3646 msixmap |= vector << (i << 2);
3647 }
3648 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3649 }
3650
3651 static int nv_request_irq(struct net_device *dev, int intr_test)
3652 {
3653 struct fe_priv *np = get_nvpriv(dev);
3654 u8 __iomem *base = get_hwbase(dev);
3655 int ret = 1;
3656 int i;
3657 irqreturn_t (*handler)(int foo, void *data);
3658
3659 if (intr_test) {
3660 handler = nv_nic_irq_test;
3661 } else {
3662 if (nv_optimized(np))
3663 handler = nv_nic_irq_optimized;
3664 else
3665 handler = nv_nic_irq;
3666 }
3667
3668 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3669 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3670 np->msi_x_entry[i].entry = i;
3671 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3672 if (ret == 0) {
3673 np->msi_flags |= NV_MSI_X_ENABLED;
3674 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3675 /* Request irq for rx handling */
3676 sprintf(np->name_rx, "%s-rx", dev->name);
3677 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3678 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3679 netdev_info(dev,
3680 "request_irq failed for rx %d\n",
3681 ret);
3682 pci_disable_msix(np->pci_dev);
3683 np->msi_flags &= ~NV_MSI_X_ENABLED;
3684 goto out_err;
3685 }
3686 /* Request irq for tx handling */
3687 sprintf(np->name_tx, "%s-tx", dev->name);
3688 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3689 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3690 netdev_info(dev,
3691 "request_irq failed for tx %d\n",
3692 ret);
3693 pci_disable_msix(np->pci_dev);
3694 np->msi_flags &= ~NV_MSI_X_ENABLED;
3695 goto out_free_rx;
3696 }
3697 /* Request irq for link and timer handling */
3698 sprintf(np->name_other, "%s-other", dev->name);
3699 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3700 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3701 netdev_info(dev,
3702 "request_irq failed for link %d\n",
3703 ret);
3704 pci_disable_msix(np->pci_dev);
3705 np->msi_flags &= ~NV_MSI_X_ENABLED;
3706 goto out_free_tx;
3707 }
3708 /* map interrupts to their respective vector */
3709 writel(0, base + NvRegMSIXMap0);
3710 writel(0, base + NvRegMSIXMap1);
3711 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3712 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3713 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3714 } else {
3715 /* Request irq for all interrupts */
3716 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3717 netdev_info(dev,
3718 "request_irq failed %d\n",
3719 ret);
3720 pci_disable_msix(np->pci_dev);
3721 np->msi_flags &= ~NV_MSI_X_ENABLED;
3722 goto out_err;
3723 }
3724
3725 /* map interrupts to vector 0 */
3726 writel(0, base + NvRegMSIXMap0);
3727 writel(0, base + NvRegMSIXMap1);
3728 }
3729 }
3730 }
3731 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3732 ret = pci_enable_msi(np->pci_dev);
3733 if (ret == 0) {
3734 np->msi_flags |= NV_MSI_ENABLED;
3735 dev->irq = np->pci_dev->irq;
3736 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3737 netdev_info(dev, "request_irq failed %d\n",
3738 ret);
3739 pci_disable_msi(np->pci_dev);
3740 np->msi_flags &= ~NV_MSI_ENABLED;
3741 dev->irq = np->pci_dev->irq;
3742 goto out_err;
3743 }
3744
3745 /* map interrupts to vector 0 */
3746 writel(0, base + NvRegMSIMap0);
3747 writel(0, base + NvRegMSIMap1);
3748 /* enable msi vector 0 */
3749 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3750 }
3751 }
3752 if (ret != 0) {
3753 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3754 goto out_err;
3755
3756 }
3757
3758 return 0;
3759 out_free_tx:
3760 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3761 out_free_rx:
3762 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3763 out_err:
3764 return 1;
3765 }
3766
3767 static void nv_free_irq(struct net_device *dev)
3768 {
3769 struct fe_priv *np = get_nvpriv(dev);
3770 int i;
3771
3772 if (np->msi_flags & NV_MSI_X_ENABLED) {
3773 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3774 free_irq(np->msi_x_entry[i].vector, dev);
3775 pci_disable_msix(np->pci_dev);
3776 np->msi_flags &= ~NV_MSI_X_ENABLED;
3777 } else {
3778 free_irq(np->pci_dev->irq, dev);
3779 if (np->msi_flags & NV_MSI_ENABLED) {
3780 pci_disable_msi(np->pci_dev);
3781 np->msi_flags &= ~NV_MSI_ENABLED;
3782 }
3783 }
3784 }
3785
3786 static void nv_do_nic_poll(unsigned long data)
3787 {
3788 struct net_device *dev = (struct net_device *) data;
3789 struct fe_priv *np = netdev_priv(dev);
3790 u8 __iomem *base = get_hwbase(dev);
3791 u32 mask = 0;
3792
3793 /*
3794 * First disable irq(s) and then
3795 * reenable interrupts on the nic, we have to do this before calling
3796 * nv_nic_irq because that may decide to do otherwise
3797 */
3798
3799 if (!using_multi_irqs(dev)) {
3800 if (np->msi_flags & NV_MSI_X_ENABLED)
3801 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3802 else
3803 disable_irq_lockdep(np->pci_dev->irq);
3804 mask = np->irqmask;
3805 } else {
3806 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3807 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3808 mask |= NVREG_IRQ_RX_ALL;
3809 }
3810 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3811 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3812 mask |= NVREG_IRQ_TX_ALL;
3813 }
3814 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3815 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3816 mask |= NVREG_IRQ_OTHER;
3817 }
3818 }
3819 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3820
3821 if (np->recover_error) {
3822 np->recover_error = 0;
3823 netdev_info(dev, "MAC in recoverable error state\n");
3824 if (netif_running(dev)) {
3825 netif_tx_lock_bh(dev);
3826 netif_addr_lock(dev);
3827 spin_lock(&np->lock);
3828 /* stop engines */
3829 nv_stop_rxtx(dev);
3830 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3831 nv_mac_reset(dev);
3832 nv_txrx_reset(dev);
3833 /* drain rx queue */
3834 nv_drain_rxtx(dev);
3835 /* reinit driver view of the rx queue */
3836 set_bufsize(dev);
3837 if (nv_init_ring(dev)) {
3838 if (!np->in_shutdown)
3839 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3840 }
3841 /* reinit nic view of the rx queue */
3842 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3843 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3844 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3845 base + NvRegRingSizes);
3846 pci_push(base);
3847 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3848 pci_push(base);
3849 /* clear interrupts */
3850 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3851 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3852 else
3853 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3854
3855 /* restart rx engine */
3856 nv_start_rxtx(dev);
3857 spin_unlock(&np->lock);
3858 netif_addr_unlock(dev);
3859 netif_tx_unlock_bh(dev);
3860 }
3861 }
3862
3863 writel(mask, base + NvRegIrqMask);
3864 pci_push(base);
3865
3866 if (!using_multi_irqs(dev)) {
3867 np->nic_poll_irq = 0;
3868 if (nv_optimized(np))
3869 nv_nic_irq_optimized(0, dev);
3870 else
3871 nv_nic_irq(0, dev);
3872 if (np->msi_flags & NV_MSI_X_ENABLED)
3873 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3874 else
3875 enable_irq_lockdep(np->pci_dev->irq);
3876 } else {
3877 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3878 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3879 nv_nic_irq_rx(0, dev);
3880 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3881 }
3882 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3883 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3884 nv_nic_irq_tx(0, dev);
3885 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3886 }
3887 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3888 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3889 nv_nic_irq_other(0, dev);
3890 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3891 }
3892 }
3893
3894 }
3895
3896 #ifdef CONFIG_NET_POLL_CONTROLLER
3897 static void nv_poll_controller(struct net_device *dev)
3898 {
3899 nv_do_nic_poll((unsigned long) dev);
3900 }
3901 #endif
3902
3903 static void nv_do_stats_poll(unsigned long data)
3904 {
3905 struct net_device *dev = (struct net_device *) data;
3906 struct fe_priv *np = netdev_priv(dev);
3907
3908 nv_get_hw_stats(dev);
3909
3910 if (!np->in_shutdown)
3911 mod_timer(&np->stats_poll,
3912 round_jiffies(jiffies + STATS_INTERVAL));
3913 }
3914
3915 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3916 {
3917 struct fe_priv *np = netdev_priv(dev);
3918 strcpy(info->driver, DRV_NAME);
3919 strcpy(info->version, FORCEDETH_VERSION);
3920 strcpy(info->bus_info, pci_name(np->pci_dev));
3921 }
3922
3923 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3924 {
3925 struct fe_priv *np = netdev_priv(dev);
3926 wolinfo->supported = WAKE_MAGIC;
3927
3928 spin_lock_irq(&np->lock);
3929 if (np->wolenabled)
3930 wolinfo->wolopts = WAKE_MAGIC;
3931 spin_unlock_irq(&np->lock);
3932 }
3933
3934 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3935 {
3936 struct fe_priv *np = netdev_priv(dev);
3937 u8 __iomem *base = get_hwbase(dev);
3938 u32 flags = 0;
3939
3940 if (wolinfo->wolopts == 0) {
3941 np->wolenabled = 0;
3942 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3943 np->wolenabled = 1;
3944 flags = NVREG_WAKEUPFLAGS_ENABLE;
3945 }
3946 if (netif_running(dev)) {
3947 spin_lock_irq(&np->lock);
3948 writel(flags, base + NvRegWakeUpFlags);
3949 spin_unlock_irq(&np->lock);
3950 }
3951 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
3952 return 0;
3953 }
3954
3955 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3956 {
3957 struct fe_priv *np = netdev_priv(dev);
3958 u32 speed;
3959 int adv;
3960
3961 spin_lock_irq(&np->lock);
3962 ecmd->port = PORT_MII;
3963 if (!netif_running(dev)) {
3964 /* We do not track link speed / duplex setting if the
3965 * interface is disabled. Force a link check */
3966 if (nv_update_linkspeed(dev)) {
3967 if (!netif_carrier_ok(dev))
3968 netif_carrier_on(dev);
3969 } else {
3970 if (netif_carrier_ok(dev))
3971 netif_carrier_off(dev);
3972 }
3973 }
3974
3975 if (netif_carrier_ok(dev)) {
3976 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3977 case NVREG_LINKSPEED_10:
3978 speed = SPEED_10;
3979 break;
3980 case NVREG_LINKSPEED_100:
3981 speed = SPEED_100;
3982 break;
3983 case NVREG_LINKSPEED_1000:
3984 speed = SPEED_1000;
3985 break;
3986 default:
3987 speed = -1;
3988 break;
3989 }
3990 ecmd->duplex = DUPLEX_HALF;
3991 if (np->duplex)
3992 ecmd->duplex = DUPLEX_FULL;
3993 } else {
3994 speed = -1;
3995 ecmd->duplex = -1;
3996 }
3997 ethtool_cmd_speed_set(ecmd, speed);
3998 ecmd->autoneg = np->autoneg;
3999
4000 ecmd->advertising = ADVERTISED_MII;
4001 if (np->autoneg) {
4002 ecmd->advertising |= ADVERTISED_Autoneg;
4003 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4004 if (adv & ADVERTISE_10HALF)
4005 ecmd->advertising |= ADVERTISED_10baseT_Half;
4006 if (adv & ADVERTISE_10FULL)
4007 ecmd->advertising |= ADVERTISED_10baseT_Full;
4008 if (adv & ADVERTISE_100HALF)
4009 ecmd->advertising |= ADVERTISED_100baseT_Half;
4010 if (adv & ADVERTISE_100FULL)
4011 ecmd->advertising |= ADVERTISED_100baseT_Full;
4012 if (np->gigabit == PHY_GIGABIT) {
4013 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4014 if (adv & ADVERTISE_1000FULL)
4015 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4016 }
4017 }
4018 ecmd->supported = (SUPPORTED_Autoneg |
4019 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4020 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4021 SUPPORTED_MII);
4022 if (np->gigabit == PHY_GIGABIT)
4023 ecmd->supported |= SUPPORTED_1000baseT_Full;
4024
4025 ecmd->phy_address = np->phyaddr;
4026 ecmd->transceiver = XCVR_EXTERNAL;
4027
4028 /* ignore maxtxpkt, maxrxpkt for now */
4029 spin_unlock_irq(&np->lock);
4030 return 0;
4031 }
4032
4033 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4034 {
4035 struct fe_priv *np = netdev_priv(dev);
4036 u32 speed = ethtool_cmd_speed(ecmd);
4037
4038 if (ecmd->port != PORT_MII)
4039 return -EINVAL;
4040 if (ecmd->transceiver != XCVR_EXTERNAL)
4041 return -EINVAL;
4042 if (ecmd->phy_address != np->phyaddr) {
4043 /* TODO: support switching between multiple phys. Should be
4044 * trivial, but not enabled due to lack of test hardware. */
4045 return -EINVAL;
4046 }
4047 if (ecmd->autoneg == AUTONEG_ENABLE) {
4048 u32 mask;
4049
4050 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4051 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4052 if (np->gigabit == PHY_GIGABIT)
4053 mask |= ADVERTISED_1000baseT_Full;
4054
4055 if ((ecmd->advertising & mask) == 0)
4056 return -EINVAL;
4057
4058 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4059 /* Note: autonegotiation disable, speed 1000 intentionally
4060 * forbidden - no one should need that. */
4061
4062 if (speed != SPEED_10 && speed != SPEED_100)
4063 return -EINVAL;
4064 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4065 return -EINVAL;
4066 } else {
4067 return -EINVAL;
4068 }
4069
4070 netif_carrier_off(dev);
4071 if (netif_running(dev)) {
4072 unsigned long flags;
4073
4074 nv_disable_irq(dev);
4075 netif_tx_lock_bh(dev);
4076 netif_addr_lock(dev);
4077 /* with plain spinlock lockdep complains */
4078 spin_lock_irqsave(&np->lock, flags);
4079 /* stop engines */
4080 /* FIXME:
4081 * this can take some time, and interrupts are disabled
4082 * due to spin_lock_irqsave, but let's hope no daemon
4083 * is going to change the settings very often...
4084 * Worst case:
4085 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4086 * + some minor delays, which is up to a second approximately
4087 */
4088 nv_stop_rxtx(dev);
4089 spin_unlock_irqrestore(&np->lock, flags);
4090 netif_addr_unlock(dev);
4091 netif_tx_unlock_bh(dev);
4092 }
4093
4094 if (ecmd->autoneg == AUTONEG_ENABLE) {
4095 int adv, bmcr;
4096
4097 np->autoneg = 1;
4098
4099 /* advertise only what has been requested */
4100 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4101 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4102 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4103 adv |= ADVERTISE_10HALF;
4104 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4105 adv |= ADVERTISE_10FULL;
4106 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4107 adv |= ADVERTISE_100HALF;
4108 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4109 adv |= ADVERTISE_100FULL;
4110 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4111 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4112 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4113 adv |= ADVERTISE_PAUSE_ASYM;
4114 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4115
4116 if (np->gigabit == PHY_GIGABIT) {
4117 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4118 adv &= ~ADVERTISE_1000FULL;
4119 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4120 adv |= ADVERTISE_1000FULL;
4121 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4122 }
4123
4124 if (netif_running(dev))
4125 netdev_info(dev, "link down\n");
4126 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4127 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4128 bmcr |= BMCR_ANENABLE;
4129 /* reset the phy in order for settings to stick,
4130 * and cause autoneg to start */
4131 if (phy_reset(dev, bmcr)) {
4132 netdev_info(dev, "phy reset failed\n");
4133 return -EINVAL;
4134 }
4135 } else {
4136 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4137 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4138 }
4139 } else {
4140 int adv, bmcr;
4141
4142 np->autoneg = 0;
4143
4144 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4145 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4146 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4147 adv |= ADVERTISE_10HALF;
4148 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4149 adv |= ADVERTISE_10FULL;
4150 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4151 adv |= ADVERTISE_100HALF;
4152 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4153 adv |= ADVERTISE_100FULL;
4154 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4155 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4156 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4157 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4158 }
4159 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4160 adv |= ADVERTISE_PAUSE_ASYM;
4161 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4162 }
4163 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4164 np->fixed_mode = adv;
4165
4166 if (np->gigabit == PHY_GIGABIT) {
4167 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4168 adv &= ~ADVERTISE_1000FULL;
4169 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4170 }
4171
4172 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4173 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4174 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4175 bmcr |= BMCR_FULLDPLX;
4176 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4177 bmcr |= BMCR_SPEED100;
4178 if (np->phy_oui == PHY_OUI_MARVELL) {
4179 /* reset the phy in order for forced mode settings to stick */
4180 if (phy_reset(dev, bmcr)) {
4181 netdev_info(dev, "phy reset failed\n");
4182 return -EINVAL;
4183 }
4184 } else {
4185 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4186 if (netif_running(dev)) {
4187 /* Wait a bit and then reconfigure the nic. */
4188 udelay(10);
4189 nv_linkchange(dev);
4190 }
4191 }
4192 }
4193
4194 if (netif_running(dev)) {
4195 nv_start_rxtx(dev);
4196 nv_enable_irq(dev);
4197 }
4198
4199 return 0;
4200 }
4201
4202 #define FORCEDETH_REGS_VER 1
4203
4204 static int nv_get_regs_len(struct net_device *dev)
4205 {
4206 struct fe_priv *np = netdev_priv(dev);
4207 return np->register_size;
4208 }
4209
4210 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4211 {
4212 struct fe_priv *np = netdev_priv(dev);
4213 u8 __iomem *base = get_hwbase(dev);
4214 u32 *rbuf = buf;
4215 int i;
4216
4217 regs->version = FORCEDETH_REGS_VER;
4218 spin_lock_irq(&np->lock);
4219 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4220 rbuf[i] = readl(base + i*sizeof(u32));
4221 spin_unlock_irq(&np->lock);
4222 }
4223
4224 static int nv_nway_reset(struct net_device *dev)
4225 {
4226 struct fe_priv *np = netdev_priv(dev);
4227 int ret;
4228
4229 if (np->autoneg) {
4230 int bmcr;
4231
4232 netif_carrier_off(dev);
4233 if (netif_running(dev)) {
4234 nv_disable_irq(dev);
4235 netif_tx_lock_bh(dev);
4236 netif_addr_lock(dev);
4237 spin_lock(&np->lock);
4238 /* stop engines */
4239 nv_stop_rxtx(dev);
4240 spin_unlock(&np->lock);
4241 netif_addr_unlock(dev);
4242 netif_tx_unlock_bh(dev);
4243 netdev_info(dev, "link down\n");
4244 }
4245
4246 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4247 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4248 bmcr |= BMCR_ANENABLE;
4249 /* reset the phy in order for settings to stick*/
4250 if (phy_reset(dev, bmcr)) {
4251 netdev_info(dev, "phy reset failed\n");
4252 return -EINVAL;
4253 }
4254 } else {
4255 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4256 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4257 }
4258
4259 if (netif_running(dev)) {
4260 nv_start_rxtx(dev);
4261 nv_enable_irq(dev);
4262 }
4263 ret = 0;
4264 } else {
4265 ret = -EINVAL;
4266 }
4267
4268 return ret;
4269 }
4270
4271 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4272 {
4273 struct fe_priv *np = netdev_priv(dev);
4274
4275 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4276 ring->rx_mini_max_pending = 0;
4277 ring->rx_jumbo_max_pending = 0;
4278 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4279
4280 ring->rx_pending = np->rx_ring_size;
4281 ring->rx_mini_pending = 0;
4282 ring->rx_jumbo_pending = 0;
4283 ring->tx_pending = np->tx_ring_size;
4284 }
4285
4286 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4287 {
4288 struct fe_priv *np = netdev_priv(dev);
4289 u8 __iomem *base = get_hwbase(dev);
4290 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4291 dma_addr_t ring_addr;
4292
4293 if (ring->rx_pending < RX_RING_MIN ||
4294 ring->tx_pending < TX_RING_MIN ||
4295 ring->rx_mini_pending != 0 ||
4296 ring->rx_jumbo_pending != 0 ||
4297 (np->desc_ver == DESC_VER_1 &&
4298 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4299 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4300 (np->desc_ver != DESC_VER_1 &&
4301 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4302 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4303 return -EINVAL;
4304 }
4305
4306 /* allocate new rings */
4307 if (!nv_optimized(np)) {
4308 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4309 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4310 &ring_addr);
4311 } else {
4312 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4313 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4314 &ring_addr);
4315 }
4316 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4317 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4318 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4319 /* fall back to old rings */
4320 if (!nv_optimized(np)) {
4321 if (rxtx_ring)
4322 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4323 rxtx_ring, ring_addr);
4324 } else {
4325 if (rxtx_ring)
4326 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4327 rxtx_ring, ring_addr);
4328 }
4329
4330 kfree(rx_skbuff);
4331 kfree(tx_skbuff);
4332 goto exit;
4333 }
4334
4335 if (netif_running(dev)) {
4336 nv_disable_irq(dev);
4337 nv_napi_disable(dev);
4338 netif_tx_lock_bh(dev);
4339 netif_addr_lock(dev);
4340 spin_lock(&np->lock);
4341 /* stop engines */
4342 nv_stop_rxtx(dev);
4343 nv_txrx_reset(dev);
4344 /* drain queues */
4345 nv_drain_rxtx(dev);
4346 /* delete queues */
4347 free_rings(dev);
4348 }
4349
4350 /* set new values */
4351 np->rx_ring_size = ring->rx_pending;
4352 np->tx_ring_size = ring->tx_pending;
4353
4354 if (!nv_optimized(np)) {
4355 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4356 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4357 } else {
4358 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4359 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4360 }
4361 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4362 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4363 np->ring_addr = ring_addr;
4364
4365 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4366 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4367
4368 if (netif_running(dev)) {
4369 /* reinit driver view of the queues */
4370 set_bufsize(dev);
4371 if (nv_init_ring(dev)) {
4372 if (!np->in_shutdown)
4373 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4374 }
4375
4376 /* reinit nic view of the queues */
4377 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4378 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4379 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4380 base + NvRegRingSizes);
4381 pci_push(base);
4382 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4383 pci_push(base);
4384
4385 /* restart engines */
4386 nv_start_rxtx(dev);
4387 spin_unlock(&np->lock);
4388 netif_addr_unlock(dev);
4389 netif_tx_unlock_bh(dev);
4390 nv_napi_enable(dev);
4391 nv_enable_irq(dev);
4392 }
4393 return 0;
4394 exit:
4395 return -ENOMEM;
4396 }
4397
4398 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4399 {
4400 struct fe_priv *np = netdev_priv(dev);
4401
4402 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4403 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4404 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4405 }
4406
4407 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4408 {
4409 struct fe_priv *np = netdev_priv(dev);
4410 int adv, bmcr;
4411
4412 if ((!np->autoneg && np->duplex == 0) ||
4413 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4414 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4415 return -EINVAL;
4416 }
4417 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4418 netdev_info(dev, "hardware does not support tx pause frames\n");
4419 return -EINVAL;
4420 }
4421
4422 netif_carrier_off(dev);
4423 if (netif_running(dev)) {
4424 nv_disable_irq(dev);
4425 netif_tx_lock_bh(dev);
4426 netif_addr_lock(dev);
4427 spin_lock(&np->lock);
4428 /* stop engines */
4429 nv_stop_rxtx(dev);
4430 spin_unlock(&np->lock);
4431 netif_addr_unlock(dev);
4432 netif_tx_unlock_bh(dev);
4433 }
4434
4435 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4436 if (pause->rx_pause)
4437 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4438 if (pause->tx_pause)
4439 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4440
4441 if (np->autoneg && pause->autoneg) {
4442 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4443
4444 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4445 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4446 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4447 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4448 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4449 adv |= ADVERTISE_PAUSE_ASYM;
4450 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4451
4452 if (netif_running(dev))
4453 netdev_info(dev, "link down\n");
4454 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4455 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4456 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4457 } else {
4458 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4459 if (pause->rx_pause)
4460 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4461 if (pause->tx_pause)
4462 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4463
4464 if (!netif_running(dev))
4465 nv_update_linkspeed(dev);
4466 else
4467 nv_update_pause(dev, np->pause_flags);
4468 }
4469
4470 if (netif_running(dev)) {
4471 nv_start_rxtx(dev);
4472 nv_enable_irq(dev);
4473 }
4474 return 0;
4475 }
4476
4477 static u32 nv_fix_features(struct net_device *dev, u32 features)
4478 {
4479 /* vlan is dependent on rx checksum offload */
4480 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4481 features |= NETIF_F_RXCSUM;
4482
4483 return features;
4484 }
4485
4486 static int nv_set_features(struct net_device *dev, u32 features)
4487 {
4488 struct fe_priv *np = netdev_priv(dev);
4489 u8 __iomem *base = get_hwbase(dev);
4490 u32 changed = dev->features ^ features;
4491
4492 if (changed & NETIF_F_RXCSUM) {
4493 spin_lock_irq(&np->lock);
4494
4495 if (features & NETIF_F_RXCSUM)
4496 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4497 else
4498 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4499
4500 if (netif_running(dev))
4501 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4502
4503 spin_unlock_irq(&np->lock);
4504 }
4505
4506 return 0;
4507 }
4508
4509 static int nv_get_sset_count(struct net_device *dev, int sset)
4510 {
4511 struct fe_priv *np = netdev_priv(dev);
4512
4513 switch (sset) {
4514 case ETH_SS_TEST:
4515 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4516 return NV_TEST_COUNT_EXTENDED;
4517 else
4518 return NV_TEST_COUNT_BASE;
4519 case ETH_SS_STATS:
4520 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4521 return NV_DEV_STATISTICS_V3_COUNT;
4522 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4523 return NV_DEV_STATISTICS_V2_COUNT;
4524 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4525 return NV_DEV_STATISTICS_V1_COUNT;
4526 else
4527 return 0;
4528 default:
4529 return -EOPNOTSUPP;
4530 }
4531 }
4532
4533 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4534 {
4535 struct fe_priv *np = netdev_priv(dev);
4536
4537 /* update stats */
4538 nv_do_stats_poll((unsigned long)dev);
4539
4540 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4541 }
4542
4543 static int nv_link_test(struct net_device *dev)
4544 {
4545 struct fe_priv *np = netdev_priv(dev);
4546 int mii_status;
4547
4548 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4549 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4550
4551 /* check phy link status */
4552 if (!(mii_status & BMSR_LSTATUS))
4553 return 0;
4554 else
4555 return 1;
4556 }
4557
4558 static int nv_register_test(struct net_device *dev)
4559 {
4560 u8 __iomem *base = get_hwbase(dev);
4561 int i = 0;
4562 u32 orig_read, new_read;
4563
4564 do {
4565 orig_read = readl(base + nv_registers_test[i].reg);
4566
4567 /* xor with mask to toggle bits */
4568 orig_read ^= nv_registers_test[i].mask;
4569
4570 writel(orig_read, base + nv_registers_test[i].reg);
4571
4572 new_read = readl(base + nv_registers_test[i].reg);
4573
4574 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4575 return 0;
4576
4577 /* restore original value */
4578 orig_read ^= nv_registers_test[i].mask;
4579 writel(orig_read, base + nv_registers_test[i].reg);
4580
4581 } while (nv_registers_test[++i].reg != 0);
4582
4583 return 1;
4584 }
4585
4586 static int nv_interrupt_test(struct net_device *dev)
4587 {
4588 struct fe_priv *np = netdev_priv(dev);
4589 u8 __iomem *base = get_hwbase(dev);
4590 int ret = 1;
4591 int testcnt;
4592 u32 save_msi_flags, save_poll_interval = 0;
4593
4594 if (netif_running(dev)) {
4595 /* free current irq */
4596 nv_free_irq(dev);
4597 save_poll_interval = readl(base+NvRegPollingInterval);
4598 }
4599
4600 /* flag to test interrupt handler */
4601 np->intr_test = 0;
4602
4603 /* setup test irq */
4604 save_msi_flags = np->msi_flags;
4605 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4606 np->msi_flags |= 0x001; /* setup 1 vector */
4607 if (nv_request_irq(dev, 1))
4608 return 0;
4609
4610 /* setup timer interrupt */
4611 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4612 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4613
4614 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4615
4616 /* wait for at least one interrupt */
4617 msleep(100);
4618
4619 spin_lock_irq(&np->lock);
4620
4621 /* flag should be set within ISR */
4622 testcnt = np->intr_test;
4623 if (!testcnt)
4624 ret = 2;
4625
4626 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4627 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4628 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4629 else
4630 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4631
4632 spin_unlock_irq(&np->lock);
4633
4634 nv_free_irq(dev);
4635
4636 np->msi_flags = save_msi_flags;
4637
4638 if (netif_running(dev)) {
4639 writel(save_poll_interval, base + NvRegPollingInterval);
4640 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4641 /* restore original irq */
4642 if (nv_request_irq(dev, 0))
4643 return 0;
4644 }
4645
4646 return ret;
4647 }
4648
4649 static int nv_loopback_test(struct net_device *dev)
4650 {
4651 struct fe_priv *np = netdev_priv(dev);
4652 u8 __iomem *base = get_hwbase(dev);
4653 struct sk_buff *tx_skb, *rx_skb;
4654 dma_addr_t test_dma_addr;
4655 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4656 u32 flags;
4657 int len, i, pkt_len;
4658 u8 *pkt_data;
4659 u32 filter_flags = 0;
4660 u32 misc1_flags = 0;
4661 int ret = 1;
4662
4663 if (netif_running(dev)) {
4664 nv_disable_irq(dev);
4665 filter_flags = readl(base + NvRegPacketFilterFlags);
4666 misc1_flags = readl(base + NvRegMisc1);
4667 } else {
4668 nv_txrx_reset(dev);
4669 }
4670
4671 /* reinit driver view of the rx queue */
4672 set_bufsize(dev);
4673 nv_init_ring(dev);
4674
4675 /* setup hardware for loopback */
4676 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4677 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4678
4679 /* reinit nic view of the rx queue */
4680 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4681 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4682 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4683 base + NvRegRingSizes);
4684 pci_push(base);
4685
4686 /* restart rx engine */
4687 nv_start_rxtx(dev);
4688
4689 /* setup packet for tx */
4690 pkt_len = ETH_DATA_LEN;
4691 tx_skb = dev_alloc_skb(pkt_len);
4692 if (!tx_skb) {
4693 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4694 ret = 0;
4695 goto out;
4696 }
4697 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4698 skb_tailroom(tx_skb),
4699 PCI_DMA_FROMDEVICE);
4700 pkt_data = skb_put(tx_skb, pkt_len);
4701 for (i = 0; i < pkt_len; i++)
4702 pkt_data[i] = (u8)(i & 0xff);
4703
4704 if (!nv_optimized(np)) {
4705 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4706 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4707 } else {
4708 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4709 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4710 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4711 }
4712 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4713 pci_push(get_hwbase(dev));
4714
4715 msleep(500);
4716
4717 /* check for rx of the packet */
4718 if (!nv_optimized(np)) {
4719 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4720 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4721
4722 } else {
4723 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4724 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4725 }
4726
4727 if (flags & NV_RX_AVAIL) {
4728 ret = 0;
4729 } else if (np->desc_ver == DESC_VER_1) {
4730 if (flags & NV_RX_ERROR)
4731 ret = 0;
4732 } else {
4733 if (flags & NV_RX2_ERROR)
4734 ret = 0;
4735 }
4736
4737 if (ret) {
4738 if (len != pkt_len) {
4739 ret = 0;
4740 } else {
4741 rx_skb = np->rx_skb[0].skb;
4742 for (i = 0; i < pkt_len; i++) {
4743 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4744 ret = 0;
4745 break;
4746 }
4747 }
4748 }
4749 }
4750
4751 pci_unmap_single(np->pci_dev, test_dma_addr,
4752 (skb_end_pointer(tx_skb) - tx_skb->data),
4753 PCI_DMA_TODEVICE);
4754 dev_kfree_skb_any(tx_skb);
4755 out:
4756 /* stop engines */
4757 nv_stop_rxtx(dev);
4758 nv_txrx_reset(dev);
4759 /* drain rx queue */
4760 nv_drain_rxtx(dev);
4761
4762 if (netif_running(dev)) {
4763 writel(misc1_flags, base + NvRegMisc1);
4764 writel(filter_flags, base + NvRegPacketFilterFlags);
4765 nv_enable_irq(dev);
4766 }
4767
4768 return ret;
4769 }
4770
4771 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4772 {
4773 struct fe_priv *np = netdev_priv(dev);
4774 u8 __iomem *base = get_hwbase(dev);
4775 int result;
4776 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4777
4778 if (!nv_link_test(dev)) {
4779 test->flags |= ETH_TEST_FL_FAILED;
4780 buffer[0] = 1;
4781 }
4782
4783 if (test->flags & ETH_TEST_FL_OFFLINE) {
4784 if (netif_running(dev)) {
4785 netif_stop_queue(dev);
4786 nv_napi_disable(dev);
4787 netif_tx_lock_bh(dev);
4788 netif_addr_lock(dev);
4789 spin_lock_irq(&np->lock);
4790 nv_disable_hw_interrupts(dev, np->irqmask);
4791 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4792 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4793 else
4794 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4795 /* stop engines */
4796 nv_stop_rxtx(dev);
4797 nv_txrx_reset(dev);
4798 /* drain rx queue */
4799 nv_drain_rxtx(dev);
4800 spin_unlock_irq(&np->lock);
4801 netif_addr_unlock(dev);
4802 netif_tx_unlock_bh(dev);
4803 }
4804
4805 if (!nv_register_test(dev)) {
4806 test->flags |= ETH_TEST_FL_FAILED;
4807 buffer[1] = 1;
4808 }
4809
4810 result = nv_interrupt_test(dev);
4811 if (result != 1) {
4812 test->flags |= ETH_TEST_FL_FAILED;
4813 buffer[2] = 1;
4814 }
4815 if (result == 0) {
4816 /* bail out */
4817 return;
4818 }
4819
4820 if (!nv_loopback_test(dev)) {
4821 test->flags |= ETH_TEST_FL_FAILED;
4822 buffer[3] = 1;
4823 }
4824
4825 if (netif_running(dev)) {
4826 /* reinit driver view of the rx queue */
4827 set_bufsize(dev);
4828 if (nv_init_ring(dev)) {
4829 if (!np->in_shutdown)
4830 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4831 }
4832 /* reinit nic view of the rx queue */
4833 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4834 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4835 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4836 base + NvRegRingSizes);
4837 pci_push(base);
4838 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4839 pci_push(base);
4840 /* restart rx engine */
4841 nv_start_rxtx(dev);
4842 netif_start_queue(dev);
4843 nv_napi_enable(dev);
4844 nv_enable_hw_interrupts(dev, np->irqmask);
4845 }
4846 }
4847 }
4848
4849 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4850 {
4851 switch (stringset) {
4852 case ETH_SS_STATS:
4853 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4854 break;
4855 case ETH_SS_TEST:
4856 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4857 break;
4858 }
4859 }
4860
4861 static const struct ethtool_ops ops = {
4862 .get_drvinfo = nv_get_drvinfo,
4863 .get_link = ethtool_op_get_link,
4864 .get_wol = nv_get_wol,
4865 .set_wol = nv_set_wol,
4866 .get_settings = nv_get_settings,
4867 .set_settings = nv_set_settings,
4868 .get_regs_len = nv_get_regs_len,
4869 .get_regs = nv_get_regs,
4870 .nway_reset = nv_nway_reset,
4871 .get_ringparam = nv_get_ringparam,
4872 .set_ringparam = nv_set_ringparam,
4873 .get_pauseparam = nv_get_pauseparam,
4874 .set_pauseparam = nv_set_pauseparam,
4875 .get_strings = nv_get_strings,
4876 .get_ethtool_stats = nv_get_ethtool_stats,
4877 .get_sset_count = nv_get_sset_count,
4878 .self_test = nv_self_test,
4879 };
4880
4881 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4882 {
4883 struct fe_priv *np = get_nvpriv(dev);
4884
4885 spin_lock_irq(&np->lock);
4886
4887 /* save vlan group */
4888 np->vlangrp = grp;
4889
4890 if (grp) {
4891 /* enable vlan on MAC */
4892 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4893 } else {
4894 /* disable vlan on MAC */
4895 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4896 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4897 }
4898
4899 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4900
4901 spin_unlock_irq(&np->lock);
4902 }
4903
4904 /* The mgmt unit and driver use a semaphore to access the phy during init */
4905 static int nv_mgmt_acquire_sema(struct net_device *dev)
4906 {
4907 struct fe_priv *np = netdev_priv(dev);
4908 u8 __iomem *base = get_hwbase(dev);
4909 int i;
4910 u32 tx_ctrl, mgmt_sema;
4911
4912 for (i = 0; i < 10; i++) {
4913 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4914 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4915 break;
4916 msleep(500);
4917 }
4918
4919 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4920 return 0;
4921
4922 for (i = 0; i < 2; i++) {
4923 tx_ctrl = readl(base + NvRegTransmitterControl);
4924 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4925 writel(tx_ctrl, base + NvRegTransmitterControl);
4926
4927 /* verify that semaphore was acquired */
4928 tx_ctrl = readl(base + NvRegTransmitterControl);
4929 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4930 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4931 np->mgmt_sema = 1;
4932 return 1;
4933 } else
4934 udelay(50);
4935 }
4936
4937 return 0;
4938 }
4939
4940 static void nv_mgmt_release_sema(struct net_device *dev)
4941 {
4942 struct fe_priv *np = netdev_priv(dev);
4943 u8 __iomem *base = get_hwbase(dev);
4944 u32 tx_ctrl;
4945
4946 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4947 if (np->mgmt_sema) {
4948 tx_ctrl = readl(base + NvRegTransmitterControl);
4949 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4950 writel(tx_ctrl, base + NvRegTransmitterControl);
4951 }
4952 }
4953 }
4954
4955
4956 static int nv_mgmt_get_version(struct net_device *dev)
4957 {
4958 struct fe_priv *np = netdev_priv(dev);
4959 u8 __iomem *base = get_hwbase(dev);
4960 u32 data_ready = readl(base + NvRegTransmitterControl);
4961 u32 data_ready2 = 0;
4962 unsigned long start;
4963 int ready = 0;
4964
4965 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4966 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
4967 start = jiffies;
4968 while (time_before(jiffies, start + 5*HZ)) {
4969 data_ready2 = readl(base + NvRegTransmitterControl);
4970 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
4971 ready = 1;
4972 break;
4973 }
4974 schedule_timeout_uninterruptible(1);
4975 }
4976
4977 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
4978 return 0;
4979
4980 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
4981
4982 return 1;
4983 }
4984
4985 static int nv_open(struct net_device *dev)
4986 {
4987 struct fe_priv *np = netdev_priv(dev);
4988 u8 __iomem *base = get_hwbase(dev);
4989 int ret = 1;
4990 int oom, i;
4991 u32 low;
4992
4993 /* power up phy */
4994 mii_rw(dev, np->phyaddr, MII_BMCR,
4995 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
4996
4997 nv_txrx_gate(dev, false);
4998 /* erase previous misconfiguration */
4999 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5000 nv_mac_reset(dev);
5001 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5002 writel(0, base + NvRegMulticastAddrB);
5003 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5004 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5005 writel(0, base + NvRegPacketFilterFlags);
5006
5007 writel(0, base + NvRegTransmitterControl);
5008 writel(0, base + NvRegReceiverControl);
5009
5010 writel(0, base + NvRegAdapterControl);
5011
5012 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5013 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5014
5015 /* initialize descriptor rings */
5016 set_bufsize(dev);
5017 oom = nv_init_ring(dev);
5018
5019 writel(0, base + NvRegLinkSpeed);
5020 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5021 nv_txrx_reset(dev);
5022 writel(0, base + NvRegUnknownSetupReg6);
5023
5024 np->in_shutdown = 0;
5025
5026 /* give hw rings */
5027 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5028 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5029 base + NvRegRingSizes);
5030
5031 writel(np->linkspeed, base + NvRegLinkSpeed);
5032 if (np->desc_ver == DESC_VER_1)
5033 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5034 else
5035 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5036 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5037 writel(np->vlanctl_bits, base + NvRegVlanControl);
5038 pci_push(base);
5039 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5040 if (reg_delay(dev, NvRegUnknownSetupReg5,
5041 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5042 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5043 netdev_info(dev,
5044 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5045
5046 writel(0, base + NvRegMIIMask);
5047 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5048 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5049
5050 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5051 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5052 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5053 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5054
5055 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5056
5057 get_random_bytes(&low, sizeof(low));
5058 low &= NVREG_SLOTTIME_MASK;
5059 if (np->desc_ver == DESC_VER_1) {
5060 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5061 } else {
5062 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5063 /* setup legacy backoff */
5064 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5065 } else {
5066 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5067 nv_gear_backoff_reseed(dev);
5068 }
5069 }
5070 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5071 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5072 if (poll_interval == -1) {
5073 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5074 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5075 else
5076 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5077 } else
5078 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5079 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5080 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5081 base + NvRegAdapterControl);
5082 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5083 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5084 if (np->wolenabled)
5085 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5086
5087 i = readl(base + NvRegPowerState);
5088 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5089 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5090
5091 pci_push(base);
5092 udelay(10);
5093 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5094
5095 nv_disable_hw_interrupts(dev, np->irqmask);
5096 pci_push(base);
5097 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5098 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5099 pci_push(base);
5100
5101 if (nv_request_irq(dev, 0))
5102 goto out_drain;
5103
5104 /* ask for interrupts */
5105 nv_enable_hw_interrupts(dev, np->irqmask);
5106
5107 spin_lock_irq(&np->lock);
5108 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5109 writel(0, base + NvRegMulticastAddrB);
5110 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5111 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5112 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5113 /* One manual link speed update: Interrupts are enabled, future link
5114 * speed changes cause interrupts and are handled by nv_link_irq().
5115 */
5116 {
5117 u32 miistat;
5118 miistat = readl(base + NvRegMIIStatus);
5119 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5120 }
5121 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5122 * to init hw */
5123 np->linkspeed = 0;
5124 ret = nv_update_linkspeed(dev);
5125 nv_start_rxtx(dev);
5126 netif_start_queue(dev);
5127 nv_napi_enable(dev);
5128
5129 if (ret) {
5130 netif_carrier_on(dev);
5131 } else {
5132 netdev_info(dev, "no link during initialization\n");
5133 netif_carrier_off(dev);
5134 }
5135 if (oom)
5136 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5137
5138 /* start statistics timer */
5139 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5140 mod_timer(&np->stats_poll,
5141 round_jiffies(jiffies + STATS_INTERVAL));
5142
5143 spin_unlock_irq(&np->lock);
5144
5145 return 0;
5146 out_drain:
5147 nv_drain_rxtx(dev);
5148 return ret;
5149 }
5150
5151 static int nv_close(struct net_device *dev)
5152 {
5153 struct fe_priv *np = netdev_priv(dev);
5154 u8 __iomem *base;
5155
5156 spin_lock_irq(&np->lock);
5157 np->in_shutdown = 1;
5158 spin_unlock_irq(&np->lock);
5159 nv_napi_disable(dev);
5160 synchronize_irq(np->pci_dev->irq);
5161
5162 del_timer_sync(&np->oom_kick);
5163 del_timer_sync(&np->nic_poll);
5164 del_timer_sync(&np->stats_poll);
5165
5166 netif_stop_queue(dev);
5167 spin_lock_irq(&np->lock);
5168 nv_stop_rxtx(dev);
5169 nv_txrx_reset(dev);
5170
5171 /* disable interrupts on the nic or we will lock up */
5172 base = get_hwbase(dev);
5173 nv_disable_hw_interrupts(dev, np->irqmask);
5174 pci_push(base);
5175
5176 spin_unlock_irq(&np->lock);
5177
5178 nv_free_irq(dev);
5179
5180 nv_drain_rxtx(dev);
5181
5182 if (np->wolenabled || !phy_power_down) {
5183 nv_txrx_gate(dev, false);
5184 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5185 nv_start_rx(dev);
5186 } else {
5187 /* power down phy */
5188 mii_rw(dev, np->phyaddr, MII_BMCR,
5189 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5190 nv_txrx_gate(dev, true);
5191 }
5192
5193 /* FIXME: power down nic */
5194
5195 return 0;
5196 }
5197
5198 static const struct net_device_ops nv_netdev_ops = {
5199 .ndo_open = nv_open,
5200 .ndo_stop = nv_close,
5201 .ndo_get_stats = nv_get_stats,
5202 .ndo_start_xmit = nv_start_xmit,
5203 .ndo_tx_timeout = nv_tx_timeout,
5204 .ndo_change_mtu = nv_change_mtu,
5205 .ndo_fix_features = nv_fix_features,
5206 .ndo_set_features = nv_set_features,
5207 .ndo_validate_addr = eth_validate_addr,
5208 .ndo_set_mac_address = nv_set_mac_address,
5209 .ndo_set_multicast_list = nv_set_multicast,
5210 .ndo_vlan_rx_register = nv_vlan_rx_register,
5211 #ifdef CONFIG_NET_POLL_CONTROLLER
5212 .ndo_poll_controller = nv_poll_controller,
5213 #endif
5214 };
5215
5216 static const struct net_device_ops nv_netdev_ops_optimized = {
5217 .ndo_open = nv_open,
5218 .ndo_stop = nv_close,
5219 .ndo_get_stats = nv_get_stats,
5220 .ndo_start_xmit = nv_start_xmit_optimized,
5221 .ndo_tx_timeout = nv_tx_timeout,
5222 .ndo_change_mtu = nv_change_mtu,
5223 .ndo_fix_features = nv_fix_features,
5224 .ndo_set_features = nv_set_features,
5225 .ndo_validate_addr = eth_validate_addr,
5226 .ndo_set_mac_address = nv_set_mac_address,
5227 .ndo_set_multicast_list = nv_set_multicast,
5228 .ndo_vlan_rx_register = nv_vlan_rx_register,
5229 #ifdef CONFIG_NET_POLL_CONTROLLER
5230 .ndo_poll_controller = nv_poll_controller,
5231 #endif
5232 };
5233
5234 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5235 {
5236 struct net_device *dev;
5237 struct fe_priv *np;
5238 unsigned long addr;
5239 u8 __iomem *base;
5240 int err, i;
5241 u32 powerstate, txreg;
5242 u32 phystate_orig = 0, phystate;
5243 int phyinitialized = 0;
5244 static int printed_version;
5245
5246 if (!printed_version++)
5247 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5248 FORCEDETH_VERSION);
5249
5250 dev = alloc_etherdev(sizeof(struct fe_priv));
5251 err = -ENOMEM;
5252 if (!dev)
5253 goto out;
5254
5255 np = netdev_priv(dev);
5256 np->dev = dev;
5257 np->pci_dev = pci_dev;
5258 spin_lock_init(&np->lock);
5259 SET_NETDEV_DEV(dev, &pci_dev->dev);
5260
5261 init_timer(&np->oom_kick);
5262 np->oom_kick.data = (unsigned long) dev;
5263 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5264 init_timer(&np->nic_poll);
5265 np->nic_poll.data = (unsigned long) dev;
5266 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5267 init_timer(&np->stats_poll);
5268 np->stats_poll.data = (unsigned long) dev;
5269 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5270
5271 err = pci_enable_device(pci_dev);
5272 if (err)
5273 goto out_free;
5274
5275 pci_set_master(pci_dev);
5276
5277 err = pci_request_regions(pci_dev, DRV_NAME);
5278 if (err < 0)
5279 goto out_disable;
5280
5281 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5282 np->register_size = NV_PCI_REGSZ_VER3;
5283 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5284 np->register_size = NV_PCI_REGSZ_VER2;
5285 else
5286 np->register_size = NV_PCI_REGSZ_VER1;
5287
5288 err = -EINVAL;
5289 addr = 0;
5290 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5291 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5292 pci_resource_len(pci_dev, i) >= np->register_size) {
5293 addr = pci_resource_start(pci_dev, i);
5294 break;
5295 }
5296 }
5297 if (i == DEVICE_COUNT_RESOURCE) {
5298 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5299 goto out_relreg;
5300 }
5301
5302 /* copy of driver data */
5303 np->driver_data = id->driver_data;
5304 /* copy of device id */
5305 np->device_id = id->device;
5306
5307 /* handle different descriptor versions */
5308 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5309 /* packet format 3: supports 40-bit addressing */
5310 np->desc_ver = DESC_VER_3;
5311 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5312 if (dma_64bit) {
5313 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5314 dev_info(&pci_dev->dev,
5315 "64-bit DMA failed, using 32-bit addressing\n");
5316 else
5317 dev->features |= NETIF_F_HIGHDMA;
5318 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5319 dev_info(&pci_dev->dev,
5320 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5321 }
5322 }
5323 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5324 /* packet format 2: supports jumbo frames */
5325 np->desc_ver = DESC_VER_2;
5326 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5327 } else {
5328 /* original packet format */
5329 np->desc_ver = DESC_VER_1;
5330 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5331 }
5332
5333 np->pkt_limit = NV_PKTLIMIT_1;
5334 if (id->driver_data & DEV_HAS_LARGEDESC)
5335 np->pkt_limit = NV_PKTLIMIT_2;
5336
5337 if (id->driver_data & DEV_HAS_CHECKSUM) {
5338 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5339 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5340 NETIF_F_TSO | NETIF_F_RXCSUM;
5341 dev->features |= dev->hw_features;
5342 }
5343
5344 np->vlanctl_bits = 0;
5345 if (id->driver_data & DEV_HAS_VLAN) {
5346 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5347 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5348 }
5349
5350 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5351 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5352 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5353 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5354 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5355 }
5356
5357 err = -ENOMEM;
5358 np->base = ioremap(addr, np->register_size);
5359 if (!np->base)
5360 goto out_relreg;
5361 dev->base_addr = (unsigned long)np->base;
5362
5363 dev->irq = pci_dev->irq;
5364
5365 np->rx_ring_size = RX_RING_DEFAULT;
5366 np->tx_ring_size = TX_RING_DEFAULT;
5367
5368 if (!nv_optimized(np)) {
5369 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5370 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5371 &np->ring_addr);
5372 if (!np->rx_ring.orig)
5373 goto out_unmap;
5374 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5375 } else {
5376 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5377 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5378 &np->ring_addr);
5379 if (!np->rx_ring.ex)
5380 goto out_unmap;
5381 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5382 }
5383 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5384 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5385 if (!np->rx_skb || !np->tx_skb)
5386 goto out_freering;
5387
5388 if (!nv_optimized(np))
5389 dev->netdev_ops = &nv_netdev_ops;
5390 else
5391 dev->netdev_ops = &nv_netdev_ops_optimized;
5392
5393 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5394 SET_ETHTOOL_OPS(dev, &ops);
5395 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5396
5397 pci_set_drvdata(pci_dev, dev);
5398
5399 /* read the mac address */
5400 base = get_hwbase(dev);
5401 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5402 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5403
5404 /* check the workaround bit for correct mac address order */
5405 txreg = readl(base + NvRegTransmitPoll);
5406 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5407 /* mac address is already in correct order */
5408 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5409 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5410 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5411 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5412 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5413 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5414 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5415 /* mac address is already in correct order */
5416 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5417 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5418 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5419 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5420 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5421 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5422 /*
5423 * Set orig mac address back to the reversed version.
5424 * This flag will be cleared during low power transition.
5425 * Therefore, we should always put back the reversed address.
5426 */
5427 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5428 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5429 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5430 } else {
5431 /* need to reverse mac address to correct order */
5432 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5433 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5434 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5435 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5436 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5437 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5438 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5439 dev_dbg(&pci_dev->dev,
5440 "%s: set workaround bit for reversed mac addr\n",
5441 __func__);
5442 }
5443 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5444
5445 if (!is_valid_ether_addr(dev->perm_addr)) {
5446 /*
5447 * Bad mac address. At least one bios sets the mac address
5448 * to 01:23:45:67:89:ab
5449 */
5450 dev_err(&pci_dev->dev,
5451 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5452 dev->dev_addr);
5453 random_ether_addr(dev->dev_addr);
5454 dev_err(&pci_dev->dev,
5455 "Using random MAC address: %pM\n", dev->dev_addr);
5456 }
5457
5458 /* set mac address */
5459 nv_copy_mac_to_hw(dev);
5460
5461 /* disable WOL */
5462 writel(0, base + NvRegWakeUpFlags);
5463 np->wolenabled = 0;
5464 device_set_wakeup_enable(&pci_dev->dev, false);
5465
5466 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5467
5468 /* take phy and nic out of low power mode */
5469 powerstate = readl(base + NvRegPowerState2);
5470 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5471 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5472 pci_dev->revision >= 0xA3)
5473 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5474 writel(powerstate, base + NvRegPowerState2);
5475 }
5476
5477 if (np->desc_ver == DESC_VER_1)
5478 np->tx_flags = NV_TX_VALID;
5479 else
5480 np->tx_flags = NV_TX2_VALID;
5481
5482 np->msi_flags = 0;
5483 if ((id->driver_data & DEV_HAS_MSI) && msi)
5484 np->msi_flags |= NV_MSI_CAPABLE;
5485
5486 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5487 /* msix has had reported issues when modifying irqmask
5488 as in the case of napi, therefore, disable for now
5489 */
5490 #if 0
5491 np->msi_flags |= NV_MSI_X_CAPABLE;
5492 #endif
5493 }
5494
5495 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5496 np->irqmask = NVREG_IRQMASK_CPU;
5497 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5498 np->msi_flags |= 0x0001;
5499 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5500 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5501 /* start off in throughput mode */
5502 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5503 /* remove support for msix mode */
5504 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5505 } else {
5506 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5507 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5508 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5509 np->msi_flags |= 0x0003;
5510 }
5511
5512 if (id->driver_data & DEV_NEED_TIMERIRQ)
5513 np->irqmask |= NVREG_IRQ_TIMER;
5514 if (id->driver_data & DEV_NEED_LINKTIMER) {
5515 np->need_linktimer = 1;
5516 np->link_timeout = jiffies + LINK_TIMEOUT;
5517 } else {
5518 np->need_linktimer = 0;
5519 }
5520
5521 /* Limit the number of tx's outstanding for hw bug */
5522 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5523 np->tx_limit = 1;
5524 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5525 pci_dev->revision >= 0xA2)
5526 np->tx_limit = 0;
5527 }
5528
5529 /* clear phy state and temporarily halt phy interrupts */
5530 writel(0, base + NvRegMIIMask);
5531 phystate = readl(base + NvRegAdapterControl);
5532 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5533 phystate_orig = 1;
5534 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5535 writel(phystate, base + NvRegAdapterControl);
5536 }
5537 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5538
5539 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5540 /* management unit running on the mac? */
5541 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5542 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5543 nv_mgmt_acquire_sema(dev) &&
5544 nv_mgmt_get_version(dev)) {
5545 np->mac_in_use = 1;
5546 if (np->mgmt_version > 0)
5547 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5548 /* management unit setup the phy already? */
5549 if (np->mac_in_use &&
5550 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5551 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5552 /* phy is inited by mgmt unit */
5553 phyinitialized = 1;
5554 } else {
5555 /* we need to init the phy */
5556 }
5557 }
5558 }
5559
5560 /* find a suitable phy */
5561 for (i = 1; i <= 32; i++) {
5562 int id1, id2;
5563 int phyaddr = i & 0x1F;
5564
5565 spin_lock_irq(&np->lock);
5566 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5567 spin_unlock_irq(&np->lock);
5568 if (id1 < 0 || id1 == 0xffff)
5569 continue;
5570 spin_lock_irq(&np->lock);
5571 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5572 spin_unlock_irq(&np->lock);
5573 if (id2 < 0 || id2 == 0xffff)
5574 continue;
5575
5576 np->phy_model = id2 & PHYID2_MODEL_MASK;
5577 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5578 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5579 np->phyaddr = phyaddr;
5580 np->phy_oui = id1 | id2;
5581
5582 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5583 if (np->phy_oui == PHY_OUI_REALTEK2)
5584 np->phy_oui = PHY_OUI_REALTEK;
5585 /* Setup phy revision for Realtek */
5586 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5587 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5588
5589 break;
5590 }
5591 if (i == 33) {
5592 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5593 goto out_error;
5594 }
5595
5596 if (!phyinitialized) {
5597 /* reset it */
5598 phy_init(dev);
5599 } else {
5600 /* see if it is a gigabit phy */
5601 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5602 if (mii_status & PHY_GIGABIT)
5603 np->gigabit = PHY_GIGABIT;
5604 }
5605
5606 /* set default link speed settings */
5607 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5608 np->duplex = 0;
5609 np->autoneg = 1;
5610
5611 err = register_netdev(dev);
5612 if (err) {
5613 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5614 goto out_error;
5615 }
5616
5617 netif_carrier_off(dev);
5618
5619 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5620 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5621
5622 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5623 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5624 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5625 "csum " : "",
5626 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5627 "vlan " : "",
5628 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5629 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5630 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5631 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5632 np->need_linktimer ? "lnktim " : "",
5633 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5634 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5635 np->desc_ver);
5636
5637 return 0;
5638
5639 out_error:
5640 if (phystate_orig)
5641 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5642 pci_set_drvdata(pci_dev, NULL);
5643 out_freering:
5644 free_rings(dev);
5645 out_unmap:
5646 iounmap(get_hwbase(dev));
5647 out_relreg:
5648 pci_release_regions(pci_dev);
5649 out_disable:
5650 pci_disable_device(pci_dev);
5651 out_free:
5652 free_netdev(dev);
5653 out:
5654 return err;
5655 }
5656
5657 static void nv_restore_phy(struct net_device *dev)
5658 {
5659 struct fe_priv *np = netdev_priv(dev);
5660 u16 phy_reserved, mii_control;
5661
5662 if (np->phy_oui == PHY_OUI_REALTEK &&
5663 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5664 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5665 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5666 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5667 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5668 phy_reserved |= PHY_REALTEK_INIT8;
5669 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5670 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5671
5672 /* restart auto negotiation */
5673 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5674 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5675 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5676 }
5677 }
5678
5679 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5680 {
5681 struct net_device *dev = pci_get_drvdata(pci_dev);
5682 struct fe_priv *np = netdev_priv(dev);
5683 u8 __iomem *base = get_hwbase(dev);
5684
5685 /* special op: write back the misordered MAC address - otherwise
5686 * the next nv_probe would see a wrong address.
5687 */
5688 writel(np->orig_mac[0], base + NvRegMacAddrA);
5689 writel(np->orig_mac[1], base + NvRegMacAddrB);
5690 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5691 base + NvRegTransmitPoll);
5692 }
5693
5694 static void __devexit nv_remove(struct pci_dev *pci_dev)
5695 {
5696 struct net_device *dev = pci_get_drvdata(pci_dev);
5697
5698 unregister_netdev(dev);
5699
5700 nv_restore_mac_addr(pci_dev);
5701
5702 /* restore any phy related changes */
5703 nv_restore_phy(dev);
5704
5705 nv_mgmt_release_sema(dev);
5706
5707 /* free all structures */
5708 free_rings(dev);
5709 iounmap(get_hwbase(dev));
5710 pci_release_regions(pci_dev);
5711 pci_disable_device(pci_dev);
5712 free_netdev(dev);
5713 pci_set_drvdata(pci_dev, NULL);
5714 }
5715
5716 #ifdef CONFIG_PM_SLEEP
5717 static int nv_suspend(struct device *device)
5718 {
5719 struct pci_dev *pdev = to_pci_dev(device);
5720 struct net_device *dev = pci_get_drvdata(pdev);
5721 struct fe_priv *np = netdev_priv(dev);
5722 u8 __iomem *base = get_hwbase(dev);
5723 int i;
5724
5725 if (netif_running(dev)) {
5726 /* Gross. */
5727 nv_close(dev);
5728 }
5729 netif_device_detach(dev);
5730
5731 /* save non-pci configuration space */
5732 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5733 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5734
5735 return 0;
5736 }
5737
5738 static int nv_resume(struct device *device)
5739 {
5740 struct pci_dev *pdev = to_pci_dev(device);
5741 struct net_device *dev = pci_get_drvdata(pdev);
5742 struct fe_priv *np = netdev_priv(dev);
5743 u8 __iomem *base = get_hwbase(dev);
5744 int i, rc = 0;
5745
5746 /* restore non-pci configuration space */
5747 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5748 writel(np->saved_config_space[i], base+i*sizeof(u32));
5749
5750 if (np->driver_data & DEV_NEED_MSI_FIX)
5751 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5752
5753 /* restore phy state, including autoneg */
5754 phy_init(dev);
5755
5756 netif_device_attach(dev);
5757 if (netif_running(dev)) {
5758 rc = nv_open(dev);
5759 nv_set_multicast(dev);
5760 }
5761 return rc;
5762 }
5763
5764 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5765 #define NV_PM_OPS (&nv_pm_ops)
5766
5767 #else
5768 #define NV_PM_OPS NULL
5769 #endif /* CONFIG_PM_SLEEP */
5770
5771 #ifdef CONFIG_PM
5772 static void nv_shutdown(struct pci_dev *pdev)
5773 {
5774 struct net_device *dev = pci_get_drvdata(pdev);
5775 struct fe_priv *np = netdev_priv(dev);
5776
5777 if (netif_running(dev))
5778 nv_close(dev);
5779
5780 /*
5781 * Restore the MAC so a kernel started by kexec won't get confused.
5782 * If we really go for poweroff, we must not restore the MAC,
5783 * otherwise the MAC for WOL will be reversed at least on some boards.
5784 */
5785 if (system_state != SYSTEM_POWER_OFF)
5786 nv_restore_mac_addr(pdev);
5787
5788 pci_disable_device(pdev);
5789 /*
5790 * Apparently it is not possible to reinitialise from D3 hot,
5791 * only put the device into D3 if we really go for poweroff.
5792 */
5793 if (system_state == SYSTEM_POWER_OFF) {
5794 pci_wake_from_d3(pdev, np->wolenabled);
5795 pci_set_power_state(pdev, PCI_D3hot);
5796 }
5797 }
5798 #else
5799 #define nv_shutdown NULL
5800 #endif /* CONFIG_PM */
5801
5802 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5803 { /* nForce Ethernet Controller */
5804 PCI_DEVICE(0x10DE, 0x01C3),
5805 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5806 },
5807 { /* nForce2 Ethernet Controller */
5808 PCI_DEVICE(0x10DE, 0x0066),
5809 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5810 },
5811 { /* nForce3 Ethernet Controller */
5812 PCI_DEVICE(0x10DE, 0x00D6),
5813 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5814 },
5815 { /* nForce3 Ethernet Controller */
5816 PCI_DEVICE(0x10DE, 0x0086),
5817 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5818 },
5819 { /* nForce3 Ethernet Controller */
5820 PCI_DEVICE(0x10DE, 0x008C),
5821 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5822 },
5823 { /* nForce3 Ethernet Controller */
5824 PCI_DEVICE(0x10DE, 0x00E6),
5825 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5826 },
5827 { /* nForce3 Ethernet Controller */
5828 PCI_DEVICE(0x10DE, 0x00DF),
5829 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5830 },
5831 { /* CK804 Ethernet Controller */
5832 PCI_DEVICE(0x10DE, 0x0056),
5833 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5834 },
5835 { /* CK804 Ethernet Controller */
5836 PCI_DEVICE(0x10DE, 0x0057),
5837 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5838 },
5839 { /* MCP04 Ethernet Controller */
5840 PCI_DEVICE(0x10DE, 0x0037),
5841 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5842 },
5843 { /* MCP04 Ethernet Controller */
5844 PCI_DEVICE(0x10DE, 0x0038),
5845 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5846 },
5847 { /* MCP51 Ethernet Controller */
5848 PCI_DEVICE(0x10DE, 0x0268),
5849 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5850 },
5851 { /* MCP51 Ethernet Controller */
5852 PCI_DEVICE(0x10DE, 0x0269),
5853 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5854 },
5855 { /* MCP55 Ethernet Controller */
5856 PCI_DEVICE(0x10DE, 0x0372),
5857 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5858 },
5859 { /* MCP55 Ethernet Controller */
5860 PCI_DEVICE(0x10DE, 0x0373),
5861 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5862 },
5863 { /* MCP61 Ethernet Controller */
5864 PCI_DEVICE(0x10DE, 0x03E5),
5865 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5866 },
5867 { /* MCP61 Ethernet Controller */
5868 PCI_DEVICE(0x10DE, 0x03E6),
5869 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5870 },
5871 { /* MCP61 Ethernet Controller */
5872 PCI_DEVICE(0x10DE, 0x03EE),
5873 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5874 },
5875 { /* MCP61 Ethernet Controller */
5876 PCI_DEVICE(0x10DE, 0x03EF),
5877 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5878 },
5879 { /* MCP65 Ethernet Controller */
5880 PCI_DEVICE(0x10DE, 0x0450),
5881 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5882 },
5883 { /* MCP65 Ethernet Controller */
5884 PCI_DEVICE(0x10DE, 0x0451),
5885 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5886 },
5887 { /* MCP65 Ethernet Controller */
5888 PCI_DEVICE(0x10DE, 0x0452),
5889 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5890 },
5891 { /* MCP65 Ethernet Controller */
5892 PCI_DEVICE(0x10DE, 0x0453),
5893 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5894 },
5895 { /* MCP67 Ethernet Controller */
5896 PCI_DEVICE(0x10DE, 0x054C),
5897 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5898 },
5899 { /* MCP67 Ethernet Controller */
5900 PCI_DEVICE(0x10DE, 0x054D),
5901 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5902 },
5903 { /* MCP67 Ethernet Controller */
5904 PCI_DEVICE(0x10DE, 0x054E),
5905 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5906 },
5907 { /* MCP67 Ethernet Controller */
5908 PCI_DEVICE(0x10DE, 0x054F),
5909 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5910 },
5911 { /* MCP73 Ethernet Controller */
5912 PCI_DEVICE(0x10DE, 0x07DC),
5913 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5914 },
5915 { /* MCP73 Ethernet Controller */
5916 PCI_DEVICE(0x10DE, 0x07DD),
5917 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5918 },
5919 { /* MCP73 Ethernet Controller */
5920 PCI_DEVICE(0x10DE, 0x07DE),
5921 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5922 },
5923 { /* MCP73 Ethernet Controller */
5924 PCI_DEVICE(0x10DE, 0x07DF),
5925 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5926 },
5927 { /* MCP77 Ethernet Controller */
5928 PCI_DEVICE(0x10DE, 0x0760),
5929 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5930 },
5931 { /* MCP77 Ethernet Controller */
5932 PCI_DEVICE(0x10DE, 0x0761),
5933 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5934 },
5935 { /* MCP77 Ethernet Controller */
5936 PCI_DEVICE(0x10DE, 0x0762),
5937 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5938 },
5939 { /* MCP77 Ethernet Controller */
5940 PCI_DEVICE(0x10DE, 0x0763),
5941 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5942 },
5943 { /* MCP79 Ethernet Controller */
5944 PCI_DEVICE(0x10DE, 0x0AB0),
5945 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5946 },
5947 { /* MCP79 Ethernet Controller */
5948 PCI_DEVICE(0x10DE, 0x0AB1),
5949 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5950 },
5951 { /* MCP79 Ethernet Controller */
5952 PCI_DEVICE(0x10DE, 0x0AB2),
5953 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5954 },
5955 { /* MCP79 Ethernet Controller */
5956 PCI_DEVICE(0x10DE, 0x0AB3),
5957 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5958 },
5959 { /* MCP89 Ethernet Controller */
5960 PCI_DEVICE(0x10DE, 0x0D7D),
5961 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
5962 },
5963 {0,},
5964 };
5965
5966 static struct pci_driver driver = {
5967 .name = DRV_NAME,
5968 .id_table = pci_tbl,
5969 .probe = nv_probe,
5970 .remove = __devexit_p(nv_remove),
5971 .shutdown = nv_shutdown,
5972 .driver.pm = NV_PM_OPS,
5973 };
5974
5975 static int __init init_nic(void)
5976 {
5977 return pci_register_driver(&driver);
5978 }
5979
5980 static void __exit exit_nic(void)
5981 {
5982 pci_unregister_driver(&driver);
5983 }
5984
5985 module_param(max_interrupt_work, int, 0);
5986 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5987 module_param(optimization_mode, int, 0);
5988 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
5989 module_param(poll_interval, int, 0);
5990 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5991 module_param(msi, int, 0);
5992 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5993 module_param(msix, int, 0);
5994 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5995 module_param(dma_64bit, int, 0);
5996 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5997 module_param(phy_cross, int, 0);
5998 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
5999 module_param(phy_power_down, int, 0);
6000 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6001
6002 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6003 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6004 MODULE_LICENSE("GPL");
6005
6006 MODULE_DEVICE_TABLE(pci, pci_tbl);
6007
6008 module_init(init_nic);
6009 module_exit(exit_nic);
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