| blob | 85c49c9e5d158b39f3dc37de0a1f0f2f3851727c |
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
5 /*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #ifndef __ASM_ARCH_MXC_MX31_H__
12 #define __ASM_ARCH_MXC_MX31_H__
14 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
16 #endif
18 /*!
19 * defines the hardware clock tick rate
20 */
21 #define CLOCK_TICK_RATE 16625000
23 /*
24 * MX31 memory map:
25 *
26 * Virt Phys Size What
27 * ---------------------------------------------------------------------------
28 * F8000000 1FFC0000 16K IRAM
29 * F9000000 30000000 256M L2CC
30 * FC000000 43F00000 1M AIPS 1
31 * FC100000 50000000 1M SPBA
32 * FC200000 53F00000 1M AIPS 2
33 * FC500000 60000000 128M ROMPATCH
34 * FC400000 68000000 128M AVIC
35 * 70000000 256M IPU (MAX M2)
36 * 80000000 256M CSD0 SDRAM/DDR
37 * 90000000 256M CSD1 SDRAM/DDR
38 * A0000000 128M CS0 Flash
39 * A8000000 128M CS1 Flash
40 * B0000000 32M CS2
41 * B2000000 32M CS3
42 * F4000000 B4000000 32M CS4
43 * B6000000 32M CS5
44 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
45 * C0000000 64M PCMCIA/CF
46 */
48 #define CS0_BASE_ADDR 0xA0000000
49 #define CS1_BASE_ADDR 0xA8000000
50 #define CS2_BASE_ADDR 0xB0000000
51 #define CS3_BASE_ADDR 0xB2000000
53 #define CS4_BASE_ADDR 0xB4000000
54 #define CS4_BASE_ADDR_VIRT 0xF4000000
55 #define CS4_SIZE SZ_32M
57 #define CS5_BASE_ADDR 0xB6000000
58 #define PCMCIA_MEM_BASE_ADDR 0xBC000000
60 /*
61 * IRAM
62 */
64 #define IRAM_BASE_ADDR_VIRT 0xF8000000
65 #define IRAM_SIZE SZ_16K
67 /*
68 * L2CC
69 */
70 #define L2CC_BASE_ADDR 0x30000000
71 #define L2CC_BASE_ADDR_VIRT 0xF9000000
72 #define L2CC_SIZE SZ_1M
74 /*
75 * AIPS 1
76 */
77 #define AIPS1_BASE_ADDR 0x43F00000
78 #define AIPS1_BASE_ADDR_VIRT 0xFC000000
79 #define AIPS1_SIZE SZ_1M
81 #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
82 #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
83 #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
84 #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
85 #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
86 #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
87 #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
88 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
89 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
90 #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
91 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
92 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
93 #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
94 #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
95 #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
96 #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
97 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
98 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
99 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
100 #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
101 #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
102 #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
104 /*
105 * SPBA global module enabled #0
106 */
107 #define SPBA0_BASE_ADDR 0x50000000
108 #define SPBA0_BASE_ADDR_VIRT 0xFC100000
109 #define SPBA0_SIZE SZ_1M
111 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
112 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
113 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
114 #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
115 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
116 #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
117 #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
118 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
119 #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
120 #define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
121 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
123 /*
124 * AIPS 2
125 */
126 #define AIPS2_BASE_ADDR 0x53F00000
127 #define AIPS2_BASE_ADDR_VIRT 0xFC200000
128 #define AIPS2_SIZE SZ_1M
129 #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
130 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
131 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
132 #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
133 #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
134 #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
135 #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
136 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
137 #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
138 #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
139 #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
140 #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
141 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
142 #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
143 #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
144 #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
145 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
146 #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
147 #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
148 #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
149 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
151 /*
152 * ROMP and AVIC
153 */
154 #define ROMP_BASE_ADDR 0x60000000
155 #define ROMP_BASE_ADDR_VIRT 0xFC500000
156 #define ROMP_SIZE SZ_1M
158 #define AVIC_BASE_ADDR 0x68000000
159 #define AVIC_BASE_ADDR_VIRT 0xFC400000
160 #define AVIC_SIZE SZ_1M
162 /*
163 * NAND, SDRAM, WEIM, M3IF, EMI controllers
164 */
165 #define X_MEMC_BASE_ADDR 0xB8000000
166 #define X_MEMC_BASE_ADDR_VIRT 0xFC320000
167 #define X_MEMC_SIZE SZ_64K
169 #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
170 #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
171 #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
172 #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
173 #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
174 #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
176 /*
177 * Memory regions and CS
178 */
179 #define IPU_MEM_BASE_ADDR 0x70000000
180 #define CSD0_BASE_ADDR 0x80000000
181 #define CSD1_BASE_ADDR 0x90000000
182 #define CS0_BASE_ADDR 0xA0000000
183 #define CS1_BASE_ADDR 0xA8000000
184 #define CS2_BASE_ADDR 0xB0000000
185 #define CS3_BASE_ADDR 0xB2000000
187 #define CS4_BASE_ADDR 0xB4000000
188 #define CS4_BASE_ADDR_VIRT 0xF4000000
189 #define CS4_SIZE SZ_32M
191 #define CS5_BASE_ADDR 0xB6000000
192 #define PCMCIA_MEM_BASE_ADDR 0xBC000000
194 /*!
195 * This macro defines the physical to virtual address mapping for all the
196 * peripheral modules. It is used by passing in the physical address as x
197 * and returning the virtual address. If the physical address is not mapped,
198 * it returns 0xDEADBEEF
199 */
200 #define IO_ADDRESS(x) \
201 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
202 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
203 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
204 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
205 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
206 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
207 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
208 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
209 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
210 0xDEADBEEF)
212 /*
213 * define the address mapping macros: in physical address order
214 */
216 #define IRAM_IO_ADDRESS(x) \
217 (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
219 #define L2CC_IO_ADDRESS(x) \
220 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
222 #define AIPS1_IO_ADDRESS(x) \
223 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
225 #define SPBA0_IO_ADDRESS(x) \
226 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
228 #define AIPS2_IO_ADDRESS(x) \
229 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
231 #define ROMP_IO_ADDRESS(x) \
232 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
234 #define AVIC_IO_ADDRESS(x) \
235 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
237 #define CS4_IO_ADDRESS(x) \
238 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
240 #define X_MEMC_IO_ADDRESS(x) \
241 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
243 #define PCMCIA_IO_ADDRESS(x) \
244 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
246 /* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
247 #define PHYS_OFFSET CSD0_BASE_ADDR
249 /*
250 * Interrupt numbers
251 */
252 #define MXC_INT_PEN_ADS7843 0
253 #define MXC_INT_RESV1 1
254 #define MXC_INT_CS8900A 2
255 #define MXC_INT_I2C3 3
256 #define MXC_INT_I2C2 4
257 #define MXC_INT_MPEG4_ENCODER 5
258 #define MXC_INT_RTIC 6
259 #define MXC_INT_FIRI 7
260 #define MXC_INT_MMC_SDHC2 8
261 #define MXC_INT_MMC_SDHC1 9
262 #define MXC_INT_I2C 10
263 #define MXC_INT_SSI2 11
264 #define MXC_INT_SSI1 12
265 #define MXC_INT_CSPI2 13
266 #define MXC_INT_CSPI1 14
267 #define MXC_INT_ATA 15
268 #define MXC_INT_MBX 16
269 #define MXC_INT_CSPI3 17
270 #define MXC_INT_UART3 18
271 #define MXC_INT_IIM 19
272 #define MXC_INT_SIM2 20
273 #define MXC_INT_SIM1 21
274 #define MXC_INT_RNGA 22
275 #define MXC_INT_EVTMON 23
276 #define MXC_INT_KPP 24
277 #define MXC_INT_RTC 25
278 #define MXC_INT_PWM 26
279 #define MXC_INT_EPIT2 27
280 #define MXC_INT_EPIT1 28
281 #define MXC_INT_GPT 29
282 #define MXC_INT_RESV30 30
283 #define MXC_INT_RESV31 31
284 #define MXC_INT_UART2 32
285 #define MXC_INT_NANDFC 33
286 #define MXC_INT_SDMA 34
287 #define MXC_INT_USB1 35
288 #define MXC_INT_USB2 36
289 #define MXC_INT_USB3 37
290 #define MXC_INT_USB4 38
291 #define MXC_INT_MSHC1 39
292 #define MXC_INT_MSHC2 40
293 #define MXC_INT_IPU_ERR 41
294 #define MXC_INT_IPU_SYN 42
295 #define MXC_INT_RESV43 43
296 #define MXC_INT_RESV44 44
297 #define MXC_INT_UART1 45
298 #define MXC_INT_UART4 46
299 #define MXC_INT_UART5 47
300 #define MXC_INT_ECT 48
301 #define MXC_INT_SCC_SCM 49
302 #define MXC_INT_SCC_SMN 50
303 #define MXC_INT_GPIO2 51
304 #define MXC_INT_GPIO1 52
305 #define MXC_INT_CCM 53
306 #define MXC_INT_PCMCIA 54
307 #define MXC_INT_WDOG 55
308 #define MXC_INT_GPIO3 56
309 #define MXC_INT_RESV57 57
310 #define MXC_INT_EXT_POWER 58
311 #define MXC_INT_EXT_TEMPER 59
312 #define MXC_INT_EXT_SENSOR60 60
313 #define MXC_INT_EXT_SENSOR61 61
314 #define MXC_INT_EXT_WDOG 62
315 #define MXC_INT_EXT_TV 63
317 #define MXC_MAX_INT_LINES 64
319 #define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
321 /*!
322 * Number of GPIO port as defined in the IC Spec
323 */
324 #define GPIO_PORT_NUM 3
325 /*!
326 * Number of GPIO pins per port
327 */
328 #define GPIO_NUM_PIN 32
332 #define SYSTEM_REV_MIN CHIP_REV_1_0
333 #define SYSTEM_REV_NUM 3