2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <mach/at91sam9g45.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
35 * The peripheral clocks.
37 static struct clk pioA_clk
= {
39 .pmc_mask
= 1 << AT91SAM9G45_ID_PIOA
,
40 .type
= CLK_TYPE_PERIPHERAL
,
42 static struct clk pioB_clk
= {
44 .pmc_mask
= 1 << AT91SAM9G45_ID_PIOB
,
45 .type
= CLK_TYPE_PERIPHERAL
,
47 static struct clk pioC_clk
= {
49 .pmc_mask
= 1 << AT91SAM9G45_ID_PIOC
,
50 .type
= CLK_TYPE_PERIPHERAL
,
52 static struct clk pioDE_clk
= {
54 .pmc_mask
= 1 << AT91SAM9G45_ID_PIODE
,
55 .type
= CLK_TYPE_PERIPHERAL
,
57 static struct clk usart0_clk
= {
59 .pmc_mask
= 1 << AT91SAM9G45_ID_US0
,
60 .type
= CLK_TYPE_PERIPHERAL
,
62 static struct clk usart1_clk
= {
64 .pmc_mask
= 1 << AT91SAM9G45_ID_US1
,
65 .type
= CLK_TYPE_PERIPHERAL
,
67 static struct clk usart2_clk
= {
69 .pmc_mask
= 1 << AT91SAM9G45_ID_US2
,
70 .type
= CLK_TYPE_PERIPHERAL
,
72 static struct clk usart3_clk
= {
74 .pmc_mask
= 1 << AT91SAM9G45_ID_US3
,
75 .type
= CLK_TYPE_PERIPHERAL
,
77 static struct clk mmc0_clk
= {
79 .pmc_mask
= 1 << AT91SAM9G45_ID_MCI0
,
80 .type
= CLK_TYPE_PERIPHERAL
,
82 static struct clk twi0_clk
= {
84 .pmc_mask
= 1 << AT91SAM9G45_ID_TWI0
,
85 .type
= CLK_TYPE_PERIPHERAL
,
87 static struct clk twi1_clk
= {
89 .pmc_mask
= 1 << AT91SAM9G45_ID_TWI1
,
90 .type
= CLK_TYPE_PERIPHERAL
,
92 static struct clk spi0_clk
= {
94 .pmc_mask
= 1 << AT91SAM9G45_ID_SPI0
,
95 .type
= CLK_TYPE_PERIPHERAL
,
97 static struct clk spi1_clk
= {
99 .pmc_mask
= 1 << AT91SAM9G45_ID_SPI1
,
100 .type
= CLK_TYPE_PERIPHERAL
,
102 static struct clk ssc0_clk
= {
104 .pmc_mask
= 1 << AT91SAM9G45_ID_SSC0
,
105 .type
= CLK_TYPE_PERIPHERAL
,
107 static struct clk ssc1_clk
= {
109 .pmc_mask
= 1 << AT91SAM9G45_ID_SSC1
,
110 .type
= CLK_TYPE_PERIPHERAL
,
112 static struct clk tcb0_clk
= {
114 .pmc_mask
= 1 << AT91SAM9G45_ID_TCB
,
115 .type
= CLK_TYPE_PERIPHERAL
,
117 static struct clk pwm_clk
= {
119 .pmc_mask
= 1 << AT91SAM9G45_ID_PWMC
,
120 .type
= CLK_TYPE_PERIPHERAL
,
122 static struct clk tsc_clk
= {
124 .pmc_mask
= 1 << AT91SAM9G45_ID_TSC
,
125 .type
= CLK_TYPE_PERIPHERAL
,
127 static struct clk dma_clk
= {
129 .pmc_mask
= 1 << AT91SAM9G45_ID_DMA
,
130 .type
= CLK_TYPE_PERIPHERAL
,
132 static struct clk uhphs_clk
= {
134 .pmc_mask
= 1 << AT91SAM9G45_ID_UHPHS
,
135 .type
= CLK_TYPE_PERIPHERAL
,
137 static struct clk lcdc_clk
= {
139 .pmc_mask
= 1 << AT91SAM9G45_ID_LCDC
,
140 .type
= CLK_TYPE_PERIPHERAL
,
142 static struct clk ac97_clk
= {
144 .pmc_mask
= 1 << AT91SAM9G45_ID_AC97C
,
145 .type
= CLK_TYPE_PERIPHERAL
,
147 static struct clk macb_clk
= {
149 .pmc_mask
= 1 << AT91SAM9G45_ID_EMAC
,
150 .type
= CLK_TYPE_PERIPHERAL
,
152 static struct clk isi_clk
= {
154 .pmc_mask
= 1 << AT91SAM9G45_ID_ISI
,
155 .type
= CLK_TYPE_PERIPHERAL
,
157 static struct clk udphs_clk
= {
159 .pmc_mask
= 1 << AT91SAM9G45_ID_UDPHS
,
160 .type
= CLK_TYPE_PERIPHERAL
,
162 static struct clk mmc1_clk
= {
164 .pmc_mask
= 1 << AT91SAM9G45_ID_MCI1
,
165 .type
= CLK_TYPE_PERIPHERAL
,
168 /* Video decoder clock - Only for sam9m10/sam9m11 */
169 static struct clk vdec_clk
= {
171 .pmc_mask
= 1 << AT91SAM9G45_ID_VDEC
,
172 .type
= CLK_TYPE_PERIPHERAL
,
175 static struct clk
*periph_clocks
[] __initdata
= {
205 static struct clk_lookup periph_clocks_lookups
[] = {
206 /* One additional fake clock for ohci */
207 CLKDEV_CON_ID("ohci_clk", &uhphs_clk
),
208 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk
),
209 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk
),
210 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk
),
211 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk
),
212 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk
),
213 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk
),
214 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk
),
215 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk
),
216 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk
),
217 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk
),
218 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk
),
221 static struct clk_lookup usart_clocks_lookups
[] = {
222 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck
),
223 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk
),
224 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk
),
225 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk
),
226 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk
),
230 * The two programmable clocks.
231 * You must configure pin multiplexing to bring these signals out.
233 static struct clk pck0
= {
235 .pmc_mask
= AT91_PMC_PCK0
,
236 .type
= CLK_TYPE_PROGRAMMABLE
,
239 static struct clk pck1
= {
241 .pmc_mask
= AT91_PMC_PCK1
,
242 .type
= CLK_TYPE_PROGRAMMABLE
,
246 static void __init
at91sam9g45_register_clocks(void)
250 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
251 clk_register(periph_clocks
[i
]);
253 clkdev_add_table(periph_clocks_lookups
,
254 ARRAY_SIZE(periph_clocks_lookups
));
255 clkdev_add_table(usart_clocks_lookups
,
256 ARRAY_SIZE(usart_clocks_lookups
));
258 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
259 clk_register(&vdec_clk
);
265 static struct clk_lookup console_clock_lookup
;
267 void __init
at91sam9g45_set_console_clock(int id
)
269 if (id
>= ARRAY_SIZE(usart_clocks_lookups
))
272 console_clock_lookup
.con_id
= "usart";
273 console_clock_lookup
.clk
= usart_clocks_lookups
[id
].clk
;
274 clkdev_add(&console_clock_lookup
);
277 /* --------------------------------------------------------------------
279 * -------------------------------------------------------------------- */
281 static struct at91_gpio_bank at91sam9g45_gpio
[] = {
283 .id
= AT91SAM9G45_ID_PIOA
,
287 .id
= AT91SAM9G45_ID_PIOB
,
291 .id
= AT91SAM9G45_ID_PIOC
,
295 .id
= AT91SAM9G45_ID_PIODE
,
299 .id
= AT91SAM9G45_ID_PIODE
,
305 static void at91sam9g45_reset(void)
307 at91_sys_write(AT91_RSTC_CR
, AT91_RSTC_KEY
| AT91_RSTC_PROCRST
| AT91_RSTC_PERRST
);
310 static void at91sam9g45_poweroff(void)
312 at91_sys_write(AT91_SHDW_CR
, AT91_SHDW_KEY
| AT91_SHDW_SHDW
);
316 /* --------------------------------------------------------------------
317 * AT91SAM9G45 processor initialization
318 * -------------------------------------------------------------------- */
320 static void __init
at91sam9g45_map_io(void)
322 at91_init_sram(0, AT91SAM9G45_SRAM_BASE
, AT91SAM9G45_SRAM_SIZE
);
323 init_consistent_dma_size(SZ_4M
);
326 static void __init
at91sam9g45_initialize(void)
328 at91_arch_reset
= at91sam9g45_reset
;
329 pm_power_off
= at91sam9g45_poweroff
;
330 at91_extern_irq
= (1 << AT91SAM9G45_ID_IRQ0
);
332 /* Register GPIO subsystem */
333 at91_gpio_init(at91sam9g45_gpio
, 5);
336 /* --------------------------------------------------------------------
337 * Interrupt initialization
338 * -------------------------------------------------------------------- */
341 * The default interrupt priority levels (0 = lowest, 7 = highest).
343 static unsigned int at91sam9g45_default_irq_priority
[NR_AIC_IRQS
] __initdata
= {
344 7, /* Advanced Interrupt Controller (FIQ) */
345 7, /* System Peripherals */
346 1, /* Parallel IO Controller A */
347 1, /* Parallel IO Controller B */
348 1, /* Parallel IO Controller C */
349 1, /* Parallel IO Controller D and E */
355 0, /* Multimedia Card Interface 0 */
356 6, /* Two-Wire Interface 0 */
357 6, /* Two-Wire Interface 1 */
358 5, /* Serial Peripheral Interface 0 */
359 5, /* Serial Peripheral Interface 1 */
360 4, /* Serial Synchronous Controller 0 */
361 4, /* Serial Synchronous Controller 1 */
362 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
363 0, /* Pulse Width Modulation Controller */
364 0, /* Touch Screen Controller */
365 0, /* DMA Controller */
366 2, /* USB Host High Speed port */
367 3, /* LDC Controller */
368 5, /* AC97 Controller */
370 0, /* Image Sensor Interface */
371 2, /* USB Device High speed port */
373 0, /* Multimedia Card Interface 1 */
375 0, /* Advanced Interrupt Controller (IRQ0) */
378 struct at91_init_soc __initdata at91sam9g45_soc
= {
379 .map_io
= at91sam9g45_map_io
,
380 .default_irq_priority
= at91sam9g45_default_irq_priority
,
381 .register_clocks
= at91sam9g45_register_clocks
,
382 .init
= at91sam9g45_initialize
,