arch/arm/mach-at91/include/mach/cpu.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/cpu.h
   3  *
   4  * Copyright (C) 2006 SAN People
   5  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13
  14 #ifndef __MACH_CPU_H__
  15 #define __MACH_CPU_H__
  16
  17 #define ARCH_ID_AT91RM9200      0x09290780
  18 #define ARCH_ID_AT91SAM9260     0x019803a0
  19 #define ARCH_ID_AT91SAM9261     0x019703a0
  20 #define ARCH_ID_AT91SAM9263     0x019607a0
  21 #define ARCH_ID_AT91SAM9G10     0x019903a0
  22 #define ARCH_ID_AT91SAM9G20     0x019905a0
  23 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
  24 #define ARCH_ID_AT91SAM9G45     0x819b05a0
  25 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
  26 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
  27 #define ARCH_ID_AT91SAM9X5      0x819a05a0
  28 #define ARCH_ID_AT91CAP9        0x039A03A0
  29
  30 #define ARCH_ID_AT91SAM9XE128   0x329973a0
  31 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
  32 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
  33
  34 #define ARCH_ID_AT91M40800      0x14080044
  35 #define ARCH_ID_AT91R40807      0x44080746
  36 #define ARCH_ID_AT91M40807      0x14080745
  37 #define ARCH_ID_AT91R40008      0x44000840
  38
  39 #define ARCH_EXID_AT91SAM9M11   0x00000001
  40 #define ARCH_EXID_AT91SAM9M10   0x00000002
  41 #define ARCH_EXID_AT91SAM9G46   0x00000003
  42 #define ARCH_EXID_AT91SAM9G45   0x00000004
  43
  44 #define ARCH_EXID_AT91SAM9G15   0x00000000
  45 #define ARCH_EXID_AT91SAM9G35   0x00000001
  46 #define ARCH_EXID_AT91SAM9X35   0x00000002
  47 #define ARCH_EXID_AT91SAM9G25   0x00000003
  48 #define ARCH_EXID_AT91SAM9X25   0x00000004
  49
  50 #define ARCH_FAMILY_AT91X92     0x09200000
  51 #define ARCH_FAMILY_AT91SAM9    0x01900000
  52 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
  53
  54 /* PMC revision */
  55 #define ARCH_REVISION_CAP9_B    0x399
  56 #define ARCH_REVISION_CAP9_C    0x601
  57
  58 /* RM9200 type */
  59 #define ARCH_REVISON_9200_BGA   (0 << 0)
  60 #define ARCH_REVISON_9200_PQFP  (1 << 0)
  61
  62 enum at91_soc_type {
  63         /* 920T */
  64         AT91_SOC_RM9200,
  65
  66         /* CAP */
  67         AT91_SOC_CAP9,
  68
  69         /* SAM92xx */
  70         AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
  71
  72         /* SAM9Gxx */
  73         AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
  74
  75         /* SAM9RL */
  76         AT91_SOC_SAM9RL,
  77
  78         /* SAM9X5 */
  79         AT91_SOC_SAM9X5,
  80
  81         /* Unknown type */
  82         AT91_SOC_NONE
  83 };
  84
  85 enum at91_soc_subtype {
  86         /* RM9200 */
  87         AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
  88
  89         /* CAP9 */
  90         AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
  91
  92         /* SAM9260 */
  93         AT91_SOC_SAM9XE,
  94
  95         /* SAM9G45 */
  96         AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
  97
  98         /* SAM9X5 */
  99         AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
 100         AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
 101
 102         /* Unknown subtype */
 103         AT91_SOC_SUBTYPE_NONE
 104 };
 105
 106 struct at91_socinfo {
 107         unsigned int type, subtype;
 108         unsigned int cidr, exid;
 109 };
 110
 111 extern struct at91_socinfo at91_soc_initdata;
 112 const char *at91_get_soc_type(struct at91_socinfo *c);
 113 const char *at91_get_soc_subtype(struct at91_socinfo *c);
 114
 115 static inline int at91_soc_is_detected(void)
 116 {
 117         return at91_soc_initdata.type != AT91_SOC_NONE;
 118 }
 119
 120 #ifdef CONFIG_ARCH_AT91RM9200
 121 #define cpu_is_at91rm9200()     (at91_soc_initdata.type == AT91_SOC_RM9200)
 122 #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
 123 #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
 124 #else
 125 #define cpu_is_at91rm9200()     (0)
 126 #define cpu_is_at91rm9200_bga() (0)
 127 #define cpu_is_at91rm9200_pqfp() (0)
 128 #endif
 129
 130 #ifdef CONFIG_ARCH_AT91SAM9260
 131 #define cpu_is_at91sam9xe()     (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
 132 #define cpu_is_at91sam9260()    (at91_soc_initdata.type == AT91_SOC_SAM9260)
 133 #else
 134 #define cpu_is_at91sam9xe()     (0)
 135 #define cpu_is_at91sam9260()    (0)
 136 #endif
 137
 138 #ifdef CONFIG_ARCH_AT91SAM9G20
 139 #define cpu_is_at91sam9g20()    (at91_soc_initdata.type == AT91_SOC_SAM9G20)
 140 #else
 141 #define cpu_is_at91sam9g20()    (0)
 142 #endif
 143
 144 #ifdef CONFIG_ARCH_AT91SAM9261
 145 #define cpu_is_at91sam9261()    (at91_soc_initdata.type == AT91_SOC_SAM9261)
 146 #else
 147 #define cpu_is_at91sam9261()    (0)
 148 #endif
 149
 150 #ifdef CONFIG_ARCH_AT91SAM9G10
 151 #define cpu_is_at91sam9g10()    (at91_soc_initdata.type == AT91_SOC_SAM9G10)
 152 #else
 153 #define cpu_is_at91sam9g10()    (0)
 154 #endif
 155
 156 #ifdef CONFIG_ARCH_AT91SAM9263
 157 #define cpu_is_at91sam9263()    (at91_soc_initdata.type == AT91_SOC_SAM9263)
 158 #else
 159 #define cpu_is_at91sam9263()    (0)
 160 #endif
 161
 162 #ifdef CONFIG_ARCH_AT91SAM9RL
 163 #define cpu_is_at91sam9rl()     (at91_soc_initdata.type == AT91_SOC_SAM9RL)
 164 #else
 165 #define cpu_is_at91sam9rl()     (0)
 166 #endif
 167
 168 #ifdef CONFIG_ARCH_AT91SAM9G45
 169 #define cpu_is_at91sam9g45()    (at91_soc_initdata.type == AT91_SOC_SAM9G45)
 170 #define cpu_is_at91sam9g45es()  (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
 171 #define cpu_is_at91sam9m10()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
 172 #define cpu_is_at91sam9g46()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
 173 #define cpu_is_at91sam9m11()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
 174 #else
 175 #define cpu_is_at91sam9g45()    (0)
 176 #define cpu_is_at91sam9g45es()  (0)
 177 #define cpu_is_at91sam9m10()    (0)
 178 #define cpu_is_at91sam9g46()    (0)
 179 #define cpu_is_at91sam9m11()    (0)
 180 #endif
 181
 182 #ifdef CONFIG_ARCH_AT91SAM9X5
 183 #define cpu_is_at91sam9x5()     (at91_soc_initdata.type == AT91_SOC_SAM9X5)
 184 #define cpu_is_at91sam9g15()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
 185 #define cpu_is_at91sam9g35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
 186 #define cpu_is_at91sam9x35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
 187 #define cpu_is_at91sam9g25()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
 188 #define cpu_is_at91sam9x25()    (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
 189 #else
 190 #define cpu_is_at91sam9x5()     (0)
 191 #define cpu_is_at91sam9g15()    (0)
 192 #define cpu_is_at91sam9g35()    (0)
 193 #define cpu_is_at91sam9x35()    (0)
 194 #define cpu_is_at91sam9g25()    (0)
 195 #define cpu_is_at91sam9x25()    (0)
 196 #endif
 197
 198 #ifdef CONFIG_ARCH_AT91CAP9
 199 #define cpu_is_at91cap9()       (at91_soc_initdata.type == AT91_SOC_CAP9)
 200 #define cpu_is_at91cap9_revB()  (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
 201 #define cpu_is_at91cap9_revC()  (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
 202 #else
 203 #define cpu_is_at91cap9()       (0)
 204 #define cpu_is_at91cap9_revB()  (0)
 205 #define cpu_is_at91cap9_revC()  (0)
 206 #endif
 207
 208 /*
 209  * Since this is ARM, we will never run on any AVR32 CPU. But these
 210  * definitions may reduce clutter in common drivers.
 211  */
 212 #define cpu_is_at32ap7000()     (0)
 213
 214 #endif /* __MACH_CPU_H__ */