arch/arm/mach-bcmring/mm.c

   1 /*****************************************************************************
   2 * Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <asm/page.h>
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/hardware.h>
  21 #include <mach/csp/mm_io.h>
  22
  23 #define IO_DESC(va, sz) { .virtual = va, \
  24         .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
  25         .length = sz, \
  26         .type = MT_DEVICE }
  27
  28 #define MEM_DESC(va, sz) { .virtual = va, \
  29         .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
  30         .length = sz, \
  31         .type = MT_MEMORY }
  32
  33 static struct map_desc bcmring_io_desc[] __initdata = {
  34         IO_DESC(MM_IO_BASE_NAND, SZ_64K),       /* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
  35         IO_DESC(MM_IO_BASE_UMI, SZ_64K),        /* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
  36
  37         IO_DESC(MM_IO_BASE_BROM, SZ_64K),       /* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
  38         MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),       /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
  39         IO_DESC(MM_IO_BASE_DMA0, SZ_1M),        /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
  40         IO_DESC(MM_IO_BASE_DMA1, SZ_1M),        /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
  41         IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
  42         IO_DESC(MM_IO_BASE_CLCD, SZ_1M),        /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
  43         IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
  44         IO_DESC(MM_IO_BASE_SPUM, SZ_1M),        /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
  45         IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),    /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
  46         IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),    /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
  47
  48         IO_DESC(MM_IO_BASE_VRAM, SZ_64K),       /* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
  49         IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),      /* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
  50         IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
  51                 SZ_16M),        /* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
  52 };
  53
  54 void __init bcmring_map_io(void)
  55 {
  56
  57         iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
  58         /* Maximum DMA memory allowed is 14M */
  59         init_consistent_dma_size(14 << 20);
  60 }