arch/arm/mach-exynos4/platsmp.c

   1 /* linux/arch/arm/mach-exynos4/platsmp.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   7  *
   8  *  Copyright (C) 2002 ARM Ltd.
   9  *  All Rights Reserved
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/smp.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/gic.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/unified.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/regs-clock.h>
  31 #include <mach/regs-pmu.h>
  32
  33 #include <plat/cpu.h>
  34
  35 extern void exynos4_secondary_startup(void);
  36
  37 #define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
  38                                 S5P_INFORM5 : S5P_VA_SYSRAM)
  39
  40 /*
  41  * control for which core is the next to come out of the secondary
  42  * boot "holding pen"
  43  */
  44
  45 volatile int __cpuinitdata pen_release = -1;
  46
  47 /*
  48  * Write pen_release in a way that is guaranteed to be visible to all
  49  * observers, irrespective of whether they're taking part in coherency
  50  * or not.  This is necessary for the hotplug code to work reliably.
  51  */
  52 static void write_pen_release(int val)
  53 {
  54         pen_release = val;
  55         smp_wmb();
  56         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  57         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  58 }
  59
  60 static void __iomem *scu_base_addr(void)
  61 {
  62         return (void __iomem *)(S5P_VA_SCU);
  63 }
  64
  65 static DEFINE_SPINLOCK(boot_lock);
  66
  67 static void __cpuinit exynos4_gic_secondary_init(void)
  68 {
  69         void __iomem *dist_base = S5P_VA_GIC_DIST +
  70                                  (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
  71         void __iomem *cpu_base = S5P_VA_GIC_CPU +
  72                                 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
  73         int i;
  74
  75         /*
  76          * Deal with the banked PPI and SGI interrupts - disable all
  77          * PPI interrupts, ensure all SGI interrupts are enabled.
  78          */
  79         __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
  80         __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
  81
  82         /*
  83          * Set priority on PPI and SGI interrupts
  84          */
  85         for (i = 0; i < 32; i += 4)
  86                 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
  87
  88         __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
  89         __raw_writel(1, cpu_base + GIC_CPU_CTRL);
  90 }
  91
  92 void __cpuinit platform_secondary_init(unsigned int cpu)
  93 {
  94         /*
  95          * if any interrupts are already enabled for the primary
  96          * core (e.g. timer irq), then they will not have been enabled
  97          * for us: do so
  98          */
  99         exynos4_gic_secondary_init();
 100
 101         /*
 102          * let the primary processor know we're out of the
 103          * pen, then head off into the C entry point
 104          */
 105         write_pen_release(-1);
 106
 107         /*
 108          * Synchronise with the boot thread.
 109          */
 110         spin_lock(&boot_lock);
 111         spin_unlock(&boot_lock);
 112
 113         set_cpu_online(cpu, true);
 114 }
 115
 116 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 117 {
 118         unsigned long timeout;
 119
 120         /*
 121          * Set synchronisation state between this boot processor
 122          * and the secondary one
 123          */
 124         spin_lock(&boot_lock);
 125
 126         /*
 127          * The secondary processor is waiting to be released from
 128          * the holding pen - release it, then wait for it to flag
 129          * that it has been released by resetting pen_release.
 130          *
 131          * Note that "pen_release" is the hardware CPU ID, whereas
 132          * "cpu" is Linux's internal ID.
 133          */
 134         write_pen_release(cpu);
 135
 136         if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
 137                 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
 138                              S5P_ARM_CORE1_CONFIGURATION);
 139
 140                 timeout = 10;
 141
 142                 /* wait max 10 ms until cpu1 is on */
 143                 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
 144                         & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
 145                         if (timeout-- == 0)
 146                                 break;
 147
 148                         mdelay(1);
 149                 }
 150
 151                 if (timeout == 0) {
 152                         printk(KERN_ERR "cpu1 power enable failed");
 153                         spin_unlock(&boot_lock);
 154                         return -ETIMEDOUT;
 155                 }
 156         }
 157         /*
 158          * Send the secondary CPU a soft interrupt, thereby causing
 159          * the boot monitor to read the system wide flags register,
 160          * and branch to the address found there.
 161          */
 162
 163         timeout = jiffies + (1 * HZ);
 164         while (time_before(jiffies, timeout)) {
 165                 smp_rmb();
 166
 167                 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
 168                         CPU1_BOOT_REG);
 169                 gic_raise_softirq(cpumask_of(cpu), 1);
 170
 171                 if (pen_release == -1)
 172                         break;
 173
 174                 udelay(10);
 175         }
 176
 177         /*
 178          * now the secondary core is starting up let it run its
 179          * calibrations, then wait for it to finish
 180          */
 181         spin_unlock(&boot_lock);
 182
 183         return pen_release != -1 ? -ENOSYS : 0;
 184 }
 185
 186 /*
 187  * Initialise the CPU possible map early - this describes the CPUs
 188  * which may be present or become present in the system.
 189  */
 190
 191 void __init smp_init_cpus(void)
 192 {
 193         void __iomem *scu_base = scu_base_addr();
 194         unsigned int i, ncores;
 195
 196         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 197
 198         /* sanity check */
 199         if (ncores > NR_CPUS) {
 200                 printk(KERN_WARNING
 201                        "EXYNOS4: no. of cores (%d) greater than configured "
 202                        "maximum of %d - clipping\n",
 203                        ncores, NR_CPUS);
 204                 ncores = NR_CPUS;
 205         }
 206
 207         for (i = 0; i < ncores; i++)
 208                 set_cpu_possible(i, true);
 209
 210         set_smp_cross_call(gic_raise_softirq);
 211 }
 212
 213 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 214 {
 215
 216         scu_enable(scu_base_addr());
 217
 218         /*
 219          * Write the address of secondary startup into the
 220          * system-wide flags register. The boot monitor waits
 221          * until it receives a soft interrupt, and then the
 222          * secondary CPU branches to this address.
 223          */
 224         __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
 225                         CPU1_BOOT_REG);
 226 }