arch/arm/mach-mmp/time.c

   1 /*
   2  * linux/arch/arm/mach-mmp/time.c
   3  *
   4  *   Support for clocksource and clockevents
   5  *
   6  * Copyright (C) 2008 Marvell International Ltd.
   7  * All rights reserved.
   8  *
   9  *   2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
  10  *   2008-10-08: Bin Yang <bin.yang@marvell.com>
  11  *
  12  * The timers module actually includes three timers, each timer with up to
  13  * three match comparators. Timer #0 is used here in free-running mode as
  14  * the clock source, and match comparator #1 used as clock event device.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/clockchips.h>
  25
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/sched_clock.h>
  31 #include <mach/addr-map.h>
  32 #include <mach/regs-timers.h>
  33 #include <mach/regs-apbc.h>
  34 #include <mach/irqs.h>
  35 #include <mach/cputype.h>
  36 #include <asm/mach/time.h>
  37
  38 #include "clock.h"
  39
  40 #define TIMERS_VIRT_BASE        TIMERS1_VIRT_BASE
  41
  42 #define MAX_DELTA               (0xfffffffe)
  43 #define MIN_DELTA               (16)
  44
  45 static DEFINE_CLOCK_DATA(cd);
  46
  47 /*
  48  * FIXME: the timer needs some delay to stablize the counter capture
  49  */
  50 static inline uint32_t timer_read(void)
  51 {
  52         int delay = 100;
  53
  54         __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
  55
  56         while (delay--)
  57                 cpu_relax();
  58
  59         return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
  60 }
  61
  62 unsigned long long notrace sched_clock(void)
  63 {
  64         u32 cyc = timer_read();
  65         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  66 }
  67
  68 static void notrace mmp_update_sched_clock(void)
  69 {
  70         u32 cyc = timer_read();
  71         update_sched_clock(&cd, cyc, (u32)~0);
  72 }
  73
  74 static irqreturn_t timer_interrupt(int irq, void *dev_id)
  75 {
  76         struct clock_event_device *c = dev_id;
  77
  78         /*
  79          * Clear pending interrupt status.
  80          */
  81         __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
  82
  83         /*
  84          * Disable timer 0.
  85          */
  86         __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
  87
  88         c->event_handler(c);
  89
  90         return IRQ_HANDLED;
  91 }
  92
  93 static int timer_set_next_event(unsigned long delta,
  94                                 struct clock_event_device *dev)
  95 {
  96         unsigned long flags;
  97
  98         local_irq_save(flags);
  99
 100         /*
 101          * Disable timer 0.
 102          */
 103         __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
 104
 105         /*
 106          * Clear and enable timer match 0 interrupt.
 107          */
 108         __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
 109         __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
 110
 111         /*
 112          * Setup new clockevent timer value.
 113          */
 114         __raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
 115
 116         /*
 117          * Enable timer 0.
 118          */
 119         __raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
 120
 121         local_irq_restore(flags);
 122
 123         return 0;
 124 }
 125
 126 static void timer_set_mode(enum clock_event_mode mode,
 127                            struct clock_event_device *dev)
 128 {
 129         unsigned long flags;
 130
 131         local_irq_save(flags);
 132         switch (mode) {
 133         case CLOCK_EVT_MODE_ONESHOT:
 134         case CLOCK_EVT_MODE_UNUSED:
 135         case CLOCK_EVT_MODE_SHUTDOWN:
 136                 /* disable the matching interrupt */
 137                 __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
 138                 break;
 139         case CLOCK_EVT_MODE_RESUME:
 140         case CLOCK_EVT_MODE_PERIODIC:
 141                 break;
 142         }
 143         local_irq_restore(flags);
 144 }
 145
 146 static struct clock_event_device ckevt = {
 147         .name           = "clockevent",
 148         .features       = CLOCK_EVT_FEAT_ONESHOT,
 149         .shift          = 32,
 150         .rating         = 200,
 151         .set_next_event = timer_set_next_event,
 152         .set_mode       = timer_set_mode,
 153 };
 154
 155 static cycle_t clksrc_read(struct clocksource *cs)
 156 {
 157         return timer_read();
 158 }
 159
 160 static struct clocksource cksrc = {
 161         .name           = "clocksource",
 162         .rating         = 200,
 163         .read           = clksrc_read,
 164         .mask           = CLOCKSOURCE_MASK(32),
 165         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 166 };
 167
 168 static void __init timer_config(void)
 169 {
 170         uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
 171
 172         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
 173
 174         ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
 175                 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
 176         __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
 177
 178         /* set timer 0 to periodic mode, and timer 1 to free-running mode */
 179         __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
 180
 181         __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
 182         __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
 183         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
 184
 185         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
 186         __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1));  /* clear status */
 187         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
 188
 189         /* enable timer 1 counter */
 190         __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
 191 }
 192
 193 static struct irqaction timer_irq = {
 194         .name           = "timer",
 195         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 196         .handler        = timer_interrupt,
 197         .dev_id         = &ckevt,
 198 };
 199
 200 void __init timer_init(int irq)
 201 {
 202         timer_config();
 203
 204         init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE);
 205
 206         ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
 207         ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
 208         ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
 209         ckevt.cpumask = cpumask_of(0);
 210
 211         setup_irq(irq, &timer_irq);
 212
 213         clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
 214         clockevents_register_device(&ckevt);
 215 }