3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial_8250.h>
20 #include <linux/i2c.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
24 #include <linux/interrupt.h>
26 #include <mach/eukrea-baseboards.h>
27 #include <mach/common.h>
28 #include <mach/hardware.h>
29 #include <mach/iomux-mx51.h>
31 #include <asm/setup.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/time.h>
36 #include "devices-imx51.h"
38 #define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
39 #define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
40 #define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
41 #define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
42 #define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
43 #define CPUIMX51_QUART_XTAL 14745600
44 #define CPUIMX51_QUART_REGSHIFT 17
47 #define MX51_USB_CTRL_1_OFFSET 0x10
48 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
50 #define MX51_USB_PLLDIV_12_MHZ 0x00
51 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
52 #define MX51_USB_PLL_DIV_24_MHZ 0x02
54 static struct plat_serial8250_port serial_platform_data
[] = {
56 .mapbase
= (unsigned long)(MX51_CS1_BASE_ADDR
+ 0x400000),
57 .irq
= gpio_to_irq(CPUIMX51_QUARTA_GPIO
),
58 .irqflags
= IRQF_TRIGGER_HIGH
,
59 .uartclk
= CPUIMX51_QUART_XTAL
,
60 .regshift
= CPUIMX51_QUART_REGSHIFT
,
62 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_IOREMAP
,
64 .mapbase
= (unsigned long)(MX51_CS1_BASE_ADDR
+ 0x800000),
65 .irq
= gpio_to_irq(CPUIMX51_QUARTB_GPIO
),
66 .irqflags
= IRQF_TRIGGER_HIGH
,
67 .uartclk
= CPUIMX51_QUART_XTAL
,
68 .regshift
= CPUIMX51_QUART_REGSHIFT
,
70 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_IOREMAP
,
72 .mapbase
= (unsigned long)(MX51_CS1_BASE_ADDR
+ 0x1000000),
73 .irq
= gpio_to_irq(CPUIMX51_QUARTC_GPIO
),
74 .irqflags
= IRQF_TRIGGER_HIGH
,
75 .uartclk
= CPUIMX51_QUART_XTAL
,
76 .regshift
= CPUIMX51_QUART_REGSHIFT
,
78 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_IOREMAP
,
80 .mapbase
= (unsigned long)(MX51_CS1_BASE_ADDR
+ 0x2000000),
81 .irq
= gpio_to_irq(CPUIMX51_QUARTD_GPIO
),
82 .irqflags
= IRQF_TRIGGER_HIGH
,
83 .uartclk
= CPUIMX51_QUART_XTAL
,
84 .regshift
= CPUIMX51_QUART_REGSHIFT
,
86 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_IOREMAP
,
91 static struct platform_device serial_device
= {
95 .platform_data
= serial_platform_data
,
99 static struct platform_device
*devices
[] __initdata
= {
103 static iomux_v3_cfg_t eukrea_cpuimx51_pads
[] = {
105 MX51_PAD_UART1_RXD__UART1_RXD
,
106 MX51_PAD_UART1_TXD__UART1_TXD
,
107 MX51_PAD_UART1_RTS__UART1_RTS
,
108 MX51_PAD_UART1_CTS__UART1_CTS
,
111 MX51_PAD_GPIO1_2__I2C2_SCL
,
112 MX51_PAD_GPIO1_3__I2C2_SDA
,
113 MX51_PAD_NANDF_D10__GPIO3_30
,
116 MX51_PAD_NANDF_D15__GPIO3_25
,
117 MX51_PAD_NANDF_D14__GPIO3_26
,
118 MX51_PAD_NANDF_D13__GPIO3_27
,
119 MX51_PAD_NANDF_D12__GPIO3_28
,
122 MX51_PAD_USBH1_CLK__USBH1_CLK
,
123 MX51_PAD_USBH1_DIR__USBH1_DIR
,
124 MX51_PAD_USBH1_NXT__USBH1_NXT
,
125 MX51_PAD_USBH1_DATA0__USBH1_DATA0
,
126 MX51_PAD_USBH1_DATA1__USBH1_DATA1
,
127 MX51_PAD_USBH1_DATA2__USBH1_DATA2
,
128 MX51_PAD_USBH1_DATA3__USBH1_DATA3
,
129 MX51_PAD_USBH1_DATA4__USBH1_DATA4
,
130 MX51_PAD_USBH1_DATA5__USBH1_DATA5
,
131 MX51_PAD_USBH1_DATA6__USBH1_DATA6
,
132 MX51_PAD_USBH1_DATA7__USBH1_DATA7
,
133 MX51_PAD_USBH1_STP__USBH1_STP
,
136 static const struct mxc_nand_platform_data
137 eukrea_cpuimx51_nand_board_info __initconst
= {
143 static const struct imxuart_platform_data uart_pdata __initconst
= {
144 .flags
= IMXUART_HAVE_RTSCTS
,
148 struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst
= {
152 static struct i2c_board_info eukrea_cpuimx51_i2c_devices
[] = {
154 I2C_BOARD_INFO("pcf8563", 0x51),
158 /* This function is board specific as the bit mask for the plldiv will also
159 be different for other Freescale SoCs, thus a common bitmask is not
160 possible and cannot get place in /plat-mxc/ehci.c.*/
161 static int initialize_otg_port(struct platform_device
*pdev
)
164 void __iomem
*usb_base
;
165 void __iomem
*usbother_base
;
167 usb_base
= ioremap(MX51_USB_OTG_BASE_ADDR
, SZ_4K
);
170 usbother_base
= usb_base
+ MX5_USBOTHER_REGS_OFFSET
;
172 /* Set the PHY clock to 19.2MHz */
173 v
= __raw_readl(usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
174 v
&= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK
;
175 v
|= MX51_USB_PLL_DIV_19_2_MHZ
;
176 __raw_writel(v
, usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
181 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY
);
184 static int initialize_usbh1_port(struct platform_device
*pdev
)
187 void __iomem
*usb_base
;
188 void __iomem
*usbother_base
;
190 usb_base
= ioremap(MX51_USB_OTG_BASE_ADDR
, SZ_4K
);
193 usbother_base
= usb_base
+ MX5_USBOTHER_REGS_OFFSET
;
195 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
196 v
= __raw_readl(usbother_base
+ MX51_USB_CTRL_1_OFFSET
);
197 __raw_writel(v
| MX51_USB_CTRL_UH1_EXT_CLK_EN
, usbother_base
+ MX51_USB_CTRL_1_OFFSET
);
202 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED
|
203 MXC_EHCI_ITC_NO_THRESHOLD
);
206 static const struct mxc_usbh_platform_data dr_utmi_config __initconst
= {
207 .init
= initialize_otg_port
,
208 .portsc
= MXC_EHCI_UTMI_16BIT
,
211 static const struct fsl_usb2_platform_data usb_pdata __initconst
= {
212 .operating_mode
= FSL_USB2_DR_DEVICE
,
213 .phy_mode
= FSL_USB2_PHY_UTMI_WIDE
,
216 static const struct mxc_usbh_platform_data usbh1_config __initconst
= {
217 .init
= initialize_usbh1_port
,
218 .portsc
= MXC_EHCI_MODE_ULPI
,
221 static int otg_mode_host
;
223 static int __init
eukrea_cpuimx51_otg_mode(char *options
)
225 if (!strcmp(options
, "host"))
227 else if (!strcmp(options
, "device"))
230 pr_info("otg_mode neither \"host\" nor \"device\". "
231 "Defaulting to device\n");
234 __setup("otg_mode=", eukrea_cpuimx51_otg_mode
);
237 * Board specific initialization.
239 static void __init
eukrea_cpuimx51_init(void)
243 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads
,
244 ARRAY_SIZE(eukrea_cpuimx51_pads
));
246 imx51_add_imx_uart(0, &uart_pdata
);
247 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info
);
249 gpio_request(CPUIMX51_QUARTA_GPIO
, "quarta_irq");
250 gpio_direction_input(CPUIMX51_QUARTA_GPIO
);
251 gpio_free(CPUIMX51_QUARTA_GPIO
);
252 gpio_request(CPUIMX51_QUARTB_GPIO
, "quartb_irq");
253 gpio_direction_input(CPUIMX51_QUARTB_GPIO
);
254 gpio_free(CPUIMX51_QUARTB_GPIO
);
255 gpio_request(CPUIMX51_QUARTC_GPIO
, "quartc_irq");
256 gpio_direction_input(CPUIMX51_QUARTC_GPIO
);
257 gpio_free(CPUIMX51_QUARTC_GPIO
);
258 gpio_request(CPUIMX51_QUARTD_GPIO
, "quartd_irq");
259 gpio_direction_input(CPUIMX51_QUARTD_GPIO
);
260 gpio_free(CPUIMX51_QUARTD_GPIO
);
263 platform_add_devices(devices
, ARRAY_SIZE(devices
));
265 imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data
);
266 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices
,
267 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices
));
270 imx51_add_mxc_ehci_otg(&dr_utmi_config
);
272 initialize_otg_port(NULL
);
273 imx51_add_fsl_usb2_udc(&usb_pdata
);
275 imx51_add_mxc_ehci_hs(1, &usbh1_config
);
277 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
278 eukrea_mbimx51_baseboard_init();
282 static void __init
eukrea_cpuimx51_timer_init(void)
284 mx51_clocks_init(32768, 24000000, 22579200, 0);
287 static struct sys_timer mxc_timer
= {
288 .init
= eukrea_cpuimx51_timer_init
,
291 MACHINE_START(EUKREA_CPUIMX51
, "Eukrea CPUIMX51 Module")
292 /* Maintainer: Eric Bénard <eric@eukrea.com> */
293 .atag_offset
= 0x100,
294 .map_io
= mx51_map_io
,
295 .init_early
= imx51_init_early
,
296 .init_irq
= mx51_init_irq
,
298 .init_machine
= eukrea_cpuimx51_init
,