arch/arm/mach-mx5/cpu.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * This file contains the CPU initialization code.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <mach/hardware.h>
  19 #include <asm/io.h>
  20
  21 static int mx5_cpu_rev = -1;
  22
  23 #define IIM_SREV 0x24
  24 #define MX50_HW_ADADIG_DIGPROG  0xB0
  25
  26 static int get_mx51_srev(void)
  27 {
  28         void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
  29         u32 rev = readl(iim_base + IIM_SREV) & 0xff;
  30
  31         switch (rev) {
  32         case 0x0:
  33                 return IMX_CHIP_REVISION_2_0;
  34         case 0x10:
  35                 return IMX_CHIP_REVISION_3_0;
  36         default:
  37                 return IMX_CHIP_REVISION_UNKNOWN;
  38         }
  39 }
  40
  41 /*
  42  * Returns:
  43  *      the silicon revision of the cpu
  44  *      -EINVAL - not a mx51
  45  */
  46 int mx51_revision(void)
  47 {
  48         if (!cpu_is_mx51())
  49                 return -EINVAL;
  50
  51         if (mx5_cpu_rev == -1)
  52                 mx5_cpu_rev = get_mx51_srev();
  53
  54         return mx5_cpu_rev;
  55 }
  56 EXPORT_SYMBOL(mx51_revision);
  57
  58 #ifdef CONFIG_NEON
  59
  60 /*
  61  * All versions of the silicon before Rev. 3 have broken NEON implementations.
  62  * Dependent on link order - so the assumption is that vfp_init is called
  63  * before us.
  64  */
  65 static int __init mx51_neon_fixup(void)
  66 {
  67         if (!cpu_is_mx51())
  68                 return 0;
  69
  70         if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
  71                 elf_hwcap &= ~HWCAP_NEON;
  72                 pr_info("Turning off NEON support, detected broken NEON implementation\n");
  73         }
  74         return 0;
  75 }
  76
  77 late_initcall(mx51_neon_fixup);
  78 #endif
  79
  80 static int get_mx53_srev(void)
  81 {
  82         void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
  83         u32 rev = readl(iim_base + IIM_SREV) & 0xff;
  84
  85         switch (rev) {
  86         case 0x0:
  87                 return IMX_CHIP_REVISION_1_0;
  88         case 0x2:
  89                 return IMX_CHIP_REVISION_2_0;
  90         case 0x3:
  91                 return IMX_CHIP_REVISION_2_1;
  92         default:
  93                 return IMX_CHIP_REVISION_UNKNOWN;
  94         }
  95 }
  96
  97 /*
  98  * Returns:
  99  *      the silicon revision of the cpu
 100  *      -EINVAL - not a mx53
 101  */
 102 int mx53_revision(void)
 103 {
 104         if (!cpu_is_mx53())
 105                 return -EINVAL;
 106
 107         if (mx5_cpu_rev == -1)
 108                 mx5_cpu_rev = get_mx53_srev();
 109
 110         return mx5_cpu_rev;
 111 }
 112 EXPORT_SYMBOL(mx53_revision);
 113
 114 static int get_mx50_srev(void)
 115 {
 116         void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
 117         u32 rev;
 118
 119         if (!anatop) {
 120                 mx5_cpu_rev = -EINVAL;
 121                 return 0;
 122         }
 123
 124         rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
 125         rev &= 0xff;
 126
 127         iounmap(anatop);
 128         if (rev == 0x0)
 129                 return IMX_CHIP_REVISION_1_0;
 130         else if (rev == 0x1)
 131                 return IMX_CHIP_REVISION_1_1;
 132         return 0;
 133 }
 134
 135 /*
 136  * Returns:
 137  *      the silicon revision of the cpu
 138  *      -EINVAL - not a mx50
 139  */
 140 int mx50_revision(void)
 141 {
 142         if (!cpu_is_mx50())
 143                 return -EINVAL;
 144
 145         if (mx5_cpu_rev == -1)
 146                 mx5_cpu_rev = get_mx50_srev();
 147
 148         return mx5_cpu_rev;
 149 }
 150 EXPORT_SYMBOL(mx50_revision);
 151
 152 static int __init post_cpu_init(void)
 153 {
 154         unsigned int reg;
 155         void __iomem *base;
 156
 157         if (cpu_is_mx51() || cpu_is_mx53()) {
 158                 if (cpu_is_mx51())
 159                         base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
 160                 else
 161                         base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
 162
 163                 __raw_writel(0x0, base + 0x40);
 164                 __raw_writel(0x0, base + 0x44);
 165                 __raw_writel(0x0, base + 0x48);
 166                 __raw_writel(0x0, base + 0x4C);
 167                 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
 168                 __raw_writel(reg, base + 0x50);
 169
 170                 if (cpu_is_mx51())
 171                         base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
 172                 else
 173                         base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
 174
 175                 __raw_writel(0x0, base + 0x40);
 176                 __raw_writel(0x0, base + 0x44);
 177                 __raw_writel(0x0, base + 0x48);
 178                 __raw_writel(0x0, base + 0x4C);
 179                 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
 180                 __raw_writel(reg, base + 0x50);
 181         }
 182
 183         return 0;
 184 }
 185
 186 postcore_initcall(post_cpu_init);