arch/arm/mach-omap2/clock2420_data.c

   1 /*
   2  * OMAP2420 clock data
   3  *
   4  * Copyright (C) 2005-2009 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2011 Nokia Corporation
   6  *
   7  * Contacts:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/clk.h>
  18 #include <linux/list.h>
  19
  20 #include <plat/clkdev_omap.h>
  21
  22 #include "clock.h"
  23 #include "clock2xxx.h"
  24 #include "opp2xxx.h"
  25 #include "cm2xxx_3xxx.h"
  26 #include "prm2xxx_3xxx.h"
  27 #include "prm-regbits-24xx.h"
  28 #include "cm-regbits-24xx.h"
  29 #include "sdrc.h"
  30 #include "control.h"
  31
  32 #define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
  33
  34 /*
  35  * 2420 clock tree.
  36  *
  37  * NOTE:In many cases here we are assigning a 'default' parent. In
  38  *      many cases the parent is selectable. The set parent calls will
  39  *      also switch sources.
  40  *
  41  *      Several sources are given initial rates which may be wrong, this will
  42  *      be fixed up in the init func.
  43  *
  44  *      Things are broadly separated below by clock domains. It is
  45  *      noteworthy that most peripherals have dependencies on multiple clock
  46  *      domains. Many get their interface clocks from the L4 domain, but get
  47  *      functional clocks from fixed sources or other core domain derived
  48  *      clocks.
  49  */
  50
  51 /* Base external input clocks */
  52 static struct clk func_32k_ck = {
  53         .name           = "func_32k_ck",
  54         .ops            = &clkops_null,
  55         .rate           = 32768,
  56         .clkdm_name     = "wkup_clkdm",
  57 };
  58
  59 static struct clk secure_32k_ck = {
  60         .name           = "secure_32k_ck",
  61         .ops            = &clkops_null,
  62         .rate           = 32768,
  63         .clkdm_name     = "wkup_clkdm",
  64 };
  65
  66 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
  67 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
  68         .name           = "osc_ck",
  69         .ops            = &clkops_oscck,
  70         .clkdm_name     = "wkup_clkdm",
  71         .recalc         = &omap2_osc_clk_recalc,
  72 };
  73
  74 /* Without modem likely 12MHz, with modem likely 13MHz */
  75 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
  76         .name           = "sys_ck",             /* ~ ref_clk also */
  77         .ops            = &clkops_null,
  78         .parent         = &osc_ck,
  79         .clkdm_name     = "wkup_clkdm",
  80         .recalc         = &omap2xxx_sys_clk_recalc,
  81 };
  82
  83 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
  84         .name           = "alt_ck",
  85         .ops            = &clkops_null,
  86         .rate           = 54000000,
  87         .clkdm_name     = "wkup_clkdm",
  88 };
  89
  90 /* Optional external clock input for McBSP CLKS */
  91 static struct clk mcbsp_clks = {
  92         .name           = "mcbsp_clks",
  93         .ops            = &clkops_null,
  94 };
  95
  96 /*
  97  * Analog domain root source clocks
  98  */
  99
 100 /* dpll_ck, is broken out in to special cases through clksel */
 101 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 102  * deal with this
 103  */
 104
 105 static struct dpll_data dpll_dd = {
 106         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 107         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 108         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 109         .clk_bypass             = &sys_ck,
 110         .clk_ref                = &sys_ck,
 111         .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 112         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 113         .max_multiplier         = 1023,
 114         .min_divider            = 1,
 115         .max_divider            = 16,
 116 };
 117
 118 /*
 119  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 120  * not just a DPLL
 121  */
 122 static struct clk dpll_ck = {
 123         .name           = "dpll_ck",
 124         .ops            = &clkops_omap2xxx_dpll_ops,
 125         .parent         = &sys_ck,              /* Can be func_32k also */
 126         .dpll_data      = &dpll_dd,
 127         .clkdm_name     = "wkup_clkdm",
 128         .recalc         = &omap2_dpllcore_recalc,
 129         .set_rate       = &omap2_reprogram_dpllcore,
 130 };
 131
 132 static struct clk apll96_ck = {
 133         .name           = "apll96_ck",
 134         .ops            = &clkops_apll96,
 135         .parent         = &sys_ck,
 136         .rate           = 96000000,
 137         .flags          = ENABLE_ON_INIT,
 138         .clkdm_name     = "wkup_clkdm",
 139         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 140         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 141 };
 142
 143 static struct clk apll54_ck = {
 144         .name           = "apll54_ck",
 145         .ops            = &clkops_apll54,
 146         .parent         = &sys_ck,
 147         .rate           = 54000000,
 148         .flags          = ENABLE_ON_INIT,
 149         .clkdm_name     = "wkup_clkdm",
 150         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 151         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 152 };
 153
 154 /*
 155  * PRCM digital base sources
 156  */
 157
 158 /* func_54m_ck */
 159
 160 static const struct clksel_rate func_54m_apll54_rates[] = {
 161         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 162         { .div = 0 },
 163 };
 164
 165 static const struct clksel_rate func_54m_alt_rates[] = {
 166         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 167         { .div = 0 },
 168 };
 169
 170 static const struct clksel func_54m_clksel[] = {
 171         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 172         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 173         { .parent = NULL },
 174 };
 175
 176 static struct clk func_54m_ck = {
 177         .name           = "func_54m_ck",
 178         .ops            = &clkops_null,
 179         .parent         = &apll54_ck,   /* can also be alt_clk */
 180         .clkdm_name     = "wkup_clkdm",
 181         .init           = &omap2_init_clksel_parent,
 182         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 183         .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
 184         .clksel         = func_54m_clksel,
 185         .recalc         = &omap2_clksel_recalc,
 186 };
 187
 188 static struct clk core_ck = {
 189         .name           = "core_ck",
 190         .ops            = &clkops_null,
 191         .parent         = &dpll_ck,             /* can also be 32k */
 192         .clkdm_name     = "wkup_clkdm",
 193         .recalc         = &followparent_recalc,
 194 };
 195
 196 static struct clk func_96m_ck = {
 197         .name           = "func_96m_ck",
 198         .ops            = &clkops_null,
 199         .parent         = &apll96_ck,
 200         .clkdm_name     = "wkup_clkdm",
 201         .recalc         = &followparent_recalc,
 202 };
 203
 204 /* func_48m_ck */
 205
 206 static const struct clksel_rate func_48m_apll96_rates[] = {
 207         { .div = 2, .val = 0, .flags = RATE_IN_24XX },
 208         { .div = 0 },
 209 };
 210
 211 static const struct clksel_rate func_48m_alt_rates[] = {
 212         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 213         { .div = 0 },
 214 };
 215
 216 static const struct clksel func_48m_clksel[] = {
 217         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 218         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 219         { .parent = NULL }
 220 };
 221
 222 static struct clk func_48m_ck = {
 223         .name           = "func_48m_ck",
 224         .ops            = &clkops_null,
 225         .parent         = &apll96_ck,    /* 96M or Alt */
 226         .clkdm_name     = "wkup_clkdm",
 227         .init           = &omap2_init_clksel_parent,
 228         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 229         .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
 230         .clksel         = func_48m_clksel,
 231         .recalc         = &omap2_clksel_recalc,
 232         .round_rate     = &omap2_clksel_round_rate,
 233         .set_rate       = &omap2_clksel_set_rate
 234 };
 235
 236 static struct clk func_12m_ck = {
 237         .name           = "func_12m_ck",
 238         .ops            = &clkops_null,
 239         .parent         = &func_48m_ck,
 240         .fixed_div      = 4,
 241         .clkdm_name     = "wkup_clkdm",
 242         .recalc         = &omap_fixed_divisor_recalc,
 243 };
 244
 245 /* Secure timer, only available in secure mode */
 246 static struct clk wdt1_osc_ck = {
 247         .name           = "ck_wdt1_osc",
 248         .ops            = &clkops_null, /* RMK: missing? */
 249         .parent         = &osc_ck,
 250         .recalc         = &followparent_recalc,
 251 };
 252
 253 /*
 254  * The common_clkout* clksel_rate structs are common to
 255  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 256  * sys_clkout2_* are 2420-only, so the
 257  * clksel_rate flags fields are inaccurate for those clocks. This is
 258  * harmless since access to those clocks are gated by the struct clk
 259  * flags fields, which mark them as 2420-only.
 260  */
 261 static const struct clksel_rate common_clkout_src_core_rates[] = {
 262         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 263         { .div = 0 }
 264 };
 265
 266 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 267         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 268         { .div = 0 }
 269 };
 270
 271 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 272         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 273         { .div = 0 }
 274 };
 275
 276 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 277         { .div = 1, .val = 3, .flags = RATE_IN_24XX },
 278         { .div = 0 }
 279 };
 280
 281 static const struct clksel common_clkout_src_clksel[] = {
 282         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 283         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 284         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 285         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 286         { .parent = NULL }
 287 };
 288
 289 static struct clk sys_clkout_src = {
 290         .name           = "sys_clkout_src",
 291         .ops            = &clkops_omap2_dflt,
 292         .parent         = &func_54m_ck,
 293         .clkdm_name     = "wkup_clkdm",
 294         .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 295         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 296         .init           = &omap2_init_clksel_parent,
 297         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 298         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 299         .clksel         = common_clkout_src_clksel,
 300         .recalc         = &omap2_clksel_recalc,
 301         .round_rate     = &omap2_clksel_round_rate,
 302         .set_rate       = &omap2_clksel_set_rate
 303 };
 304
 305 static const struct clksel_rate common_clkout_rates[] = {
 306         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 307         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 308         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 309         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 310         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 311         { .div = 0 },
 312 };
 313
 314 static const struct clksel sys_clkout_clksel[] = {
 315         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 316         { .parent = NULL }
 317 };
 318
 319 static struct clk sys_clkout = {
 320         .name           = "sys_clkout",
 321         .ops            = &clkops_null,
 322         .parent         = &sys_clkout_src,
 323         .clkdm_name     = "wkup_clkdm",
 324         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 325         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 326         .clksel         = sys_clkout_clksel,
 327         .recalc         = &omap2_clksel_recalc,
 328         .round_rate     = &omap2_clksel_round_rate,
 329         .set_rate       = &omap2_clksel_set_rate
 330 };
 331
 332 /* In 2430, new in 2420 ES2 */
 333 static struct clk sys_clkout2_src = {
 334         .name           = "sys_clkout2_src",
 335         .ops            = &clkops_omap2_dflt,
 336         .parent         = &func_54m_ck,
 337         .clkdm_name     = "wkup_clkdm",
 338         .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 339         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 340         .init           = &omap2_init_clksel_parent,
 341         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 342         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 343         .clksel         = common_clkout_src_clksel,
 344         .recalc         = &omap2_clksel_recalc,
 345         .round_rate     = &omap2_clksel_round_rate,
 346         .set_rate       = &omap2_clksel_set_rate
 347 };
 348
 349 static const struct clksel sys_clkout2_clksel[] = {
 350         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 351         { .parent = NULL }
 352 };
 353
 354 /* In 2430, new in 2420 ES2 */
 355 static struct clk sys_clkout2 = {
 356         .name           = "sys_clkout2",
 357         .ops            = &clkops_null,
 358         .parent         = &sys_clkout2_src,
 359         .clkdm_name     = "wkup_clkdm",
 360         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 361         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 362         .clksel         = sys_clkout2_clksel,
 363         .recalc         = &omap2_clksel_recalc,
 364         .round_rate     = &omap2_clksel_round_rate,
 365         .set_rate       = &omap2_clksel_set_rate
 366 };
 367
 368 static struct clk emul_ck = {
 369         .name           = "emul_ck",
 370         .ops            = &clkops_omap2_dflt,
 371         .parent         = &func_54m_ck,
 372         .clkdm_name     = "wkup_clkdm",
 373         .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
 374         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 375         .recalc         = &followparent_recalc,
 376
 377 };
 378
 379 /*
 380  * MPU clock domain
 381  *      Clocks:
 382  *              MPU_FCLK, MPU_ICLK
 383  *              INT_M_FCLK, INT_M_I_CLK
 384  *
 385  * - Individual clocks are hardware managed.
 386  * - Base divider comes from: CM_CLKSEL_MPU
 387  *
 388  */
 389 static const struct clksel_rate mpu_core_rates[] = {
 390         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 391         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 392         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 393         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 394         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 395         { .div = 0 },
 396 };
 397
 398 static const struct clksel mpu_clksel[] = {
 399         { .parent = &core_ck, .rates = mpu_core_rates },
 400         { .parent = NULL }
 401 };
 402
 403 static struct clk mpu_ck = {    /* Control cpu */
 404         .name           = "mpu_ck",
 405         .ops            = &clkops_null,
 406         .parent         = &core_ck,
 407         .clkdm_name     = "mpu_clkdm",
 408         .init           = &omap2_init_clksel_parent,
 409         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 410         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 411         .clksel         = mpu_clksel,
 412         .recalc         = &omap2_clksel_recalc,
 413 };
 414
 415 /*
 416  * DSP (2420-UMA+IVA1) clock domain
 417  * Clocks:
 418  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 419  *
 420  * Won't be too specific here. The core clock comes into this block
 421  * it is divided then tee'ed. One branch goes directly to xyz enable
 422  * controls. The other branch gets further divided by 2 then possibly
 423  * routed into a synchronizer and out of clocks abc.
 424  */
 425 static const struct clksel_rate dsp_fck_core_rates[] = {
 426         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 427         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 428         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 429         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 430         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 431         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 432         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 433         { .div = 0 },
 434 };
 435
 436 static const struct clksel dsp_fck_clksel[] = {
 437         { .parent = &core_ck, .rates = dsp_fck_core_rates },
 438         { .parent = NULL }
 439 };
 440
 441 static struct clk dsp_fck = {
 442         .name           = "dsp_fck",
 443         .ops            = &clkops_omap2_dflt_wait,
 444         .parent         = &core_ck,
 445         .clkdm_name     = "dsp_clkdm",
 446         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 447         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 448         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 449         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 450         .clksel         = dsp_fck_clksel,
 451         .recalc         = &omap2_clksel_recalc,
 452 };
 453
 454 static const struct clksel dsp_ick_clksel[] = {
 455         { .parent = &dsp_fck, .rates = dsp_ick_rates },
 456         { .parent = NULL }
 457 };
 458
 459 static struct clk dsp_ick = {
 460         .name           = "dsp_ick",     /* apparently ipi and isp */
 461         .ops            = &clkops_omap2_iclk_dflt_wait,
 462         .parent         = &dsp_fck,
 463         .clkdm_name     = "dsp_clkdm",
 464         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 465         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
 466         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 467         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 468         .clksel         = dsp_ick_clksel,
 469         .recalc         = &omap2_clksel_recalc,
 470 };
 471
 472 /*
 473  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
 474  * the C54x, but which is contained in the DSP powerdomain.  Does not
 475  * exist on later OMAPs.
 476  */
 477 static struct clk iva1_ifck = {
 478         .name           = "iva1_ifck",
 479         .ops            = &clkops_omap2_dflt_wait,
 480         .parent         = &core_ck,
 481         .clkdm_name     = "iva1_clkdm",
 482         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 483         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 484         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 485         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
 486         .clksel         = dsp_fck_clksel,
 487         .recalc         = &omap2_clksel_recalc,
 488 };
 489
 490 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 491 static struct clk iva1_mpu_int_ifck = {
 492         .name           = "iva1_mpu_int_ifck",
 493         .ops            = &clkops_omap2_dflt_wait,
 494         .parent         = &iva1_ifck,
 495         .clkdm_name     = "iva1_clkdm",
 496         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 497         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 498         .fixed_div      = 2,
 499         .recalc         = &omap_fixed_divisor_recalc,
 500 };
 501
 502 /*
 503  * L3 clock domain
 504  * L3 clocks are used for both interface and functional clocks to
 505  * multiple entities. Some of these clocks are completely managed
 506  * by hardware, and some others allow software control. Hardware
 507  * managed ones general are based on directly CLK_REQ signals and
 508  * various auto idle settings. The functional spec sets many of these
 509  * as 'tie-high' for their enables.
 510  *
 511  * I-CLOCKS:
 512  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 513  *      CAM, HS-USB.
 514  * F-CLOCK
 515  *      SSI.
 516  *
 517  * GPMC memories and SDRC have timing and clock sensitive registers which
 518  * may very well need notification when the clock changes. Currently for low
 519  * operating points, these are taken care of in sleep.S.
 520  */
 521 static const struct clksel_rate core_l3_core_rates[] = {
 522         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 523         { .div = 2, .val = 2, .flags = RATE_IN_242X },
 524         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 525         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 526         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 527         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 528         { .div = 16, .val = 16, .flags = RATE_IN_242X },
 529         { .div = 0 }
 530 };
 531
 532 static const struct clksel core_l3_clksel[] = {
 533         { .parent = &core_ck, .rates = core_l3_core_rates },
 534         { .parent = NULL }
 535 };
 536
 537 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 538         .name           = "core_l3_ck",
 539         .ops            = &clkops_null,
 540         .parent         = &core_ck,
 541         .clkdm_name     = "core_l3_clkdm",
 542         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 543         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
 544         .clksel         = core_l3_clksel,
 545         .recalc         = &omap2_clksel_recalc,
 546 };
 547
 548 /* usb_l4_ick */
 549 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
 550         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 551         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 552         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 553         { .div = 0 }
 554 };
 555
 556 static const struct clksel usb_l4_ick_clksel[] = {
 557         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
 558         { .parent = NULL },
 559 };
 560
 561 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 562 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 563         .name           = "usb_l4_ick",
 564         .ops            = &clkops_omap2_iclk_dflt_wait,
 565         .parent         = &core_l3_ck,
 566         .clkdm_name     = "core_l4_clkdm",
 567         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 568         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 569         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 570         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
 571         .clksel         = usb_l4_ick_clksel,
 572         .recalc         = &omap2_clksel_recalc,
 573 };
 574
 575 /*
 576  * L4 clock management domain
 577  *
 578  * This domain contains lots of interface clocks from the L4 interface, some
 579  * functional clocks.   Fixed APLL functional source clocks are managed in
 580  * this domain.
 581  */
 582 static const struct clksel_rate l4_core_l3_rates[] = {
 583         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 584         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 585         { .div = 0 }
 586 };
 587
 588 static const struct clksel l4_clksel[] = {
 589         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
 590         { .parent = NULL }
 591 };
 592
 593 static struct clk l4_ck = {             /* used both as an ick and fck */
 594         .name           = "l4_ck",
 595         .ops            = &clkops_null,
 596         .parent         = &core_l3_ck,
 597         .clkdm_name     = "core_l4_clkdm",
 598         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 599         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
 600         .clksel         = l4_clksel,
 601         .recalc         = &omap2_clksel_recalc,
 602 };
 603
 604 /*
 605  * SSI is in L3 management domain, its direct parent is core not l3,
 606  * many core power domain entities are grouped into the L3 clock
 607  * domain.
 608  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
 609  *
 610  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 611  */
 612 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
 613         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 614         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 615         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 616         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 617         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 618         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 619         { .div = 0 }
 620 };
 621
 622 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
 623         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
 624         { .parent = NULL }
 625 };
 626
 627 static struct clk ssi_ssr_sst_fck = {
 628         .name           = "ssi_fck",
 629         .ops            = &clkops_omap2_dflt_wait,
 630         .parent         = &core_ck,
 631         .clkdm_name     = "core_l3_clkdm",
 632         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 633         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 634         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 635         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
 636         .clksel         = ssi_ssr_sst_fck_clksel,
 637         .recalc         = &omap2_clksel_recalc,
 638 };
 639
 640 /*
 641  * Presumably this is the same as SSI_ICLK.
 642  * TRM contradicts itself on what clockdomain SSI_ICLK is in
 643  */
 644 static struct clk ssi_l4_ick = {
 645         .name           = "ssi_l4_ick",
 646         .ops            = &clkops_omap2_iclk_dflt_wait,
 647         .parent         = &l4_ck,
 648         .clkdm_name     = "core_l4_clkdm",
 649         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 650         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 651         .recalc         = &followparent_recalc,
 652 };
 653
 654
 655 /*
 656  * GFX clock domain
 657  *      Clocks:
 658  * GFX_FCLK, GFX_ICLK
 659  * GFX_CG1(2d), GFX_CG2(3d)
 660  *
 661  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 662  * The 2d and 3d clocks run at a hardware determined
 663  * divided value of fclk.
 664  *
 665  */
 666
 667 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
 668 static const struct clksel gfx_fck_clksel[] = {
 669         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
 670         { .parent = NULL },
 671 };
 672
 673 static struct clk gfx_3d_fck = {
 674         .name           = "gfx_3d_fck",
 675         .ops            = &clkops_omap2_dflt_wait,
 676         .parent         = &core_l3_ck,
 677         .clkdm_name     = "gfx_clkdm",
 678         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 679         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 680         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 681         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 682         .clksel         = gfx_fck_clksel,
 683         .recalc         = &omap2_clksel_recalc,
 684         .round_rate     = &omap2_clksel_round_rate,
 685         .set_rate       = &omap2_clksel_set_rate
 686 };
 687
 688 static struct clk gfx_2d_fck = {
 689         .name           = "gfx_2d_fck",
 690         .ops            = &clkops_omap2_dflt_wait,
 691         .parent         = &core_l3_ck,
 692         .clkdm_name     = "gfx_clkdm",
 693         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 694         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 695         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 696         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 697         .clksel         = gfx_fck_clksel,
 698         .recalc         = &omap2_clksel_recalc,
 699 };
 700
 701 /* This interface clock does not have a CM_AUTOIDLE bit */
 702 static struct clk gfx_ick = {
 703         .name           = "gfx_ick",            /* From l3 */
 704         .ops            = &clkops_omap2_dflt_wait,
 705         .parent         = &core_l3_ck,
 706         .clkdm_name     = "gfx_clkdm",
 707         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 708         .enable_bit     = OMAP_EN_GFX_SHIFT,
 709         .recalc         = &followparent_recalc,
 710 };
 711
 712 /*
 713  * DSS clock domain
 714  * CLOCKs:
 715  * DSS_L4_ICLK, DSS_L3_ICLK,
 716  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
 717  *
 718  * DSS is both initiator and target.
 719  */
 720 /* XXX Add RATE_NOT_VALIDATED */
 721
 722 static const struct clksel_rate dss1_fck_sys_rates[] = {
 723         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 724         { .div = 0 }
 725 };
 726
 727 static const struct clksel_rate dss1_fck_core_rates[] = {
 728         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 729         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 730         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 731         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 732         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
 733         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 734         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
 735         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
 736         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 737         { .div = 16, .val = 16, .flags = RATE_IN_24XX },
 738         { .div = 0 }
 739 };
 740
 741 static const struct clksel dss1_fck_clksel[] = {
 742         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
 743         { .parent = &core_ck, .rates = dss1_fck_core_rates },
 744         { .parent = NULL },
 745 };
 746
 747 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
 748         .name           = "dss_ick",
 749         .ops            = &clkops_omap2_iclk_dflt,
 750         .parent         = &l4_ck,       /* really both l3 and l4 */
 751         .clkdm_name     = "dss_clkdm",
 752         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 753         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 754         .recalc         = &followparent_recalc,
 755 };
 756
 757 static struct clk dss1_fck = {
 758         .name           = "dss1_fck",
 759         .ops            = &clkops_omap2_dflt,
 760         .parent         = &core_ck,             /* Core or sys */
 761         .clkdm_name     = "dss_clkdm",
 762         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 763         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 764         .init           = &omap2_init_clksel_parent,
 765         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 766         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
 767         .clksel         = dss1_fck_clksel,
 768         .recalc         = &omap2_clksel_recalc,
 769 };
 770
 771 static const struct clksel_rate dss2_fck_sys_rates[] = {
 772         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 773         { .div = 0 }
 774 };
 775
 776 static const struct clksel_rate dss2_fck_48m_rates[] = {
 777         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 778         { .div = 0 }
 779 };
 780
 781 static const struct clksel dss2_fck_clksel[] = {
 782         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
 783         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
 784         { .parent = NULL }
 785 };
 786
 787 static struct clk dss2_fck = {          /* Alt clk used in power management */
 788         .name           = "dss2_fck",
 789         .ops            = &clkops_omap2_dflt,
 790         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
 791         .clkdm_name     = "dss_clkdm",
 792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 793         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
 794         .init           = &omap2_init_clksel_parent,
 795         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 796         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
 797         .clksel         = dss2_fck_clksel,
 798         .recalc         = &omap2_clksel_recalc,
 799 };
 800
 801 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
 802         .name           = "dss_54m_fck",        /* 54m tv clk */
 803         .ops            = &clkops_omap2_dflt_wait,
 804         .parent         = &func_54m_ck,
 805         .clkdm_name     = "dss_clkdm",
 806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 807         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
 808         .recalc         = &followparent_recalc,
 809 };
 810
 811 static struct clk wu_l4_ick = {
 812         .name           = "wu_l4_ick",
 813         .ops            = &clkops_null,
 814         .parent         = &sys_ck,
 815         .clkdm_name     = "wkup_clkdm",
 816         .recalc         = &followparent_recalc,
 817 };
 818
 819 /*
 820  * CORE power domain ICLK & FCLK defines.
 821  * Many of the these can have more than one possible parent. Entries
 822  * here will likely have an L4 interface parent, and may have multiple
 823  * functional clock parents.
 824  */
 825 static const struct clksel_rate gpt_alt_rates[] = {
 826         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 827         { .div = 0 }
 828 };
 829
 830 static const struct clksel omap24xx_gpt_clksel[] = {
 831         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
 832         { .parent = &sys_ck,      .rates = gpt_sys_rates },
 833         { .parent = &alt_ck,      .rates = gpt_alt_rates },
 834         { .parent = NULL },
 835 };
 836
 837 static struct clk gpt1_ick = {
 838         .name           = "gpt1_ick",
 839         .ops            = &clkops_omap2_iclk_dflt_wait,
 840         .parent         = &wu_l4_ick,
 841         .clkdm_name     = "wkup_clkdm",
 842         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 843         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 844         .recalc         = &followparent_recalc,
 845 };
 846
 847 static struct clk gpt1_fck = {
 848         .name           = "gpt1_fck",
 849         .ops            = &clkops_omap2_dflt_wait,
 850         .parent         = &func_32k_ck,
 851         .clkdm_name     = "core_l4_clkdm",
 852         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 853         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 854         .init           = &omap2_init_clksel_parent,
 855         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
 856         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
 857         .clksel         = omap24xx_gpt_clksel,
 858         .recalc         = &omap2_clksel_recalc,
 859         .round_rate     = &omap2_clksel_round_rate,
 860         .set_rate       = &omap2_clksel_set_rate
 861 };
 862
 863 static struct clk gpt2_ick = {
 864         .name           = "gpt2_ick",
 865         .ops            = &clkops_omap2_iclk_dflt_wait,
 866         .parent         = &l4_ck,
 867         .clkdm_name     = "core_l4_clkdm",
 868         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 869         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 870         .recalc         = &followparent_recalc,
 871 };
 872
 873 static struct clk gpt2_fck = {
 874         .name           = "gpt2_fck",
 875         .ops            = &clkops_omap2_dflt_wait,
 876         .parent         = &func_32k_ck,
 877         .clkdm_name     = "core_l4_clkdm",
 878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 879         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 880         .init           = &omap2_init_clksel_parent,
 881         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 882         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
 883         .clksel         = omap24xx_gpt_clksel,
 884         .recalc         = &omap2_clksel_recalc,
 885 };
 886
 887 static struct clk gpt3_ick = {
 888         .name           = "gpt3_ick",
 889         .ops            = &clkops_omap2_iclk_dflt_wait,
 890         .parent         = &l4_ck,
 891         .clkdm_name     = "core_l4_clkdm",
 892         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 893         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 894         .recalc         = &followparent_recalc,
 895 };
 896
 897 static struct clk gpt3_fck = {
 898         .name           = "gpt3_fck",
 899         .ops            = &clkops_omap2_dflt_wait,
 900         .parent         = &func_32k_ck,
 901         .clkdm_name     = "core_l4_clkdm",
 902         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 903         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 904         .init           = &omap2_init_clksel_parent,
 905         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 906         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
 907         .clksel         = omap24xx_gpt_clksel,
 908         .recalc         = &omap2_clksel_recalc,
 909 };
 910
 911 static struct clk gpt4_ick = {
 912         .name           = "gpt4_ick",
 913         .ops            = &clkops_omap2_iclk_dflt_wait,
 914         .parent         = &l4_ck,
 915         .clkdm_name     = "core_l4_clkdm",
 916         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 917         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 918         .recalc         = &followparent_recalc,
 919 };
 920
 921 static struct clk gpt4_fck = {
 922         .name           = "gpt4_fck",
 923         .ops            = &clkops_omap2_dflt_wait,
 924         .parent         = &func_32k_ck,
 925         .clkdm_name     = "core_l4_clkdm",
 926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 927         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 928         .init           = &omap2_init_clksel_parent,
 929         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 930         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
 931         .clksel         = omap24xx_gpt_clksel,
 932         .recalc         = &omap2_clksel_recalc,
 933 };
 934
 935 static struct clk gpt5_ick = {
 936         .name           = "gpt5_ick",
 937         .ops            = &clkops_omap2_iclk_dflt_wait,
 938         .parent         = &l4_ck,
 939         .clkdm_name     = "core_l4_clkdm",
 940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 941         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 942         .recalc         = &followparent_recalc,
 943 };
 944
 945 static struct clk gpt5_fck = {
 946         .name           = "gpt5_fck",
 947         .ops            = &clkops_omap2_dflt_wait,
 948         .parent         = &func_32k_ck,
 949         .clkdm_name     = "core_l4_clkdm",
 950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 951         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 952         .init           = &omap2_init_clksel_parent,
 953         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 954         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
 955         .clksel         = omap24xx_gpt_clksel,
 956         .recalc         = &omap2_clksel_recalc,
 957 };
 958
 959 static struct clk gpt6_ick = {
 960         .name           = "gpt6_ick",
 961         .ops            = &clkops_omap2_iclk_dflt_wait,
 962         .parent         = &l4_ck,
 963         .clkdm_name     = "core_l4_clkdm",
 964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 965         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 966         .recalc         = &followparent_recalc,
 967 };
 968
 969 static struct clk gpt6_fck = {
 970         .name           = "gpt6_fck",
 971         .ops            = &clkops_omap2_dflt_wait,
 972         .parent         = &func_32k_ck,
 973         .clkdm_name     = "core_l4_clkdm",
 974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 975         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 976         .init           = &omap2_init_clksel_parent,
 977         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 978         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
 979         .clksel         = omap24xx_gpt_clksel,
 980         .recalc         = &omap2_clksel_recalc,
 981 };
 982
 983 static struct clk gpt7_ick = {
 984         .name           = "gpt7_ick",
 985         .ops            = &clkops_omap2_iclk_dflt_wait,
 986         .parent         = &l4_ck,
 987         .clkdm_name     = "core_l4_clkdm",
 988         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 989         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 990         .recalc         = &followparent_recalc,
 991 };
 992
 993 static struct clk gpt7_fck = {
 994         .name           = "gpt7_fck",
 995         .ops            = &clkops_omap2_dflt_wait,
 996         .parent         = &func_32k_ck,
 997         .clkdm_name     = "core_l4_clkdm",
 998         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 999         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1000         .init           = &omap2_init_clksel_parent,
1001         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1002         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1003         .clksel         = omap24xx_gpt_clksel,
1004         .recalc         = &omap2_clksel_recalc,
1005 };
1006
1007 static struct clk gpt8_ick = {
1008         .name           = "gpt8_ick",
1009         .ops            = &clkops_omap2_iclk_dflt_wait,
1010         .parent         = &l4_ck,
1011         .clkdm_name     = "core_l4_clkdm",
1012         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1013         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1014         .recalc         = &followparent_recalc,
1015 };
1016
1017 static struct clk gpt8_fck = {
1018         .name           = "gpt8_fck",
1019         .ops            = &clkops_omap2_dflt_wait,
1020         .parent         = &func_32k_ck,
1021         .clkdm_name     = "core_l4_clkdm",
1022         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1023         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1024         .init           = &omap2_init_clksel_parent,
1025         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1026         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1027         .clksel         = omap24xx_gpt_clksel,
1028         .recalc         = &omap2_clksel_recalc,
1029 };
1030
1031 static struct clk gpt9_ick = {
1032         .name           = "gpt9_ick",
1033         .ops            = &clkops_omap2_iclk_dflt_wait,
1034         .parent         = &l4_ck,
1035         .clkdm_name     = "core_l4_clkdm",
1036         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1037         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1038         .recalc         = &followparent_recalc,
1039 };
1040
1041 static struct clk gpt9_fck = {
1042         .name           = "gpt9_fck",
1043         .ops            = &clkops_omap2_dflt_wait,
1044         .parent         = &func_32k_ck,
1045         .clkdm_name     = "core_l4_clkdm",
1046         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1047         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1048         .init           = &omap2_init_clksel_parent,
1049         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1050         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1051         .clksel         = omap24xx_gpt_clksel,
1052         .recalc         = &omap2_clksel_recalc,
1053 };
1054
1055 static struct clk gpt10_ick = {
1056         .name           = "gpt10_ick",
1057         .ops            = &clkops_omap2_iclk_dflt_wait,
1058         .parent         = &l4_ck,
1059         .clkdm_name     = "core_l4_clkdm",
1060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1061         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1062         .recalc         = &followparent_recalc,
1063 };
1064
1065 static struct clk gpt10_fck = {
1066         .name           = "gpt10_fck",
1067         .ops            = &clkops_omap2_dflt_wait,
1068         .parent         = &func_32k_ck,
1069         .clkdm_name     = "core_l4_clkdm",
1070         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1071         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1072         .init           = &omap2_init_clksel_parent,
1073         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1074         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1075         .clksel         = omap24xx_gpt_clksel,
1076         .recalc         = &omap2_clksel_recalc,
1077 };
1078
1079 static struct clk gpt11_ick = {
1080         .name           = "gpt11_ick",
1081         .ops            = &clkops_omap2_iclk_dflt_wait,
1082         .parent         = &l4_ck,
1083         .clkdm_name     = "core_l4_clkdm",
1084         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1085         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1086         .recalc         = &followparent_recalc,
1087 };
1088
1089 static struct clk gpt11_fck = {
1090         .name           = "gpt11_fck",
1091         .ops            = &clkops_omap2_dflt_wait,
1092         .parent         = &func_32k_ck,
1093         .clkdm_name     = "core_l4_clkdm",
1094         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1095         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1096         .init           = &omap2_init_clksel_parent,
1097         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1098         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1099         .clksel         = omap24xx_gpt_clksel,
1100         .recalc         = &omap2_clksel_recalc,
1101 };
1102
1103 static struct clk gpt12_ick = {
1104         .name           = "gpt12_ick",
1105         .ops            = &clkops_omap2_iclk_dflt_wait,
1106         .parent         = &l4_ck,
1107         .clkdm_name     = "core_l4_clkdm",
1108         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1109         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1110         .recalc         = &followparent_recalc,
1111 };
1112
1113 static struct clk gpt12_fck = {
1114         .name           = "gpt12_fck",
1115         .ops            = &clkops_omap2_dflt_wait,
1116         .parent         = &secure_32k_ck,
1117         .clkdm_name     = "core_l4_clkdm",
1118         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1119         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1120         .init           = &omap2_init_clksel_parent,
1121         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1122         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1123         .clksel         = omap24xx_gpt_clksel,
1124         .recalc         = &omap2_clksel_recalc,
1125 };
1126
1127 static struct clk mcbsp1_ick = {
1128         .name           = "mcbsp1_ick",
1129         .ops            = &clkops_omap2_iclk_dflt_wait,
1130         .parent         = &l4_ck,
1131         .clkdm_name     = "core_l4_clkdm",
1132         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1133         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1134         .recalc         = &followparent_recalc,
1135 };
1136
1137 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1138         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1139         { .div = 0 }
1140 };
1141
1142 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1143         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1144         { .div = 0 }
1145 };
1146
1147 static const struct clksel mcbsp_fck_clksel[] = {
1148         { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
1149         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1150         { .parent = NULL }
1151 };
1152
1153 static struct clk mcbsp1_fck = {
1154         .name           = "mcbsp1_fck",
1155         .ops            = &clkops_omap2_dflt_wait,
1156         .parent         = &func_96m_ck,
1157         .init           = &omap2_init_clksel_parent,
1158         .clkdm_name     = "core_l4_clkdm",
1159         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1160         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1161         .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1162         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1163         .clksel         = mcbsp_fck_clksel,
1164         .recalc         = &omap2_clksel_recalc,
1165 };
1166
1167 static struct clk mcbsp2_ick = {
1168         .name           = "mcbsp2_ick",
1169         .ops            = &clkops_omap2_iclk_dflt_wait,
1170         .parent         = &l4_ck,
1171         .clkdm_name     = "core_l4_clkdm",
1172         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1173         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1174         .recalc         = &followparent_recalc,
1175 };
1176
1177 static struct clk mcbsp2_fck = {
1178         .name           = "mcbsp2_fck",
1179         .ops            = &clkops_omap2_dflt_wait,
1180         .parent         = &func_96m_ck,
1181         .init           = &omap2_init_clksel_parent,
1182         .clkdm_name     = "core_l4_clkdm",
1183         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1184         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1185         .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1186         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
1187         .clksel         = mcbsp_fck_clksel,
1188         .recalc         = &omap2_clksel_recalc,
1189 };
1190
1191 static struct clk mcspi1_ick = {
1192         .name           = "mcspi1_ick",
1193         .ops            = &clkops_omap2_iclk_dflt_wait,
1194         .parent         = &l4_ck,
1195         .clkdm_name     = "core_l4_clkdm",
1196         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1197         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1198         .recalc         = &followparent_recalc,
1199 };
1200
1201 static struct clk mcspi1_fck = {
1202         .name           = "mcspi1_fck",
1203         .ops            = &clkops_omap2_dflt_wait,
1204         .parent         = &func_48m_ck,
1205         .clkdm_name     = "core_l4_clkdm",
1206         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1207         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1208         .recalc         = &followparent_recalc,
1209 };
1210
1211 static struct clk mcspi2_ick = {
1212         .name           = "mcspi2_ick",
1213         .ops            = &clkops_omap2_iclk_dflt_wait,
1214         .parent         = &l4_ck,
1215         .clkdm_name     = "core_l4_clkdm",
1216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1217         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1218         .recalc         = &followparent_recalc,
1219 };
1220
1221 static struct clk mcspi2_fck = {
1222         .name           = "mcspi2_fck",
1223         .ops            = &clkops_omap2_dflt_wait,
1224         .parent         = &func_48m_ck,
1225         .clkdm_name     = "core_l4_clkdm",
1226         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1227         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1228         .recalc         = &followparent_recalc,
1229 };
1230
1231 static struct clk uart1_ick = {
1232         .name           = "uart1_ick",
1233         .ops            = &clkops_omap2_iclk_dflt_wait,
1234         .parent         = &l4_ck,
1235         .clkdm_name     = "core_l4_clkdm",
1236         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1237         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1238         .recalc         = &followparent_recalc,
1239 };
1240
1241 static struct clk uart1_fck = {
1242         .name           = "uart1_fck",
1243         .ops            = &clkops_omap2_dflt_wait,
1244         .parent         = &func_48m_ck,
1245         .clkdm_name     = "core_l4_clkdm",
1246         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1247         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1248         .recalc         = &followparent_recalc,
1249 };
1250
1251 static struct clk uart2_ick = {
1252         .name           = "uart2_ick",
1253         .ops            = &clkops_omap2_iclk_dflt_wait,
1254         .parent         = &l4_ck,
1255         .clkdm_name     = "core_l4_clkdm",
1256         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1258         .recalc         = &followparent_recalc,
1259 };
1260
1261 static struct clk uart2_fck = {
1262         .name           = "uart2_fck",
1263         .ops            = &clkops_omap2_dflt_wait,
1264         .parent         = &func_48m_ck,
1265         .clkdm_name     = "core_l4_clkdm",
1266         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1268         .recalc         = &followparent_recalc,
1269 };
1270
1271 static struct clk uart3_ick = {
1272         .name           = "uart3_ick",
1273         .ops            = &clkops_omap2_iclk_dflt_wait,
1274         .parent         = &l4_ck,
1275         .clkdm_name     = "core_l4_clkdm",
1276         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1277         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1278         .recalc         = &followparent_recalc,
1279 };
1280
1281 static struct clk uart3_fck = {
1282         .name           = "uart3_fck",
1283         .ops            = &clkops_omap2_dflt_wait,
1284         .parent         = &func_48m_ck,
1285         .clkdm_name     = "core_l4_clkdm",
1286         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1287         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1288         .recalc         = &followparent_recalc,
1289 };
1290
1291 static struct clk gpios_ick = {
1292         .name           = "gpios_ick",
1293         .ops            = &clkops_omap2_iclk_dflt_wait,
1294         .parent         = &wu_l4_ick,
1295         .clkdm_name     = "wkup_clkdm",
1296         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1297         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 static struct clk gpios_fck = {
1302         .name           = "gpios_fck",
1303         .ops            = &clkops_omap2_dflt_wait,
1304         .parent         = &func_32k_ck,
1305         .clkdm_name     = "wkup_clkdm",
1306         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1307         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1308         .recalc         = &followparent_recalc,
1309 };
1310
1311 static struct clk mpu_wdt_ick = {
1312         .name           = "mpu_wdt_ick",
1313         .ops            = &clkops_omap2_iclk_dflt_wait,
1314         .parent         = &wu_l4_ick,
1315         .clkdm_name     = "wkup_clkdm",
1316         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1317         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1318         .recalc         = &followparent_recalc,
1319 };
1320
1321 static struct clk mpu_wdt_fck = {
1322         .name           = "mpu_wdt_fck",
1323         .ops            = &clkops_omap2_dflt_wait,
1324         .parent         = &func_32k_ck,
1325         .clkdm_name     = "wkup_clkdm",
1326         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1327         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1328         .recalc         = &followparent_recalc,
1329 };
1330
1331 static struct clk sync_32k_ick = {
1332         .name           = "sync_32k_ick",
1333         .ops            = &clkops_omap2_iclk_dflt_wait,
1334         .parent         = &wu_l4_ick,
1335         .clkdm_name     = "wkup_clkdm",
1336         .flags          = ENABLE_ON_INIT,
1337         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1338         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1339         .recalc         = &followparent_recalc,
1340 };
1341
1342 static struct clk wdt1_ick = {
1343         .name           = "wdt1_ick",
1344         .ops            = &clkops_omap2_iclk_dflt_wait,
1345         .parent         = &wu_l4_ick,
1346         .clkdm_name     = "wkup_clkdm",
1347         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1348         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1349         .recalc         = &followparent_recalc,
1350 };
1351
1352 static struct clk omapctrl_ick = {
1353         .name           = "omapctrl_ick",
1354         .ops            = &clkops_omap2_iclk_dflt_wait,
1355         .parent         = &wu_l4_ick,
1356         .clkdm_name     = "wkup_clkdm",
1357         .flags          = ENABLE_ON_INIT,
1358         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1359         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1360         .recalc         = &followparent_recalc,
1361 };
1362
1363 static struct clk cam_ick = {
1364         .name           = "cam_ick",
1365         .ops            = &clkops_omap2_iclk_dflt,
1366         .parent         = &l4_ck,
1367         .clkdm_name     = "core_l4_clkdm",
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1369         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1370         .recalc         = &followparent_recalc,
1371 };
1372
1373 /*
1374  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
1375  * split into two separate clocks, since the parent clocks are different
1376  * and the clockdomains are also different.
1377  */
1378 static struct clk cam_fck = {
1379         .name           = "cam_fck",
1380         .ops            = &clkops_omap2_dflt,
1381         .parent         = &func_96m_ck,
1382         .clkdm_name     = "core_l3_clkdm",
1383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1385         .recalc         = &followparent_recalc,
1386 };
1387
1388 static struct clk mailboxes_ick = {
1389         .name           = "mailboxes_ick",
1390         .ops            = &clkops_omap2_iclk_dflt_wait,
1391         .parent         = &l4_ck,
1392         .clkdm_name     = "core_l4_clkdm",
1393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1394         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1395         .recalc         = &followparent_recalc,
1396 };
1397
1398 static struct clk wdt4_ick = {
1399         .name           = "wdt4_ick",
1400         .ops            = &clkops_omap2_iclk_dflt_wait,
1401         .parent         = &l4_ck,
1402         .clkdm_name     = "core_l4_clkdm",
1403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1404         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1405         .recalc         = &followparent_recalc,
1406 };
1407
1408 static struct clk wdt4_fck = {
1409         .name           = "wdt4_fck",
1410         .ops            = &clkops_omap2_dflt_wait,
1411         .parent         = &func_32k_ck,
1412         .clkdm_name     = "core_l4_clkdm",
1413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1415         .recalc         = &followparent_recalc,
1416 };
1417
1418 static struct clk wdt3_ick = {
1419         .name           = "wdt3_ick",
1420         .ops            = &clkops_omap2_iclk_dflt_wait,
1421         .parent         = &l4_ck,
1422         .clkdm_name     = "core_l4_clkdm",
1423         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1424         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1425         .recalc         = &followparent_recalc,
1426 };
1427
1428 static struct clk wdt3_fck = {
1429         .name           = "wdt3_fck",
1430         .ops            = &clkops_omap2_dflt_wait,
1431         .parent         = &func_32k_ck,
1432         .clkdm_name     = "core_l4_clkdm",
1433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1435         .recalc         = &followparent_recalc,
1436 };
1437
1438 static struct clk mspro_ick = {
1439         .name           = "mspro_ick",
1440         .ops            = &clkops_omap2_iclk_dflt_wait,
1441         .parent         = &l4_ck,
1442         .clkdm_name     = "core_l4_clkdm",
1443         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1444         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1445         .recalc         = &followparent_recalc,
1446 };
1447
1448 static struct clk mspro_fck = {
1449         .name           = "mspro_fck",
1450         .ops            = &clkops_omap2_dflt_wait,
1451         .parent         = &func_96m_ck,
1452         .clkdm_name     = "core_l4_clkdm",
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1455         .recalc         = &followparent_recalc,
1456 };
1457
1458 static struct clk mmc_ick = {
1459         .name           = "mmc_ick",
1460         .ops            = &clkops_omap2_iclk_dflt_wait,
1461         .parent         = &l4_ck,
1462         .clkdm_name     = "core_l4_clkdm",
1463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1464         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 static struct clk mmc_fck = {
1469         .name           = "mmc_fck",
1470         .ops            = &clkops_omap2_dflt_wait,
1471         .parent         = &func_96m_ck,
1472         .clkdm_name     = "core_l4_clkdm",
1473         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 static struct clk fac_ick = {
1479         .name           = "fac_ick",
1480         .ops            = &clkops_omap2_iclk_dflt_wait,
1481         .parent         = &l4_ck,
1482         .clkdm_name     = "core_l4_clkdm",
1483         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1484         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1485         .recalc         = &followparent_recalc,
1486 };
1487
1488 static struct clk fac_fck = {
1489         .name           = "fac_fck",
1490         .ops            = &clkops_omap2_dflt_wait,
1491         .parent         = &func_12m_ck,
1492         .clkdm_name     = "core_l4_clkdm",
1493         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk eac_ick = {
1499         .name           = "eac_ick",
1500         .ops            = &clkops_omap2_iclk_dflt_wait,
1501         .parent         = &l4_ck,
1502         .clkdm_name     = "core_l4_clkdm",
1503         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1504         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1505         .recalc         = &followparent_recalc,
1506 };
1507
1508 static struct clk eac_fck = {
1509         .name           = "eac_fck",
1510         .ops            = &clkops_omap2_dflt_wait,
1511         .parent         = &func_96m_ck,
1512         .clkdm_name     = "core_l4_clkdm",
1513         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1515         .recalc         = &followparent_recalc,
1516 };
1517
1518 static struct clk hdq_ick = {
1519         .name           = "hdq_ick",
1520         .ops            = &clkops_omap2_iclk_dflt_wait,
1521         .parent         = &l4_ck,
1522         .clkdm_name     = "core_l4_clkdm",
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1524         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1525         .recalc         = &followparent_recalc,
1526 };
1527
1528 static struct clk hdq_fck = {
1529         .name           = "hdq_fck",
1530         .ops            = &clkops_omap2_dflt_wait,
1531         .parent         = &func_12m_ck,
1532         .clkdm_name     = "core_l4_clkdm",
1533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1535         .recalc         = &followparent_recalc,
1536 };
1537
1538 static struct clk i2c2_ick = {
1539         .name           = "i2c2_ick",
1540         .ops            = &clkops_omap2_iclk_dflt_wait,
1541         .parent         = &l4_ck,
1542         .clkdm_name     = "core_l4_clkdm",
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1545         .recalc         = &followparent_recalc,
1546 };
1547
1548 static struct clk i2c2_fck = {
1549         .name           = "i2c2_fck",
1550         .ops            = &clkops_omap2_dflt_wait,
1551         .parent         = &func_12m_ck,
1552         .clkdm_name     = "core_l4_clkdm",
1553         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1555         .recalc         = &followparent_recalc,
1556 };
1557
1558 static struct clk i2c1_ick = {
1559         .name           = "i2c1_ick",
1560         .ops            = &clkops_omap2_iclk_dflt_wait,
1561         .parent         = &l4_ck,
1562         .clkdm_name     = "core_l4_clkdm",
1563         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1564         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1565         .recalc         = &followparent_recalc,
1566 };
1567
1568 static struct clk i2c1_fck = {
1569         .name           = "i2c1_fck",
1570         .ops            = &clkops_omap2_dflt_wait,
1571         .parent         = &func_12m_ck,
1572         .clkdm_name     = "core_l4_clkdm",
1573         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1575         .recalc         = &followparent_recalc,
1576 };
1577
1578 /*
1579  * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1580  * accesses derived from this data.
1581  */
1582 static struct clk gpmc_fck = {
1583         .name           = "gpmc_fck",
1584         .ops            = &clkops_omap2_iclk_idle_only,
1585         .parent         = &core_l3_ck,
1586         .flags          = ENABLE_ON_INIT,
1587         .clkdm_name     = "core_l3_clkdm",
1588         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1589         .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk sdma_fck = {
1594         .name           = "sdma_fck",
1595         .ops            = &clkops_null, /* RMK: missing? */
1596         .parent         = &core_l3_ck,
1597         .clkdm_name     = "core_l3_clkdm",
1598         .recalc         = &followparent_recalc,
1599 };
1600
1601 /*
1602  * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1603  * accesses derived from this data.
1604  */
1605 static struct clk sdma_ick = {
1606         .name           = "sdma_ick",
1607         .ops            = &clkops_omap2_iclk_idle_only,
1608         .parent         = &core_l3_ck,
1609         .clkdm_name     = "core_l3_clkdm",
1610         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1611         .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 /*
1616  * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1617  * accesses derived from this data.
1618  */
1619 static struct clk sdrc_ick = {
1620         .name           = "sdrc_ick",
1621         .ops            = &clkops_omap2_iclk_idle_only,
1622         .parent         = &core_l3_ck,
1623         .flags          = ENABLE_ON_INIT,
1624         .clkdm_name     = "core_l3_clkdm",
1625         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1626         .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
1627         .recalc         = &followparent_recalc,
1628 };
1629
1630 static struct clk vlynq_ick = {
1631         .name           = "vlynq_ick",
1632         .ops            = &clkops_omap2_iclk_dflt_wait,
1633         .parent         = &core_l3_ck,
1634         .clkdm_name     = "core_l3_clkdm",
1635         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1636         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1637         .recalc         = &followparent_recalc,
1638 };
1639
1640 static const struct clksel_rate vlynq_fck_96m_rates[] = {
1641         { .div = 1, .val = 0, .flags = RATE_IN_242X },
1642         { .div = 0 }
1643 };
1644
1645 static const struct clksel_rate vlynq_fck_core_rates[] = {
1646         { .div = 1, .val = 1, .flags = RATE_IN_242X },
1647         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1648         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1649         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1650         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1651         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1652         { .div = 9, .val = 9, .flags = RATE_IN_242X },
1653         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1654         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1655         { .div = 18, .val = 18, .flags = RATE_IN_242X },
1656         { .div = 0 }
1657 };
1658
1659 static const struct clksel vlynq_fck_clksel[] = {
1660         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1661         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
1662         { .parent = NULL }
1663 };
1664
1665 static struct clk vlynq_fck = {
1666         .name           = "vlynq_fck",
1667         .ops            = &clkops_omap2_dflt_wait,
1668         .parent         = &func_96m_ck,
1669         .clkdm_name     = "core_l3_clkdm",
1670         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1672         .init           = &omap2_init_clksel_parent,
1673         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1674         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
1675         .clksel         = vlynq_fck_clksel,
1676         .recalc         = &omap2_clksel_recalc,
1677 };
1678
1679 static struct clk des_ick = {
1680         .name           = "des_ick",
1681         .ops            = &clkops_omap2_iclk_dflt_wait,
1682         .parent         = &l4_ck,
1683         .clkdm_name     = "core_l4_clkdm",
1684         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1685         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1686         .recalc         = &followparent_recalc,
1687 };
1688
1689 static struct clk sha_ick = {
1690         .name           = "sha_ick",
1691         .ops            = &clkops_omap2_iclk_dflt_wait,
1692         .parent         = &l4_ck,
1693         .clkdm_name     = "core_l4_clkdm",
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1695         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1696         .recalc         = &followparent_recalc,
1697 };
1698
1699 static struct clk rng_ick = {
1700         .name           = "rng_ick",
1701         .ops            = &clkops_omap2_iclk_dflt_wait,
1702         .parent         = &l4_ck,
1703         .clkdm_name     = "core_l4_clkdm",
1704         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1705         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1706         .recalc         = &followparent_recalc,
1707 };
1708
1709 static struct clk aes_ick = {
1710         .name           = "aes_ick",
1711         .ops            = &clkops_omap2_iclk_dflt_wait,
1712         .parent         = &l4_ck,
1713         .clkdm_name     = "core_l4_clkdm",
1714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1715         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 static struct clk pka_ick = {
1720         .name           = "pka_ick",
1721         .ops            = &clkops_omap2_iclk_dflt_wait,
1722         .parent         = &l4_ck,
1723         .clkdm_name     = "core_l4_clkdm",
1724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1725         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1726         .recalc         = &followparent_recalc,
1727 };
1728
1729 static struct clk usb_fck = {
1730         .name           = "usb_fck",
1731         .ops            = &clkops_omap2_dflt_wait,
1732         .parent         = &func_48m_ck,
1733         .clkdm_name     = "core_l3_clkdm",
1734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1735         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 /*
1740  * This clock is a composite clock which does entire set changes then
1741  * forces a rebalance. It keys on the MPU speed, but it really could
1742  * be any key speed part of a set in the rate table.
1743  *
1744  * to really change a set, you need memory table sets which get changed
1745  * in sram, pre-notifiers & post notifiers, changing the top set, without
1746  * having low level display recalc's won't work... this is why dpm notifiers
1747  * work, isr's off, walk a list of clocks already _off_ and not messing with
1748  * the bus.
1749  *
1750  * This clock should have no parent. It embodies the entire upper level
1751  * active set. A parent will mess up some of the init also.
1752  */
1753 static struct clk virt_prcm_set = {
1754         .name           = "virt_prcm_set",
1755         .ops            = &clkops_null,
1756         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1757         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
1758         .set_rate       = &omap2_select_table_rate,
1759         .round_rate     = &omap2_round_to_table_rate,
1760 };
1761
1762
1763 /*
1764  * clkdev integration
1765  */
1766
1767 static struct omap_clk omap2420_clks[] = {
1768         /* external root sources */
1769         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
1770         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
1771         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
1772         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
1773         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
1774         CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
1775         CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
1776         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
1777         /* internal analog sources */
1778         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
1779         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
1780         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
1781         /* internal prcm root sources */
1782         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
1783         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
1784         CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
1785         CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
1786         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
1787         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
1788         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
1789         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
1790         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
1791         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
1792         CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1793         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
1794         CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
1795         /* mpu domain clocks */
1796         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
1797         /* dsp domain clocks */
1798         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
1799         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
1800         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
1801         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1802         /* GFX domain clocks */
1803         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
1804         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
1805         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
1806         /* DSS domain clocks */
1807         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
1808         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
1809         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
1810         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
1811         /* L3 domain clocks */
1812         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
1813         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
1814         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
1815         /* L4 domain clocks */
1816         CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
1817         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
1818         CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
1819         /* virtual meta-group clock */
1820         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
1821         /* general l4 interface ck, multi-parent functional clk */
1822         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
1823         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
1824         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
1825         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
1826         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
1827         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
1828         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
1829         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
1830         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
1831         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
1832         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
1833         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
1834         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
1835         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
1836         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
1837         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
1838         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
1839         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
1840         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
1841         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
1842         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
1843         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
1844         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
1845         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
1846         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
1847         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
1848         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
1849         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
1850         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
1851         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
1852         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
1853         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
1854         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
1855         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
1856         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
1857         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
1858         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
1859         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
1860         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
1861         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
1862         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
1863         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
1864         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
1865         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
1866         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
1867         CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
1868         CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
1869         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
1870         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
1871         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
1872         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
1873         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
1874         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
1875         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
1876         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
1877         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
1878         CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
1879         CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
1880         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
1881         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
1882         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
1883         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
1884         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
1885         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
1886         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
1887         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
1888         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
1889         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
1890         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
1891         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
1892         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
1893         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
1894         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
1895         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
1896         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
1897         CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
1898         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
1899         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
1900         CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
1901 };
1902
1903 /*
1904  * init code
1905  */
1906
1907 int __init omap2420_clk_init(void)
1908 {
1909         const struct prcm_config *prcm;
1910         struct omap_clk *c;
1911         u32 clkrate;
1912
1913         prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1914         cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1915         cpu_mask = RATE_IN_242X;
1916         rate_table = omap2420_rate_table;
1917
1918         clk_init(&omap2_clk_functions);
1919
1920         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1921              c++)
1922                 clk_preinit(c->lk.clk);
1923
1924         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1925         propagate_rate(&osc_ck);
1926         sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1927         propagate_rate(&sys_ck);
1928
1929         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1930              c++) {
1931                 clkdev_add(&c->lk);
1932                 clk_register(c->lk.clk);
1933                 omap2_init_clk_clkdm(c->lk.clk);
1934         }
1935
1936         /* Disable autoidle on all clocks; let the PM code enable it later */
1937         omap_clk_disable_autoidle_all();
1938
1939         /* Check the MPU rate set by bootloader */
1940         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1941         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1942                 if (!(prcm->flags & cpu_mask))
1943                         continue;
1944                 if (prcm->xtal_speed != sys_ck.rate)
1945                         continue;
1946                 if (prcm->dpll_speed <= clkrate)
1947                         break;
1948         }
1949         curr_prcm_set = prcm;
1950
1951         recalculate_root_clocks();
1952
1953         pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1954                 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1955                 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1956
1957         /*
1958          * Only enable those clocks we will need, let the drivers
1959          * enable other clocks as necessary
1960          */
1961         clk_enable_init_clocks();
1962
1963         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1964         vclk = clk_get(NULL, "virt_prcm_set");
1965         sclk = clk_get(NULL, "sys_ck");
1966         dclk = clk_get(NULL, "dpll_ck");
1967
1968         return 0;
1969 }
1970