arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <mach/hardware.h>
  18 #include <plat/mmc.h>
  19 #include <plat/omap-pm.h>
  20 #include <plat/mux.h>
  21 #include <plat/omap_device.h>
  22
  23 #include "mux.h"
  24 #include "hsmmc.h"
  25 #include "control.h"
  26
  27 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  28
  29 static u16 control_pbias_offset;
  30 static u16 control_devconf1_offset;
  31 static u16 control_mmc1;
  32
  33 #define HSMMC_NAME_LEN  9
  34
  35 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  36
  37 static int hsmmc_get_context_loss(struct device *dev)
  38 {
  39         return omap_pm_get_dev_context_loss_count(dev);
  40 }
  41
  42 #else
  43 #define hsmmc_get_context_loss NULL
  44 #endif
  45
  46 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  47                                   int power_on, int vdd)
  48 {
  49         u32 reg, prog_io;
  50         struct omap_mmc_platform_data *mmc = dev->platform_data;
  51
  52         if (mmc->slots[0].remux)
  53                 mmc->slots[0].remux(dev, slot, power_on);
  54
  55         /*
  56          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  57          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  58          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  59          *
  60          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  61          * is most naturally TWL VSIM; those pins also use PBIAS.
  62          *
  63          * FIXME handle VMMC1A as needed ...
  64          */
  65         if (power_on) {
  66                 if (cpu_is_omap2430()) {
  67                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  68                         if ((1 << vdd) >= MMC_VDD_30_31)
  69                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  70                         else
  71                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  72                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  73                 }
  74
  75                 if (mmc->slots[0].internal_clock) {
  76                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  77                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  78                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  79                 }
  80
  81                 reg = omap_ctrl_readl(control_pbias_offset);
  82                 if (cpu_is_omap3630()) {
  83                         /* Set MMC I/O to 52Mhz */
  84                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  85                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  86                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  87                 } else {
  88                         reg |= OMAP2_PBIASSPEEDCTRL0;
  89                 }
  90                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  91                 omap_ctrl_writel(reg, control_pbias_offset);
  92         } else {
  93                 reg = omap_ctrl_readl(control_pbias_offset);
  94                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  95                 omap_ctrl_writel(reg, control_pbias_offset);
  96         }
  97 }
  98
  99 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
 100                                  int power_on, int vdd)
 101 {
 102         u32 reg;
 103
 104         /* 100ms delay required for PBIAS configuration */
 105         msleep(100);
 106
 107         if (power_on) {
 108                 reg = omap_ctrl_readl(control_pbias_offset);
 109                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 110                 if ((1 << vdd) <= MMC_VDD_165_195)
 111                         reg &= ~OMAP2_PBIASLITEVMODE0;
 112                 else
 113                         reg |= OMAP2_PBIASLITEVMODE0;
 114                 omap_ctrl_writel(reg, control_pbias_offset);
 115         } else {
 116                 reg = omap_ctrl_readl(control_pbias_offset);
 117                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 118                         OMAP2_PBIASLITEVMODE0);
 119                 omap_ctrl_writel(reg, control_pbias_offset);
 120         }
 121 }
 122
 123 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 124                                   int power_on, int vdd)
 125 {
 126         u32 reg;
 127
 128         /*
 129          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 130          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 131          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 132          *
 133          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
 134          * is most naturally TWL VSIM; those pins also use PBIAS.
 135          *
 136          * FIXME handle VMMC1A as needed ...
 137          */
 138         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 139         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 140                 OMAP4_MMC1_PWRDNZ_MASK |
 141                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 142         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 143 }
 144
 145 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 146                                  int power_on, int vdd)
 147 {
 148         u32 reg;
 149         unsigned long timeout;
 150
 151         if (power_on) {
 152                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 153                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 154                 if ((1 << vdd) <= MMC_VDD_165_195)
 155                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 156                 else
 157                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 158                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 159                         OMAP4_MMC1_PWRDNZ_MASK |
 160                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 161                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 162
 163                 timeout = jiffies + msecs_to_jiffies(5);
 164                 do {
 165                         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 166                         if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
 167                                 break;
 168                         usleep_range(100, 200);
 169                 } while (!time_after(jiffies, timeout));
 170
 171                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 172                         pr_err("Pbias Voltage is not same as LDO\n");
 173                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 174                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
 175                                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 176                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 177                 }
 178         } else {
 179                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 180                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 181                         OMAP4_MMC1_PWRDNZ_MASK |
 182                         OMAP4_MMC1_PBIASLITE_VMODE_MASK |
 183                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 184                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 185         }
 186 }
 187
 188 static void hsmmc23_before_set_reg(struct device *dev, int slot,
 189                                    int power_on, int vdd)
 190 {
 191         struct omap_mmc_platform_data *mmc = dev->platform_data;
 192
 193         if (mmc->slots[0].remux)
 194                 mmc->slots[0].remux(dev, slot, power_on);
 195
 196         if (power_on) {
 197                 /* Only MMC2 supports a CLKIN */
 198                 if (mmc->slots[0].internal_clock) {
 199                         u32 reg;
 200
 201                         reg = omap_ctrl_readl(control_devconf1_offset);
 202                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 203                         omap_ctrl_writel(reg, control_devconf1_offset);
 204                 }
 205         }
 206 }
 207
 208 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 209                                                         int vdd)
 210 {
 211         return 0;
 212 }
 213
 214 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 215                         int controller_nr)
 216 {
 217         if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
 218                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 219                                         OMAP_PIN_INPUT_PULLUP);
 220         if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
 221                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 222                                         OMAP_PIN_INPUT_PULLUP);
 223         if (cpu_is_omap34xx()) {
 224                 if (controller_nr == 0) {
 225                         omap_mux_init_signal("sdmmc1_clk",
 226                                 OMAP_PIN_INPUT_PULLUP);
 227                         omap_mux_init_signal("sdmmc1_cmd",
 228                                 OMAP_PIN_INPUT_PULLUP);
 229                         omap_mux_init_signal("sdmmc1_dat0",
 230                                 OMAP_PIN_INPUT_PULLUP);
 231                         if (mmc_controller->slots[0].caps &
 232                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 233                                 omap_mux_init_signal("sdmmc1_dat1",
 234                                         OMAP_PIN_INPUT_PULLUP);
 235                                 omap_mux_init_signal("sdmmc1_dat2",
 236                                         OMAP_PIN_INPUT_PULLUP);
 237                                 omap_mux_init_signal("sdmmc1_dat3",
 238                                         OMAP_PIN_INPUT_PULLUP);
 239                         }
 240                         if (mmc_controller->slots[0].caps &
 241                                                 MMC_CAP_8_BIT_DATA) {
 242                                 omap_mux_init_signal("sdmmc1_dat4",
 243                                         OMAP_PIN_INPUT_PULLUP);
 244                                 omap_mux_init_signal("sdmmc1_dat5",
 245                                         OMAP_PIN_INPUT_PULLUP);
 246                                 omap_mux_init_signal("sdmmc1_dat6",
 247                                         OMAP_PIN_INPUT_PULLUP);
 248                                 omap_mux_init_signal("sdmmc1_dat7",
 249                                         OMAP_PIN_INPUT_PULLUP);
 250                         }
 251                 }
 252                 if (controller_nr == 1) {
 253                         /* MMC2 */
 254                         omap_mux_init_signal("sdmmc2_clk",
 255                                 OMAP_PIN_INPUT_PULLUP);
 256                         omap_mux_init_signal("sdmmc2_cmd",
 257                                 OMAP_PIN_INPUT_PULLUP);
 258                         omap_mux_init_signal("sdmmc2_dat0",
 259                                 OMAP_PIN_INPUT_PULLUP);
 260
 261                         /*
 262                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 263                          * need to be muxed in the board-*.c files
 264                          */
 265                         if (mmc_controller->slots[0].caps &
 266                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 267                                 omap_mux_init_signal("sdmmc2_dat1",
 268                                         OMAP_PIN_INPUT_PULLUP);
 269                                 omap_mux_init_signal("sdmmc2_dat2",
 270                                         OMAP_PIN_INPUT_PULLUP);
 271                                 omap_mux_init_signal("sdmmc2_dat3",
 272                                         OMAP_PIN_INPUT_PULLUP);
 273                         }
 274                         if (mmc_controller->slots[0].caps &
 275                                                         MMC_CAP_8_BIT_DATA) {
 276                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 277                                         OMAP_PIN_INPUT_PULLUP);
 278                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 279                                         OMAP_PIN_INPUT_PULLUP);
 280                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 281                                         OMAP_PIN_INPUT_PULLUP);
 282                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 283                                         OMAP_PIN_INPUT_PULLUP);
 284                         }
 285                 }
 286
 287                 /*
 288                  * For MMC3 the pins need to be muxed in the board-*.c files
 289                  */
 290         }
 291 }
 292
 293 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 294                                         struct omap_mmc_platform_data *mmc)
 295 {
 296         char *hc_name;
 297
 298         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 299         if (!hc_name) {
 300                 pr_err("Cannot allocate memory for controller slot name\n");
 301                 kfree(hc_name);
 302                 return -ENOMEM;
 303         }
 304
 305         if (c->name)
 306                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 307         else
 308                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 309                                                                 c->mmc, 1);
 310         mmc->slots[0].name = hc_name;
 311         mmc->nr_slots = 1;
 312         mmc->slots[0].caps = c->caps;
 313         mmc->slots[0].internal_clock = !c->ext_clock;
 314         mmc->dma_mask = 0xffffffff;
 315         if (cpu_is_omap44xx())
 316                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 317         else
 318                 mmc->reg_offset = 0;
 319
 320         mmc->get_context_loss_count = hsmmc_get_context_loss;
 321
 322         mmc->slots[0].switch_pin = c->gpio_cd;
 323         mmc->slots[0].gpio_wp = c->gpio_wp;
 324
 325         mmc->slots[0].remux = c->remux;
 326         mmc->slots[0].init_card = c->init_card;
 327
 328         if (c->cover_only)
 329                 mmc->slots[0].cover = 1;
 330
 331         if (c->nonremovable)
 332                 mmc->slots[0].nonremovable = 1;
 333
 334         if (c->power_saving)
 335                 mmc->slots[0].power_saving = 1;
 336
 337         if (c->no_off)
 338                 mmc->slots[0].no_off = 1;
 339
 340         if (c->no_off_init)
 341                 mmc->slots[0].no_regulator_off_init = c->no_off_init;
 342
 343         if (c->vcc_aux_disable_is_sleep)
 344                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 345
 346         /*
 347          * NOTE:  MMC slots should have a Vcc regulator set up.
 348          * This may be from a TWL4030-family chip, another
 349          * controllable regulator, or a fixed supply.
 350          *
 351          * temporary HACK: ocr_mask instead of fixed supply
 352          */
 353         mmc->slots[0].ocr_mask = c->ocr_mask;
 354
 355         if (cpu_is_omap3517() || cpu_is_omap3505())
 356                 mmc->slots[0].set_power = nop_mmc_set_power;
 357         else
 358                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 359
 360         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 361                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 362
 363         switch (c->mmc) {
 364         case 1:
 365                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 366                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 367                         if (cpu_is_omap44xx()) {
 368                                 mmc->slots[0].before_set_reg =
 369                                                 omap4_hsmmc1_before_set_reg;
 370                                 mmc->slots[0].after_set_reg =
 371                                                 omap4_hsmmc1_after_set_reg;
 372                         } else {
 373                                 mmc->slots[0].before_set_reg =
 374                                                 omap_hsmmc1_before_set_reg;
 375                                 mmc->slots[0].after_set_reg =
 376                                                 omap_hsmmc1_after_set_reg;
 377                         }
 378                 }
 379
 380                 /* OMAP3630 HSMMC1 supports only 4-bit */
 381                 if (cpu_is_omap3630() &&
 382                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 383                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 384                         c->caps |= MMC_CAP_4_BIT_DATA;
 385                         mmc->slots[0].caps = c->caps;
 386                 }
 387                 break;
 388         case 2:
 389                 if (c->ext_clock)
 390                         c->transceiver = 1;
 391                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 392                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 393                         c->caps |= MMC_CAP_4_BIT_DATA;
 394                 }
 395                 /* FALLTHROUGH */
 396         case 3:
 397                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 398                         /* off-chip level shifting, or none */
 399                         mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
 400                         mmc->slots[0].after_set_reg = NULL;
 401                 }
 402                 break;
 403         case 4:
 404         case 5:
 405                 mmc->slots[0].before_set_reg = NULL;
 406                 mmc->slots[0].after_set_reg = NULL;
 407                 break;
 408         default:
 409                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 410                 kfree(hc_name);
 411                 return -ENODEV;
 412         }
 413         return 0;
 414 }
 415
 416 static struct omap_device_pm_latency omap_hsmmc_latency[] = {
 417         [0] = {
 418                 .deactivate_func = omap_device_idle_hwmods,
 419                 .activate_func   = omap_device_enable_hwmods,
 420                 .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
 421         },
 422         /*
 423          * XXX There should also be an entry here to power off/on the
 424          * MMC regulators/PBIAS cells, etc.
 425          */
 426 };
 427
 428 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 429
 430 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 431 {
 432         struct omap_hwmod *oh;
 433         struct omap_device *od;
 434         struct omap_device_pm_latency *ohl;
 435         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 436         struct omap_mmc_platform_data *mmc_data;
 437         struct omap_mmc_dev_attr *mmc_dev_attr;
 438         char *name;
 439         int l;
 440         int ohl_cnt = 0;
 441
 442         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 443         if (!mmc_data) {
 444                 pr_err("Cannot allocate memory for mmc device!\n");
 445                 goto done;
 446         }
 447
 448         if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
 449                 pr_err("%s fails!\n", __func__);
 450                 goto done;
 451         }
 452         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 453
 454         name = "omap_hsmmc";
 455         ohl = omap_hsmmc_latency;
 456         ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
 457
 458         l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 459                      "mmc%d", ctrl_nr);
 460         WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 461              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 462         oh = omap_hwmod_lookup(oh_name);
 463         if (!oh) {
 464                 pr_err("Could not look up %s\n", oh_name);
 465                 kfree(mmc_data->slots[0].name);
 466                 goto done;
 467         }
 468
 469         if (oh->dev_attr != NULL) {
 470                 mmc_dev_attr = oh->dev_attr;
 471                 mmc_data->controller_flags = mmc_dev_attr->flags;
 472         }
 473
 474         od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
 475                 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
 476         if (IS_ERR(od)) {
 477                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
 478                 kfree(mmc_data->slots[0].name);
 479                 goto done;
 480         }
 481         /*
 482          * return device handle to board setup code
 483          * required to populate for regulator framework structure
 484          */
 485         hsmmcinfo->dev = &od->pdev.dev;
 486
 487 done:
 488         kfree(mmc_data);
 489 }
 490
 491 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 492 {
 493         u32 reg;
 494
 495         if (!cpu_is_omap44xx()) {
 496                 if (cpu_is_omap2430()) {
 497                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 498                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 499                 } else {
 500                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 501                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 502                 }
 503         } else {
 504                 control_pbias_offset =
 505                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 506                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 507                 reg = omap4_ctrl_pad_readl(control_mmc1);
 508                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 509                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 510                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 511                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 512                 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
 513                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 514                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 515                 omap4_ctrl_pad_writel(reg, control_mmc1);
 516         }
 517
 518         for (; controllers->mmc; controllers++)
 519                 omap_init_hsmmc(controllers, controllers->mmc);
 520
 521 }
 522
 523 #endif