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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / arch / arm / mach-omap2 / id.c
blob37efb8696927bdf2c2d81cdf8b6a17c85ef772e2
1 /*
2 * linux/arch/arm/mach-omap2/id.c
3 *
4 * OMAP2 CPU identification code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21
22 #include <asm/cputype.h>
23
24 #include <plat/common.h>
25 #include <plat/cpu.h>
26
27 #include <mach/id.h>
28
29 #include "control.h"
30
31 static struct omap_chip_id omap_chip;
32 static unsigned int omap_revision;
33
34 u32 omap_features;
35
36 unsigned int omap_rev(void)
37 {
38 return omap_revision;
39 }
40 EXPORT_SYMBOL(omap_rev);
41
42 /**
43 * omap_chip_is - test whether currently running OMAP matches a chip type
44 * @oc: omap_chip_t to test against
45 *
46 * Test whether the currently-running OMAP chip matches the supplied
47 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
48 */
49 int omap_chip_is(struct omap_chip_id oci)
50 {
51 return (oci.oc & omap_chip.oc) ? 1 : 0;
52 }
53 EXPORT_SYMBOL(omap_chip_is);
54
55 int omap_type(void)
56 {
57 u32 val = 0;
58
59 if (cpu_is_omap24xx()) {
60 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
61 } else if (cpu_is_omap34xx()) {
62 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
63 } else if (cpu_is_omap44xx()) {
64 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
65 } else {
66 pr_err("Cannot detect omap type!\n");
67 goto out;
68 }
69
70 val &= OMAP2_DEVICETYPE_MASK;
71 val >>= 8;
72
73 out:
74 return val;
75 }
76 EXPORT_SYMBOL(omap_type);
77
78
79 /*----------------------------------------------------------------------------*/
80
81 #define OMAP_TAP_IDCODE 0x0204
82 #define OMAP_TAP_DIE_ID_0 0x0218
83 #define OMAP_TAP_DIE_ID_1 0x021C
84 #define OMAP_TAP_DIE_ID_2 0x0220
85 #define OMAP_TAP_DIE_ID_3 0x0224
86
87 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
88 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
89 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
90 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
91
92 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
93
94 struct omap_id {
95 u16 hawkeye; /* Silicon type (Hawkeye id) */
96 u8 dev; /* Device type from production_id reg */
97 u32 type; /* Combined type id copied to omap_revision */
98 };
99
100 /* Register values to detect the OMAP version */
101 static struct omap_id omap_ids[] __initdata = {
102 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
103 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
104 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
105 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
106 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
107 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
108 };
109
110 static void __iomem *tap_base;
111 static u16 tap_prod_id;
112
113 void omap_get_die_id(struct omap_die_id *odi)
114 {
115 if (cpu_is_omap44xx()) {
116 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
117 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
118 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
119 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
120
121 return;
122 }
123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
127 }
128
129 static void __init omap24xx_check_revision(void)
130 {
131 int i, j;
132 u32 idcode, prod_id;
133 u16 hawkeye;
134 u8 dev_type, rev;
135 struct omap_die_id odi;
136
137 idcode = read_tap_reg(OMAP_TAP_IDCODE);
138 prod_id = read_tap_reg(tap_prod_id);
139 hawkeye = (idcode >> 12) & 0xffff;
140 rev = (idcode >> 28) & 0x0f;
141 dev_type = (prod_id >> 16) & 0x0f;
142 omap_get_die_id(&odi);
143
144 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
145 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
146 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
147 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
148 odi.id_1, (odi.id_1 >> 28) & 0xf);
149 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
150 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
151 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
152 prod_id, dev_type);
153
154 /* Check hawkeye ids */
155 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
156 if (hawkeye == omap_ids[i].hawkeye)
157 break;
158 }
159
160 if (i == ARRAY_SIZE(omap_ids)) {
161 printk(KERN_ERR "Unknown OMAP CPU id\n");
162 return;
163 }
164
165 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
166 if (dev_type == omap_ids[j].dev)
167 break;
168 }
169
170 if (j == ARRAY_SIZE(omap_ids)) {
171 printk(KERN_ERR "Unknown OMAP device type. "
172 "Handling it as OMAP%04x\n",
173 omap_ids[i].type >> 16);
174 j = i;
175 }
176
177 pr_info("OMAP%04x", omap_rev() >> 16);
178 if ((omap_rev() >> 8) & 0x0f)
179 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
180 pr_info("\n");
181 }
182
183 #define OMAP3_CHECK_FEATURE(status,feat) \
184 if (((status & OMAP3_ ##feat## _MASK) \
185 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
186 omap_features |= OMAP3_HAS_ ##feat; \
187 }
188
189 static void __init omap3_check_features(void)
190 {
191 u32 status;
192
193 omap_features = 0;
194
195 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
196
197 OMAP3_CHECK_FEATURE(status, L2CACHE);
198 OMAP3_CHECK_FEATURE(status, IVA);
199 OMAP3_CHECK_FEATURE(status, SGX);
200 OMAP3_CHECK_FEATURE(status, NEON);
201 OMAP3_CHECK_FEATURE(status, ISP);
202 if (cpu_is_omap3630())
203 omap_features |= OMAP3_HAS_192MHZ_CLK;
204 if (!cpu_is_omap3505() && !cpu_is_omap3517())
205 omap_features |= OMAP3_HAS_IO_WAKEUP;
206
207 omap_features |= OMAP3_HAS_SDRC;
208
209 /*
210 * TODO: Get additional info (where applicable)
211 * e.g. Size of L2 cache.
212 */
213 }
214
215 static void __init omap4_check_features(void)
216 {
217 u32 si_type;
218
219 if (cpu_is_omap443x())
220 omap_features |= OMAP4_HAS_MPU_1GHZ;
221
222
223 if (cpu_is_omap446x()) {
224 si_type =
225 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
226 switch ((si_type & (3 << 16)) >> 16) {
227 case 2:
228 /* High performance device */
229 omap_features |= OMAP4_HAS_MPU_1_5GHZ;
230 break;
231 case 1:
232 default:
233 /* Standard device */
234 omap_features |= OMAP4_HAS_MPU_1_2GHZ;
235 break;
236 }
237 }
238 }
239
240 static void __init ti816x_check_features(void)
241 {
242 omap_features = OMAP3_HAS_NEON;
243 }
244
245 static void __init omap3_check_revision(void)
246 {
247 u32 cpuid, idcode;
248 u16 hawkeye;
249 u8 rev;
250
251 omap_chip.oc = CHIP_IS_OMAP3430;
252
253 /*
254 * We cannot access revision registers on ES1.0.
255 * If the processor type is Cortex-A8 and the revision is 0x0
256 * it means its Cortex r0p0 which is 3430 ES1.0.
257 */
258 cpuid = read_cpuid(CPUID_ID);
259 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
260 omap_revision = OMAP3430_REV_ES1_0;
261 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
262 return;
263 }
264
265 /*
266 * Detection for 34xx ES2.0 and above can be done with just
267 * hawkeye and rev. See TRM 1.5.2 Device Identification.
268 * Note that rev does not map directly to our defined processor
269 * revision numbers as ES1.0 uses value 0.
270 */
271 idcode = read_tap_reg(OMAP_TAP_IDCODE);
272 hawkeye = (idcode >> 12) & 0xffff;
273 rev = (idcode >> 28) & 0xff;
274
275 switch (hawkeye) {
276 case 0xb7ae:
277 /* Handle 34xx/35xx devices */
278 switch (rev) {
279 case 0: /* Take care of early samples */
280 case 1:
281 omap_revision = OMAP3430_REV_ES2_0;
282 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
283 break;
284 case 2:
285 omap_revision = OMAP3430_REV_ES2_1;
286 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
287 break;
288 case 3:
289 omap_revision = OMAP3430_REV_ES3_0;
290 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
291 break;
292 case 4:
293 omap_revision = OMAP3430_REV_ES3_1;
294 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
295 break;
296 case 7:
297 /* FALLTHROUGH */
298 default:
299 /* Use the latest known revision as default */
300 omap_revision = OMAP3430_REV_ES3_1_2;
301
302 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
303 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
304 }
305 break;
306 case 0xb868:
307 /* Handle OMAP35xx/AM35xx devices
308 *
309 * Set the device to be OMAP3505 here. Actual device
310 * is identified later based on the features.
311 *
312 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
313 */
314 omap_revision = OMAP3505_REV(rev);
315 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
316 break;
317 case 0xb891:
318 /* Handle 36xx devices */
319 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
320
321 switch(rev) {
322 case 0: /* Take care of early samples */
323 omap_revision = OMAP3630_REV_ES1_0;
324 break;
325 case 1:
326 omap_revision = OMAP3630_REV_ES1_1;
327 omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
328 break;
329 case 2:
330 default:
331 omap_revision = OMAP3630_REV_ES1_2;
332 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
333 }
334 break;
335 case 0xb81e:
336 omap_chip.oc = CHIP_IS_TI816X;
337
338 switch (rev) {
339 case 0:
340 omap_revision = TI8168_REV_ES1_0;
341 break;
342 case 1:
343 omap_revision = TI8168_REV_ES1_1;
344 break;
345 default:
346 omap_revision = TI8168_REV_ES1_1;
347 }
348 break;
349 default:
350 /* Unknown default to latest silicon rev as default*/
351 omap_revision = OMAP3630_REV_ES1_2;
352 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
353 }
354 }
355
356 static void __init omap4_check_revision(void)
357 {
358 u32 idcode;
359 u16 hawkeye;
360 u8 rev;
361
362 /*
363 * The IC rev detection is done with hawkeye and rev.
364 * Note that rev does not map directly to defined processor
365 * revision numbers as ES1.0 uses value 0.
366 */
367 idcode = read_tap_reg(OMAP_TAP_IDCODE);
368 hawkeye = (idcode >> 12) & 0xffff;
369 rev = (idcode >> 28) & 0xf;
370
371 /*
372 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
373 * Use ARM register to detect the correct ES version
374 */
375 if (!rev && (hawkeye != 0xb94e)) {
376 idcode = read_cpuid(CPUID_ID);
377 rev = (idcode & 0xf) - 1;
378 }
379
380 switch (hawkeye) {
381 case 0xb852:
382 switch (rev) {
383 case 0:
384 omap_revision = OMAP4430_REV_ES1_0;
385 omap_chip.oc |= CHIP_IS_OMAP4430ES1;
386 break;
387 case 1:
388 default:
389 omap_revision = OMAP4430_REV_ES2_0;
390 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
391 }
392 break;
393 case 0xb95c:
394 switch (rev) {
395 case 3:
396 omap_revision = OMAP4430_REV_ES2_1;
397 omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
398 break;
399 case 4:
400 default:
401 omap_revision = OMAP4430_REV_ES2_2;
402 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
403 }
404 break;
405 case 0xb94e:
406 switch (rev) {
407 case 0:
408 default:
409 omap_revision = OMAP4460_REV_ES1_0;
410 omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
411 break;
412 }
413 break;
414 default:
415 /* Unknown default to latest silicon rev as default */
416 omap_revision = OMAP4430_REV_ES2_2;
417 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
418 }
419
420 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
421 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
422 }
423
424 #define OMAP3_SHOW_FEATURE(feat) \
425 if (omap3_has_ ##feat()) \
426 printk(#feat" ");
427
428 static void __init omap3_cpuinfo(void)
429 {
430 u8 rev = GET_OMAP_REVISION();
431 char cpu_name[16], cpu_rev[16];
432
433 /* OMAP3430 and OMAP3530 are assumed to be same.
434 *
435 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
436 * on available features. Upon detection, update the CPU id
437 * and CPU class bits.
438 */
439 if (cpu_is_omap3630()) {
440 strcpy(cpu_name, "OMAP3630");
441 } else if (cpu_is_omap3505()) {
442 /*
443 * AM35xx devices
444 */
445 if (omap3_has_sgx()) {
446 omap_revision = OMAP3517_REV(rev);
447 strcpy(cpu_name, "AM3517");
448 } else {
449 /* Already set in omap3_check_revision() */
450 strcpy(cpu_name, "AM3505");
451 }
452 } else if (cpu_is_ti816x()) {
453 strcpy(cpu_name, "TI816X");
454 } else if (omap3_has_iva() && omap3_has_sgx()) {
455 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
456 strcpy(cpu_name, "OMAP3430/3530");
457 } else if (omap3_has_iva()) {
458 omap_revision = OMAP3525_REV(rev);
459 strcpy(cpu_name, "OMAP3525");
460 } else if (omap3_has_sgx()) {
461 omap_revision = OMAP3515_REV(rev);
462 strcpy(cpu_name, "OMAP3515");
463 } else {
464 omap_revision = OMAP3503_REV(rev);
465 strcpy(cpu_name, "OMAP3503");
466 }
467
468 if (cpu_is_omap3630() || cpu_is_ti816x()) {
469 switch (rev) {
470 case OMAP_REVBITS_00:
471 strcpy(cpu_rev, "1.0");
472 break;
473 case OMAP_REVBITS_01:
474 strcpy(cpu_rev, "1.1");
475 break;
476 case OMAP_REVBITS_02:
477 /* FALLTHROUGH */
478 default:
479 /* Use the latest known revision as default */
480 strcpy(cpu_rev, "1.2");
481 }
482 } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
483 switch (rev) {
484 case OMAP_REVBITS_00:
485 strcpy(cpu_rev, "1.0");
486 break;
487 case OMAP_REVBITS_01:
488 /* FALLTHROUGH */
489 default:
490 /* Use the latest known revision as default */
491 strcpy(cpu_rev, "1.1");
492 }
493 } else {
494 switch (rev) {
495 case OMAP_REVBITS_00:
496 strcpy(cpu_rev, "1.0");
497 break;
498 case OMAP_REVBITS_01:
499 strcpy(cpu_rev, "2.0");
500 break;
501 case OMAP_REVBITS_02:
502 strcpy(cpu_rev, "2.1");
503 break;
504 case OMAP_REVBITS_03:
505 strcpy(cpu_rev, "3.0");
506 break;
507 case OMAP_REVBITS_04:
508 strcpy(cpu_rev, "3.1");
509 break;
510 case OMAP_REVBITS_05:
511 /* FALLTHROUGH */
512 default:
513 /* Use the latest known revision as default */
514 strcpy(cpu_rev, "3.1.2");
515 }
516 }
517
518 /* Print verbose information */
519 pr_info("%s ES%s (", cpu_name, cpu_rev);
520
521 OMAP3_SHOW_FEATURE(l2cache);
522 OMAP3_SHOW_FEATURE(iva);
523 OMAP3_SHOW_FEATURE(sgx);
524 OMAP3_SHOW_FEATURE(neon);
525 OMAP3_SHOW_FEATURE(isp);
526 OMAP3_SHOW_FEATURE(192mhz_clk);
527
528 printk(")\n");
529 }
530
531 /*
532 * Try to detect the exact revision of the omap we're running on
533 */
534 void __init omap2_check_revision(void)
535 {
536 /*
537 * At this point we have an idea about the processor revision set
538 * earlier with omap2_set_globals_tap().
539 */
540 if (cpu_is_omap24xx()) {
541 omap24xx_check_revision();
542 } else if (cpu_is_omap34xx()) {
543 omap3_check_revision();
544
545 /* TI816X doesn't have feature register */
546 if (!cpu_is_ti816x())
547 omap3_check_features();
548 else
549 ti816x_check_features();
550
551 omap3_cpuinfo();
552 return;
553 } else if (cpu_is_omap44xx()) {
554 omap4_check_revision();
555 omap4_check_features();
556 return;
557 } else {
558 pr_err("OMAP revision unknown, please fix!\n");
559 }
560
561 /*
562 * OK, now we know the exact revision. Initialize omap_chip bits
563 * for powerdowmain and clockdomain code.
564 */
565 if (cpu_is_omap243x()) {
566 /* Currently only supports 2430ES2.1 and 2430-all */
567 omap_chip.oc |= CHIP_IS_OMAP2430;
568 return;
569 } else if (cpu_is_omap242x()) {
570 /* Currently only supports 2420ES2.1.1 and 2420-all */
571 omap_chip.oc |= CHIP_IS_OMAP2420;
572 return;
573 }
574
575 pr_err("Uninitialized omap_chip, please fix!\n");
576 }
577
578 /*
579 * Set up things for map_io and processor detection later on. Gets called
580 * pretty much first thing from board init. For multi-omap, this gets
581 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
582 * detect the exact revision later on in omap2_detect_revision() once map_io
583 * is done.
584 */
585 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
586 {
587 omap_revision = omap2_globals->class;
588 tap_base = omap2_globals->tap;
589
590 if (cpu_is_omap34xx())
591 tap_prod_id = 0x0210;
592 else
593 tap_prod_id = 0x0208;
594 }
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