arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/mmc.h>
  25 #include <plat/l3_2xxx.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "prm-regbits-24xx.h"
  30 #include "cm-regbits-24xx.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * ALl of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 static struct omap_hwmod omap2430_mpu_hwmod;
  43 static struct omap_hwmod omap2430_iva_hwmod;
  44 static struct omap_hwmod omap2430_l3_main_hwmod;
  45 static struct omap_hwmod omap2430_l4_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_core_hwmod;
  47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  49 static struct omap_hwmod omap2430_dss_venc_hwmod;
  50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  51 static struct omap_hwmod omap2430_gpio1_hwmod;
  52 static struct omap_hwmod omap2430_gpio2_hwmod;
  53 static struct omap_hwmod omap2430_gpio3_hwmod;
  54 static struct omap_hwmod omap2430_gpio4_hwmod;
  55 static struct omap_hwmod omap2430_gpio5_hwmod;
  56 static struct omap_hwmod omap2430_dma_system_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  62 static struct omap_hwmod omap2430_mcspi1_hwmod;
  63 static struct omap_hwmod omap2430_mcspi2_hwmod;
  64 static struct omap_hwmod omap2430_mcspi3_hwmod;
  65 static struct omap_hwmod omap2430_mmc1_hwmod;
  66 static struct omap_hwmod omap2430_mmc2_hwmod;
  67
  68 /* L3 -> L4_CORE interface */
  69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  70         .master = &omap2430_l3_main_hwmod,
  71         .slave  = &omap2430_l4_core_hwmod,
  72         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  73 };
  74
  75 /* MPU -> L3 interface */
  76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  77         .master = &omap2430_mpu_hwmod,
  78         .slave  = &omap2430_l3_main_hwmod,
  79         .user   = OCP_USER_MPU,
  80 };
  81
  82 /* Slave interfaces on the L3 interconnect */
  83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  84         &omap2430_mpu__l3_main,
  85 };
  86
  87 /* DSS -> l3 */
  88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  89         .master         = &omap2430_dss_core_hwmod,
  90         .slave          = &omap2430_l3_main_hwmod,
  91         .fw = {
  92                 .omap2 = {
  93                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  94                         .flags  = OMAP_FIREWALL_L3,
  95                 }
  96         },
  97         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  98 };
  99
 100 /* Master interfaces on the L3 interconnect */
 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
 102         &omap2430_l3_main__l4_core,
 103 };
 104
 105 /* L3 */
 106 static struct omap_hwmod omap2430_l3_main_hwmod = {
 107         .name           = "l3_main",
 108         .class          = &l3_hwmod_class,
 109         .masters        = omap2430_l3_main_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 111         .slaves         = omap2430_l3_main_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 114         .flags          = HWMOD_NO_IDLEST,
 115 };
 116
 117 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 118 static struct omap_hwmod omap2430_uart1_hwmod;
 119 static struct omap_hwmod omap2430_uart2_hwmod;
 120 static struct omap_hwmod omap2430_uart3_hwmod;
 121 static struct omap_hwmod omap2430_i2c1_hwmod;
 122 static struct omap_hwmod omap2430_i2c2_hwmod;
 123
 124 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 125
 126 /* l3_core -> usbhsotg  interface */
 127 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 128         .master         = &omap2430_usbhsotg_hwmod,
 129         .slave          = &omap2430_l3_main_hwmod,
 130         .clk            = "core_l3_ck",
 131         .user           = OCP_USER_MPU,
 132 };
 133
 134 /* L4 CORE -> I2C1 interface */
 135 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 136         .master         = &omap2430_l4_core_hwmod,
 137         .slave          = &omap2430_i2c1_hwmod,
 138         .clk            = "i2c1_ick",
 139         .addr           = omap2_i2c1_addr_space,
 140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 141 };
 142
 143 /* L4 CORE -> I2C2 interface */
 144 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 145         .master         = &omap2430_l4_core_hwmod,
 146         .slave          = &omap2430_i2c2_hwmod,
 147         .clk            = "i2c2_ick",
 148         .addr           = omap2_i2c2_addr_space,
 149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 150 };
 151
 152 /* L4_CORE -> L4_WKUP interface */
 153 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 154         .master = &omap2430_l4_core_hwmod,
 155         .slave  = &omap2430_l4_wkup_hwmod,
 156         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 CORE -> UART1 interface */
 160 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 161         .master         = &omap2430_l4_core_hwmod,
 162         .slave          = &omap2430_uart1_hwmod,
 163         .clk            = "uart1_ick",
 164         .addr           = omap2xxx_uart1_addr_space,
 165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 166 };
 167
 168 /* L4 CORE -> UART2 interface */
 169 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 170         .master         = &omap2430_l4_core_hwmod,
 171         .slave          = &omap2430_uart2_hwmod,
 172         .clk            = "uart2_ick",
 173         .addr           = omap2xxx_uart2_addr_space,
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 PER -> UART3 interface */
 178 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 179         .master         = &omap2430_l4_core_hwmod,
 180         .slave          = &omap2430_uart3_hwmod,
 181         .clk            = "uart3_ick",
 182         .addr           = omap2xxx_uart3_addr_space,
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /*
 187 * usbhsotg interface data
 188 */
 189 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 190         {
 191                 .pa_start       = OMAP243X_HS_BASE,
 192                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 193                 .flags          = ADDR_TYPE_RT
 194         },
 195 };
 196
 197 /*  l4_core ->usbhsotg  interface */
 198 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 199         .master         = &omap2430_l4_core_hwmod,
 200         .slave          = &omap2430_usbhsotg_hwmod,
 201         .clk            = "usb_l4_ick",
 202         .addr           = omap2430_usbhsotg_addrs,
 203         .user           = OCP_USER_MPU,
 204 };
 205
 206 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 207         &omap2430_usbhsotg__l3,
 208 };
 209
 210 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 211         &omap2430_l4_core__usbhsotg,
 212 };
 213
 214 /* L4 CORE -> MMC1 interface */
 215 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 216         .master         = &omap2430_l4_core_hwmod,
 217         .slave          = &omap2430_mmc1_hwmod,
 218         .clk            = "mmchs1_ick",
 219         .addr           = omap2430_mmc1_addr_space,
 220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 221 };
 222
 223 /* L4 CORE -> MMC2 interface */
 224 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 225         .master         = &omap2430_l4_core_hwmod,
 226         .slave          = &omap2430_mmc2_hwmod,
 227         .clk            = "mmchs2_ick",
 228         .addr           = omap2430_mmc2_addr_space,
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* Slave interfaces on the L4_CORE interconnect */
 233 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 234         &omap2430_l3_main__l4_core,
 235 };
 236
 237 /* Master interfaces on the L4_CORE interconnect */
 238 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 239         &omap2430_l4_core__l4_wkup,
 240         &omap2430_l4_core__mmc1,
 241         &omap2430_l4_core__mmc2,
 242 };
 243
 244 /* L4 CORE */
 245 static struct omap_hwmod omap2430_l4_core_hwmod = {
 246         .name           = "l4_core",
 247         .class          = &l4_hwmod_class,
 248         .masters        = omap2430_l4_core_masters,
 249         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 250         .slaves         = omap2430_l4_core_slaves,
 251         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 252         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 253         .flags          = HWMOD_NO_IDLEST,
 254 };
 255
 256 /* Slave interfaces on the L4_WKUP interconnect */
 257 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 258         &omap2430_l4_core__l4_wkup,
 259         &omap2_l4_core__uart1,
 260         &omap2_l4_core__uart2,
 261         &omap2_l4_core__uart3,
 262 };
 263
 264 /* Master interfaces on the L4_WKUP interconnect */
 265 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 266 };
 267
 268 /* l4 core -> mcspi1 interface */
 269 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 270         .master         = &omap2430_l4_core_hwmod,
 271         .slave          = &omap2430_mcspi1_hwmod,
 272         .clk            = "mcspi1_ick",
 273         .addr           = omap2_mcspi1_addr_space,
 274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 275 };
 276
 277 /* l4 core -> mcspi2 interface */
 278 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 279         .master         = &omap2430_l4_core_hwmod,
 280         .slave          = &omap2430_mcspi2_hwmod,
 281         .clk            = "mcspi2_ick",
 282         .addr           = omap2_mcspi2_addr_space,
 283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 284 };
 285
 286 /* l4 core -> mcspi3 interface */
 287 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 288         .master         = &omap2430_l4_core_hwmod,
 289         .slave          = &omap2430_mcspi3_hwmod,
 290         .clk            = "mcspi3_ick",
 291         .addr           = omap2430_mcspi3_addr_space,
 292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 293 };
 294
 295 /* L4 WKUP */
 296 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 297         .name           = "l4_wkup",
 298         .class          = &l4_hwmod_class,
 299         .masters        = omap2430_l4_wkup_masters,
 300         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 301         .slaves         = omap2430_l4_wkup_slaves,
 302         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 303         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 304         .flags          = HWMOD_NO_IDLEST,
 305 };
 306
 307 /* Master interfaces on the MPU device */
 308 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 309         &omap2430_mpu__l3_main,
 310 };
 311
 312 /* MPU */
 313 static struct omap_hwmod omap2430_mpu_hwmod = {
 314         .name           = "mpu",
 315         .class          = &mpu_hwmod_class,
 316         .main_clk       = "mpu_ck",
 317         .masters        = omap2430_mpu_masters,
 318         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 319         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 320 };
 321
 322 /*
 323  * IVA2_1 interface data
 324  */
 325
 326 /* IVA2 <- L3 interface */
 327 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 328         .master         = &omap2430_l3_main_hwmod,
 329         .slave          = &omap2430_iva_hwmod,
 330         .clk            = "dsp_fck",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 335         &omap2430_l3__iva,
 336 };
 337
 338 /*
 339  * IVA2 (IVA2)
 340  */
 341
 342 static struct omap_hwmod omap2430_iva_hwmod = {
 343         .name           = "iva",
 344         .class          = &iva_hwmod_class,
 345         .masters        = omap2430_iva_masters,
 346         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 347         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 348 };
 349
 350 /* timer1 */
 351 static struct omap_hwmod omap2430_timer1_hwmod;
 352
 353 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 354         {
 355                 .pa_start       = 0x49018000,
 356                 .pa_end         = 0x49018000 + SZ_1K - 1,
 357                 .flags          = ADDR_TYPE_RT
 358         },
 359         { }
 360 };
 361
 362 /* l4_wkup -> timer1 */
 363 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 364         .master         = &omap2430_l4_wkup_hwmod,
 365         .slave          = &omap2430_timer1_hwmod,
 366         .clk            = "gpt1_ick",
 367         .addr           = omap2430_timer1_addrs,
 368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 369 };
 370
 371 /* timer1 slave port */
 372 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 373         &omap2430_l4_wkup__timer1,
 374 };
 375
 376 /* timer1 hwmod */
 377 static struct omap_hwmod omap2430_timer1_hwmod = {
 378         .name           = "timer1",
 379         .mpu_irqs       = omap2_timer1_mpu_irqs,
 380         .main_clk       = "gpt1_fck",
 381         .prcm           = {
 382                 .omap2 = {
 383                         .prcm_reg_id = 1,
 384                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 385                         .module_offs = WKUP_MOD,
 386                         .idlest_reg_id = 1,
 387                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 388                 },
 389         },
 390         .slaves         = omap2430_timer1_slaves,
 391         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 392         .class          = &omap2xxx_timer_hwmod_class,
 393         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 394 };
 395
 396 /* timer2 */
 397 static struct omap_hwmod omap2430_timer2_hwmod;
 398
 399 /* l4_core -> timer2 */
 400 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 401         .master         = &omap2430_l4_core_hwmod,
 402         .slave          = &omap2430_timer2_hwmod,
 403         .clk            = "gpt2_ick",
 404         .addr           = omap2xxx_timer2_addrs,
 405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 406 };
 407
 408 /* timer2 slave port */
 409 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 410         &omap2430_l4_core__timer2,
 411 };
 412
 413 /* timer2 hwmod */
 414 static struct omap_hwmod omap2430_timer2_hwmod = {
 415         .name           = "timer2",
 416         .mpu_irqs       = omap2_timer2_mpu_irqs,
 417         .main_clk       = "gpt2_fck",
 418         .prcm           = {
 419                 .omap2 = {
 420                         .prcm_reg_id = 1,
 421                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 422                         .module_offs = CORE_MOD,
 423                         .idlest_reg_id = 1,
 424                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 425                 },
 426         },
 427         .slaves         = omap2430_timer2_slaves,
 428         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 429         .class          = &omap2xxx_timer_hwmod_class,
 430         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 431 };
 432
 433 /* timer3 */
 434 static struct omap_hwmod omap2430_timer3_hwmod;
 435
 436 /* l4_core -> timer3 */
 437 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 438         .master         = &omap2430_l4_core_hwmod,
 439         .slave          = &omap2430_timer3_hwmod,
 440         .clk            = "gpt3_ick",
 441         .addr           = omap2xxx_timer3_addrs,
 442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 443 };
 444
 445 /* timer3 slave port */
 446 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 447         &omap2430_l4_core__timer3,
 448 };
 449
 450 /* timer3 hwmod */
 451 static struct omap_hwmod omap2430_timer3_hwmod = {
 452         .name           = "timer3",
 453         .mpu_irqs       = omap2_timer3_mpu_irqs,
 454         .main_clk       = "gpt3_fck",
 455         .prcm           = {
 456                 .omap2 = {
 457                         .prcm_reg_id = 1,
 458                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 459                         .module_offs = CORE_MOD,
 460                         .idlest_reg_id = 1,
 461                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 462                 },
 463         },
 464         .slaves         = omap2430_timer3_slaves,
 465         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 466         .class          = &omap2xxx_timer_hwmod_class,
 467         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 468 };
 469
 470 /* timer4 */
 471 static struct omap_hwmod omap2430_timer4_hwmod;
 472
 473 /* l4_core -> timer4 */
 474 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 475         .master         = &omap2430_l4_core_hwmod,
 476         .slave          = &omap2430_timer4_hwmod,
 477         .clk            = "gpt4_ick",
 478         .addr           = omap2xxx_timer4_addrs,
 479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 480 };
 481
 482 /* timer4 slave port */
 483 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 484         &omap2430_l4_core__timer4,
 485 };
 486
 487 /* timer4 hwmod */
 488 static struct omap_hwmod omap2430_timer4_hwmod = {
 489         .name           = "timer4",
 490         .mpu_irqs       = omap2_timer4_mpu_irqs,
 491         .main_clk       = "gpt4_fck",
 492         .prcm           = {
 493                 .omap2 = {
 494                         .prcm_reg_id = 1,
 495                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 496                         .module_offs = CORE_MOD,
 497                         .idlest_reg_id = 1,
 498                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 499                 },
 500         },
 501         .slaves         = omap2430_timer4_slaves,
 502         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 503         .class          = &omap2xxx_timer_hwmod_class,
 504         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 505 };
 506
 507 /* timer5 */
 508 static struct omap_hwmod omap2430_timer5_hwmod;
 509
 510 /* l4_core -> timer5 */
 511 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 512         .master         = &omap2430_l4_core_hwmod,
 513         .slave          = &omap2430_timer5_hwmod,
 514         .clk            = "gpt5_ick",
 515         .addr           = omap2xxx_timer5_addrs,
 516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 517 };
 518
 519 /* timer5 slave port */
 520 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 521         &omap2430_l4_core__timer5,
 522 };
 523
 524 /* timer5 hwmod */
 525 static struct omap_hwmod omap2430_timer5_hwmod = {
 526         .name           = "timer5",
 527         .mpu_irqs       = omap2_timer5_mpu_irqs,
 528         .main_clk       = "gpt5_fck",
 529         .prcm           = {
 530                 .omap2 = {
 531                         .prcm_reg_id = 1,
 532                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 533                         .module_offs = CORE_MOD,
 534                         .idlest_reg_id = 1,
 535                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 536                 },
 537         },
 538         .slaves         = omap2430_timer5_slaves,
 539         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 540         .class          = &omap2xxx_timer_hwmod_class,
 541         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 542 };
 543
 544 /* timer6 */
 545 static struct omap_hwmod omap2430_timer6_hwmod;
 546
 547 /* l4_core -> timer6 */
 548 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 549         .master         = &omap2430_l4_core_hwmod,
 550         .slave          = &omap2430_timer6_hwmod,
 551         .clk            = "gpt6_ick",
 552         .addr           = omap2xxx_timer6_addrs,
 553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 554 };
 555
 556 /* timer6 slave port */
 557 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 558         &omap2430_l4_core__timer6,
 559 };
 560
 561 /* timer6 hwmod */
 562 static struct omap_hwmod omap2430_timer6_hwmod = {
 563         .name           = "timer6",
 564         .mpu_irqs       = omap2_timer6_mpu_irqs,
 565         .main_clk       = "gpt6_fck",
 566         .prcm           = {
 567                 .omap2 = {
 568                         .prcm_reg_id = 1,
 569                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 570                         .module_offs = CORE_MOD,
 571                         .idlest_reg_id = 1,
 572                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 573                 },
 574         },
 575         .slaves         = omap2430_timer6_slaves,
 576         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 577         .class          = &omap2xxx_timer_hwmod_class,
 578         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 579 };
 580
 581 /* timer7 */
 582 static struct omap_hwmod omap2430_timer7_hwmod;
 583
 584 /* l4_core -> timer7 */
 585 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 586         .master         = &omap2430_l4_core_hwmod,
 587         .slave          = &omap2430_timer7_hwmod,
 588         .clk            = "gpt7_ick",
 589         .addr           = omap2xxx_timer7_addrs,
 590         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 591 };
 592
 593 /* timer7 slave port */
 594 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 595         &omap2430_l4_core__timer7,
 596 };
 597
 598 /* timer7 hwmod */
 599 static struct omap_hwmod omap2430_timer7_hwmod = {
 600         .name           = "timer7",
 601         .mpu_irqs       = omap2_timer7_mpu_irqs,
 602         .main_clk       = "gpt7_fck",
 603         .prcm           = {
 604                 .omap2 = {
 605                         .prcm_reg_id = 1,
 606                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 607                         .module_offs = CORE_MOD,
 608                         .idlest_reg_id = 1,
 609                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 610                 },
 611         },
 612         .slaves         = omap2430_timer7_slaves,
 613         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 614         .class          = &omap2xxx_timer_hwmod_class,
 615         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 616 };
 617
 618 /* timer8 */
 619 static struct omap_hwmod omap2430_timer8_hwmod;
 620
 621 /* l4_core -> timer8 */
 622 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 623         .master         = &omap2430_l4_core_hwmod,
 624         .slave          = &omap2430_timer8_hwmod,
 625         .clk            = "gpt8_ick",
 626         .addr           = omap2xxx_timer8_addrs,
 627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 628 };
 629
 630 /* timer8 slave port */
 631 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 632         &omap2430_l4_core__timer8,
 633 };
 634
 635 /* timer8 hwmod */
 636 static struct omap_hwmod omap2430_timer8_hwmod = {
 637         .name           = "timer8",
 638         .mpu_irqs       = omap2_timer8_mpu_irqs,
 639         .main_clk       = "gpt8_fck",
 640         .prcm           = {
 641                 .omap2 = {
 642                         .prcm_reg_id = 1,
 643                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 644                         .module_offs = CORE_MOD,
 645                         .idlest_reg_id = 1,
 646                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 647                 },
 648         },
 649         .slaves         = omap2430_timer8_slaves,
 650         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 651         .class          = &omap2xxx_timer_hwmod_class,
 652         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 653 };
 654
 655 /* timer9 */
 656 static struct omap_hwmod omap2430_timer9_hwmod;
 657
 658 /* l4_core -> timer9 */
 659 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 660         .master         = &omap2430_l4_core_hwmod,
 661         .slave          = &omap2430_timer9_hwmod,
 662         .clk            = "gpt9_ick",
 663         .addr           = omap2xxx_timer9_addrs,
 664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 665 };
 666
 667 /* timer9 slave port */
 668 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 669         &omap2430_l4_core__timer9,
 670 };
 671
 672 /* timer9 hwmod */
 673 static struct omap_hwmod omap2430_timer9_hwmod = {
 674         .name           = "timer9",
 675         .mpu_irqs       = omap2_timer9_mpu_irqs,
 676         .main_clk       = "gpt9_fck",
 677         .prcm           = {
 678                 .omap2 = {
 679                         .prcm_reg_id = 1,
 680                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 681                         .module_offs = CORE_MOD,
 682                         .idlest_reg_id = 1,
 683                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 684                 },
 685         },
 686         .slaves         = omap2430_timer9_slaves,
 687         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 688         .class          = &omap2xxx_timer_hwmod_class,
 689         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 690 };
 691
 692 /* timer10 */
 693 static struct omap_hwmod omap2430_timer10_hwmod;
 694
 695 /* l4_core -> timer10 */
 696 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 697         .master         = &omap2430_l4_core_hwmod,
 698         .slave          = &omap2430_timer10_hwmod,
 699         .clk            = "gpt10_ick",
 700         .addr           = omap2_timer10_addrs,
 701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 702 };
 703
 704 /* timer10 slave port */
 705 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 706         &omap2430_l4_core__timer10,
 707 };
 708
 709 /* timer10 hwmod */
 710 static struct omap_hwmod omap2430_timer10_hwmod = {
 711         .name           = "timer10",
 712         .mpu_irqs       = omap2_timer10_mpu_irqs,
 713         .main_clk       = "gpt10_fck",
 714         .prcm           = {
 715                 .omap2 = {
 716                         .prcm_reg_id = 1,
 717                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 718                         .module_offs = CORE_MOD,
 719                         .idlest_reg_id = 1,
 720                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 721                 },
 722         },
 723         .slaves         = omap2430_timer10_slaves,
 724         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 725         .class          = &omap2xxx_timer_hwmod_class,
 726         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 727 };
 728
 729 /* timer11 */
 730 static struct omap_hwmod omap2430_timer11_hwmod;
 731
 732 /* l4_core -> timer11 */
 733 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 734         .master         = &omap2430_l4_core_hwmod,
 735         .slave          = &omap2430_timer11_hwmod,
 736         .clk            = "gpt11_ick",
 737         .addr           = omap2_timer11_addrs,
 738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 739 };
 740
 741 /* timer11 slave port */
 742 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 743         &omap2430_l4_core__timer11,
 744 };
 745
 746 /* timer11 hwmod */
 747 static struct omap_hwmod omap2430_timer11_hwmod = {
 748         .name           = "timer11",
 749         .mpu_irqs       = omap2_timer11_mpu_irqs,
 750         .main_clk       = "gpt11_fck",
 751         .prcm           = {
 752                 .omap2 = {
 753                         .prcm_reg_id = 1,
 754                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 755                         .module_offs = CORE_MOD,
 756                         .idlest_reg_id = 1,
 757                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 758                 },
 759         },
 760         .slaves         = omap2430_timer11_slaves,
 761         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
 762         .class          = &omap2xxx_timer_hwmod_class,
 763         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 764 };
 765
 766 /* timer12 */
 767 static struct omap_hwmod omap2430_timer12_hwmod;
 768
 769 /* l4_core -> timer12 */
 770 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
 771         .master         = &omap2430_l4_core_hwmod,
 772         .slave          = &omap2430_timer12_hwmod,
 773         .clk            = "gpt12_ick",
 774         .addr           = omap2xxx_timer12_addrs,
 775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 776 };
 777
 778 /* timer12 slave port */
 779 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 780         &omap2430_l4_core__timer12,
 781 };
 782
 783 /* timer12 hwmod */
 784 static struct omap_hwmod omap2430_timer12_hwmod = {
 785         .name           = "timer12",
 786         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 787         .main_clk       = "gpt12_fck",
 788         .prcm           = {
 789                 .omap2 = {
 790                         .prcm_reg_id = 1,
 791                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 792                         .module_offs = CORE_MOD,
 793                         .idlest_reg_id = 1,
 794                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 795                 },
 796         },
 797         .slaves         = omap2430_timer12_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
 799         .class          = &omap2xxx_timer_hwmod_class,
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 801 };
 802
 803 /* l4_wkup -> wd_timer2 */
 804 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 805         {
 806                 .pa_start       = 0x49016000,
 807                 .pa_end         = 0x4901607f,
 808                 .flags          = ADDR_TYPE_RT
 809         },
 810         { }
 811 };
 812
 813 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 814         .master         = &omap2430_l4_wkup_hwmod,
 815         .slave          = &omap2430_wd_timer2_hwmod,
 816         .clk            = "mpu_wdt_ick",
 817         .addr           = omap2430_wd_timer2_addrs,
 818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 819 };
 820
 821 /* wd_timer2 */
 822 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 823         &omap2430_l4_wkup__wd_timer2,
 824 };
 825
 826 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 827         .name           = "wd_timer2",
 828         .class          = &omap2xxx_wd_timer_hwmod_class,
 829         .main_clk       = "mpu_wdt_fck",
 830         .prcm           = {
 831                 .omap2 = {
 832                         .prcm_reg_id = 1,
 833                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 834                         .module_offs = WKUP_MOD,
 835                         .idlest_reg_id = 1,
 836                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 837                 },
 838         },
 839         .slaves         = omap2430_wd_timer2_slaves,
 840         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
 841         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 842 };
 843
 844 /* UART1 */
 845
 846 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
 847         &omap2_l4_core__uart1,
 848 };
 849
 850 static struct omap_hwmod omap2430_uart1_hwmod = {
 851         .name           = "uart1",
 852         .mpu_irqs       = omap2_uart1_mpu_irqs,
 853         .sdma_reqs      = omap2_uart1_sdma_reqs,
 854         .main_clk       = "uart1_fck",
 855         .prcm           = {
 856                 .omap2 = {
 857                         .module_offs = CORE_MOD,
 858                         .prcm_reg_id = 1,
 859                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 860                         .idlest_reg_id = 1,
 861                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 862                 },
 863         },
 864         .slaves         = omap2430_uart1_slaves,
 865         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
 866         .class          = &omap2_uart_class,
 867         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 868 };
 869
 870 /* UART2 */
 871
 872 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
 873         &omap2_l4_core__uart2,
 874 };
 875
 876 static struct omap_hwmod omap2430_uart2_hwmod = {
 877         .name           = "uart2",
 878         .mpu_irqs       = omap2_uart2_mpu_irqs,
 879         .sdma_reqs      = omap2_uart2_sdma_reqs,
 880         .main_clk       = "uart2_fck",
 881         .prcm           = {
 882                 .omap2 = {
 883                         .module_offs = CORE_MOD,
 884                         .prcm_reg_id = 1,
 885                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 886                         .idlest_reg_id = 1,
 887                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 888                 },
 889         },
 890         .slaves         = omap2430_uart2_slaves,
 891         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
 892         .class          = &omap2_uart_class,
 893         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 894 };
 895
 896 /* UART3 */
 897
 898 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
 899         &omap2_l4_core__uart3,
 900 };
 901
 902 static struct omap_hwmod omap2430_uart3_hwmod = {
 903         .name           = "uart3",
 904         .mpu_irqs       = omap2_uart3_mpu_irqs,
 905         .sdma_reqs      = omap2_uart3_sdma_reqs,
 906         .main_clk       = "uart3_fck",
 907         .prcm           = {
 908                 .omap2 = {
 909                         .module_offs = CORE_MOD,
 910                         .prcm_reg_id = 2,
 911                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 912                         .idlest_reg_id = 2,
 913                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 914                 },
 915         },
 916         .slaves         = omap2430_uart3_slaves,
 917         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
 918         .class          = &omap2_uart_class,
 919         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 920 };
 921
 922 /* dss */
 923 /* dss master ports */
 924 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
 925         &omap2430_dss__l3,
 926 };
 927
 928 /* l4_core -> dss */
 929 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
 930         .master         = &omap2430_l4_core_hwmod,
 931         .slave          = &omap2430_dss_core_hwmod,
 932         .clk            = "dss_ick",
 933         .addr           = omap2_dss_addrs,
 934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 935 };
 936
 937 /* dss slave ports */
 938 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 939         &omap2430_l4_core__dss,
 940 };
 941
 942 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 943         { .role = "tv_clk", .clk = "dss_54m_fck" },
 944         { .role = "sys_clk", .clk = "dss2_fck" },
 945 };
 946
 947 static struct omap_hwmod omap2430_dss_core_hwmod = {
 948         .name           = "dss_core",
 949         .class          = &omap2_dss_hwmod_class,
 950         .main_clk       = "dss1_fck", /* instead of dss_fck */
 951         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 952         .prcm           = {
 953                 .omap2 = {
 954                         .prcm_reg_id = 1,
 955                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 956                         .module_offs = CORE_MOD,
 957                         .idlest_reg_id = 1,
 958                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 959                 },
 960         },
 961         .opt_clks       = dss_opt_clks,
 962         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 963         .slaves         = omap2430_dss_slaves,
 964         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
 965         .masters        = omap2430_dss_masters,
 966         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
 967         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 968         .flags          = HWMOD_NO_IDLEST,
 969 };
 970
 971 /* l4_core -> dss_dispc */
 972 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
 973         .master         = &omap2430_l4_core_hwmod,
 974         .slave          = &omap2430_dss_dispc_hwmod,
 975         .clk            = "dss_ick",
 976         .addr           = omap2_dss_dispc_addrs,
 977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 978 };
 979
 980 /* dss_dispc slave ports */
 981 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
 982         &omap2430_l4_core__dss_dispc,
 983 };
 984
 985 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
 986         .name           = "dss_dispc",
 987         .class          = &omap2_dispc_hwmod_class,
 988         .mpu_irqs       = omap2_dispc_irqs,
 989         .main_clk       = "dss1_fck",
 990         .prcm           = {
 991                 .omap2 = {
 992                         .prcm_reg_id = 1,
 993                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 994                         .module_offs = CORE_MOD,
 995                         .idlest_reg_id = 1,
 996                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 997                 },
 998         },
 999         .slaves         = omap2430_dss_dispc_slaves,
1000         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1001         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1002         .flags          = HWMOD_NO_IDLEST,
1003 };
1004
1005 /* l4_core -> dss_rfbi */
1006 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1007         .master         = &omap2430_l4_core_hwmod,
1008         .slave          = &omap2430_dss_rfbi_hwmod,
1009         .clk            = "dss_ick",
1010         .addr           = omap2_dss_rfbi_addrs,
1011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1012 };
1013
1014 /* dss_rfbi slave ports */
1015 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1016         &omap2430_l4_core__dss_rfbi,
1017 };
1018
1019 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1020         .name           = "dss_rfbi",
1021         .class          = &omap2_rfbi_hwmod_class,
1022         .main_clk       = "dss1_fck",
1023         .prcm           = {
1024                 .omap2 = {
1025                         .prcm_reg_id = 1,
1026                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1027                         .module_offs = CORE_MOD,
1028                 },
1029         },
1030         .slaves         = omap2430_dss_rfbi_slaves,
1031         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1032         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1033         .flags          = HWMOD_NO_IDLEST,
1034 };
1035
1036 /* l4_core -> dss_venc */
1037 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1038         .master         = &omap2430_l4_core_hwmod,
1039         .slave          = &omap2430_dss_venc_hwmod,
1040         .clk            = "dss_54m_fck",
1041         .addr           = omap2_dss_venc_addrs,
1042         .flags          = OCPIF_SWSUP_IDLE,
1043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1044 };
1045
1046 /* dss_venc slave ports */
1047 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1048         &omap2430_l4_core__dss_venc,
1049 };
1050
1051 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1052         .name           = "dss_venc",
1053         .class          = &omap2_venc_hwmod_class,
1054         .main_clk       = "dss1_fck",
1055         .prcm           = {
1056                 .omap2 = {
1057                         .prcm_reg_id = 1,
1058                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1059                         .module_offs = CORE_MOD,
1060                 },
1061         },
1062         .slaves         = omap2430_dss_venc_slaves,
1063         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1064         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1065         .flags          = HWMOD_NO_IDLEST,
1066 };
1067
1068 /* I2C common */
1069 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1070         .rev_offs       = 0x00,
1071         .sysc_offs      = 0x20,
1072         .syss_offs      = 0x10,
1073         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1074                            SYSS_HAS_RESET_STATUS),
1075         .sysc_fields    = &omap_hwmod_sysc_type1,
1076 };
1077
1078 static struct omap_hwmod_class i2c_class = {
1079         .name           = "i2c",
1080         .sysc           = &i2c_sysc,
1081         .rev            = OMAP_I2C_IP_VERSION_1,
1082         .reset          = &omap_i2c_reset,
1083 };
1084
1085 static struct omap_i2c_dev_attr i2c_dev_attr = {
1086         .fifo_depth     = 8, /* bytes */
1087         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1088                           OMAP_I2C_FLAG_BUS_SHIFT_2 |
1089                           OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1090 };
1091
1092 /* I2C1 */
1093
1094 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1095         &omap2430_l4_core__i2c1,
1096 };
1097
1098 static struct omap_hwmod omap2430_i2c1_hwmod = {
1099         .name           = "i2c1",
1100         .flags          = HWMOD_16BIT_REG,
1101         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1102         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1103         .main_clk       = "i2chs1_fck",
1104         .prcm           = {
1105                 .omap2 = {
1106                         /*
1107                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1108                          * I2CHS IP's do not follow the usual pattern.
1109                          * prcm_reg_id alone cannot be used to program
1110                          * the iclk and fclk. Needs to be handled using
1111                          * additional flags when clk handling is moved
1112                          * to hwmod framework.
1113                          */
1114                         .module_offs = CORE_MOD,
1115                         .prcm_reg_id = 1,
1116                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1117                         .idlest_reg_id = 1,
1118                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1119                 },
1120         },
1121         .slaves         = omap2430_i2c1_slaves,
1122         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1123         .class          = &i2c_class,
1124         .dev_attr       = &i2c_dev_attr,
1125         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1126 };
1127
1128 /* I2C2 */
1129
1130 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1131         &omap2430_l4_core__i2c2,
1132 };
1133
1134 static struct omap_hwmod omap2430_i2c2_hwmod = {
1135         .name           = "i2c2",
1136         .flags          = HWMOD_16BIT_REG,
1137         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1138         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1139         .main_clk       = "i2chs2_fck",
1140         .prcm           = {
1141                 .omap2 = {
1142                         .module_offs = CORE_MOD,
1143                         .prcm_reg_id = 1,
1144                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1145                         .idlest_reg_id = 1,
1146                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1147                 },
1148         },
1149         .slaves         = omap2430_i2c2_slaves,
1150         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1151         .class          = &i2c_class,
1152         .dev_attr       = &i2c_dev_attr,
1153         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1154 };
1155
1156 /* l4_wkup -> gpio1 */
1157 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1158         {
1159                 .pa_start       = 0x4900C000,
1160                 .pa_end         = 0x4900C1ff,
1161                 .flags          = ADDR_TYPE_RT
1162         },
1163         { }
1164 };
1165
1166 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1167         .master         = &omap2430_l4_wkup_hwmod,
1168         .slave          = &omap2430_gpio1_hwmod,
1169         .clk            = "gpios_ick",
1170         .addr           = omap2430_gpio1_addr_space,
1171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1172 };
1173
1174 /* l4_wkup -> gpio2 */
1175 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1176         {
1177                 .pa_start       = 0x4900E000,
1178                 .pa_end         = 0x4900E1ff,
1179                 .flags          = ADDR_TYPE_RT
1180         },
1181         { }
1182 };
1183
1184 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1185         .master         = &omap2430_l4_wkup_hwmod,
1186         .slave          = &omap2430_gpio2_hwmod,
1187         .clk            = "gpios_ick",
1188         .addr           = omap2430_gpio2_addr_space,
1189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1190 };
1191
1192 /* l4_wkup -> gpio3 */
1193 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1194         {
1195                 .pa_start       = 0x49010000,
1196                 .pa_end         = 0x490101ff,
1197                 .flags          = ADDR_TYPE_RT
1198         },
1199         { }
1200 };
1201
1202 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1203         .master         = &omap2430_l4_wkup_hwmod,
1204         .slave          = &omap2430_gpio3_hwmod,
1205         .clk            = "gpios_ick",
1206         .addr           = omap2430_gpio3_addr_space,
1207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1208 };
1209
1210 /* l4_wkup -> gpio4 */
1211 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1212         {
1213                 .pa_start       = 0x49012000,
1214                 .pa_end         = 0x490121ff,
1215                 .flags          = ADDR_TYPE_RT
1216         },
1217         { }
1218 };
1219
1220 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1221         .master         = &omap2430_l4_wkup_hwmod,
1222         .slave          = &omap2430_gpio4_hwmod,
1223         .clk            = "gpios_ick",
1224         .addr           = omap2430_gpio4_addr_space,
1225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1226 };
1227
1228 /* l4_core -> gpio5 */
1229 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1230         {
1231                 .pa_start       = 0x480B6000,
1232                 .pa_end         = 0x480B61ff,
1233                 .flags          = ADDR_TYPE_RT
1234         },
1235         { }
1236 };
1237
1238 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1239         .master         = &omap2430_l4_core_hwmod,
1240         .slave          = &omap2430_gpio5_hwmod,
1241         .clk            = "gpio5_ick",
1242         .addr           = omap2430_gpio5_addr_space,
1243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1244 };
1245
1246 /* gpio dev_attr */
1247 static struct omap_gpio_dev_attr gpio_dev_attr = {
1248         .bank_width = 32,
1249         .dbck_flag = false,
1250 };
1251
1252 /* gpio1 */
1253 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1254         &omap2430_l4_wkup__gpio1,
1255 };
1256
1257 static struct omap_hwmod omap2430_gpio1_hwmod = {
1258         .name           = "gpio1",
1259         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1260         .mpu_irqs       = omap2_gpio1_irqs,
1261         .main_clk       = "gpios_fck",
1262         .prcm           = {
1263                 .omap2 = {
1264                         .prcm_reg_id = 1,
1265                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1266                         .module_offs = WKUP_MOD,
1267                         .idlest_reg_id = 1,
1268                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1269                 },
1270         },
1271         .slaves         = omap2430_gpio1_slaves,
1272         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1273         .class          = &omap2xxx_gpio_hwmod_class,
1274         .dev_attr       = &gpio_dev_attr,
1275         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1276 };
1277
1278 /* gpio2 */
1279 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1280         &omap2430_l4_wkup__gpio2,
1281 };
1282
1283 static struct omap_hwmod omap2430_gpio2_hwmod = {
1284         .name           = "gpio2",
1285         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1286         .mpu_irqs       = omap2_gpio2_irqs,
1287         .main_clk       = "gpios_fck",
1288         .prcm           = {
1289                 .omap2 = {
1290                         .prcm_reg_id = 1,
1291                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1292                         .module_offs = WKUP_MOD,
1293                         .idlest_reg_id = 1,
1294                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1295                 },
1296         },
1297         .slaves         = omap2430_gpio2_slaves,
1298         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1299         .class          = &omap2xxx_gpio_hwmod_class,
1300         .dev_attr       = &gpio_dev_attr,
1301         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1302 };
1303
1304 /* gpio3 */
1305 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1306         &omap2430_l4_wkup__gpio3,
1307 };
1308
1309 static struct omap_hwmod omap2430_gpio3_hwmod = {
1310         .name           = "gpio3",
1311         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1312         .mpu_irqs       = omap2_gpio3_irqs,
1313         .main_clk       = "gpios_fck",
1314         .prcm           = {
1315                 .omap2 = {
1316                         .prcm_reg_id = 1,
1317                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1318                         .module_offs = WKUP_MOD,
1319                         .idlest_reg_id = 1,
1320                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1321                 },
1322         },
1323         .slaves         = omap2430_gpio3_slaves,
1324         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1325         .class          = &omap2xxx_gpio_hwmod_class,
1326         .dev_attr       = &gpio_dev_attr,
1327         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1328 };
1329
1330 /* gpio4 */
1331 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1332         &omap2430_l4_wkup__gpio4,
1333 };
1334
1335 static struct omap_hwmod omap2430_gpio4_hwmod = {
1336         .name           = "gpio4",
1337         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1338         .mpu_irqs       = omap2_gpio4_irqs,
1339         .main_clk       = "gpios_fck",
1340         .prcm           = {
1341                 .omap2 = {
1342                         .prcm_reg_id = 1,
1343                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1344                         .module_offs = WKUP_MOD,
1345                         .idlest_reg_id = 1,
1346                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1347                 },
1348         },
1349         .slaves         = omap2430_gpio4_slaves,
1350         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1351         .class          = &omap2xxx_gpio_hwmod_class,
1352         .dev_attr       = &gpio_dev_attr,
1353         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1354 };
1355
1356 /* gpio5 */
1357 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1358         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1359         { .irq = -1 }
1360 };
1361
1362 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1363         &omap2430_l4_core__gpio5,
1364 };
1365
1366 static struct omap_hwmod omap2430_gpio5_hwmod = {
1367         .name           = "gpio5",
1368         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1369         .mpu_irqs       = omap243x_gpio5_irqs,
1370         .main_clk       = "gpio5_fck",
1371         .prcm           = {
1372                 .omap2 = {
1373                         .prcm_reg_id = 2,
1374                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1375                         .module_offs = CORE_MOD,
1376                         .idlest_reg_id = 2,
1377                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1378                 },
1379         },
1380         .slaves         = omap2430_gpio5_slaves,
1381         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1382         .class          = &omap2xxx_gpio_hwmod_class,
1383         .dev_attr       = &gpio_dev_attr,
1384         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1385 };
1386
1387 /* dma attributes */
1388 static struct omap_dma_dev_attr dma_dev_attr = {
1389         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1390                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1391         .lch_count = 32,
1392 };
1393
1394 /* dma_system -> L3 */
1395 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1396         .master         = &omap2430_dma_system_hwmod,
1397         .slave          = &omap2430_l3_main_hwmod,
1398         .clk            = "core_l3_ck",
1399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1400 };
1401
1402 /* dma_system master ports */
1403 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1404         &omap2430_dma_system__l3,
1405 };
1406
1407 /* l4_core -> dma_system */
1408 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1409         .master         = &omap2430_l4_core_hwmod,
1410         .slave          = &omap2430_dma_system_hwmod,
1411         .clk            = "sdma_ick",
1412         .addr           = omap2_dma_system_addrs,
1413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1414 };
1415
1416 /* dma_system slave ports */
1417 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1418         &omap2430_l4_core__dma_system,
1419 };
1420
1421 static struct omap_hwmod omap2430_dma_system_hwmod = {
1422         .name           = "dma",
1423         .class          = &omap2xxx_dma_hwmod_class,
1424         .mpu_irqs       = omap2_dma_system_irqs,
1425         .main_clk       = "core_l3_ck",
1426         .slaves         = omap2430_dma_system_slaves,
1427         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1428         .masters        = omap2430_dma_system_masters,
1429         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1430         .dev_attr       = &dma_dev_attr,
1431         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1432         .flags          = HWMOD_NO_IDLEST,
1433 };
1434
1435 /* mailbox */
1436 static struct omap_hwmod omap2430_mailbox_hwmod;
1437 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1438         { .irq = 26 },
1439         { .irq = -1 }
1440 };
1441
1442 /* l4_core -> mailbox */
1443 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1444         .master         = &omap2430_l4_core_hwmod,
1445         .slave          = &omap2430_mailbox_hwmod,
1446         .addr           = omap2_mailbox_addrs,
1447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1448 };
1449
1450 /* mailbox slave ports */
1451 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1452         &omap2430_l4_core__mailbox,
1453 };
1454
1455 static struct omap_hwmod omap2430_mailbox_hwmod = {
1456         .name           = "mailbox",
1457         .class          = &omap2xxx_mailbox_hwmod_class,
1458         .mpu_irqs       = omap2430_mailbox_irqs,
1459         .main_clk       = "mailboxes_ick",
1460         .prcm           = {
1461                 .omap2 = {
1462                         .prcm_reg_id = 1,
1463                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1464                         .module_offs = CORE_MOD,
1465                         .idlest_reg_id = 1,
1466                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1467                 },
1468         },
1469         .slaves         = omap2430_mailbox_slaves,
1470         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
1471         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1472 };
1473
1474 /* mcspi1 */
1475 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1476         &omap2430_l4_core__mcspi1,
1477 };
1478
1479 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1480         .num_chipselect = 4,
1481 };
1482
1483 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1484         .name           = "mcspi1_hwmod",
1485         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1486         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1487         .main_clk       = "mcspi1_fck",
1488         .prcm           = {
1489                 .omap2 = {
1490                         .module_offs = CORE_MOD,
1491                         .prcm_reg_id = 1,
1492                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1493                         .idlest_reg_id = 1,
1494                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1495                 },
1496         },
1497         .slaves         = omap2430_mcspi1_slaves,
1498         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
1499         .class          = &omap2xxx_mcspi_class,
1500         .dev_attr       = &omap_mcspi1_dev_attr,
1501         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1502 };
1503
1504 /* mcspi2 */
1505 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1506         &omap2430_l4_core__mcspi2,
1507 };
1508
1509 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1510         .num_chipselect = 2,
1511 };
1512
1513 static struct omap_hwmod omap2430_mcspi2_hwmod = {
1514         .name           = "mcspi2_hwmod",
1515         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1516         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1517         .main_clk       = "mcspi2_fck",
1518         .prcm           = {
1519                 .omap2 = {
1520                         .module_offs = CORE_MOD,
1521                         .prcm_reg_id = 1,
1522                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1523                         .idlest_reg_id = 1,
1524                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1525                 },
1526         },
1527         .slaves         = omap2430_mcspi2_slaves,
1528         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
1529         .class          = &omap2xxx_mcspi_class,
1530         .dev_attr       = &omap_mcspi2_dev_attr,
1531         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1532 };
1533
1534 /* mcspi3 */
1535 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1536         { .irq = 91 },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1541         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1542         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1543         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1544         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1545         { .dma_req = -1 }
1546 };
1547
1548 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1549         &omap2430_l4_core__mcspi3,
1550 };
1551
1552 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1553         .num_chipselect = 2,
1554 };
1555
1556 static struct omap_hwmod omap2430_mcspi3_hwmod = {
1557         .name           = "mcspi3_hwmod",
1558         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
1559         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
1560         .main_clk       = "mcspi3_fck",
1561         .prcm           = {
1562                 .omap2 = {
1563                         .module_offs = CORE_MOD,
1564                         .prcm_reg_id = 2,
1565                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1566                         .idlest_reg_id = 2,
1567                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1568                 },
1569         },
1570         .slaves         = omap2430_mcspi3_slaves,
1571         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
1572         .class          = &omap2xxx_mcspi_class,
1573         .dev_attr       = &omap_mcspi3_dev_attr,
1574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1575 };
1576
1577 /*
1578  * usbhsotg
1579  */
1580 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1581         .rev_offs       = 0x0400,
1582         .sysc_offs      = 0x0404,
1583         .syss_offs      = 0x0408,
1584         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1585                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1586                           SYSC_HAS_AUTOIDLE),
1587         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1588                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1589         .sysc_fields    = &omap_hwmod_sysc_type1,
1590 };
1591
1592 static struct omap_hwmod_class usbotg_class = {
1593         .name = "usbotg",
1594         .sysc = &omap2430_usbhsotg_sysc,
1595 };
1596
1597 /* usb_otg_hs */
1598 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1599
1600         { .name = "mc", .irq = 92 },
1601         { .name = "dma", .irq = 93 },
1602         { .irq = -1 }
1603 };
1604
1605 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1606         .name           = "usb_otg_hs",
1607         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
1608         .main_clk       = "usbhs_ick",
1609         .prcm           = {
1610                 .omap2 = {
1611                         .prcm_reg_id = 1,
1612                         .module_bit = OMAP2430_EN_USBHS_MASK,
1613                         .module_offs = CORE_MOD,
1614                         .idlest_reg_id = 1,
1615                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1616                 },
1617         },
1618         .masters        = omap2430_usbhsotg_masters,
1619         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
1620         .slaves         = omap2430_usbhsotg_slaves,
1621         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1622         .class          = &usbotg_class,
1623         /*
1624          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1625          * broken when autoidle is enabled
1626          * workaround is to disable the autoidle bit at module level.
1627          */
1628         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1629                                 | HWMOD_SWSUP_MSTANDBY,
1630         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1631 };
1632
1633 /*
1634  * 'mcbsp' class
1635  * multi channel buffered serial port controller
1636  */
1637
1638 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
1639         .rev_offs       = 0x007C,
1640         .sysc_offs      = 0x008C,
1641         .sysc_flags     = (SYSC_HAS_SOFTRESET),
1642         .sysc_fields    = &omap_hwmod_sysc_type1,
1643 };
1644
1645 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
1646         .name = "mcbsp",
1647         .sysc = &omap2430_mcbsp_sysc,
1648         .rev  = MCBSP_CONFIG_TYPE2,
1649 };
1650
1651 /* mcbsp1 */
1652 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1653         { .name = "tx",         .irq = 59 },
1654         { .name = "rx",         .irq = 60 },
1655         { .name = "ovr",        .irq = 61 },
1656         { .name = "common",     .irq = 64 },
1657         { .irq = -1 }
1658 };
1659
1660 /* l4_core -> mcbsp1 */
1661 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1662         .master         = &omap2430_l4_core_hwmod,
1663         .slave          = &omap2430_mcbsp1_hwmod,
1664         .clk            = "mcbsp1_ick",
1665         .addr           = omap2_mcbsp1_addrs,
1666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1667 };
1668
1669 /* mcbsp1 slave ports */
1670 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1671         &omap2430_l4_core__mcbsp1,
1672 };
1673
1674 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1675         .name           = "mcbsp1",
1676         .class          = &omap2430_mcbsp_hwmod_class,
1677         .mpu_irqs       = omap2430_mcbsp1_irqs,
1678         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1679         .main_clk       = "mcbsp1_fck",
1680         .prcm           = {
1681                 .omap2 = {
1682                         .prcm_reg_id = 1,
1683                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1684                         .module_offs = CORE_MOD,
1685                         .idlest_reg_id = 1,
1686                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1687                 },
1688         },
1689         .slaves         = omap2430_mcbsp1_slaves,
1690         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1691         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1692 };
1693
1694 /* mcbsp2 */
1695 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1696         { .name = "tx",         .irq = 62 },
1697         { .name = "rx",         .irq = 63 },
1698         { .name = "common",     .irq = 16 },
1699         { .irq = -1 }
1700 };
1701
1702 /* l4_core -> mcbsp2 */
1703 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1704         .master         = &omap2430_l4_core_hwmod,
1705         .slave          = &omap2430_mcbsp2_hwmod,
1706         .clk            = "mcbsp2_ick",
1707         .addr           = omap2xxx_mcbsp2_addrs,
1708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1709 };
1710
1711 /* mcbsp2 slave ports */
1712 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1713         &omap2430_l4_core__mcbsp2,
1714 };
1715
1716 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1717         .name           = "mcbsp2",
1718         .class          = &omap2430_mcbsp_hwmod_class,
1719         .mpu_irqs       = omap2430_mcbsp2_irqs,
1720         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1721         .main_clk       = "mcbsp2_fck",
1722         .prcm           = {
1723                 .omap2 = {
1724                         .prcm_reg_id = 1,
1725                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1726                         .module_offs = CORE_MOD,
1727                         .idlest_reg_id = 1,
1728                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1729                 },
1730         },
1731         .slaves         = omap2430_mcbsp2_slaves,
1732         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1733         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1734 };
1735
1736 /* mcbsp3 */
1737 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1738         { .name = "tx",         .irq = 89 },
1739         { .name = "rx",         .irq = 90 },
1740         { .name = "common",     .irq = 17 },
1741         { .irq = -1 }
1742 };
1743
1744 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1745         {
1746                 .name           = "mpu",
1747                 .pa_start       = 0x4808C000,
1748                 .pa_end         = 0x4808C0ff,
1749                 .flags          = ADDR_TYPE_RT
1750         },
1751         { }
1752 };
1753
1754 /* l4_core -> mcbsp3 */
1755 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1756         .master         = &omap2430_l4_core_hwmod,
1757         .slave          = &omap2430_mcbsp3_hwmod,
1758         .clk            = "mcbsp3_ick",
1759         .addr           = omap2430_mcbsp3_addrs,
1760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1761 };
1762
1763 /* mcbsp3 slave ports */
1764 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1765         &omap2430_l4_core__mcbsp3,
1766 };
1767
1768 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1769         .name           = "mcbsp3",
1770         .class          = &omap2430_mcbsp_hwmod_class,
1771         .mpu_irqs       = omap2430_mcbsp3_irqs,
1772         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1773         .main_clk       = "mcbsp3_fck",
1774         .prcm           = {
1775                 .omap2 = {
1776                         .prcm_reg_id = 1,
1777                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
1778                         .module_offs = CORE_MOD,
1779                         .idlest_reg_id = 2,
1780                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1781                 },
1782         },
1783         .slaves         = omap2430_mcbsp3_slaves,
1784         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1785         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1786 };
1787
1788 /* mcbsp4 */
1789 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
1790         { .name = "tx",         .irq = 54 },
1791         { .name = "rx",         .irq = 55 },
1792         { .name = "common",     .irq = 18 },
1793         { .irq = -1 }
1794 };
1795
1796 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1797         { .name = "rx", .dma_req = 20 },
1798         { .name = "tx", .dma_req = 19 },
1799         { .dma_req = -1 }
1800 };
1801
1802 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1803         {
1804                 .name           = "mpu",
1805                 .pa_start       = 0x4808E000,
1806                 .pa_end         = 0x4808E0ff,
1807                 .flags          = ADDR_TYPE_RT
1808         },
1809         { }
1810 };
1811
1812 /* l4_core -> mcbsp4 */
1813 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1814         .master         = &omap2430_l4_core_hwmod,
1815         .slave          = &omap2430_mcbsp4_hwmod,
1816         .clk            = "mcbsp4_ick",
1817         .addr           = omap2430_mcbsp4_addrs,
1818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1819 };
1820
1821 /* mcbsp4 slave ports */
1822 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1823         &omap2430_l4_core__mcbsp4,
1824 };
1825
1826 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1827         .name           = "mcbsp4",
1828         .class          = &omap2430_mcbsp_hwmod_class,
1829         .mpu_irqs       = omap2430_mcbsp4_irqs,
1830         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
1831         .main_clk       = "mcbsp4_fck",
1832         .prcm           = {
1833                 .omap2 = {
1834                         .prcm_reg_id = 1,
1835                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
1836                         .module_offs = CORE_MOD,
1837                         .idlest_reg_id = 2,
1838                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1839                 },
1840         },
1841         .slaves         = omap2430_mcbsp4_slaves,
1842         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1843         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1844 };
1845
1846 /* mcbsp5 */
1847 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
1848         { .name = "tx",         .irq = 81 },
1849         { .name = "rx",         .irq = 82 },
1850         { .name = "common",     .irq = 19 },
1851         { .irq = -1 }
1852 };
1853
1854 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1855         { .name = "rx", .dma_req = 22 },
1856         { .name = "tx", .dma_req = 21 },
1857         { .dma_req = -1 }
1858 };
1859
1860 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1861         {
1862                 .name           = "mpu",
1863                 .pa_start       = 0x48096000,
1864                 .pa_end         = 0x480960ff,
1865                 .flags          = ADDR_TYPE_RT
1866         },
1867         { }
1868 };
1869
1870 /* l4_core -> mcbsp5 */
1871 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1872         .master         = &omap2430_l4_core_hwmod,
1873         .slave          = &omap2430_mcbsp5_hwmod,
1874         .clk            = "mcbsp5_ick",
1875         .addr           = omap2430_mcbsp5_addrs,
1876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1877 };
1878
1879 /* mcbsp5 slave ports */
1880 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1881         &omap2430_l4_core__mcbsp5,
1882 };
1883
1884 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1885         .name           = "mcbsp5",
1886         .class          = &omap2430_mcbsp_hwmod_class,
1887         .mpu_irqs       = omap2430_mcbsp5_irqs,
1888         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
1889         .main_clk       = "mcbsp5_fck",
1890         .prcm           = {
1891                 .omap2 = {
1892                         .prcm_reg_id = 1,
1893                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
1894                         .module_offs = CORE_MOD,
1895                         .idlest_reg_id = 2,
1896                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1897                 },
1898         },
1899         .slaves         = omap2430_mcbsp5_slaves,
1900         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1901         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1902 };
1903
1904 /* MMC/SD/SDIO common */
1905
1906 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1907         .rev_offs       = 0x1fc,
1908         .sysc_offs      = 0x10,
1909         .syss_offs      = 0x14,
1910         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1911                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1912                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1914         .sysc_fields    = &omap_hwmod_sysc_type1,
1915 };
1916
1917 static struct omap_hwmod_class omap2430_mmc_class = {
1918         .name = "mmc",
1919         .sysc = &omap2430_mmc_sysc,
1920 };
1921
1922 /* MMC/SD/SDIO1 */
1923
1924 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1925         { .irq = 83 },
1926         { .irq = -1 }
1927 };
1928
1929 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
1930         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
1931         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1932         { .dma_req = -1 }
1933 };
1934
1935 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1936         { .role = "dbck", .clk = "mmchsdb1_fck" },
1937 };
1938
1939 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1940         &omap2430_l4_core__mmc1,
1941 };
1942
1943 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1944         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1945 };
1946
1947 static struct omap_hwmod omap2430_mmc1_hwmod = {
1948         .name           = "mmc1",
1949         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1950         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
1951         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
1952         .opt_clks       = omap2430_mmc1_opt_clks,
1953         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
1954         .main_clk       = "mmchs1_fck",
1955         .prcm           = {
1956                 .omap2 = {
1957                         .module_offs = CORE_MOD,
1958                         .prcm_reg_id = 2,
1959                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
1960                         .idlest_reg_id = 2,
1961                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
1962                 },
1963         },
1964         .dev_attr       = &mmc1_dev_attr,
1965         .slaves         = omap2430_mmc1_slaves,
1966         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
1967         .class          = &omap2430_mmc_class,
1968         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1969 };
1970
1971 /* MMC/SD/SDIO2 */
1972
1973 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1974         { .irq = 86 },
1975         { .irq = -1 }
1976 };
1977
1978 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
1979         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
1980         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1981         { .dma_req = -1 }
1982 };
1983
1984 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1985         { .role = "dbck", .clk = "mmchsdb2_fck" },
1986 };
1987
1988 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1989         &omap2430_l4_core__mmc2,
1990 };
1991
1992 static struct omap_hwmod omap2430_mmc2_hwmod = {
1993         .name           = "mmc2",
1994         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1995         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
1996         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
1997         .opt_clks       = omap2430_mmc2_opt_clks,
1998         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
1999         .main_clk       = "mmchs2_fck",
2000         .prcm           = {
2001                 .omap2 = {
2002                         .module_offs = CORE_MOD,
2003                         .prcm_reg_id = 2,
2004                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
2005                         .idlest_reg_id = 2,
2006                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2007                 },
2008         },
2009         .slaves         = omap2430_mmc2_slaves,
2010         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
2011         .class          = &omap2430_mmc_class,
2012         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2013 };
2014
2015 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2016         &omap2430_l3_main_hwmod,
2017         &omap2430_l4_core_hwmod,
2018         &omap2430_l4_wkup_hwmod,
2019         &omap2430_mpu_hwmod,
2020         &omap2430_iva_hwmod,
2021
2022         &omap2430_timer1_hwmod,
2023         &omap2430_timer2_hwmod,
2024         &omap2430_timer3_hwmod,
2025         &omap2430_timer4_hwmod,
2026         &omap2430_timer5_hwmod,
2027         &omap2430_timer6_hwmod,
2028         &omap2430_timer7_hwmod,
2029         &omap2430_timer8_hwmod,
2030         &omap2430_timer9_hwmod,
2031         &omap2430_timer10_hwmod,
2032         &omap2430_timer11_hwmod,
2033         &omap2430_timer12_hwmod,
2034
2035         &omap2430_wd_timer2_hwmod,
2036         &omap2430_uart1_hwmod,
2037         &omap2430_uart2_hwmod,
2038         &omap2430_uart3_hwmod,
2039         /* dss class */
2040         &omap2430_dss_core_hwmod,
2041         &omap2430_dss_dispc_hwmod,
2042         &omap2430_dss_rfbi_hwmod,
2043         &omap2430_dss_venc_hwmod,
2044         /* i2c class */
2045         &omap2430_i2c1_hwmod,
2046         &omap2430_i2c2_hwmod,
2047         &omap2430_mmc1_hwmod,
2048         &omap2430_mmc2_hwmod,
2049
2050         /* gpio class */
2051         &omap2430_gpio1_hwmod,
2052         &omap2430_gpio2_hwmod,
2053         &omap2430_gpio3_hwmod,
2054         &omap2430_gpio4_hwmod,
2055         &omap2430_gpio5_hwmod,
2056
2057         /* dma_system class*/
2058         &omap2430_dma_system_hwmod,
2059
2060         /* mcbsp class */
2061         &omap2430_mcbsp1_hwmod,
2062         &omap2430_mcbsp2_hwmod,
2063         &omap2430_mcbsp3_hwmod,
2064         &omap2430_mcbsp4_hwmod,
2065         &omap2430_mcbsp5_hwmod,
2066
2067         /* mailbox class */
2068         &omap2430_mailbox_hwmod,
2069
2070         /* mcspi class */
2071         &omap2430_mcspi1_hwmod,
2072         &omap2430_mcspi2_hwmod,
2073         &omap2430_mcspi3_hwmod,
2074
2075         /* usbotg class*/
2076         &omap2430_usbhsotg_hwmod,
2077
2078         NULL,
2079 };
2080
2081 int __init omap2430_hwmod_init(void)
2082 {
2083         return omap_hwmod_register(omap2430_hwmods);
2084 }