arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/gpio.h>
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/suspend.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/i2c/pxa-i2c.h>
  24
  25 #include <asm/mach/map.h>
  26 #include <mach/hardware.h>
  27 #include <asm/irq.h>
  28 #include <asm/suspend.h>
  29 #include <mach/irqs.h>
  30 #include <mach/pxa27x.h>
  31 #include <mach/reset.h>
  32 #include <mach/ohci.h>
  33 #include <mach/pm.h>
  34 #include <mach/dma.h>
  35 #include <mach/smemc.h>
  36
  37 #include "generic.h"
  38 #include "devices.h"
  39 #include "clock.h"
  40
  41 void pxa27x_clear_otgph(void)
  42 {
  43         if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
  44                 PSSR |= PSSR_OTGPH;
  45 }
  46 EXPORT_SYMBOL(pxa27x_clear_otgph);
  47
  48 static unsigned long ac97_reset_config[] = {
  49         GPIO113_GPIO,
  50         GPIO113_AC97_nRESET,
  51         GPIO95_GPIO,
  52         GPIO95_AC97_nRESET,
  53 };
  54
  55 void pxa27x_assert_ac97reset(int reset_gpio, int on)
  56 {
  57         if (reset_gpio == 113)
  58                 pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
  59                                        &ac97_reset_config[1], 1);
  60
  61         if (reset_gpio == 95)
  62                 pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
  63                                        &ac97_reset_config[3], 1);
  64 }
  65 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
  66
  67 /* Crystal clock: 13MHz */
  68 #define BASE_CLK        13000000
  69
  70 /*
  71  * Get the clock frequency as reflected by CCSR and the turbo flag.
  72  * We assume these values have been applied via a fcs.
  73  * If info is not 0 we also display the current settings.
  74  */
  75 unsigned int pxa27x_get_clk_frequency_khz(int info)
  76 {
  77         unsigned long ccsr, clkcfg;
  78         unsigned int l, L, m, M, n2, N, S;
  79         int cccr_a, t, ht, b;
  80
  81         ccsr = CCSR;
  82         cccr_a = CCCR & (1 << 25);
  83
  84         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  85         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  86         t  = clkcfg & (1 << 0);
  87         ht = clkcfg & (1 << 2);
  88         b  = clkcfg & (1 << 3);
  89
  90         l  = ccsr & 0x1f;
  91         n2 = (ccsr>>7) & 0xf;
  92         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  93
  94         L  = l * BASE_CLK;
  95         N  = (L * n2) / 2;
  96         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  97         S  = (b) ? L : (L/2);
  98
  99         if (info) {
 100                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
 101                         L / 1000000, (L % 1000000) / 10000, l );
 102                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
 103                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
 104                         (t) ? "" : "in" );
 105                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
 106                         M / 1000000, (M % 1000000) / 10000, m );
 107                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
 108                         S / 1000000, (S % 1000000) / 10000 );
 109         }
 110
 111         return (t) ? (N/1000) : (L/1000);
 112 }
 113
 114 /*
 115  * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 116  */
 117 static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 118 {
 119         unsigned long ccsr, clkcfg;
 120         unsigned int l, L, m, M;
 121         int cccr_a, b;
 122
 123         ccsr = CCSR;
 124         cccr_a = CCCR & (1 << 25);
 125
 126         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
 127         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
 128         b = clkcfg & (1 << 3);
 129
 130         l = ccsr & 0x1f;
 131         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 132
 133         L = l * BASE_CLK;
 134         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 135
 136         return M;
 137 }
 138
 139 static const struct clkops clk_pxa27x_mem_ops = {
 140         .enable         = clk_dummy_enable,
 141         .disable        = clk_dummy_disable,
 142         .getrate        = clk_pxa27x_mem_getrate,
 143 };
 144
 145 /*
 146  * Return the current LCD clock frequency in units of 10kHz as
 147  */
 148 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 149 {
 150         unsigned long ccsr;
 151         unsigned int l, L, k, K;
 152
 153         ccsr = CCSR;
 154
 155         l = ccsr & 0x1f;
 156         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 157
 158         L = l * BASE_CLK;
 159         K = L / k;
 160
 161         return (K / 10000);
 162 }
 163
 164 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 165 {
 166         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 167 }
 168
 169 static const struct clkops clk_pxa27x_lcd_ops = {
 170         .enable         = clk_pxa2xx_cken_enable,
 171         .disable        = clk_pxa2xx_cken_disable,
 172         .getrate        = clk_pxa27x_lcd_getrate,
 173 };
 174
 175 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
 176 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
 177 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
 178 static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
 179 static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
 180 static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
 181 static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
 182 static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
 183 static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
 184 static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
 185 static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
 186 static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
 187 static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
 188 static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
 189 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
 190 static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
 191 static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
 192 static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
 193 static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
 194 static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
 195 static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
 196 static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
 197 static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
 198
 199 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 200 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 201 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 202
 203 static struct clk_lookup pxa27x_clkregs[] = {
 204         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
 205         INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
 206         INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
 207         INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
 208         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
 209         INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
 210         INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
 211         INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
 212         INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
 213         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
 214         INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
 215         INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
 216         INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
 217         INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
 218         INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
 219         INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
 220         INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
 221         INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
 222         INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
 223         INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
 224         INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
 225         INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
 226         INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
 227         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
 228         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
 229         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 230         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
 231 };
 232
 233 #ifdef CONFIG_PM
 234
 235 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 236 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 237
 238 /*
 239  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 240  */
 241 static unsigned int pwrmode = PWRMODE_SLEEP;
 242
 243 int __init pxa27x_set_pwrmode(unsigned int mode)
 244 {
 245         switch (mode) {
 246         case PWRMODE_SLEEP:
 247         case PWRMODE_DEEPSLEEP:
 248                 pwrmode = mode;
 249                 return 0;
 250         }
 251
 252         return -EINVAL;
 253 }
 254
 255 /*
 256  * List of global PXA peripheral registers to preserve.
 257  * More ones like CP and general purpose register values are preserved
 258  * with the stack pointer in sleep.S.
 259  */
 260 enum {
 261         SLEEP_SAVE_PSTR,
 262         SLEEP_SAVE_MDREFR,
 263         SLEEP_SAVE_PCFR,
 264         SLEEP_SAVE_COUNT
 265 };
 266
 267 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 268 {
 269         sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
 270         SAVE(PCFR);
 271
 272         SAVE(PSTR);
 273 }
 274
 275 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 276 {
 277         __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
 278         RESTORE(PCFR);
 279
 280         PSSR = PSSR_RDH | PSSR_PH;
 281
 282         RESTORE(PSTR);
 283 }
 284
 285 void pxa27x_cpu_pm_enter(suspend_state_t state)
 286 {
 287         extern void pxa_cpu_standby(void);
 288 #ifndef CONFIG_IWMMXT
 289         u64 acc0;
 290
 291         asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
 292 #endif
 293
 294         /* ensure voltage-change sequencer not initiated, which hangs */
 295         PCFR &= ~PCFR_FVC;
 296
 297         /* Clear edge-detect status register. */
 298         PEDR = 0xDF12FE1B;
 299
 300         /* Clear reset status */
 301         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 302
 303         switch (state) {
 304         case PM_SUSPEND_STANDBY:
 305                 pxa_cpu_standby();
 306                 break;
 307         case PM_SUSPEND_MEM:
 308                 cpu_suspend(pwrmode, pxa27x_finish_suspend);
 309 #ifndef CONFIG_IWMMXT
 310                 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
 311 #endif
 312                 break;
 313         }
 314 }
 315
 316 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 317 {
 318         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 319 }
 320
 321 static int pxa27x_cpu_pm_prepare(void)
 322 {
 323         /* set resume return address */
 324         PSPR = virt_to_phys(cpu_resume);
 325         return 0;
 326 }
 327
 328 static void pxa27x_cpu_pm_finish(void)
 329 {
 330         /* ensure not to come back here if it wasn't intended */
 331         PSPR = 0;
 332 }
 333
 334 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 335         .save_count     = SLEEP_SAVE_COUNT,
 336         .save           = pxa27x_cpu_pm_save,
 337         .restore        = pxa27x_cpu_pm_restore,
 338         .valid          = pxa27x_cpu_pm_valid,
 339         .enter          = pxa27x_cpu_pm_enter,
 340         .prepare        = pxa27x_cpu_pm_prepare,
 341         .finish         = pxa27x_cpu_pm_finish,
 342 };
 343
 344 static void __init pxa27x_init_pm(void)
 345 {
 346         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 347 }
 348 #else
 349 static inline void pxa27x_init_pm(void) {}
 350 #endif
 351
 352 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 353  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 354  */
 355 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 356 {
 357         int gpio = irq_to_gpio(d->irq);
 358         uint32_t mask;
 359
 360         if (gpio >= 0 && gpio < 128)
 361                 return gpio_set_wake(gpio, on);
 362
 363         if (d->irq == IRQ_KEYPAD)
 364                 return keypad_set_wake(on);
 365
 366         switch (d->irq) {
 367         case IRQ_RTCAlrm:
 368                 mask = PWER_RTC;
 369                 break;
 370         case IRQ_USB:
 371                 mask = 1u << 26;
 372                 break;
 373         default:
 374                 return -EINVAL;
 375         }
 376
 377         if (on)
 378                 PWER |= mask;
 379         else
 380                 PWER &=~mask;
 381
 382         return 0;
 383 }
 384
 385 void __init pxa27x_init_irq(void)
 386 {
 387         pxa_init_irq(34, pxa27x_set_wake);
 388         pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 389 }
 390
 391 static struct map_desc pxa27x_io_desc[] __initdata = {
 392         {       /* Mem Ctl */
 393                 .virtual        = SMEMC_VIRT,
 394                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
 395                 .length         = 0x00200000,
 396                 .type           = MT_DEVICE
 397         }, {    /* IMem ctl */
 398                 .virtual        =  0xfe000000,
 399                 .pfn            = __phys_to_pfn(0x58000000),
 400                 .length         = 0x00100000,
 401                 .type           = MT_DEVICE
 402         },
 403 };
 404
 405 void __init pxa27x_map_io(void)
 406 {
 407         pxa_map_io();
 408         iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
 409         pxa27x_get_clk_frequency_khz(1);
 410 }
 411
 412 /*
 413  * device registration specific to PXA27x.
 414  */
 415 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 416 {
 417         local_irq_disable();
 418         PCFR |= PCFR_PI2CEN;
 419         local_irq_enable();
 420         pxa_register_device(&pxa27x_device_i2c_power, info);
 421 }
 422
 423 static struct platform_device *devices[] __initdata = {
 424         &pxa27x_device_udc,
 425         &pxa_device_pmu,
 426         &pxa_device_i2s,
 427         &pxa_device_asoc_ssp1,
 428         &pxa_device_asoc_ssp2,
 429         &pxa_device_asoc_ssp3,
 430         &pxa_device_asoc_platform,
 431         &sa1100_device_rtc,
 432         &pxa_device_rtc,
 433         &pxa27x_device_ssp1,
 434         &pxa27x_device_ssp2,
 435         &pxa27x_device_ssp3,
 436         &pxa27x_device_pwm0,
 437         &pxa27x_device_pwm1,
 438 };
 439
 440 static int __init pxa27x_init(void)
 441 {
 442         int ret = 0;
 443
 444         if (cpu_is_pxa27x()) {
 445
 446                 reset_status = RCSR;
 447
 448                 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 449
 450                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 451                         return ret;
 452
 453                 pxa27x_init_pm();
 454
 455                 register_syscore_ops(&pxa_irq_syscore_ops);
 456                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
 457                 register_syscore_ops(&pxa_gpio_syscore_ops);
 458                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 459
 460                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 461         }
 462
 463         return ret;
 464 }
 465
 466 postcore_initcall(pxa27x_init);