arch/arm/mach-shmobile/pm-sh7372.c

   1 /*
   2  * sh7372 Power management support
   3  *
   4  *  Copyright (C) 2011 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/pm.h>
  12 #include <linux/suspend.h>
  13 #include <linux/cpuidle.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_clock.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <asm/system.h>
  22 #include <asm/io.h>
  23 #include <asm/tlbflush.h>
  24 #include <mach/common.h>
  25 #include <mach/sh7372.h>
  26
  27 #define SMFRAM 0xe6a70000
  28 #define SYSTBCR 0xe6150024
  29 #define SBAR 0xe6180020
  30 #define APARMBAREA 0xe6f10020
  31
  32 #define SPDCR 0xe6180008
  33 #define SWUCR 0xe6180014
  34 #define PSTR 0xe6180080
  35
  36 #define PSTR_RETRIES 100
  37 #define PSTR_DELAY_US 10
  38
  39 #ifdef CONFIG_PM
  40
  41 static int pd_power_down(struct generic_pm_domain *genpd)
  42 {
  43         struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  44         unsigned int mask = 1 << sh7372_pd->bit_shift;
  45
  46         if (__raw_readl(PSTR) & mask) {
  47                 unsigned int retry_count;
  48
  49                 __raw_writel(mask, SPDCR);
  50
  51                 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  52                         if (!(__raw_readl(SPDCR) & mask))
  53                                 break;
  54                         cpu_relax();
  55                 }
  56         }
  57
  58         pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
  59                  mask, __raw_readl(PSTR));
  60
  61         return 0;
  62 }
  63
  64 static int pd_power_up(struct generic_pm_domain *genpd)
  65 {
  66         struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  67         unsigned int mask = 1 << sh7372_pd->bit_shift;
  68         unsigned int retry_count;
  69         int ret = 0;
  70
  71         if (__raw_readl(PSTR) & mask)
  72                 goto out;
  73
  74         __raw_writel(mask, SWUCR);
  75
  76         for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
  77                 if (!(__raw_readl(SWUCR) & mask))
  78                         goto out;
  79                 if (retry_count > PSTR_RETRIES)
  80                         udelay(PSTR_DELAY_US);
  81                 else
  82                         cpu_relax();
  83         }
  84         if (__raw_readl(SWUCR) & mask)
  85                 ret = -EIO;
  86
  87  out:
  88         pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
  89                  mask, __raw_readl(PSTR));
  90
  91         return ret;
  92 }
  93
  94 static bool pd_active_wakeup(struct device *dev)
  95 {
  96         return true;
  97 }
  98
  99 void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
 100 {
 101         struct generic_pm_domain *genpd = &sh7372_pd->genpd;
 102
 103         pm_genpd_init(genpd, NULL, false);
 104         genpd->stop_device = pm_clk_suspend;
 105         genpd->start_device = pm_clk_resume;
 106         genpd->dev_irq_safe = true;
 107         genpd->active_wakeup = pd_active_wakeup;
 108         genpd->power_off = pd_power_down;
 109         genpd->power_on = pd_power_up;
 110         genpd->power_on(&sh7372_pd->genpd);
 111 }
 112
 113 void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
 114                                  struct platform_device *pdev)
 115 {
 116         struct device *dev = &pdev->dev;
 117
 118         pm_genpd_add_device(&sh7372_pd->genpd, dev);
 119         if (pm_clk_no_clocks(dev))
 120                 pm_clk_add(dev, NULL);
 121 }
 122
 123 void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
 124                              struct sh7372_pm_domain *sh7372_sd)
 125 {
 126         pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
 127 }
 128
 129 struct sh7372_pm_domain sh7372_a4lc = {
 130         .bit_shift = 1,
 131 };
 132
 133 struct sh7372_pm_domain sh7372_a4mp = {
 134         .bit_shift = 2,
 135 };
 136
 137 struct sh7372_pm_domain sh7372_d4 = {
 138         .bit_shift = 3,
 139 };
 140
 141 struct sh7372_pm_domain sh7372_a3rv = {
 142         .bit_shift = 6,
 143 };
 144
 145 struct sh7372_pm_domain sh7372_a3ri = {
 146         .bit_shift = 8,
 147 };
 148
 149 struct sh7372_pm_domain sh7372_a3sg = {
 150         .bit_shift = 13,
 151 };
 152
 153 #endif /* CONFIG_PM */
 154
 155 static void sh7372_enter_core_standby(void)
 156 {
 157         void __iomem *smfram = (void __iomem *)SMFRAM;
 158
 159         __raw_writel(0, APARMBAREA); /* translate 4k */
 160         __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
 161         __raw_writel(0x10, SYSTBCR); /* enable core standby */
 162
 163         __raw_writel(0, smfram + 0x3c); /* clear page table address */
 164
 165         sh7372_cpu_suspend();
 166         cpu_init();
 167
 168         /* if page table address is non-NULL then we have been powered down */
 169         if (__raw_readl(smfram + 0x3c)) {
 170                 __raw_writel(__raw_readl(smfram + 0x40),
 171                              __va(__raw_readl(smfram + 0x3c)));
 172
 173                 flush_tlb_all();
 174                 set_cr(__raw_readl(smfram + 0x38));
 175         }
 176
 177         __raw_writel(0, SYSTBCR); /* disable core standby */
 178         __raw_writel(0, SBAR); /* disable reset vector translation */
 179 }
 180
 181 #ifdef CONFIG_CPU_IDLE
 182 static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
 183 {
 184         struct cpuidle_state *state;
 185         int i = dev->state_count;
 186
 187         state = &dev->states[i];
 188         snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
 189         strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
 190         state->exit_latency = 10;
 191         state->target_residency = 20 + 10;
 192         state->power_usage = 1; /* perhaps not */
 193         state->flags = 0;
 194         state->flags |= CPUIDLE_FLAG_TIME_VALID;
 195         shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
 196
 197         dev->state_count = i + 1;
 198 }
 199
 200 static void sh7372_cpuidle_init(void)
 201 {
 202         shmobile_cpuidle_setup = sh7372_cpuidle_setup;
 203 }
 204 #else
 205 static void sh7372_cpuidle_init(void) {}
 206 #endif
 207
 208 #ifdef CONFIG_SUSPEND
 209 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 210 {
 211         sh7372_enter_core_standby();
 212         return 0;
 213 }
 214
 215 static void sh7372_suspend_init(void)
 216 {
 217         shmobile_suspend_ops.enter = sh7372_enter_suspend;
 218 }
 219 #else
 220 static void sh7372_suspend_init(void) {}
 221 #endif
 222
 223 #define DBGREG1 0xe6100020
 224 #define DBGREG9 0xe6100040
 225
 226 void __init sh7372_pm_init(void)
 227 {
 228         /* enable DBG hardware block to kick SYSC */
 229         __raw_writel(0x0000a500, DBGREG9);
 230         __raw_writel(0x0000a501, DBGREG9);
 231         __raw_writel(0x00000000, DBGREG1);
 232
 233         sh7372_suspend_init();
 234         sh7372_cpuidle_init();
 235 }