arch/arm/mach-u300/timer.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/timer.c
   4  *
   5  *
   6  * Copyright (C) 2007-2009 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Timer COH 901 328, runs the OS timer interrupt.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/interrupt.h>
  12 #include <linux/sched.h>
  13 #include <linux/time.h>
  14 #include <linux/timex.h>
  15 #include <linux/clockchips.h>
  16 #include <linux/clocksource.h>
  17 #include <linux/types.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21
  22 #include <mach/hardware.h>
  23
  24 /* Generic stuff */
  25 #include <asm/sched_clock.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/time.h>
  28 #include <asm/mach/irq.h>
  29
  30 /*
  31  * APP side special timer registers
  32  * This timer contains four timers which can fire an interrupt each.
  33  * OS (operating system) timer @ 32768 Hz
  34  * DD (device driver) timer @ 1 kHz
  35  * GP1 (general purpose 1) timer @ 1MHz
  36  * GP2 (general purpose 2) timer @ 1MHz
  37  */
  38
  39 /* Reset OS Timer 32bit (-/W) */
  40 #define U300_TIMER_APP_ROST                                     (0x0000)
  41 #define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  42 /* Enable OS Timer 32bit (-/W) */
  43 #define U300_TIMER_APP_EOST                                     (0x0004)
  44 #define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  45 /* Disable OS Timer 32bit (-/W) */
  46 #define U300_TIMER_APP_DOST                                     (0x0008)
  47 #define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  48 /* OS Timer Mode Register 32bit (-/W) */
  49 #define U300_TIMER_APP_SOSTM                                    (0x000c)
  50 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  51 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  52 /* OS Timer Status Register 32bit (R/-) */
  53 #define U300_TIMER_APP_OSTS                                     (0x0010)
  54 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  55 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  56 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  57 #define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  58 #define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  59 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  60 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  61 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  62 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  63 /* OS Timer Current Count Register 32bit (R/-) */
  64 #define U300_TIMER_APP_OSTCC                                    (0x0014)
  65 /* OS Timer Terminal Count Register 32bit (R/W) */
  66 #define U300_TIMER_APP_OSTTC                                    (0x0018)
  67 /* OS Timer Interrupt Enable Register 32bit (-/W) */
  68 #define U300_TIMER_APP_OSTIE                                    (0x001c)
  69 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  70 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  71 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  72 #define U300_TIMER_APP_OSTIA                                    (0x0020)
  73 #define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  74
  75 /* Reset DD Timer 32bit (-/W) */
  76 #define U300_TIMER_APP_RDDT                                     (0x0040)
  77 #define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  78 /* Enable DD Timer 32bit (-/W) */
  79 #define U300_TIMER_APP_EDDT                                     (0x0044)
  80 #define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  81 /* Disable DD Timer 32bit (-/W) */
  82 #define U300_TIMER_APP_DDDT                                     (0x0048)
  83 #define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  84 /* DD Timer Mode Register 32bit (-/W) */
  85 #define U300_TIMER_APP_SDDTM                                    (0x004c)
  86 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  87 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  88 /* DD Timer Status Register 32bit (R/-) */
  89 #define U300_TIMER_APP_DDTS                                     (0x0050)
  90 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  91 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  92 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  93 #define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  94 #define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
  95 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
  96 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
  97 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
  98 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
  99 /* DD Timer Current Count Register 32bit (R/-) */
 100 #define U300_TIMER_APP_DDTCC                                    (0x0054)
 101 /* DD Timer Terminal Count Register 32bit (R/W) */
 102 #define U300_TIMER_APP_DDTTC                                    (0x0058)
 103 /* DD Timer Interrupt Enable Register 32bit (-/W) */
 104 #define U300_TIMER_APP_DDTIE                                    (0x005c)
 105 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 106 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 107 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 108 #define U300_TIMER_APP_DDTIA                                    (0x0060)
 109 #define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 110
 111 /* Reset GP1 Timer 32bit (-/W) */
 112 #define U300_TIMER_APP_RGPT1                                    (0x0080)
 113 #define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 114 /* Enable GP1 Timer 32bit (-/W) */
 115 #define U300_TIMER_APP_EGPT1                                    (0x0084)
 116 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 117 /* Disable GP1 Timer 32bit (-/W) */
 118 #define U300_TIMER_APP_DGPT1                                    (0x0088)
 119 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 120 /* GP1 Timer Mode Register 32bit (-/W) */
 121 #define U300_TIMER_APP_SGPT1M                                   (0x008c)
 122 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 123 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 124 /* GP1 Timer Status Register 32bit (R/-) */
 125 #define U300_TIMER_APP_GPT1S                                    (0x0090)
 126 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 127 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 128 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 129 #define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 130 #define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 131 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 132 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 133 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 134 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 135 /* GP1 Timer Current Count Register 32bit (R/-) */
 136 #define U300_TIMER_APP_GPT1CC                                   (0x0094)
 137 /* GP1 Timer Terminal Count Register 32bit (R/W) */
 138 #define U300_TIMER_APP_GPT1TC                                   (0x0098)
 139 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 140 #define U300_TIMER_APP_GPT1IE                                   (0x009c)
 141 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 142 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 143 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 144 #define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 145 #define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 146
 147 /* Reset GP2 Timer 32bit (-/W) */
 148 #define U300_TIMER_APP_RGPT2                                    (0x00c0)
 149 #define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 150 /* Enable GP2 Timer 32bit (-/W) */
 151 #define U300_TIMER_APP_EGPT2                                    (0x00c4)
 152 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 153 /* Disable GP2 Timer 32bit (-/W) */
 154 #define U300_TIMER_APP_DGPT2                                    (0x00c8)
 155 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 156 /* GP2 Timer Mode Register 32bit (-/W) */
 157 #define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 158 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 159 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 160 /* GP2 Timer Status Register 32bit (R/-) */
 161 #define U300_TIMER_APP_GPT2S                                    (0x00d0)
 162 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 163 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 164 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 165 #define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 166 #define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 167 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 168 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 169 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 170 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 171 /* GP2 Timer Current Count Register 32bit (R/-) */
 172 #define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 173 /* GP2 Timer Terminal Count Register 32bit (R/W) */
 174 #define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 175 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 176 #define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 177 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 178 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 179 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 180 #define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 181 #define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 182
 183 /* Clock request control register - all four timers */
 184 #define U300_TIMER_APP_CRC                                      (0x100)
 185 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 186
 187 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 188 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 189
 190 /*
 191  * The u300_set_mode() function is always called first, if we
 192  * have oneshot timer active, the oneshot scheduling function
 193  * u300_set_next_event() is called immediately after.
 194  */
 195 static void u300_set_mode(enum clock_event_mode mode,
 196                           struct clock_event_device *evt)
 197 {
 198         switch (mode) {
 199         case CLOCK_EVT_MODE_PERIODIC:
 200                 /* Disable interrupts on GPT1 */
 201                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 202                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 203                 /* Disable GP1 while we're reprogramming it. */
 204                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 205                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 206                 /*
 207                  * Set the periodic mode to a certain number of ticks per
 208                  * jiffy.
 209                  */
 210                 writel(TICKS_PER_JIFFY,
 211                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 212                 /*
 213                  * Set continuous mode, so the timer keeps triggering
 214                  * interrupts.
 215                  */
 216                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 217                        U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 218                 /* Enable timer interrupts */
 219                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 220                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 221                 /* Then enable the OS timer again */
 222                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 223                        U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 224                 break;
 225         case CLOCK_EVT_MODE_ONESHOT:
 226                 /* Just break; here? */
 227                 /*
 228                  * The actual event will be programmed by the next event hook,
 229                  * so we just set a dummy value somewhere at the end of the
 230                  * universe here.
 231                  */
 232                 /* Disable interrupts on GPT1 */
 233                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 234                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 235                 /* Disable GP1 while we're reprogramming it. */
 236                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 237                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 238                 /*
 239                  * Expire far in the future, u300_set_next_event() will be
 240                  * called soon...
 241                  */
 242                 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 243                 /* We run one shot per tick here! */
 244                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 245                        U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 246                 /* Enable interrupts for this timer */
 247                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 248                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 249                 /* Enable timer */
 250                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 251                        U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 252                 break;
 253         case CLOCK_EVT_MODE_UNUSED:
 254         case CLOCK_EVT_MODE_SHUTDOWN:
 255                 /* Disable interrupts on GP1 */
 256                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 257                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 258                 /* Disable GP1 */
 259                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 260                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 261                 break;
 262         case CLOCK_EVT_MODE_RESUME:
 263                 /* Ignore this call */
 264                 break;
 265         }
 266 }
 267
 268 /*
 269  * The app timer in one shot mode obviously has to be reprogrammed
 270  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 271  * the interrupt disable + timer disable commands with a reset command,
 272  * it will fail miserably. Apparently (and I found this the hard way)
 273  * the timer is very sensitive to the instruction order, though you don't
 274  * get that impression from the data sheet.
 275  */
 276 static int u300_set_next_event(unsigned long cycles,
 277                                struct clock_event_device *evt)
 278
 279 {
 280         /* Disable interrupts on GPT1 */
 281         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 282                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 283         /* Disable GP1 while we're reprogramming it. */
 284         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 285                U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 286         /* Reset the General Purpose timer 1. */
 287         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 288                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 289         /* IRQ in n * cycles */
 290         writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 291         /*
 292          * We run one shot per tick here! (This is necessary to reconfigure,
 293          * the timer will tilt if you don't!)
 294          */
 295         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 296                U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 297         /* Enable timer interrupts */
 298         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 299                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 300         /* Then enable the OS timer again */
 301         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 302                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 303         return 0;
 304 }
 305
 306
 307 /* Use general purpose timer 1 as clock event */
 308 static struct clock_event_device clockevent_u300_1mhz = {
 309         .name           = "GPT1",
 310         .rating         = 300, /* Reasonably fast and accurate clock event */
 311         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 312         .set_next_event = u300_set_next_event,
 313         .set_mode       = u300_set_mode,
 314 };
 315
 316 /* Clock event timer interrupt handler */
 317 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 318 {
 319         struct clock_event_device *evt = &clockevent_u300_1mhz;
 320         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 321         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 322                 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
 323         evt->event_handler(evt);
 324         return IRQ_HANDLED;
 325 }
 326
 327 static struct irqaction u300_timer_irq = {
 328         .name           = "U300 Timer Tick",
 329         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 330         .handler        = u300_timer_interrupt,
 331 };
 332
 333 /*
 334  * Override the global weak sched_clock symbol with this
 335  * local implementation which uses the clocksource to get some
 336  * better resolution when scheduling the kernel. We accept that
 337  * this wraps around for now, since it is just a relative time
 338  * stamp. (Inspired by OMAP implementation.)
 339  */
 340 static DEFINE_CLOCK_DATA(cd);
 341
 342 unsigned long long notrace sched_clock(void)
 343 {
 344         u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 345         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 346 }
 347
 348 static void notrace u300_update_sched_clock(void)
 349 {
 350         u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 351         update_sched_clock(&cd, cyc, (u32)~0);
 352 }
 353
 354
 355 /*
 356  * This sets up the system timers, clock source and clock event.
 357  */
 358 static void __init u300_timer_init(void)
 359 {
 360         struct clk *clk;
 361         unsigned long rate;
 362
 363         /* Clock the interrupt controller */
 364         clk = clk_get_sys("apptimer", NULL);
 365         BUG_ON(IS_ERR(clk));
 366         clk_enable(clk);
 367         rate = clk_get_rate(clk);
 368
 369         init_sched_clock(&cd, u300_update_sched_clock, 32, rate);
 370
 371         /*
 372          * Disable the "OS" and "DD" timers - these are designed for Symbian!
 373          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 374          */
 375         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 376                 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
 377         writel(U300_TIMER_APP_ROST_TIMER_RESET,
 378                 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
 379         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 380                 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
 381         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 382                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
 383         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 384                 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
 385
 386         /* Reset the General Purpose timer 1. */
 387         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 388                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 389
 390         /* Set up the IRQ handler */
 391         setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
 392
 393         /* Reset the General Purpose timer 2 */
 394         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 395                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
 396         /* Set this timer to run around forever */
 397         writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
 398         /* Set continuous mode so it wraps around */
 399         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 400                U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
 401         /* Disable timer interrupts */
 402         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 403                 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
 404         /* Then enable the GP2 timer to use as a free running us counter */
 405         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 406                 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
 407
 408         /* Use general purpose timer 2 as clock source */
 409         if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
 410                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 411                 pr_err("timer: failed to initialize U300 clock source\n");
 412
 413         /* Configure and register the clockevent */
 414         clockevents_config_and_register(&clockevent_u300_1mhz, rate,
 415                                         1, 0xffffffff);
 416
 417         /*
 418          * TODO: init and register the rest of the timers too, they can be
 419          * used by hrtimers!
 420          */
 421 }
 422
 423 /*
 424  * Very simple system timer that only register the clock event and
 425  * clock source.
 426  */
 427 struct sys_timer u300_timer = {
 428         .init           = u300_timer_init,
 429 };