| blob | 4251421c0ed50c1af75f320b509ae7faff38b833 |
1 /*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47 #define MAX_AREA_SIZE 32768
49 /*
50 * The size of one data cache line.
51 */
52 #define CACHE_DLINESIZE 32
54 /*
55 * The number of data cache segments.
56 */
57 #define CACHE_DSEGMENTS 16
59 /*
60 * The number of lines in a cache segment.
61 */
62 #define CACHE_DENTRIES 64
64 /*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintenance instructions.
68 */
69 #define CACHE_DLIMIT 32768
71 .text
72 /*
73 * cpu_arm1020e_proc_init()
74 */
75 ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
78 /*
79 * cpu_arm1020e_proc_fin()
80 */
81 ENTRY(cpu_arm1020e_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mov pc, lr
88 /*
89 * cpu_arm1020e_reset(loc)
90 *
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
94 *
95 * loc: location to jump to for soft reset
96 */
97 .align 5
98 ENTRY(cpu_arm1020e_reset)
99 mov ip, #0
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 #ifdef CONFIG_MMU
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
104 #endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mov pc, r0
111 /*
112 * cpu_arm1020e_do_idle()
113 */
114 .align 5
115 ENTRY(cpu_arm1020e_do_idle)
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
117 mov pc, lr
119 /* ================================= CACHE ================================ */
121 .align 5
123 /*
124 * flush_icache_all()
125 *
126 * Unconditionally clean and invalidate the entire icache.
127 */
128 ENTRY(arm1020e_flush_icache_all)
129 #ifndef CONFIG_CPU_ICACHE_DISABLE
130 mov r0, #0
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 #endif
133 mov pc, lr
134 ENDPROC(arm1020e_flush_icache_all)
136 /*
137 * flush_user_cache_all()
138 *
139 * Invalidate all cache entries in a particular address
140 * space.
141 */
142 ENTRY(arm1020e_flush_user_cache_all)
143 /* FALLTHROUGH */
144 /*
145 * flush_kern_cache_all()
146 *
147 * Clean and invalidate the entire cache.
148 */
149 ENTRY(arm1020e_flush_kern_cache_all)
150 mov r2, #VM_EXEC
151 mov ip, #0
152 __flush_whole_cache:
153 #ifndef CONFIG_CPU_DCACHE_DISABLE
154 mcr p15, 0, ip, c7, c10, 4 @ drain WB
155 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
156 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
157 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 subs r3, r3, #1 << 26
159 bcs 2b @ entries 63 to 0
160 subs r1, r1, #1 << 5
161 bcs 1b @ segments 15 to 0
162 #endif
163 tst r2, #VM_EXEC
164 #ifndef CONFIG_CPU_ICACHE_DISABLE
165 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
166 #endif
167 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
168 mov pc, lr
170 /*
171 * flush_user_cache_range(start, end, flags)
172 *
173 * Invalidate a range of cache entries in the specified
174 * address space.
175 *
176 * - start - start address (inclusive)
177 * - end - end address (exclusive)
178 * - flags - vm_flags for this space
179 */
180 ENTRY(arm1020e_flush_user_cache_range)
181 mov ip, #0
182 sub r3, r1, r0 @ calculate total size
183 cmp r3, #CACHE_DLIMIT
184 bhs __flush_whole_cache
186 #ifndef CONFIG_CPU_DCACHE_DISABLE
187 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
188 add r0, r0, #CACHE_DLINESIZE
189 cmp r0, r1
190 blo 1b
191 #endif
192 tst r2, #VM_EXEC
193 #ifndef CONFIG_CPU_ICACHE_DISABLE
194 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
195 #endif
196 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
197 mov pc, lr
199 /*
200 * coherent_kern_range(start, end)
201 *
202 * Ensure coherency between the Icache and the Dcache in the
203 * region described by start. If you have non-snooping
204 * Harvard caches, you need to implement this function.
205 *
206 * - start - virtual start address
207 * - end - virtual end address
208 */
209 ENTRY(arm1020e_coherent_kern_range)
210 /* FALLTHROUGH */
211 /*
212 * coherent_user_range(start, end)
213 *
214 * Ensure coherency between the Icache and the Dcache in the
215 * region described by start. If you have non-snooping
216 * Harvard caches, you need to implement this function.
217 *
218 * - start - virtual start address
219 * - end - virtual end address
220 */
221 ENTRY(arm1020e_coherent_user_range)
222 mov ip, #0
223 bic r0, r0, #CACHE_DLINESIZE - 1
224 1:
225 #ifndef CONFIG_CPU_DCACHE_DISABLE
226 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
227 #endif
228 #ifndef CONFIG_CPU_ICACHE_DISABLE
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
230 #endif
231 add r0, r0, #CACHE_DLINESIZE
232 cmp r0, r1
233 blo 1b
234 mcr p15, 0, ip, c7, c10, 4 @ drain WB
235 mov pc, lr
237 /*
238 * flush_kern_dcache_area(void *addr, size_t size)
239 *
240 * Ensure no D cache aliasing occurs, either with itself or
241 * the I cache
242 *
243 * - addr - kernel address
244 * - size - region size
245 */
246 ENTRY(arm1020e_flush_kern_dcache_area)
247 mov ip, #0
248 #ifndef CONFIG_CPU_DCACHE_DISABLE
249 add r1, r0, r1
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
253 blo 1b
254 #endif
255 mcr p15, 0, ip, c7, c10, 4 @ drain WB
256 mov pc, lr
258 /*
259 * dma_inv_range(start, end)
260 *
261 * Invalidate (discard) the specified virtual address range.
262 * May not write back any entries. If 'start' or 'end'
263 * are not cache line aligned, those lines must be written
264 * back.
265 *
266 * - start - virtual start address
267 * - end - virtual end address
268 *
269 * (same as v4wb)
270 */
271 arm1020e_dma_inv_range:
272 mov ip, #0
273 #ifndef CONFIG_CPU_DCACHE_DISABLE
274 tst r0, #CACHE_DLINESIZE - 1
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
277 tst r1, #CACHE_DLINESIZE - 1
278 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
279 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
280 add r0, r0, #CACHE_DLINESIZE
281 cmp r0, r1
282 blo 1b
283 #endif
284 mcr p15, 0, ip, c7, c10, 4 @ drain WB
285 mov pc, lr
287 /*
288 * dma_clean_range(start, end)
289 *
290 * Clean the specified virtual address range.
291 *
292 * - start - virtual start address
293 * - end - virtual end address
294 *
295 * (same as v4wb)
296 */
297 arm1020e_dma_clean_range:
298 mov ip, #0
299 #ifndef CONFIG_CPU_DCACHE_DISABLE
300 bic r0, r0, #CACHE_DLINESIZE - 1
301 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
304 blo 1b
305 #endif
306 mcr p15, 0, ip, c7, c10, 4 @ drain WB
307 mov pc, lr
309 /*
310 * dma_flush_range(start, end)
311 *
312 * Clean and invalidate the specified virtual address range.
313 *
314 * - start - virtual start address
315 * - end - virtual end address
316 */
317 ENTRY(arm1020e_dma_flush_range)
318 mov ip, #0
319 #ifndef CONFIG_CPU_DCACHE_DISABLE
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
322 add r0, r0, #CACHE_DLINESIZE
323 cmp r0, r1
324 blo 1b
325 #endif
326 mcr p15, 0, ip, c7, c10, 4 @ drain WB
327 mov pc, lr
329 /*
330 * dma_map_area(start, size, dir)
331 * - start - kernel virtual start address
332 * - size - size of region
333 * - dir - DMA direction
334 */
335 ENTRY(arm1020e_dma_map_area)
336 add r1, r1, r0
337 cmp r2, #DMA_TO_DEVICE
338 beq arm1020e_dma_clean_range
339 bcs arm1020e_dma_inv_range
340 b arm1020e_dma_flush_range
341 ENDPROC(arm1020e_dma_map_area)
343 /*
344 * dma_unmap_area(start, size, dir)
345 * - start - kernel virtual start address
346 * - size - size of region
347 * - dir - DMA direction
348 */
349 ENTRY(arm1020e_dma_unmap_area)
350 mov pc, lr
351 ENDPROC(arm1020e_dma_unmap_area)
353 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
354 define_cache_functions arm1020e
356 .align 5
357 ENTRY(cpu_arm1020e_dcache_clean_area)
358 #ifndef CONFIG_CPU_DCACHE_DISABLE
359 mov ip, #0
360 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
361 add r0, r0, #CACHE_DLINESIZE
362 subs r1, r1, #CACHE_DLINESIZE
363 bhi 1b
364 #endif
365 mov pc, lr
367 /* =============================== PageTable ============================== */
369 /*
370 * cpu_arm1020e_switch_mm(pgd)
371 *
372 * Set the translation base pointer to be as described by pgd.
373 *
374 * pgd: new page tables
375 */
376 .align 5
377 ENTRY(cpu_arm1020e_switch_mm)
378 #ifdef CONFIG_MMU
379 #ifndef CONFIG_CPU_DCACHE_DISABLE
380 mcr p15, 0, r3, c7, c10, 4
381 mov r1, #0xF @ 16 segments
382 1: mov r3, #0x3F @ 64 entries
383 2: mov ip, r3, LSL #26 @ shift up entry
384 orr ip, ip, r1, LSL #5 @ shift in/up index
385 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
386 mov ip, #0
387 subs r3, r3, #1
388 cmp r3, #0
389 bge 2b @ entries 3F to 0
390 subs r1, r1, #1
391 cmp r1, #0
392 bge 1b @ segments 15 to 0
394 #endif
395 mov r1, #0
396 #ifndef CONFIG_CPU_ICACHE_DISABLE
397 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
398 #endif
399 mcr p15, 0, r1, c7, c10, 4 @ drain WB
400 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
401 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
402 #endif
403 mov pc, lr
405 /*
406 * cpu_arm1020e_set_pte(ptep, pte)
407 *
408 * Set a PTE and flush it out
409 */
410 .align 5
411 ENTRY(cpu_arm1020e_set_pte_ext)
412 #ifdef CONFIG_MMU
413 armv3_set_pte_ext
414 mov r0, r0
415 #ifndef CONFIG_CPU_DCACHE_DISABLE
416 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
417 #endif
418 #endif /* CONFIG_MMU */
419 mov pc, lr
421 __CPUINIT
423 .type __arm1020e_setup, #function
424 __arm1020e_setup:
425 mov r0, #0
426 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
427 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
428 #ifdef CONFIG_MMU
429 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
430 #endif
431 adr r5, arm1020e_crval
432 ldmia r5, {r5, r6}
433 mrc p15, 0, r0, c1, c0 @ get control register v4
434 bic r0, r0, r5
435 orr r0, r0, r6
436 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
437 orr r0, r0, #0x4000 @ .R.. .... .... ....
438 #endif
439 mov pc, lr
440 .size __arm1020e_setup, . - __arm1020e_setup
442 /*
443 * R
444 * .RVI ZFRS BLDP WCAM
445 * .011 1001 ..11 0101
446 */
447 .type arm1020e_crval, #object
448 arm1020e_crval:
449 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
451 __INITDATA
452 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
453 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
455 .section ".rodata"
457 string cpu_arch_name, "armv5te"
458 string cpu_elf_name, "v5"
459 string cpu_arm1020e_name, "ARM1020E"
461 .align
463 .section ".proc.info.init", #alloc, #execinstr
465 .type __arm1020e_proc_info,#object
466 __arm1020e_proc_info:
467 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
468 .long 0xff0ffff0
469 .long PMD_TYPE_SECT | \
470 PMD_BIT4 | \
471 PMD_SECT_AP_WRITE | \
472 PMD_SECT_AP_READ
473 .long PMD_TYPE_SECT | \
474 PMD_BIT4 | \
475 PMD_SECT_AP_WRITE | \
476 PMD_SECT_AP_READ
477 b __arm1020e_setup
478 .long cpu_arch_name
479 .long cpu_elf_name
480 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
481 .long cpu_arm1020e_name
482 .long arm1020e_processor_functions
483 .long v4wbi_tlb_fns
484 .long v4wb_user_fns
485 .long arm1020e_cache_fns
486 .size __arm1020e_proc_info, . - __arm1020e_proc_info