arch/arm/plat-mxc/include/mach/system.h

   1 /*
   2  *  Copyright (C) 1999 ARM Limited
   3  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   4  *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
  18 #define __ASM_ARCH_MXC_SYSTEM_H__
  19
  20 #include <mach/hardware.h>
  21 #include <mach/common.h>
  22
  23 extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
  24
  25 static inline void arch_idle(void)
  26 {
  27         /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
  28         if (cpu_is_mx31() || cpu_is_mx35()) {
  29                 unsigned long reg = 0;
  30                 __asm__ __volatile__(
  31                         /* disable I and D cache */
  32                         "mrc p15, 0, %0, c1, c0, 0\n"
  33                         "bic %0, %0, #0x00001000\n"
  34                         "bic %0, %0, #0x00000004\n"
  35                         "mcr p15, 0, %0, c1, c0, 0\n"
  36                         /* invalidate I cache */
  37                         "mov %0, #0\n"
  38                         "mcr p15, 0, %0, c7, c5, 0\n"
  39                         /* clear and invalidate D cache */
  40                         "mov %0, #0\n"
  41                         "mcr p15, 0, %0, c7, c14, 0\n"
  42                         /* WFI */
  43                         "mov %0, #0\n"
  44                         "mcr p15, 0, %0, c7, c0, 4\n"
  45                         "nop\n" "nop\n" "nop\n" "nop\n"
  46                         "nop\n" "nop\n" "nop\n"
  47                         /* enable I and D cache */
  48                         "mrc p15, 0, %0, c1, c0, 0\n"
  49                         "orr %0, %0, #0x00001000\n"
  50                         "orr %0, %0, #0x00000004\n"
  51                         "mcr p15, 0, %0, c1, c0, 0\n"
  52                         : "=r" (reg));
  53         } else if (cpu_is_mx51())
  54                 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
  55         else
  56                 cpu_do_idle();
  57 }
  58
  59 void arch_reset(char mode, const char *cmd);
  60
  61 #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */