1 /* linux/arch/arm/plat-s3c24xx/cpu.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
34 #include <mach/hardware.h>
36 #include <asm/cacheflush.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/map.h>
41 #include <mach/system-reset.h>
43 #include <mach/regs-gpio.h>
44 #include <plat/regs-serial.h>
47 #include <plat/devs.h>
48 #include <plat/clock.h>
49 #include <plat/s3c2410.h>
50 #include <plat/s3c2412.h>
51 #include <plat/s3c2416.h>
52 #include <plat/s3c244x.h>
53 #include <plat/s3c2443.h>
55 /* table of supported CPUs */
57 static const char name_s3c2410
[] = "S3C2410";
58 static const char name_s3c2412
[] = "S3C2412";
59 static const char name_s3c2416
[] = "S3C2416/S3C2450";
60 static const char name_s3c2440
[] = "S3C2440";
61 static const char name_s3c2442
[] = "S3C2442";
62 static const char name_s3c2442b
[] = "S3C2442B";
63 static const char name_s3c2443
[] = "S3C2443";
64 static const char name_s3c2410a
[] = "S3C2410A";
65 static const char name_s3c2440a
[] = "S3C2440A";
67 static struct cpu_table cpu_ids
[] __initdata
= {
71 .map_io
= s3c2410_map_io
,
72 .init_clocks
= s3c2410_init_clocks
,
73 .init_uarts
= s3c2410_init_uarts
,
80 .map_io
= s3c2410_map_io
,
81 .init_clocks
= s3c2410_init_clocks
,
82 .init_uarts
= s3c2410_init_uarts
,
83 .init
= s3c2410a_init
,
89 .map_io
= s3c2440_map_io
,
90 .init_clocks
= s3c244x_init_clocks
,
91 .init_uarts
= s3c244x_init_uarts
,
98 .map_io
= s3c2440_map_io
,
99 .init_clocks
= s3c244x_init_clocks
,
100 .init_uarts
= s3c244x_init_uarts
,
101 .init
= s3c2440_init
,
102 .name
= name_s3c2440a
105 .idcode
= 0x32440aaa,
106 .idmask
= 0xffffffff,
107 .map_io
= s3c2442_map_io
,
108 .init_clocks
= s3c244x_init_clocks
,
109 .init_uarts
= s3c244x_init_uarts
,
110 .init
= s3c2442_init
,
114 .idcode
= 0x32440aab,
115 .idmask
= 0xffffffff,
116 .map_io
= s3c2442_map_io
,
117 .init_clocks
= s3c244x_init_clocks
,
118 .init_uarts
= s3c244x_init_uarts
,
119 .init
= s3c2442_init
,
120 .name
= name_s3c2442b
123 .idcode
= 0x32412001,
124 .idmask
= 0xffffffff,
125 .map_io
= s3c2412_map_io
,
126 .init_clocks
= s3c2412_init_clocks
,
127 .init_uarts
= s3c2412_init_uarts
,
128 .init
= s3c2412_init
,
129 .name
= name_s3c2412
,
131 { /* a newer version of the s3c2412 */
132 .idcode
= 0x32412003,
133 .idmask
= 0xffffffff,
134 .map_io
= s3c2412_map_io
,
135 .init_clocks
= s3c2412_init_clocks
,
136 .init_uarts
= s3c2412_init_uarts
,
137 .init
= s3c2412_init
,
138 .name
= name_s3c2412
,
140 { /* a strange version of the s3c2416 */
141 .idcode
= 0x32450003,
142 .idmask
= 0xffffffff,
143 .map_io
= s3c2416_map_io
,
144 .init_clocks
= s3c2416_init_clocks
,
145 .init_uarts
= s3c2416_init_uarts
,
146 .init
= s3c2416_init
,
147 .name
= name_s3c2416
,
150 .idcode
= 0x32443001,
151 .idmask
= 0xffffffff,
152 .map_io
= s3c2443_map_io
,
153 .init_clocks
= s3c2443_init_clocks
,
154 .init_uarts
= s3c2443_init_uarts
,
155 .init
= s3c2443_init
,
156 .name
= name_s3c2443
,
160 /* minimal IO mapping */
162 static struct map_desc s3c_iodesc
[] __initdata
= {
169 /* read cpu identificaiton code */
171 static unsigned long s3c24xx_read_idcode_v5(void)
173 #if defined(CONFIG_CPU_S3C2416)
174 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
176 u32 gs
= __raw_readl(S3C24XX_GSTATUS1
);
178 /* test for s3c2416 or similar device */
179 if ((gs
>> 16) == 0x3245)
183 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
184 return __raw_readl(S3C2412_GSTATUS1
);
186 return 1UL; /* don't look like an 2400 */
190 static unsigned long s3c24xx_read_idcode_v4(void)
192 return __raw_readl(S3C2410_GSTATUS1
);
195 /* Hook for arm_pm_restart to ensure we execute the reset code
196 * with the caches enabled. It seems at least the S3C2440 has a problem
197 * resetting if there is bus activity interrupted by the reset.
199 static void s3c24xx_pm_restart(char mode
, const char *cmd
)
204 local_irq_save(flags
);
205 __cpuc_flush_kern_all();
206 __cpuc_flush_user_all();
208 arch_reset(mode
, cmd
);
209 local_irq_restore(flags
);
212 /* fallback, or unhandled */
213 arm_machine_restart(mode
, cmd
);
216 void __init
s3c24xx_init_io(struct map_desc
*mach_desc
, int size
)
218 /* initialise the io descriptors we need for initialisation */
219 iotable_init(mach_desc
, size
);
220 iotable_init(s3c_iodesc
, ARRAY_SIZE(s3c_iodesc
));
222 if (cpu_architecture() >= CPU_ARCH_ARMv5
) {
223 samsung_cpu_id
= s3c24xx_read_idcode_v5();
225 samsung_cpu_id
= s3c24xx_read_idcode_v4();
229 arm_pm_restart
= s3c24xx_pm_restart
;
231 s3c_init_cpu(samsung_cpu_id
, cpu_ids
, ARRAY_SIZE(cpu_ids
));