arch/arm/plat-s3c24xx/include/plat/regs-udc.h

   1 /* arch/arm/mach-s3c2410/include/mach/regs-udc.h
   2  *
   3  * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
   4  *
   5  * This include file is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9 */
  10
  11 #ifndef __ASM_ARCH_REGS_UDC_H
  12 #define __ASM_ARCH_REGS_UDC_H
  13
  14 #define S3C2410_USBDREG(x) (x)
  15
  16 #define S3C2410_UDC_FUNC_ADDR_REG       S3C2410_USBDREG(0x0140)
  17 #define S3C2410_UDC_PWR_REG             S3C2410_USBDREG(0x0144)
  18 #define S3C2410_UDC_EP_INT_REG          S3C2410_USBDREG(0x0148)
  19
  20 #define S3C2410_UDC_USB_INT_REG         S3C2410_USBDREG(0x0158)
  21 #define S3C2410_UDC_EP_INT_EN_REG       S3C2410_USBDREG(0x015c)
  22
  23 #define S3C2410_UDC_USB_INT_EN_REG      S3C2410_USBDREG(0x016c)
  24
  25 #define S3C2410_UDC_FRAME_NUM1_REG      S3C2410_USBDREG(0x0170)
  26 #define S3C2410_UDC_FRAME_NUM2_REG      S3C2410_USBDREG(0x0174)
  27
  28 #define S3C2410_UDC_EP0_FIFO_REG        S3C2410_USBDREG(0x01c0)
  29 #define S3C2410_UDC_EP1_FIFO_REG        S3C2410_USBDREG(0x01c4)
  30 #define S3C2410_UDC_EP2_FIFO_REG        S3C2410_USBDREG(0x01c8)
  31 #define S3C2410_UDC_EP3_FIFO_REG        S3C2410_USBDREG(0x01cc)
  32 #define S3C2410_UDC_EP4_FIFO_REG        S3C2410_USBDREG(0x01d0)
  33
  34 #define S3C2410_UDC_EP1_DMA_CON         S3C2410_USBDREG(0x0200)
  35 #define S3C2410_UDC_EP1_DMA_UNIT        S3C2410_USBDREG(0x0204)
  36 #define S3C2410_UDC_EP1_DMA_FIFO        S3C2410_USBDREG(0x0208)
  37 #define S3C2410_UDC_EP1_DMA_TTC_L       S3C2410_USBDREG(0x020c)
  38 #define S3C2410_UDC_EP1_DMA_TTC_M       S3C2410_USBDREG(0x0210)
  39 #define S3C2410_UDC_EP1_DMA_TTC_H       S3C2410_USBDREG(0x0214)
  40
  41 #define S3C2410_UDC_EP2_DMA_CON         S3C2410_USBDREG(0x0218)
  42 #define S3C2410_UDC_EP2_DMA_UNIT        S3C2410_USBDREG(0x021c)
  43 #define S3C2410_UDC_EP2_DMA_FIFO        S3C2410_USBDREG(0x0220)
  44 #define S3C2410_UDC_EP2_DMA_TTC_L       S3C2410_USBDREG(0x0224)
  45 #define S3C2410_UDC_EP2_DMA_TTC_M       S3C2410_USBDREG(0x0228)
  46 #define S3C2410_UDC_EP2_DMA_TTC_H       S3C2410_USBDREG(0x022c)
  47
  48 #define S3C2410_UDC_EP3_DMA_CON         S3C2410_USBDREG(0x0240)
  49 #define S3C2410_UDC_EP3_DMA_UNIT        S3C2410_USBDREG(0x0244)
  50 #define S3C2410_UDC_EP3_DMA_FIFO        S3C2410_USBDREG(0x0248)
  51 #define S3C2410_UDC_EP3_DMA_TTC_L       S3C2410_USBDREG(0x024c)
  52 #define S3C2410_UDC_EP3_DMA_TTC_M       S3C2410_USBDREG(0x0250)
  53 #define S3C2410_UDC_EP3_DMA_TTC_H       S3C2410_USBDREG(0x0254)
  54
  55 #define S3C2410_UDC_EP4_DMA_CON         S3C2410_USBDREG(0x0258)
  56 #define S3C2410_UDC_EP4_DMA_UNIT        S3C2410_USBDREG(0x025c)
  57 #define S3C2410_UDC_EP4_DMA_FIFO        S3C2410_USBDREG(0x0260)
  58 #define S3C2410_UDC_EP4_DMA_TTC_L       S3C2410_USBDREG(0x0264)
  59 #define S3C2410_UDC_EP4_DMA_TTC_M       S3C2410_USBDREG(0x0268)
  60 #define S3C2410_UDC_EP4_DMA_TTC_H       S3C2410_USBDREG(0x026c)
  61
  62 #define S3C2410_UDC_INDEX_REG           S3C2410_USBDREG(0x0178)
  63
  64 /* indexed registers */
  65
  66 #define S3C2410_UDC_MAXP_REG            S3C2410_USBDREG(0x0180)
  67
  68 #define S3C2410_UDC_EP0_CSR_REG         S3C2410_USBDREG(0x0184)
  69
  70 #define S3C2410_UDC_IN_CSR1_REG         S3C2410_USBDREG(0x0184)
  71 #define S3C2410_UDC_IN_CSR2_REG         S3C2410_USBDREG(0x0188)
  72
  73 #define S3C2410_UDC_OUT_CSR1_REG        S3C2410_USBDREG(0x0190)
  74 #define S3C2410_UDC_OUT_CSR2_REG        S3C2410_USBDREG(0x0194)
  75 #define S3C2410_UDC_OUT_FIFO_CNT1_REG   S3C2410_USBDREG(0x0198)
  76 #define S3C2410_UDC_OUT_FIFO_CNT2_REG   S3C2410_USBDREG(0x019c)
  77
  78 #define S3C2410_UDC_FUNCADDR_UPDATE     (1<<7)
  79
  80 #define S3C2410_UDC_PWR_ISOUP           (1<<7) // R/W
  81 #define S3C2410_UDC_PWR_RESET           (1<<3) // R
  82 #define S3C2410_UDC_PWR_RESUME          (1<<2) // R/W
  83 #define S3C2410_UDC_PWR_SUSPEND         (1<<1) // R
  84 #define S3C2410_UDC_PWR_ENSUSPEND       (1<<0) // R/W
  85
  86 #define S3C2410_UDC_PWR_DEFAULT         0x00
  87
  88 #define S3C2410_UDC_INT_EP4             (1<<4) // R/W (clear only)
  89 #define S3C2410_UDC_INT_EP3             (1<<3) // R/W (clear only)
  90 #define S3C2410_UDC_INT_EP2             (1<<2) // R/W (clear only)
  91 #define S3C2410_UDC_INT_EP1             (1<<1) // R/W (clear only)
  92 #define S3C2410_UDC_INT_EP0             (1<<0) // R/W (clear only)
  93
  94 #define S3C2410_UDC_USBINT_RESET        (1<<2) // R/W (clear only)
  95 #define S3C2410_UDC_USBINT_RESUME       (1<<1) // R/W (clear only)
  96 #define S3C2410_UDC_USBINT_SUSPEND      (1<<0) // R/W (clear only)
  97
  98 #define S3C2410_UDC_INTE_EP4            (1<<4) // R/W
  99 #define S3C2410_UDC_INTE_EP3            (1<<3) // R/W
 100 #define S3C2410_UDC_INTE_EP2            (1<<2) // R/W
 101 #define S3C2410_UDC_INTE_EP1            (1<<1) // R/W
 102 #define S3C2410_UDC_INTE_EP0            (1<<0) // R/W
 103
 104 #define S3C2410_UDC_USBINTE_RESET       (1<<2) // R/W
 105 #define S3C2410_UDC_USBINTE_SUSPEND     (1<<0) // R/W
 106
 107
 108 #define S3C2410_UDC_INDEX_EP0           (0x00)
 109 #define S3C2410_UDC_INDEX_EP1           (0x01) // ??
 110 #define S3C2410_UDC_INDEX_EP2           (0x02) // ??
 111 #define S3C2410_UDC_INDEX_EP3           (0x03) // ??
 112 #define S3C2410_UDC_INDEX_EP4           (0x04) // ??
 113
 114 #define S3C2410_UDC_ICSR1_CLRDT         (1<<6) // R/W
 115 #define S3C2410_UDC_ICSR1_SENTSTL       (1<<5) // R/W (clear only)
 116 #define S3C2410_UDC_ICSR1_SENDSTL       (1<<4) // R/W
 117 #define S3C2410_UDC_ICSR1_FFLUSH        (1<<3) // W   (set only)
 118 #define S3C2410_UDC_ICSR1_UNDRUN        (1<<2) // R/W (clear only)
 119 #define S3C2410_UDC_ICSR1_PKTRDY        (1<<0) // R/W (set only)
 120
 121 #define S3C2410_UDC_ICSR2_AUTOSET       (1<<7) // R/W
 122 #define S3C2410_UDC_ICSR2_ISO           (1<<6) // R/W
 123 #define S3C2410_UDC_ICSR2_MODEIN        (1<<5) // R/W
 124 #define S3C2410_UDC_ICSR2_DMAIEN        (1<<4) // R/W
 125
 126 #define S3C2410_UDC_OCSR1_CLRDT         (1<<7) // R/W
 127 #define S3C2410_UDC_OCSR1_SENTSTL       (1<<6) // R/W (clear only)
 128 #define S3C2410_UDC_OCSR1_SENDSTL       (1<<5) // R/W
 129 #define S3C2410_UDC_OCSR1_FFLUSH        (1<<4) // R/W
 130 #define S3C2410_UDC_OCSR1_DERROR        (1<<3) // R
 131 #define S3C2410_UDC_OCSR1_OVRRUN        (1<<2) // R/W (clear only)
 132 #define S3C2410_UDC_OCSR1_PKTRDY        (1<<0) // R/W (clear only)
 133
 134 #define S3C2410_UDC_OCSR2_AUTOCLR       (1<<7) // R/W
 135 #define S3C2410_UDC_OCSR2_ISO           (1<<6) // R/W
 136 #define S3C2410_UDC_OCSR2_DMAIEN        (1<<5) // R/W
 137
 138 #define S3C2410_UDC_EP0_CSR_OPKRDY      (1<<0)
 139 #define S3C2410_UDC_EP0_CSR_IPKRDY      (1<<1)
 140 #define S3C2410_UDC_EP0_CSR_SENTSTL     (1<<2)
 141 #define S3C2410_UDC_EP0_CSR_DE          (1<<3)
 142 #define S3C2410_UDC_EP0_CSR_SE          (1<<4)
 143 #define S3C2410_UDC_EP0_CSR_SENDSTL     (1<<5)
 144 #define S3C2410_UDC_EP0_CSR_SOPKTRDY    (1<<6)
 145 #define S3C2410_UDC_EP0_CSR_SSE (1<<7)
 146
 147 #define S3C2410_UDC_MAXP_8              (1<<0)
 148 #define S3C2410_UDC_MAXP_16             (1<<1)
 149 #define S3C2410_UDC_MAXP_32             (1<<2)
 150 #define S3C2410_UDC_MAXP_64             (1<<3)
 151
 152
 153 #endif