arch/arm/plat-s5p/include/plat/irqs.h

   1 /* linux/arch/arm/plat-s5p/include/plat/irqs.h
   2  *
   3  * Copyright (c) 2009 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5P Common IRQ support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_PLAT_S5P_IRQS_H
  14 #define __ASM_PLAT_S5P_IRQS_H __FILE__
  15
  16 /* we keep the first set of CPU IRQs out of the range of
  17  * the ISA space, so that the PC104 has them to itself
  18  * and we don't end up having to do horrible things to the
  19  * standard ISA drivers....
  20  *
  21  * note, since we're using the VICs, our start must be a
  22  * mulitple of 32 to allow the common code to work
  23  */
  24
  25 #define S5P_IRQ_OFFSET          (32)
  26
  27 #define S5P_IRQ(x)              ((x) + S5P_IRQ_OFFSET)
  28
  29 #define S5P_VIC0_BASE           S5P_IRQ(0)
  30 #define S5P_VIC1_BASE           S5P_IRQ(32)
  31 #define S5P_VIC2_BASE           S5P_IRQ(64)
  32 #define S5P_VIC3_BASE           S5P_IRQ(96)
  33
  34 #define VIC_BASE(x)             (S5P_VIC0_BASE + ((x)*32))
  35
  36 #define IRQ_VIC0_BASE           S5P_VIC0_BASE
  37 #define IRQ_VIC1_BASE           S5P_VIC1_BASE
  38 #define IRQ_VIC2_BASE           S5P_VIC2_BASE
  39
  40 /* VIC based IRQs */
  41
  42 #define S5P_IRQ_VIC0(x)         (S5P_VIC0_BASE + (x))
  43 #define S5P_IRQ_VIC1(x)         (S5P_VIC1_BASE + (x))
  44 #define S5P_IRQ_VIC2(x)         (S5P_VIC2_BASE + (x))
  45 #define S5P_IRQ_VIC3(x)         (S5P_VIC3_BASE + (x))
  46
  47 #define S5P_TIMER_IRQ(x)        (11 + (x))
  48
  49 #define IRQ_TIMER0              S5P_TIMER_IRQ(0)
  50 #define IRQ_TIMER1              S5P_TIMER_IRQ(1)
  51 #define IRQ_TIMER2              S5P_TIMER_IRQ(2)
  52 #define IRQ_TIMER3              S5P_TIMER_IRQ(3)
  53 #define IRQ_TIMER4              S5P_TIMER_IRQ(4)
  54
  55 #define IRQ_EINT(x)             ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
  56                                         : ((x) - 16 + S5P_EINT_BASE2))
  57
  58 #define EINT_OFFSET(irq)        ((irq) < S5P_EINT_BASE2 ? \
  59                                                 ((irq) - S5P_EINT_BASE1) : \
  60                                                 ((irq) + 16 - S5P_EINT_BASE2))
  61
  62 #define IRQ_EINT_BIT(x)         EINT_OFFSET(x)
  63
  64 /* Typically only a few gpio chips require gpio interrupt support.
  65    To avoid memory waste irq descriptors are allocated only for
  66    S5P_GPIOINT_GROUP_COUNT chips, each with total number of
  67    S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
  68    to any gpio chip with the s5p_register_gpio_interrupt() function */
  69 #define S5P_GPIOINT_GROUP_COUNT 4
  70 #define S5P_GPIOINT_GROUP_SIZE  8
  71 #define S5P_GPIOINT_COUNT       (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
  72
  73 /* IRQ types common for all s5p platforms */
  74 #define S5P_IRQ_TYPE_LEVEL_LOW          (0x00)
  75 #define S5P_IRQ_TYPE_LEVEL_HIGH         (0x01)
  76 #define S5P_IRQ_TYPE_EDGE_FALLING       (0x02)
  77 #define S5P_IRQ_TYPE_EDGE_RISING        (0x03)
  78 #define S5P_IRQ_TYPE_EDGE_BOTH          (0x04)
  79
  80 #endif /* __ASM_PLAT_S5P_IRQS_H */