arch/arm/plat-samsung/clock.c

   1 /* linux/arch/arm/plat-s3c24xx/clock.c
   2  *
   3  * Copyright 2004-2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C24XX Core clock control support
   7  *
   8  * Based on, and code from linux/arch/arm/mach-versatile/clock.c
   9  **
  10  **  Copyright (C) 2004 ARM Limited.
  11  **  Written by Deep Blue Solutions Limited.
  12  *
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27 */
  28
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/errno.h>
  34 #include <linux/err.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/sysdev.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/ioport.h>
  39 #include <linux/clk.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/io.h>
  42 #if defined(CONFIG_DEBUG_FS)
  43 #include <linux/debugfs.h>
  44 #endif
  45
  46 #include <mach/hardware.h>
  47 #include <asm/irq.h>
  48
  49 #include <plat/cpu-freq.h>
  50
  51 #include <plat/clock.h>
  52 #include <plat/cpu.h>
  53
  54 #include <linux/serial_core.h>
  55 #include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
  56
  57 /* clock information */
  58
  59 static LIST_HEAD(clocks);
  60
  61 /* We originally used an mutex here, but some contexts (see resume)
  62  * are calling functions such as clk_set_parent() with IRQs disabled
  63  * causing an BUG to be triggered.
  64  */
  65 DEFINE_SPINLOCK(clocks_lock);
  66
  67 /* enable and disable calls for use with the clk struct */
  68
  69 static int clk_null_enable(struct clk *clk, int enable)
  70 {
  71         return 0;
  72 }
  73
  74 int clk_enable(struct clk *clk)
  75 {
  76         if (IS_ERR(clk) || clk == NULL)
  77                 return -EINVAL;
  78
  79         clk_enable(clk->parent);
  80
  81         spin_lock(&clocks_lock);
  82
  83         if ((clk->usage++) == 0)
  84                 (clk->enable)(clk, 1);
  85
  86         spin_unlock(&clocks_lock);
  87         return 0;
  88 }
  89
  90 void clk_disable(struct clk *clk)
  91 {
  92         if (IS_ERR(clk) || clk == NULL)
  93                 return;
  94
  95         spin_lock(&clocks_lock);
  96
  97         if ((--clk->usage) == 0)
  98                 (clk->enable)(clk, 0);
  99
 100         spin_unlock(&clocks_lock);
 101         clk_disable(clk->parent);
 102 }
 103
 104
 105 unsigned long clk_get_rate(struct clk *clk)
 106 {
 107         if (IS_ERR(clk))
 108                 return 0;
 109
 110         if (clk->rate != 0)
 111                 return clk->rate;
 112
 113         if (clk->ops != NULL && clk->ops->get_rate != NULL)
 114                 return (clk->ops->get_rate)(clk);
 115
 116         if (clk->parent != NULL)
 117                 return clk_get_rate(clk->parent);
 118
 119         return clk->rate;
 120 }
 121
 122 long clk_round_rate(struct clk *clk, unsigned long rate)
 123 {
 124         if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
 125                 return (clk->ops->round_rate)(clk, rate);
 126
 127         return rate;
 128 }
 129
 130 int clk_set_rate(struct clk *clk, unsigned long rate)
 131 {
 132         int ret;
 133
 134         if (IS_ERR(clk))
 135                 return -EINVAL;
 136
 137         /* We do not default just do a clk->rate = rate as
 138          * the clock may have been made this way by choice.
 139          */
 140
 141         WARN_ON(clk->ops == NULL);
 142         WARN_ON(clk->ops && clk->ops->set_rate == NULL);
 143
 144         if (clk->ops == NULL || clk->ops->set_rate == NULL)
 145                 return -EINVAL;
 146
 147         spin_lock(&clocks_lock);
 148         ret = (clk->ops->set_rate)(clk, rate);
 149         spin_unlock(&clocks_lock);
 150
 151         return ret;
 152 }
 153
 154 struct clk *clk_get_parent(struct clk *clk)
 155 {
 156         return clk->parent;
 157 }
 158
 159 int clk_set_parent(struct clk *clk, struct clk *parent)
 160 {
 161         int ret = 0;
 162
 163         if (IS_ERR(clk))
 164                 return -EINVAL;
 165
 166         spin_lock(&clocks_lock);
 167
 168         if (clk->ops && clk->ops->set_parent)
 169                 ret = (clk->ops->set_parent)(clk, parent);
 170
 171         spin_unlock(&clocks_lock);
 172
 173         return ret;
 174 }
 175
 176 EXPORT_SYMBOL(clk_enable);
 177 EXPORT_SYMBOL(clk_disable);
 178 EXPORT_SYMBOL(clk_get_rate);
 179 EXPORT_SYMBOL(clk_round_rate);
 180 EXPORT_SYMBOL(clk_set_rate);
 181 EXPORT_SYMBOL(clk_get_parent);
 182 EXPORT_SYMBOL(clk_set_parent);
 183
 184 /* base clocks */
 185
 186 int clk_default_setrate(struct clk *clk, unsigned long rate)
 187 {
 188         clk->rate = rate;
 189         return 0;
 190 }
 191
 192 struct clk_ops clk_ops_def_setrate = {
 193         .set_rate       = clk_default_setrate,
 194 };
 195
 196 struct clk clk_xtal = {
 197         .name           = "xtal",
 198         .rate           = 0,
 199         .parent         = NULL,
 200         .ctrlbit        = 0,
 201 };
 202
 203 struct clk clk_ext = {
 204         .name           = "ext",
 205 };
 206
 207 struct clk clk_epll = {
 208         .name           = "epll",
 209 };
 210
 211 struct clk clk_mpll = {
 212         .name           = "mpll",
 213         .ops            = &clk_ops_def_setrate,
 214 };
 215
 216 struct clk clk_upll = {
 217         .name           = "upll",
 218         .parent         = NULL,
 219         .ctrlbit        = 0,
 220 };
 221
 222 struct clk clk_f = {
 223         .name           = "fclk",
 224         .rate           = 0,
 225         .parent         = &clk_mpll,
 226         .ctrlbit        = 0,
 227 };
 228
 229 struct clk clk_h = {
 230         .name           = "hclk",
 231         .rate           = 0,
 232         .parent         = NULL,
 233         .ctrlbit        = 0,
 234         .ops            = &clk_ops_def_setrate,
 235 };
 236
 237 struct clk clk_p = {
 238         .name           = "pclk",
 239         .rate           = 0,
 240         .parent         = NULL,
 241         .ctrlbit        = 0,
 242         .ops            = &clk_ops_def_setrate,
 243 };
 244
 245 struct clk clk_usb_bus = {
 246         .name           = "usb-bus",
 247         .rate           = 0,
 248         .parent         = &clk_upll,
 249 };
 250
 251
 252 struct clk s3c24xx_uclk = {
 253         .name           = "uclk",
 254 };
 255
 256 /* initialise the clock system */
 257
 258 /**
 259  * s3c24xx_register_clock() - register a clock
 260  * @clk: The clock to register
 261  *
 262  * Add the specified clock to the list of clocks known by the system.
 263  */
 264 int s3c24xx_register_clock(struct clk *clk)
 265 {
 266         if (clk->enable == NULL)
 267                 clk->enable = clk_null_enable;
 268
 269         /* fill up the clk_lookup structure and register it*/
 270         clk->lookup.dev_id = clk->devname;
 271         clk->lookup.con_id = clk->name;
 272         clk->lookup.clk = clk;
 273         clkdev_add(&clk->lookup);
 274
 275         return 0;
 276 }
 277
 278 /**
 279  * s3c24xx_register_clocks() - register an array of clock pointers
 280  * @clks: Pointer to an array of struct clk pointers
 281  * @nr_clks: The number of clocks in the @clks array.
 282  *
 283  * Call s3c24xx_register_clock() for all the clock pointers contained
 284  * in the @clks list. Returns the number of failures.
 285  */
 286 int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
 287 {
 288         int fails = 0;
 289
 290         for (; nr_clks > 0; nr_clks--, clks++) {
 291                 if (s3c24xx_register_clock(*clks) < 0) {
 292                         struct clk *clk = *clks;
 293                         printk(KERN_ERR "%s: failed to register %p: %s\n",
 294                                __func__, clk, clk->name);
 295                         fails++;
 296                 }
 297         }
 298
 299         return fails;
 300 }
 301
 302 /**
 303  * s3c_register_clocks() - register an array of clocks
 304  * @clkp: Pointer to the first clock in the array.
 305  * @nr_clks: Number of clocks to register.
 306  *
 307  * Call s3c24xx_register_clock() on the @clkp array given, printing an
 308  * error if it fails to register the clock (unlikely).
 309  */
 310 void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
 311 {
 312         int ret;
 313
 314         for (; nr_clks > 0; nr_clks--, clkp++) {
 315                 ret = s3c24xx_register_clock(clkp);
 316
 317                 if (ret < 0) {
 318                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 319                                clkp->name, ret);
 320                 }
 321         }
 322 }
 323
 324 /**
 325  * s3c_disable_clocks() - disable an array of clocks
 326  * @clkp: Pointer to the first clock in the array.
 327  * @nr_clks: Number of clocks to register.
 328  *
 329  * for internal use only at initialisation time. disable the clocks in the
 330  * @clkp array.
 331  */
 332
 333 void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
 334 {
 335         for (; nr_clks > 0; nr_clks--, clkp++)
 336                 (clkp->enable)(clkp, 0);
 337 }
 338
 339 /* initialise all the clocks */
 340
 341 int __init s3c24xx_register_baseclocks(unsigned long xtal)
 342 {
 343         printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
 344
 345         clk_xtal.rate = xtal;
 346
 347         /* register our clocks */
 348
 349         if (s3c24xx_register_clock(&clk_xtal) < 0)
 350                 printk(KERN_ERR "failed to register master xtal\n");
 351
 352         if (s3c24xx_register_clock(&clk_mpll) < 0)
 353                 printk(KERN_ERR "failed to register mpll clock\n");
 354
 355         if (s3c24xx_register_clock(&clk_upll) < 0)
 356                 printk(KERN_ERR "failed to register upll clock\n");
 357
 358         if (s3c24xx_register_clock(&clk_f) < 0)
 359                 printk(KERN_ERR "failed to register cpu fclk\n");
 360
 361         if (s3c24xx_register_clock(&clk_h) < 0)
 362                 printk(KERN_ERR "failed to register cpu hclk\n");
 363
 364         if (s3c24xx_register_clock(&clk_p) < 0)
 365                 printk(KERN_ERR "failed to register cpu pclk\n");
 366
 367         return 0;
 368 }
 369
 370 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 371 /* debugfs support to trace clock tree hierarchy and attributes */
 372
 373 static struct dentry *clk_debugfs_root;
 374
 375 static int clk_debugfs_register_one(struct clk *c)
 376 {
 377         int err;
 378         struct dentry *d;
 379         struct clk *pa = c->parent;
 380         char s[255];
 381         char *p = s;
 382
 383         p += sprintf(p, "%s", c->devname);
 384
 385         d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
 386         if (!d)
 387                 return -ENOMEM;
 388
 389         c->dent = d;
 390
 391         d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
 392         if (!d) {
 393                 err = -ENOMEM;
 394                 goto err_out;
 395         }
 396
 397         d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
 398         if (!d) {
 399                 err = -ENOMEM;
 400                 goto err_out;
 401         }
 402         return 0;
 403
 404 err_out:
 405         debugfs_remove_recursive(c->dent);
 406         return err;
 407 }
 408
 409 static int clk_debugfs_register(struct clk *c)
 410 {
 411         int err;
 412         struct clk *pa = c->parent;
 413
 414         if (pa && !pa->dent) {
 415                 err = clk_debugfs_register(pa);
 416                 if (err)
 417                         return err;
 418         }
 419
 420         if (!c->dent) {
 421                 err = clk_debugfs_register_one(c);
 422                 if (err)
 423                         return err;
 424         }
 425         return 0;
 426 }
 427
 428 static int __init clk_debugfs_init(void)
 429 {
 430         struct clk *c;
 431         struct dentry *d;
 432         int err;
 433
 434         d = debugfs_create_dir("clock", NULL);
 435         if (!d)
 436                 return -ENOMEM;
 437         clk_debugfs_root = d;
 438
 439         list_for_each_entry(c, &clocks, list) {
 440                 err = clk_debugfs_register(c);
 441                 if (err)
 442                         goto err_out;
 443         }
 444         return 0;
 445
 446 err_out:
 447         debugfs_remove_recursive(clk_debugfs_root);
 448         return err;
 449 }
 450 late_initcall(clk_debugfs_init);
 451
 452 #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */