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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / arch / mips / kernel / traps.c
blobd32a53cff18db3d1d9a6acd283efa8ff7d027069
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
24 #include <linux/ptrace.h>
25 #include <linux/kgdb.h>
26 #include <linux/kdebug.h>
27 #include <linux/kprobes.h>
28 #include <linux/notifier.h>
29 #include <linux/kdb.h>
30 #include <linux/irq.h>
31 #include <linux/perf_event.h>
32
33 #include <asm/bootinfo.h>
34 #include <asm/branch.h>
35 #include <asm/break.h>
36 #include <asm/cop2.h>
37 #include <asm/cpu.h>
38 #include <asm/dsp.h>
39 #include <asm/fpu.h>
40 #include <asm/fpu_emulator.h>
41 #include <asm/mipsregs.h>
42 #include <asm/mipsmtregs.h>
43 #include <asm/module.h>
44 #include <asm/pgtable.h>
45 #include <asm/ptrace.h>
46 #include <asm/sections.h>
47 #include <asm/system.h>
48 #include <asm/tlbdebug.h>
49 #include <asm/traps.h>
50 #include <asm/uaccess.h>
51 #include <asm/watch.h>
52 #include <asm/mmu_context.h>
53 #include <asm/types.h>
54 #include <asm/stacktrace.h>
55 #include <asm/uasm.h>
56
57 extern void check_wait(void);
58 extern asmlinkage void r4k_wait(void);
59 extern asmlinkage void rollback_handle_int(void);
60 extern asmlinkage void handle_int(void);
61 extern asmlinkage void handle_tlbm(void);
62 extern asmlinkage void handle_tlbl(void);
63 extern asmlinkage void handle_tlbs(void);
64 extern asmlinkage void handle_adel(void);
65 extern asmlinkage void handle_ades(void);
66 extern asmlinkage void handle_ibe(void);
67 extern asmlinkage void handle_dbe(void);
68 extern asmlinkage void handle_sys(void);
69 extern asmlinkage void handle_bp(void);
70 extern asmlinkage void handle_ri(void);
71 extern asmlinkage void handle_ri_rdhwr_vivt(void);
72 extern asmlinkage void handle_ri_rdhwr(void);
73 extern asmlinkage void handle_cpu(void);
74 extern asmlinkage void handle_ov(void);
75 extern asmlinkage void handle_tr(void);
76 extern asmlinkage void handle_fpe(void);
77 extern asmlinkage void handle_mdmx(void);
78 extern asmlinkage void handle_watch(void);
79 extern asmlinkage void handle_mt(void);
80 extern asmlinkage void handle_dsp(void);
81 extern asmlinkage void handle_mcheck(void);
82 extern asmlinkage void handle_reserved(void);
83
84 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
85 struct mips_fpu_struct *ctx, int has_fpu,
86 void *__user *fault_addr);
87
88 void (*board_be_init)(void);
89 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
90 void (*board_nmi_handler_setup)(void);
91 void (*board_ejtag_handler_setup)(void);
92 void (*board_bind_eic_interrupt)(int irq, int regset);
93
94
95 static void show_raw_backtrace(unsigned long reg29)
96 {
97 unsigned long *sp = (unsigned long *)(reg29 & ~3);
98 unsigned long addr;
99
100 printk("Call Trace:");
101 #ifdef CONFIG_KALLSYMS
102 printk("\n");
103 #endif
104 while (!kstack_end(sp)) {
105 unsigned long __user *p =
106 (unsigned long __user *)(unsigned long)sp++;
107 if (__get_user(addr, p)) {
108 printk(" (Bad stack address)");
109 break;
110 }
111 if (__kernel_text_address(addr))
112 print_ip_sym(addr);
113 }
114 printk("\n");
115 }
116
117 #ifdef CONFIG_KALLSYMS
118 int raw_show_trace;
119 static int __init set_raw_show_trace(char *str)
120 {
121 raw_show_trace = 1;
122 return 1;
123 }
124 __setup("raw_show_trace", set_raw_show_trace);
125 #endif
126
127 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
128 {
129 unsigned long sp = regs->regs[29];
130 unsigned long ra = regs->regs[31];
131 unsigned long pc = regs->cp0_epc;
132
133 if (raw_show_trace || !__kernel_text_address(pc)) {
134 show_raw_backtrace(sp);
135 return;
136 }
137 printk("Call Trace:\n");
138 do {
139 print_ip_sym(pc);
140 pc = unwind_stack(task, &sp, pc, &ra);
141 } while (pc);
142 printk("\n");
143 }
144
145 /*
146 * This routine abuses get_user()/put_user() to reference pointers
147 * with at least a bit of error checking ...
148 */
149 static void show_stacktrace(struct task_struct *task,
150 const struct pt_regs *regs)
151 {
152 const int field = 2 * sizeof(unsigned long);
153 long stackdata;
154 int i;
155 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
156
157 printk("Stack :");
158 i = 0;
159 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
160 if (i && ((i % (64 / field)) == 0))
161 printk("\n ");
162 if (i > 39) {
163 printk(" ...");
164 break;
165 }
166
167 if (__get_user(stackdata, sp++)) {
168 printk(" (Bad stack address)");
169 break;
170 }
171
172 printk(" %0*lx", field, stackdata);
173 i++;
174 }
175 printk("\n");
176 show_backtrace(task, regs);
177 }
178
179 void show_stack(struct task_struct *task, unsigned long *sp)
180 {
181 struct pt_regs regs;
182 if (sp) {
183 regs.regs[29] = (unsigned long)sp;
184 regs.regs[31] = 0;
185 regs.cp0_epc = 0;
186 } else {
187 if (task && task != current) {
188 regs.regs[29] = task->thread.reg29;
189 regs.regs[31] = 0;
190 regs.cp0_epc = task->thread.reg31;
191 #ifdef CONFIG_KGDB_KDB
192 } else if (atomic_read(&kgdb_active) != -1 &&
193 kdb_current_regs) {
194 memcpy(&regs, kdb_current_regs, sizeof(regs));
195 #endif /* CONFIG_KGDB_KDB */
196 } else {
197 prepare_frametrace(&regs);
198 }
199 }
200 show_stacktrace(task, &regs);
201 }
202
203 /*
204 * The architecture-independent dump_stack generator
205 */
206 void dump_stack(void)
207 {
208 struct pt_regs regs;
209
210 prepare_frametrace(&regs);
211 show_backtrace(current, &regs);
212 }
213
214 EXPORT_SYMBOL(dump_stack);
215
216 static void show_code(unsigned int __user *pc)
217 {
218 long i;
219 unsigned short __user *pc16 = NULL;
220
221 printk("\nCode:");
222
223 if ((unsigned long)pc & 1)
224 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
225 for(i = -3 ; i < 6 ; i++) {
226 unsigned int insn;
227 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
228 printk(" (Bad address in epc)\n");
229 break;
230 }
231 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
232 }
233 }
234
235 static void __show_regs(const struct pt_regs *regs)
236 {
237 const int field = 2 * sizeof(unsigned long);
238 unsigned int cause = regs->cp0_cause;
239 int i;
240
241 printk("Cpu %d\n", smp_processor_id());
242
243 /*
244 * Saved main processor registers
245 */
246 for (i = 0; i < 32; ) {
247 if ((i % 4) == 0)
248 printk("$%2d :", i);
249 if (i == 0)
250 printk(" %0*lx", field, 0UL);
251 else if (i == 26 || i == 27)
252 printk(" %*s", field, "");
253 else
254 printk(" %0*lx", field, regs->regs[i]);
255
256 i++;
257 if ((i % 4) == 0)
258 printk("\n");
259 }
260
261 #ifdef CONFIG_CPU_HAS_SMARTMIPS
262 printk("Acx : %0*lx\n", field, regs->acx);
263 #endif
264 printk("Hi : %0*lx\n", field, regs->hi);
265 printk("Lo : %0*lx\n", field, regs->lo);
266
267 /*
268 * Saved cp0 registers
269 */
270 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
271 (void *) regs->cp0_epc);
272 printk(" %s\n", print_tainted());
273 printk("ra : %0*lx %pS\n", field, regs->regs[31],
274 (void *) regs->regs[31]);
275
276 printk("Status: %08x ", (uint32_t) regs->cp0_status);
277
278 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
279 if (regs->cp0_status & ST0_KUO)
280 printk("KUo ");
281 if (regs->cp0_status & ST0_IEO)
282 printk("IEo ");
283 if (regs->cp0_status & ST0_KUP)
284 printk("KUp ");
285 if (regs->cp0_status & ST0_IEP)
286 printk("IEp ");
287 if (regs->cp0_status & ST0_KUC)
288 printk("KUc ");
289 if (regs->cp0_status & ST0_IEC)
290 printk("IEc ");
291 } else {
292 if (regs->cp0_status & ST0_KX)
293 printk("KX ");
294 if (regs->cp0_status & ST0_SX)
295 printk("SX ");
296 if (regs->cp0_status & ST0_UX)
297 printk("UX ");
298 switch (regs->cp0_status & ST0_KSU) {
299 case KSU_USER:
300 printk("USER ");
301 break;
302 case KSU_SUPERVISOR:
303 printk("SUPERVISOR ");
304 break;
305 case KSU_KERNEL:
306 printk("KERNEL ");
307 break;
308 default:
309 printk("BAD_MODE ");
310 break;
311 }
312 if (regs->cp0_status & ST0_ERL)
313 printk("ERL ");
314 if (regs->cp0_status & ST0_EXL)
315 printk("EXL ");
316 if (regs->cp0_status & ST0_IE)
317 printk("IE ");
318 }
319 printk("\n");
320
321 printk("Cause : %08x\n", cause);
322
323 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
324 if (1 <= cause && cause <= 5)
325 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
326
327 printk("PrId : %08x (%s)\n", read_c0_prid(),
328 cpu_name_string());
329 }
330
331 /*
332 * FIXME: really the generic show_regs should take a const pointer argument.
333 */
334 void show_regs(struct pt_regs *regs)
335 {
336 __show_regs((struct pt_regs *)regs);
337 }
338
339 void show_registers(struct pt_regs *regs)
340 {
341 const int field = 2 * sizeof(unsigned long);
342
343 __show_regs(regs);
344 print_modules();
345 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
346 current->comm, current->pid, current_thread_info(), current,
347 field, current_thread_info()->tp_value);
348 if (cpu_has_userlocal) {
349 unsigned long tls;
350
351 tls = read_c0_userlocal();
352 if (tls != current_thread_info()->tp_value)
353 printk("*HwTLS: %0*lx\n", field, tls);
354 }
355
356 show_stacktrace(current, regs);
357 show_code((unsigned int __user *) regs->cp0_epc);
358 printk("\n");
359 }
360
361 static int regs_to_trapnr(struct pt_regs *regs)
362 {
363 return (regs->cp0_cause >> 2) & 0x1f;
364 }
365
366 static DEFINE_RAW_SPINLOCK(die_lock);
367
368 void __noreturn die(const char *str, struct pt_regs *regs)
369 {
370 static int die_counter;
371 int sig = SIGSEGV;
372 #ifdef CONFIG_MIPS_MT_SMTC
373 unsigned long dvpret = dvpe();
374 #endif /* CONFIG_MIPS_MT_SMTC */
375
376 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
377 sig = 0;
378
379 console_verbose();
380 raw_spin_lock_irq(&die_lock);
381 bust_spinlocks(1);
382 #ifdef CONFIG_MIPS_MT_SMTC
383 mips_mt_regdump(dvpret);
384 #endif /* CONFIG_MIPS_MT_SMTC */
385
386 printk("%s[#%d]:\n", str, ++die_counter);
387 show_registers(regs);
388 add_taint(TAINT_DIE);
389 raw_spin_unlock_irq(&die_lock);
390
391 if (in_interrupt())
392 panic("Fatal exception in interrupt");
393
394 if (panic_on_oops) {
395 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
396 ssleep(5);
397 panic("Fatal exception");
398 }
399
400 do_exit(sig);
401 }
402
403 extern struct exception_table_entry __start___dbe_table[];
404 extern struct exception_table_entry __stop___dbe_table[];
405
406 __asm__(
407 " .section __dbe_table, \"a\"\n"
408 " .previous \n");
409
410 /* Given an address, look for it in the exception tables. */
411 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
412 {
413 const struct exception_table_entry *e;
414
415 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
416 if (!e)
417 e = search_module_dbetables(addr);
418 return e;
419 }
420
421 asmlinkage void do_be(struct pt_regs *regs)
422 {
423 const int field = 2 * sizeof(unsigned long);
424 const struct exception_table_entry *fixup = NULL;
425 int data = regs->cp0_cause & 4;
426 int action = MIPS_BE_FATAL;
427
428 /* XXX For now. Fixme, this searches the wrong table ... */
429 if (data && !user_mode(regs))
430 fixup = search_dbe_tables(exception_epc(regs));
431
432 if (fixup)
433 action = MIPS_BE_FIXUP;
434
435 if (board_be_handler)
436 action = board_be_handler(regs, fixup != NULL);
437
438 switch (action) {
439 case MIPS_BE_DISCARD:
440 return;
441 case MIPS_BE_FIXUP:
442 if (fixup) {
443 regs->cp0_epc = fixup->nextinsn;
444 return;
445 }
446 break;
447 default:
448 break;
449 }
450
451 /*
452 * Assume it would be too dangerous to continue ...
453 */
454 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
455 data ? "Data" : "Instruction",
456 field, regs->cp0_epc, field, regs->regs[31]);
457 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
458 == NOTIFY_STOP)
459 return;
460
461 die_if_kernel("Oops", regs);
462 force_sig(SIGBUS, current);
463 }
464
465 /*
466 * ll/sc, rdhwr, sync emulation
467 */
468
469 #define OPCODE 0xfc000000
470 #define BASE 0x03e00000
471 #define RT 0x001f0000
472 #define OFFSET 0x0000ffff
473 #define LL 0xc0000000
474 #define SC 0xe0000000
475 #define SPEC0 0x00000000
476 #define SPEC3 0x7c000000
477 #define RD 0x0000f800
478 #define FUNC 0x0000003f
479 #define SYNC 0x0000000f
480 #define RDHWR 0x0000003b
481
482 /*
483 * The ll_bit is cleared by r*_switch.S
484 */
485
486 unsigned int ll_bit;
487 struct task_struct *ll_task;
488
489 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
490 {
491 unsigned long value, __user *vaddr;
492 long offset;
493
494 /*
495 * analyse the ll instruction that just caused a ri exception
496 * and put the referenced address to addr.
497 */
498
499 /* sign extend offset */
500 offset = opcode & OFFSET;
501 offset <<= 16;
502 offset >>= 16;
503
504 vaddr = (unsigned long __user *)
505 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
506
507 if ((unsigned long)vaddr & 3)
508 return SIGBUS;
509 if (get_user(value, vaddr))
510 return SIGSEGV;
511
512 preempt_disable();
513
514 if (ll_task == NULL || ll_task == current) {
515 ll_bit = 1;
516 } else {
517 ll_bit = 0;
518 }
519 ll_task = current;
520
521 preempt_enable();
522
523 regs->regs[(opcode & RT) >> 16] = value;
524
525 return 0;
526 }
527
528 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
529 {
530 unsigned long __user *vaddr;
531 unsigned long reg;
532 long offset;
533
534 /*
535 * analyse the sc instruction that just caused a ri exception
536 * and put the referenced address to addr.
537 */
538
539 /* sign extend offset */
540 offset = opcode & OFFSET;
541 offset <<= 16;
542 offset >>= 16;
543
544 vaddr = (unsigned long __user *)
545 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
546 reg = (opcode & RT) >> 16;
547
548 if ((unsigned long)vaddr & 3)
549 return SIGBUS;
550
551 preempt_disable();
552
553 if (ll_bit == 0 || ll_task != current) {
554 regs->regs[reg] = 0;
555 preempt_enable();
556 return 0;
557 }
558
559 preempt_enable();
560
561 if (put_user(regs->regs[reg], vaddr))
562 return SIGSEGV;
563
564 regs->regs[reg] = 1;
565
566 return 0;
567 }
568
569 /*
570 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
571 * opcodes are supposed to result in coprocessor unusable exceptions if
572 * executed on ll/sc-less processors. That's the theory. In practice a
573 * few processors such as NEC's VR4100 throw reserved instruction exceptions
574 * instead, so we're doing the emulation thing in both exception handlers.
575 */
576 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
577 {
578 if ((opcode & OPCODE) == LL) {
579 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
580 1, regs, 0);
581 return simulate_ll(regs, opcode);
582 }
583 if ((opcode & OPCODE) == SC) {
584 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
585 1, regs, 0);
586 return simulate_sc(regs, opcode);
587 }
588
589 return -1; /* Must be something else ... */
590 }
591
592 /*
593 * Simulate trapping 'rdhwr' instructions to provide user accessible
594 * registers not implemented in hardware.
595 */
596 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
597 {
598 struct thread_info *ti = task_thread_info(current);
599
600 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
601 int rd = (opcode & RD) >> 11;
602 int rt = (opcode & RT) >> 16;
603 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
604 1, regs, 0);
605 switch (rd) {
606 case 0: /* CPU number */
607 regs->regs[rt] = smp_processor_id();
608 return 0;
609 case 1: /* SYNCI length */
610 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
611 current_cpu_data.icache.linesz);
612 return 0;
613 case 2: /* Read count register */
614 regs->regs[rt] = read_c0_count();
615 return 0;
616 case 3: /* Count register resolution */
617 switch (current_cpu_data.cputype) {
618 case CPU_20KC:
619 case CPU_25KF:
620 regs->regs[rt] = 1;
621 break;
622 default:
623 regs->regs[rt] = 2;
624 }
625 return 0;
626 case 29:
627 regs->regs[rt] = ti->tp_value;
628 return 0;
629 default:
630 return -1;
631 }
632 }
633
634 /* Not ours. */
635 return -1;
636 }
637
638 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
639 {
640 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
641 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
642 1, regs, 0);
643 return 0;
644 }
645
646 return -1; /* Must be something else ... */
647 }
648
649 asmlinkage void do_ov(struct pt_regs *regs)
650 {
651 siginfo_t info;
652
653 die_if_kernel("Integer overflow", regs);
654
655 info.si_code = FPE_INTOVF;
656 info.si_signo = SIGFPE;
657 info.si_errno = 0;
658 info.si_addr = (void __user *) regs->cp0_epc;
659 force_sig_info(SIGFPE, &info, current);
660 }
661
662 static int process_fpemu_return(int sig, void __user *fault_addr)
663 {
664 if (sig == SIGSEGV || sig == SIGBUS) {
665 struct siginfo si = {0};
666 si.si_addr = fault_addr;
667 si.si_signo = sig;
668 if (sig == SIGSEGV) {
669 if (find_vma(current->mm, (unsigned long)fault_addr))
670 si.si_code = SEGV_ACCERR;
671 else
672 si.si_code = SEGV_MAPERR;
673 } else {
674 si.si_code = BUS_ADRERR;
675 }
676 force_sig_info(sig, &si, current);
677 return 1;
678 } else if (sig) {
679 force_sig(sig, current);
680 return 1;
681 } else {
682 return 0;
683 }
684 }
685
686 /*
687 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
688 */
689 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
690 {
691 siginfo_t info = {0};
692
693 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
694 == NOTIFY_STOP)
695 return;
696 die_if_kernel("FP exception in kernel code", regs);
697
698 if (fcr31 & FPU_CSR_UNI_X) {
699 int sig;
700 void __user *fault_addr = NULL;
701
702 /*
703 * Unimplemented operation exception. If we've got the full
704 * software emulator on-board, let's use it...
705 *
706 * Force FPU to dump state into task/thread context. We're
707 * moving a lot of data here for what is probably a single
708 * instruction, but the alternative is to pre-decode the FP
709 * register operands before invoking the emulator, which seems
710 * a bit extreme for what should be an infrequent event.
711 */
712 /* Ensure 'resume' not overwrite saved fp context again. */
713 lose_fpu(1);
714
715 /* Run the emulator */
716 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
717 &fault_addr);
718
719 /*
720 * We can't allow the emulated instruction to leave any of
721 * the cause bit set in $fcr31.
722 */
723 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
724
725 /* Restore the hardware register state */
726 own_fpu(1); /* Using the FPU again. */
727
728 /* If something went wrong, signal */
729 process_fpemu_return(sig, fault_addr);
730
731 return;
732 } else if (fcr31 & FPU_CSR_INV_X)
733 info.si_code = FPE_FLTINV;
734 else if (fcr31 & FPU_CSR_DIV_X)
735 info.si_code = FPE_FLTDIV;
736 else if (fcr31 & FPU_CSR_OVF_X)
737 info.si_code = FPE_FLTOVF;
738 else if (fcr31 & FPU_CSR_UDF_X)
739 info.si_code = FPE_FLTUND;
740 else if (fcr31 & FPU_CSR_INE_X)
741 info.si_code = FPE_FLTRES;
742 else
743 info.si_code = __SI_FAULT;
744 info.si_signo = SIGFPE;
745 info.si_errno = 0;
746 info.si_addr = (void __user *) regs->cp0_epc;
747 force_sig_info(SIGFPE, &info, current);
748 }
749
750 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
751 const char *str)
752 {
753 siginfo_t info;
754 char b[40];
755
756 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
757 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
758 return;
759 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
760
761 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
762 return;
763
764 /*
765 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
766 * insns, even for trap and break codes that indicate arithmetic
767 * failures. Weird ...
768 * But should we continue the brokenness??? --macro
769 */
770 switch (code) {
771 case BRK_OVERFLOW:
772 case BRK_DIVZERO:
773 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
774 die_if_kernel(b, regs);
775 if (code == BRK_DIVZERO)
776 info.si_code = FPE_INTDIV;
777 else
778 info.si_code = FPE_INTOVF;
779 info.si_signo = SIGFPE;
780 info.si_errno = 0;
781 info.si_addr = (void __user *) regs->cp0_epc;
782 force_sig_info(SIGFPE, &info, current);
783 break;
784 case BRK_BUG:
785 die_if_kernel("Kernel bug detected", regs);
786 force_sig(SIGTRAP, current);
787 break;
788 case BRK_MEMU:
789 /*
790 * Address errors may be deliberately induced by the FPU
791 * emulator to retake control of the CPU after executing the
792 * instruction in the delay slot of an emulated branch.
793 *
794 * Terminate if exception was recognized as a delay slot return
795 * otherwise handle as normal.
796 */
797 if (do_dsemulret(regs))
798 return;
799
800 die_if_kernel("Math emu break/trap", regs);
801 force_sig(SIGTRAP, current);
802 break;
803 default:
804 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
805 die_if_kernel(b, regs);
806 force_sig(SIGTRAP, current);
807 }
808 }
809
810 asmlinkage void do_bp(struct pt_regs *regs)
811 {
812 unsigned int opcode, bcode;
813
814 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
815 goto out_sigsegv;
816
817 /*
818 * There is the ancient bug in the MIPS assemblers that the break
819 * code starts left to bit 16 instead to bit 6 in the opcode.
820 * Gas is bug-compatible, but not always, grrr...
821 * We handle both cases with a simple heuristics. --macro
822 */
823 bcode = ((opcode >> 6) & ((1 << 20) - 1));
824 if (bcode >= (1 << 10))
825 bcode >>= 10;
826
827 /*
828 * notify the kprobe handlers, if instruction is likely to
829 * pertain to them.
830 */
831 switch (bcode) {
832 case BRK_KPROBE_BP:
833 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
834 return;
835 else
836 break;
837 case BRK_KPROBE_SSTEPBP:
838 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
839 return;
840 else
841 break;
842 default:
843 break;
844 }
845
846 do_trap_or_bp(regs, bcode, "Break");
847 return;
848
849 out_sigsegv:
850 force_sig(SIGSEGV, current);
851 }
852
853 asmlinkage void do_tr(struct pt_regs *regs)
854 {
855 unsigned int opcode, tcode = 0;
856
857 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
858 goto out_sigsegv;
859
860 /* Immediate versions don't provide a code. */
861 if (!(opcode & OPCODE))
862 tcode = ((opcode >> 6) & ((1 << 10) - 1));
863
864 do_trap_or_bp(regs, tcode, "Trap");
865 return;
866
867 out_sigsegv:
868 force_sig(SIGSEGV, current);
869 }
870
871 asmlinkage void do_ri(struct pt_regs *regs)
872 {
873 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
874 unsigned long old_epc = regs->cp0_epc;
875 unsigned int opcode = 0;
876 int status = -1;
877
878 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
879 == NOTIFY_STOP)
880 return;
881
882 die_if_kernel("Reserved instruction in kernel code", regs);
883
884 if (unlikely(compute_return_epc(regs) < 0))
885 return;
886
887 if (unlikely(get_user(opcode, epc) < 0))
888 status = SIGSEGV;
889
890 if (!cpu_has_llsc && status < 0)
891 status = simulate_llsc(regs, opcode);
892
893 if (status < 0)
894 status = simulate_rdhwr(regs, opcode);
895
896 if (status < 0)
897 status = simulate_sync(regs, opcode);
898
899 if (status < 0)
900 status = SIGILL;
901
902 if (unlikely(status > 0)) {
903 regs->cp0_epc = old_epc; /* Undo skip-over. */
904 force_sig(status, current);
905 }
906 }
907
908 /*
909 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
910 * emulated more than some threshold number of instructions, force migration to
911 * a "CPU" that has FP support.
912 */
913 static void mt_ase_fp_affinity(void)
914 {
915 #ifdef CONFIG_MIPS_MT_FPAFF
916 if (mt_fpemul_threshold > 0 &&
917 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
918 /*
919 * If there's no FPU present, or if the application has already
920 * restricted the allowed set to exclude any CPUs with FPUs,
921 * we'll skip the procedure.
922 */
923 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
924 cpumask_t tmask;
925
926 current->thread.user_cpus_allowed
927 = current->cpus_allowed;
928 cpus_and(tmask, current->cpus_allowed,
929 mt_fpu_cpumask);
930 set_cpus_allowed_ptr(current, &tmask);
931 set_thread_flag(TIF_FPUBOUND);
932 }
933 }
934 #endif /* CONFIG_MIPS_MT_FPAFF */
935 }
936
937 /*
938 * No lock; only written during early bootup by CPU 0.
939 */
940 static RAW_NOTIFIER_HEAD(cu2_chain);
941
942 int __ref register_cu2_notifier(struct notifier_block *nb)
943 {
944 return raw_notifier_chain_register(&cu2_chain, nb);
945 }
946
947 int cu2_notifier_call_chain(unsigned long val, void *v)
948 {
949 return raw_notifier_call_chain(&cu2_chain, val, v);
950 }
951
952 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
953 void *data)
954 {
955 struct pt_regs *regs = data;
956
957 switch (action) {
958 default:
959 die_if_kernel("Unhandled kernel unaligned access or invalid "
960 "instruction", regs);
961 /* Fall through */
962
963 case CU2_EXCEPTION:
964 force_sig(SIGILL, current);
965 }
966
967 return NOTIFY_OK;
968 }
969
970 asmlinkage void do_cpu(struct pt_regs *regs)
971 {
972 unsigned int __user *epc;
973 unsigned long old_epc;
974 unsigned int opcode;
975 unsigned int cpid;
976 int status;
977 unsigned long __maybe_unused flags;
978
979 die_if_kernel("do_cpu invoked from kernel context!", regs);
980
981 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
982
983 switch (cpid) {
984 case 0:
985 epc = (unsigned int __user *)exception_epc(regs);
986 old_epc = regs->cp0_epc;
987 opcode = 0;
988 status = -1;
989
990 if (unlikely(compute_return_epc(regs) < 0))
991 return;
992
993 if (unlikely(get_user(opcode, epc) < 0))
994 status = SIGSEGV;
995
996 if (!cpu_has_llsc && status < 0)
997 status = simulate_llsc(regs, opcode);
998
999 if (status < 0)
1000 status = simulate_rdhwr(regs, opcode);
1001
1002 if (status < 0)
1003 status = SIGILL;
1004
1005 if (unlikely(status > 0)) {
1006 regs->cp0_epc = old_epc; /* Undo skip-over. */
1007 force_sig(status, current);
1008 }
1009
1010 return;
1011
1012 case 1:
1013 if (used_math()) /* Using the FPU again. */
1014 own_fpu(1);
1015 else { /* First time FPU user. */
1016 init_fpu();
1017 set_used_math();
1018 }
1019
1020 if (!raw_cpu_has_fpu) {
1021 int sig;
1022 void __user *fault_addr = NULL;
1023 sig = fpu_emulator_cop1Handler(regs,
1024 &current->thread.fpu,
1025 0, &fault_addr);
1026 if (!process_fpemu_return(sig, fault_addr))
1027 mt_ase_fp_affinity();
1028 }
1029
1030 return;
1031
1032 case 2:
1033 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1034 return;
1035
1036 case 3:
1037 break;
1038 }
1039
1040 force_sig(SIGILL, current);
1041 }
1042
1043 asmlinkage void do_mdmx(struct pt_regs *regs)
1044 {
1045 force_sig(SIGILL, current);
1046 }
1047
1048 /*
1049 * Called with interrupts disabled.
1050 */
1051 asmlinkage void do_watch(struct pt_regs *regs)
1052 {
1053 u32 cause;
1054
1055 /*
1056 * Clear WP (bit 22) bit of cause register so we don't loop
1057 * forever.
1058 */
1059 cause = read_c0_cause();
1060 cause &= ~(1 << 22);
1061 write_c0_cause(cause);
1062
1063 /*
1064 * If the current thread has the watch registers loaded, save
1065 * their values and send SIGTRAP. Otherwise another thread
1066 * left the registers set, clear them and continue.
1067 */
1068 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1069 mips_read_watch_registers();
1070 local_irq_enable();
1071 force_sig(SIGTRAP, current);
1072 } else {
1073 mips_clear_watch_registers();
1074 local_irq_enable();
1075 }
1076 }
1077
1078 asmlinkage void do_mcheck(struct pt_regs *regs)
1079 {
1080 const int field = 2 * sizeof(unsigned long);
1081 int multi_match = regs->cp0_status & ST0_TS;
1082
1083 show_regs(regs);
1084
1085 if (multi_match) {
1086 printk("Index : %0x\n", read_c0_index());
1087 printk("Pagemask: %0x\n", read_c0_pagemask());
1088 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1089 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1090 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1091 printk("\n");
1092 dump_tlb_all();
1093 }
1094
1095 show_code((unsigned int __user *) regs->cp0_epc);
1096
1097 /*
1098 * Some chips may have other causes of machine check (e.g. SB1
1099 * graduation timer)
1100 */
1101 panic("Caught Machine Check exception - %scaused by multiple "
1102 "matching entries in the TLB.",
1103 (multi_match) ? "" : "not ");
1104 }
1105
1106 asmlinkage void do_mt(struct pt_regs *regs)
1107 {
1108 int subcode;
1109
1110 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1111 >> VPECONTROL_EXCPT_SHIFT;
1112 switch (subcode) {
1113 case 0:
1114 printk(KERN_DEBUG "Thread Underflow\n");
1115 break;
1116 case 1:
1117 printk(KERN_DEBUG "Thread Overflow\n");
1118 break;
1119 case 2:
1120 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1121 break;
1122 case 3:
1123 printk(KERN_DEBUG "Gating Storage Exception\n");
1124 break;
1125 case 4:
1126 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1127 break;
1128 case 5:
1129 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1130 break;
1131 default:
1132 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1133 subcode);
1134 break;
1135 }
1136 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1137
1138 force_sig(SIGILL, current);
1139 }
1140
1141
1142 asmlinkage void do_dsp(struct pt_regs *regs)
1143 {
1144 if (cpu_has_dsp)
1145 panic("Unexpected DSP exception\n");
1146
1147 force_sig(SIGILL, current);
1148 }
1149
1150 asmlinkage void do_reserved(struct pt_regs *regs)
1151 {
1152 /*
1153 * Game over - no way to handle this if it ever occurs. Most probably
1154 * caused by a new unknown cpu type or after another deadly
1155 * hard/software error.
1156 */
1157 show_regs(regs);
1158 panic("Caught reserved exception %ld - should not happen.",
1159 (regs->cp0_cause & 0x7f) >> 2);
1160 }
1161
1162 static int __initdata l1parity = 1;
1163 static int __init nol1parity(char *s)
1164 {
1165 l1parity = 0;
1166 return 1;
1167 }
1168 __setup("nol1par", nol1parity);
1169 static int __initdata l2parity = 1;
1170 static int __init nol2parity(char *s)
1171 {
1172 l2parity = 0;
1173 return 1;
1174 }
1175 __setup("nol2par", nol2parity);
1176
1177 /*
1178 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1179 * it different ways.
1180 */
1181 static inline void parity_protection_init(void)
1182 {
1183 switch (current_cpu_type()) {
1184 case CPU_24K:
1185 case CPU_34K:
1186 case CPU_74K:
1187 case CPU_1004K:
1188 {
1189 #define ERRCTL_PE 0x80000000
1190 #define ERRCTL_L2P 0x00800000
1191 unsigned long errctl;
1192 unsigned int l1parity_present, l2parity_present;
1193
1194 errctl = read_c0_ecc();
1195 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1196
1197 /* probe L1 parity support */
1198 write_c0_ecc(errctl | ERRCTL_PE);
1199 back_to_back_c0_hazard();
1200 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1201
1202 /* probe L2 parity support */
1203 write_c0_ecc(errctl|ERRCTL_L2P);
1204 back_to_back_c0_hazard();
1205 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1206
1207 if (l1parity_present && l2parity_present) {
1208 if (l1parity)
1209 errctl |= ERRCTL_PE;
1210 if (l1parity ^ l2parity)
1211 errctl |= ERRCTL_L2P;
1212 } else if (l1parity_present) {
1213 if (l1parity)
1214 errctl |= ERRCTL_PE;
1215 } else if (l2parity_present) {
1216 if (l2parity)
1217 errctl |= ERRCTL_L2P;
1218 } else {
1219 /* No parity available */
1220 }
1221
1222 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1223
1224 write_c0_ecc(errctl);
1225 back_to_back_c0_hazard();
1226 errctl = read_c0_ecc();
1227 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1228
1229 if (l1parity_present)
1230 printk(KERN_INFO "Cache parity protection %sabled\n",
1231 (errctl & ERRCTL_PE) ? "en" : "dis");
1232
1233 if (l2parity_present) {
1234 if (l1parity_present && l1parity)
1235 errctl ^= ERRCTL_L2P;
1236 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1237 (errctl & ERRCTL_L2P) ? "en" : "dis");
1238 }
1239 }
1240 break;
1241
1242 case CPU_5KC:
1243 write_c0_ecc(0x80000000);
1244 back_to_back_c0_hazard();
1245 /* Set the PE bit (bit 31) in the c0_errctl register. */
1246 printk(KERN_INFO "Cache parity protection %sabled\n",
1247 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1248 break;
1249 case CPU_20KC:
1250 case CPU_25KF:
1251 /* Clear the DE bit (bit 16) in the c0_status register. */
1252 printk(KERN_INFO "Enable cache parity protection for "
1253 "MIPS 20KC/25KF CPUs.\n");
1254 clear_c0_status(ST0_DE);
1255 break;
1256 default:
1257 break;
1258 }
1259 }
1260
1261 asmlinkage void cache_parity_error(void)
1262 {
1263 const int field = 2 * sizeof(unsigned long);
1264 unsigned int reg_val;
1265
1266 /* For the moment, report the problem and hang. */
1267 printk("Cache error exception:\n");
1268 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1269 reg_val = read_c0_cacheerr();
1270 printk("c0_cacheerr == %08x\n", reg_val);
1271
1272 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1273 reg_val & (1<<30) ? "secondary" : "primary",
1274 reg_val & (1<<31) ? "data" : "insn");
1275 printk("Error bits: %s%s%s%s%s%s%s\n",
1276 reg_val & (1<<29) ? "ED " : "",
1277 reg_val & (1<<28) ? "ET " : "",
1278 reg_val & (1<<26) ? "EE " : "",
1279 reg_val & (1<<25) ? "EB " : "",
1280 reg_val & (1<<24) ? "EI " : "",
1281 reg_val & (1<<23) ? "E1 " : "",
1282 reg_val & (1<<22) ? "E0 " : "");
1283 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1284
1285 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1286 if (reg_val & (1<<22))
1287 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1288
1289 if (reg_val & (1<<23))
1290 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1291 #endif
1292
1293 panic("Can't handle the cache error!");
1294 }
1295
1296 /*
1297 * SDBBP EJTAG debug exception handler.
1298 * We skip the instruction and return to the next instruction.
1299 */
1300 void ejtag_exception_handler(struct pt_regs *regs)
1301 {
1302 const int field = 2 * sizeof(unsigned long);
1303 unsigned long depc, old_epc;
1304 unsigned int debug;
1305
1306 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1307 depc = read_c0_depc();
1308 debug = read_c0_debug();
1309 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1310 if (debug & 0x80000000) {
1311 /*
1312 * In branch delay slot.
1313 * We cheat a little bit here and use EPC to calculate the
1314 * debug return address (DEPC). EPC is restored after the
1315 * calculation.
1316 */
1317 old_epc = regs->cp0_epc;
1318 regs->cp0_epc = depc;
1319 __compute_return_epc(regs);
1320 depc = regs->cp0_epc;
1321 regs->cp0_epc = old_epc;
1322 } else
1323 depc += 4;
1324 write_c0_depc(depc);
1325
1326 #if 0
1327 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1328 write_c0_debug(debug | 0x100);
1329 #endif
1330 }
1331
1332 /*
1333 * NMI exception handler.
1334 */
1335 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1336 {
1337 bust_spinlocks(1);
1338 printk("NMI taken!!!!\n");
1339 die("NMI", regs);
1340 }
1341
1342 #define VECTORSPACING 0x100 /* for EI/VI mode */
1343
1344 unsigned long ebase;
1345 unsigned long exception_handlers[32];
1346 unsigned long vi_handlers[64];
1347
1348 void __init *set_except_vector(int n, void *addr)
1349 {
1350 unsigned long handler = (unsigned long) addr;
1351 unsigned long old_handler = exception_handlers[n];
1352
1353 exception_handlers[n] = handler;
1354 if (n == 0 && cpu_has_divec) {
1355 unsigned long jump_mask = ~((1 << 28) - 1);
1356 u32 *buf = (u32 *)(ebase + 0x200);
1357 unsigned int k0 = 26;
1358 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1359 uasm_i_j(&buf, handler & ~jump_mask);
1360 uasm_i_nop(&buf);
1361 } else {
1362 UASM_i_LA(&buf, k0, handler);
1363 uasm_i_jr(&buf, k0);
1364 uasm_i_nop(&buf);
1365 }
1366 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1367 }
1368 return (void *)old_handler;
1369 }
1370
1371 static asmlinkage void do_default_vi(void)
1372 {
1373 show_regs(get_irq_regs());
1374 panic("Caught unexpected vectored interrupt.");
1375 }
1376
1377 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1378 {
1379 unsigned long handler;
1380 unsigned long old_handler = vi_handlers[n];
1381 int srssets = current_cpu_data.srsets;
1382 u32 *w;
1383 unsigned char *b;
1384
1385 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1386
1387 if (addr == NULL) {
1388 handler = (unsigned long) do_default_vi;
1389 srs = 0;
1390 } else
1391 handler = (unsigned long) addr;
1392 vi_handlers[n] = (unsigned long) addr;
1393
1394 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1395
1396 if (srs >= srssets)
1397 panic("Shadow register set %d not supported", srs);
1398
1399 if (cpu_has_veic) {
1400 if (board_bind_eic_interrupt)
1401 board_bind_eic_interrupt(n, srs);
1402 } else if (cpu_has_vint) {
1403 /* SRSMap is only defined if shadow sets are implemented */
1404 if (srssets > 1)
1405 change_c0_srsmap(0xf << n*4, srs << n*4);
1406 }
1407
1408 if (srs == 0) {
1409 /*
1410 * If no shadow set is selected then use the default handler
1411 * that does normal register saving and a standard interrupt exit
1412 */
1413
1414 extern char except_vec_vi, except_vec_vi_lui;
1415 extern char except_vec_vi_ori, except_vec_vi_end;
1416 extern char rollback_except_vec_vi;
1417 char *vec_start = (cpu_wait == r4k_wait) ?
1418 &rollback_except_vec_vi : &except_vec_vi;
1419 #ifdef CONFIG_MIPS_MT_SMTC
1420 /*
1421 * We need to provide the SMTC vectored interrupt handler
1422 * not only with the address of the handler, but with the
1423 * Status.IM bit to be masked before going there.
1424 */
1425 extern char except_vec_vi_mori;
1426 const int mori_offset = &except_vec_vi_mori - vec_start;
1427 #endif /* CONFIG_MIPS_MT_SMTC */
1428 const int handler_len = &except_vec_vi_end - vec_start;
1429 const int lui_offset = &except_vec_vi_lui - vec_start;
1430 const int ori_offset = &except_vec_vi_ori - vec_start;
1431
1432 if (handler_len > VECTORSPACING) {
1433 /*
1434 * Sigh... panicing won't help as the console
1435 * is probably not configured :(
1436 */
1437 panic("VECTORSPACING too small");
1438 }
1439
1440 memcpy(b, vec_start, handler_len);
1441 #ifdef CONFIG_MIPS_MT_SMTC
1442 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1443
1444 w = (u32 *)(b + mori_offset);
1445 *w = (*w & 0xffff0000) | (0x100 << n);
1446 #endif /* CONFIG_MIPS_MT_SMTC */
1447 w = (u32 *)(b + lui_offset);
1448 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1449 w = (u32 *)(b + ori_offset);
1450 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1451 local_flush_icache_range((unsigned long)b,
1452 (unsigned long)(b+handler_len));
1453 }
1454 else {
1455 /*
1456 * In other cases jump directly to the interrupt handler
1457 *
1458 * It is the handlers responsibility to save registers if required
1459 * (eg hi/lo) and return from the exception using "eret"
1460 */
1461 w = (u32 *)b;
1462 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1463 *w = 0;
1464 local_flush_icache_range((unsigned long)b,
1465 (unsigned long)(b+8));
1466 }
1467
1468 return (void *)old_handler;
1469 }
1470
1471 void *set_vi_handler(int n, vi_handler_t addr)
1472 {
1473 return set_vi_srs_handler(n, addr, 0);
1474 }
1475
1476 extern void cpu_cache_init(void);
1477 extern void tlb_init(void);
1478 extern void flush_tlb_handlers(void);
1479
1480 /*
1481 * Timer interrupt
1482 */
1483 int cp0_compare_irq;
1484 int cp0_compare_irq_shift;
1485
1486 /*
1487 * Performance counter IRQ or -1 if shared with timer
1488 */
1489 int cp0_perfcount_irq;
1490 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1491
1492 static int __cpuinitdata noulri;
1493
1494 static int __init ulri_disable(char *s)
1495 {
1496 pr_info("Disabling ulri\n");
1497 noulri = 1;
1498
1499 return 1;
1500 }
1501 __setup("noulri", ulri_disable);
1502
1503 void __cpuinit per_cpu_trap_init(void)
1504 {
1505 unsigned int cpu = smp_processor_id();
1506 unsigned int status_set = ST0_CU0;
1507 unsigned int hwrena = cpu_hwrena_impl_bits;
1508 #ifdef CONFIG_MIPS_MT_SMTC
1509 int secondaryTC = 0;
1510 int bootTC = (cpu == 0);
1511
1512 /*
1513 * Only do per_cpu_trap_init() for first TC of Each VPE.
1514 * Note that this hack assumes that the SMTC init code
1515 * assigns TCs consecutively and in ascending order.
1516 */
1517
1518 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1519 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1520 secondaryTC = 1;
1521 #endif /* CONFIG_MIPS_MT_SMTC */
1522
1523 /*
1524 * Disable coprocessors and select 32-bit or 64-bit addressing
1525 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1526 * flag that some firmware may have left set and the TS bit (for
1527 * IP27). Set XX for ISA IV code to work.
1528 */
1529 #ifdef CONFIG_64BIT
1530 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1531 #endif
1532 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1533 status_set |= ST0_XX;
1534 if (cpu_has_dsp)
1535 status_set |= ST0_MX;
1536
1537 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1538 status_set);
1539
1540 if (cpu_has_mips_r2)
1541 hwrena |= 0x0000000f;
1542
1543 if (!noulri && cpu_has_userlocal)
1544 hwrena |= (1 << 29);
1545
1546 if (hwrena)
1547 write_c0_hwrena(hwrena);
1548
1549 #ifdef CONFIG_MIPS_MT_SMTC
1550 if (!secondaryTC) {
1551 #endif /* CONFIG_MIPS_MT_SMTC */
1552
1553 if (cpu_has_veic || cpu_has_vint) {
1554 unsigned long sr = set_c0_status(ST0_BEV);
1555 write_c0_ebase(ebase);
1556 write_c0_status(sr);
1557 /* Setting vector spacing enables EI/VI mode */
1558 change_c0_intctl(0x3e0, VECTORSPACING);
1559 }
1560 if (cpu_has_divec) {
1561 if (cpu_has_mipsmt) {
1562 unsigned int vpflags = dvpe();
1563 set_c0_cause(CAUSEF_IV);
1564 evpe(vpflags);
1565 } else
1566 set_c0_cause(CAUSEF_IV);
1567 }
1568
1569 /*
1570 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1571 *
1572 * o read IntCtl.IPTI to determine the timer interrupt
1573 * o read IntCtl.IPPCI to determine the performance counter interrupt
1574 */
1575 if (cpu_has_mips_r2) {
1576 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1577 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1578 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1579 if (cp0_perfcount_irq == cp0_compare_irq)
1580 cp0_perfcount_irq = -1;
1581 } else {
1582 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1583 cp0_compare_irq_shift = cp0_compare_irq;
1584 cp0_perfcount_irq = -1;
1585 }
1586
1587 #ifdef CONFIG_MIPS_MT_SMTC
1588 }
1589 #endif /* CONFIG_MIPS_MT_SMTC */
1590
1591 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1592
1593 atomic_inc(&init_mm.mm_count);
1594 current->active_mm = &init_mm;
1595 BUG_ON(current->mm);
1596 enter_lazy_tlb(&init_mm, current);
1597
1598 #ifdef CONFIG_MIPS_MT_SMTC
1599 if (bootTC) {
1600 #endif /* CONFIG_MIPS_MT_SMTC */
1601 cpu_cache_init();
1602 tlb_init();
1603 #ifdef CONFIG_MIPS_MT_SMTC
1604 } else if (!secondaryTC) {
1605 /*
1606 * First TC in non-boot VPE must do subset of tlb_init()
1607 * for MMU countrol registers.
1608 */
1609 write_c0_pagemask(PM_DEFAULT_MASK);
1610 write_c0_wired(0);
1611 }
1612 #endif /* CONFIG_MIPS_MT_SMTC */
1613 TLBMISS_HANDLER_SETUP();
1614 }
1615
1616 /* Install CPU exception handler */
1617 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1618 {
1619 memcpy((void *)(ebase + offset), addr, size);
1620 local_flush_icache_range(ebase + offset, ebase + offset + size);
1621 }
1622
1623 static char panic_null_cerr[] __cpuinitdata =
1624 "Trying to set NULL cache error exception handler";
1625
1626 /*
1627 * Install uncached CPU exception handler.
1628 * This is suitable only for the cache error exception which is the only
1629 * exception handler that is being run uncached.
1630 */
1631 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1632 unsigned long size)
1633 {
1634 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1635
1636 if (!addr)
1637 panic(panic_null_cerr);
1638
1639 memcpy((void *)(uncached_ebase + offset), addr, size);
1640 }
1641
1642 static int __initdata rdhwr_noopt;
1643 static int __init set_rdhwr_noopt(char *str)
1644 {
1645 rdhwr_noopt = 1;
1646 return 1;
1647 }
1648
1649 __setup("rdhwr_noopt", set_rdhwr_noopt);
1650
1651 void __init trap_init(void)
1652 {
1653 extern char except_vec3_generic, except_vec3_r4000;
1654 extern char except_vec4;
1655 unsigned long i;
1656 int rollback;
1657
1658 check_wait();
1659 rollback = (cpu_wait == r4k_wait);
1660
1661 #if defined(CONFIG_KGDB)
1662 if (kgdb_early_setup)
1663 return; /* Already done */
1664 #endif
1665
1666 if (cpu_has_veic || cpu_has_vint) {
1667 unsigned long size = 0x200 + VECTORSPACING*64;
1668 ebase = (unsigned long)
1669 __alloc_bootmem(size, 1 << fls(size), 0);
1670 } else {
1671 ebase = CKSEG0;
1672 if (cpu_has_mips_r2)
1673 ebase += (read_c0_ebase() & 0x3ffff000);
1674 }
1675
1676 per_cpu_trap_init();
1677
1678 /*
1679 * Copy the generic exception handlers to their final destination.
1680 * This will be overriden later as suitable for a particular
1681 * configuration.
1682 */
1683 set_handler(0x180, &except_vec3_generic, 0x80);
1684
1685 /*
1686 * Setup default vectors
1687 */
1688 for (i = 0; i <= 31; i++)
1689 set_except_vector(i, handle_reserved);
1690
1691 /*
1692 * Copy the EJTAG debug exception vector handler code to it's final
1693 * destination.
1694 */
1695 if (cpu_has_ejtag && board_ejtag_handler_setup)
1696 board_ejtag_handler_setup();
1697
1698 /*
1699 * Only some CPUs have the watch exceptions.
1700 */
1701 if (cpu_has_watch)
1702 set_except_vector(23, handle_watch);
1703
1704 /*
1705 * Initialise interrupt handlers
1706 */
1707 if (cpu_has_veic || cpu_has_vint) {
1708 int nvec = cpu_has_veic ? 64 : 8;
1709 for (i = 0; i < nvec; i++)
1710 set_vi_handler(i, NULL);
1711 }
1712 else if (cpu_has_divec)
1713 set_handler(0x200, &except_vec4, 0x8);
1714
1715 /*
1716 * Some CPUs can enable/disable for cache parity detection, but does
1717 * it different ways.
1718 */
1719 parity_protection_init();
1720
1721 /*
1722 * The Data Bus Errors / Instruction Bus Errors are signaled
1723 * by external hardware. Therefore these two exceptions
1724 * may have board specific handlers.
1725 */
1726 if (board_be_init)
1727 board_be_init();
1728
1729 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1730 set_except_vector(1, handle_tlbm);
1731 set_except_vector(2, handle_tlbl);
1732 set_except_vector(3, handle_tlbs);
1733
1734 set_except_vector(4, handle_adel);
1735 set_except_vector(5, handle_ades);
1736
1737 set_except_vector(6, handle_ibe);
1738 set_except_vector(7, handle_dbe);
1739
1740 set_except_vector(8, handle_sys);
1741 set_except_vector(9, handle_bp);
1742 set_except_vector(10, rdhwr_noopt ? handle_ri :
1743 (cpu_has_vtag_icache ?
1744 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1745 set_except_vector(11, handle_cpu);
1746 set_except_vector(12, handle_ov);
1747 set_except_vector(13, handle_tr);
1748
1749 if (current_cpu_type() == CPU_R6000 ||
1750 current_cpu_type() == CPU_R6000A) {
1751 /*
1752 * The R6000 is the only R-series CPU that features a machine
1753 * check exception (similar to the R4000 cache error) and
1754 * unaligned ldc1/sdc1 exception. The handlers have not been
1755 * written yet. Well, anyway there is no R6000 machine on the
1756 * current list of targets for Linux/MIPS.
1757 * (Duh, crap, there is someone with a triple R6k machine)
1758 */
1759 //set_except_vector(14, handle_mc);
1760 //set_except_vector(15, handle_ndc);
1761 }
1762
1763
1764 if (board_nmi_handler_setup)
1765 board_nmi_handler_setup();
1766
1767 if (cpu_has_fpu && !cpu_has_nofpuex)
1768 set_except_vector(15, handle_fpe);
1769
1770 set_except_vector(22, handle_mdmx);
1771
1772 if (cpu_has_mcheck)
1773 set_except_vector(24, handle_mcheck);
1774
1775 if (cpu_has_mipsmt)
1776 set_except_vector(25, handle_mt);
1777
1778 set_except_vector(26, handle_dsp);
1779
1780 if (cpu_has_vce)
1781 /* Special exception: R4[04]00 uses also the divec space. */
1782 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1783 else if (cpu_has_4kex)
1784 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1785 else
1786 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1787
1788 local_flush_icache_range(ebase, ebase + 0x400);
1789 flush_tlb_handlers();
1790
1791 sort_extable(__start___dbe_table, __stop___dbe_table);
1792
1793 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1794 }
linux-next