arch/mips/kernel/unaligned.c

   1 /*
   2  * Handle unaligned accesses by emulation.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  *
  11  * This file contains exception handler for address error exception with the
  12  * special capability to execute faulting instructions in software.  The
  13  * handler does not try to handle the case when the program counter points
  14  * to an address not aligned to a word boundary.
  15  *
  16  * Putting data to unaligned addresses is a bad practice even on Intel where
  17  * only the performance is affected.  Much worse is that such code is non-
  18  * portable.  Due to several programs that die on MIPS due to alignment
  19  * problems I decided to implement this handler anyway though I originally
  20  * didn't intend to do this at all for user code.
  21  *
  22  * For now I enable fixing of address errors by default to make life easier.
  23  * I however intend to disable this somewhen in the future when the alignment
  24  * problems with user programs have been fixed.  For programmers this is the
  25  * right way to go.
  26  *
  27  * Fixing address errors is a per process option.  The option is inherited
  28  * across fork(2) and execve(2) calls.  If you really want to use the
  29  * option in your user programs - I discourage the use of the software
  30  * emulation strongly - use the following code in your userland stuff:
  31  *
  32  * #include <sys/sysmips.h>
  33  *
  34  * ...
  35  * sysmips(MIPS_FIXADE, x);
  36  * ...
  37  *
  38  * The argument x is 0 for disabling software emulation, enabled otherwise.
  39  *
  40  * Below a little program to play around with this feature.
  41  *
  42  * #include <stdio.h>
  43  * #include <sys/sysmips.h>
  44  *
  45  * struct foo {
  46  *         unsigned char bar[8];
  47  * };
  48  *
  49  * main(int argc, char *argv[])
  50  * {
  51  *         struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
  52  *         unsigned int *p = (unsigned int *) (x.bar + 3);
  53  *         int i;
  54  *
  55  *         if (argc > 1)
  56  *                 sysmips(MIPS_FIXADE, atoi(argv[1]));
  57  *
  58  *         printf("*p = %08lx\n", *p);
  59  *
  60  *         *p = 0xdeadface;
  61  *
  62  *         for(i = 0; i <= 7; i++)
  63  *         printf("%02x ", x.bar[i]);
  64  *         printf("\n");
  65  * }
  66  *
  67  * Coprocessor loads are not supported; I think this case is unimportant
  68  * in the practice.
  69  *
  70  * TODO: Handle ndc (attempted store to doubleword in uncached memory)
  71  *       exception for the R6000.
  72  *       A store crossing a page boundary might be executed only partially.
  73  *       Undo the partial store in this case.
  74  */
  75 #include <linux/mm.h>
  76 #include <linux/signal.h>
  77 #include <linux/smp.h>
  78 #include <linux/sched.h>
  79 #include <linux/debugfs.h>
  80 #include <linux/perf_event.h>
  81
  82 #include <asm/asm.h>
  83 #include <asm/branch.h>
  84 #include <asm/byteorder.h>
  85 #include <asm/cop2.h>
  86 #include <asm/inst.h>
  87 #include <asm/uaccess.h>
  88 #include <asm/system.h>
  89
  90 #define STR(x)  __STR(x)
  91 #define __STR(x)  #x
  92
  93 enum {
  94         UNALIGNED_ACTION_QUIET,
  95         UNALIGNED_ACTION_SIGNAL,
  96         UNALIGNED_ACTION_SHOW,
  97 };
  98 #ifdef CONFIG_DEBUG_FS
  99 static u32 unaligned_instructions;
 100 static u32 unaligned_action;
 101 #else
 102 #define unaligned_action UNALIGNED_ACTION_QUIET
 103 #endif
 104 extern void show_registers(struct pt_regs *regs);
 105
 106 static void emulate_load_store_insn(struct pt_regs *regs,
 107         void __user *addr, unsigned int __user *pc)
 108 {
 109         union mips_instruction insn;
 110         unsigned long value;
 111         unsigned int res;
 112
 113         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 114
 115         /*
 116          * This load never faults.
 117          */
 118         __get_user(insn.word, pc);
 119
 120         switch (insn.i_format.opcode) {
 121         /*
 122          * These are instructions that a compiler doesn't generate.  We
 123          * can assume therefore that the code is MIPS-aware and
 124          * really buggy.  Emulating these instructions would break the
 125          * semantics anyway.
 126          */
 127         case ll_op:
 128         case lld_op:
 129         case sc_op:
 130         case scd_op:
 131
 132         /*
 133          * For these instructions the only way to create an address
 134          * error is an attempted access to kernel/supervisor address
 135          * space.
 136          */
 137         case ldl_op:
 138         case ldr_op:
 139         case lwl_op:
 140         case lwr_op:
 141         case sdl_op:
 142         case sdr_op:
 143         case swl_op:
 144         case swr_op:
 145         case lb_op:
 146         case lbu_op:
 147         case sb_op:
 148                 goto sigbus;
 149
 150         /*
 151          * The remaining opcodes are the ones that are really of interest.
 152          */
 153         case lh_op:
 154                 if (!access_ok(VERIFY_READ, addr, 2))
 155                         goto sigbus;
 156
 157                 __asm__ __volatile__ (".set\tnoat\n"
 158 #ifdef __BIG_ENDIAN
 159                         "1:\tlb\t%0, 0(%2)\n"
 160                         "2:\tlbu\t$1, 1(%2)\n\t"
 161 #endif
 162 #ifdef __LITTLE_ENDIAN
 163                         "1:\tlb\t%0, 1(%2)\n"
 164                         "2:\tlbu\t$1, 0(%2)\n\t"
 165 #endif
 166                         "sll\t%0, 0x8\n\t"
 167                         "or\t%0, $1\n\t"
 168                         "li\t%1, 0\n"
 169                         "3:\t.set\tat\n\t"
 170                         ".section\t.fixup,\"ax\"\n\t"
 171                         "4:\tli\t%1, %3\n\t"
 172                         "j\t3b\n\t"
 173                         ".previous\n\t"
 174                         ".section\t__ex_table,\"a\"\n\t"
 175                         STR(PTR)"\t1b, 4b\n\t"
 176                         STR(PTR)"\t2b, 4b\n\t"
 177                         ".previous"
 178                         : "=&r" (value), "=r" (res)
 179                         : "r" (addr), "i" (-EFAULT));
 180                 if (res)
 181                         goto fault;
 182                 compute_return_epc(regs);
 183                 regs->regs[insn.i_format.rt] = value;
 184                 break;
 185
 186         case lw_op:
 187                 if (!access_ok(VERIFY_READ, addr, 4))
 188                         goto sigbus;
 189
 190                 __asm__ __volatile__ (
 191 #ifdef __BIG_ENDIAN
 192                         "1:\tlwl\t%0, (%2)\n"
 193                         "2:\tlwr\t%0, 3(%2)\n\t"
 194 #endif
 195 #ifdef __LITTLE_ENDIAN
 196                         "1:\tlwl\t%0, 3(%2)\n"
 197                         "2:\tlwr\t%0, (%2)\n\t"
 198 #endif
 199                         "li\t%1, 0\n"
 200                         "3:\t.section\t.fixup,\"ax\"\n\t"
 201                         "4:\tli\t%1, %3\n\t"
 202                         "j\t3b\n\t"
 203                         ".previous\n\t"
 204                         ".section\t__ex_table,\"a\"\n\t"
 205                         STR(PTR)"\t1b, 4b\n\t"
 206                         STR(PTR)"\t2b, 4b\n\t"
 207                         ".previous"
 208                         : "=&r" (value), "=r" (res)
 209                         : "r" (addr), "i" (-EFAULT));
 210                 if (res)
 211                         goto fault;
 212                 compute_return_epc(regs);
 213                 regs->regs[insn.i_format.rt] = value;
 214                 break;
 215
 216         case lhu_op:
 217                 if (!access_ok(VERIFY_READ, addr, 2))
 218                         goto sigbus;
 219
 220                 __asm__ __volatile__ (
 221                         ".set\tnoat\n"
 222 #ifdef __BIG_ENDIAN
 223                         "1:\tlbu\t%0, 0(%2)\n"
 224                         "2:\tlbu\t$1, 1(%2)\n\t"
 225 #endif
 226 #ifdef __LITTLE_ENDIAN
 227                         "1:\tlbu\t%0, 1(%2)\n"
 228                         "2:\tlbu\t$1, 0(%2)\n\t"
 229 #endif
 230                         "sll\t%0, 0x8\n\t"
 231                         "or\t%0, $1\n\t"
 232                         "li\t%1, 0\n"
 233                         "3:\t.set\tat\n\t"
 234                         ".section\t.fixup,\"ax\"\n\t"
 235                         "4:\tli\t%1, %3\n\t"
 236                         "j\t3b\n\t"
 237                         ".previous\n\t"
 238                         ".section\t__ex_table,\"a\"\n\t"
 239                         STR(PTR)"\t1b, 4b\n\t"
 240                         STR(PTR)"\t2b, 4b\n\t"
 241                         ".previous"
 242                         : "=&r" (value), "=r" (res)
 243                         : "r" (addr), "i" (-EFAULT));
 244                 if (res)
 245                         goto fault;
 246                 compute_return_epc(regs);
 247                 regs->regs[insn.i_format.rt] = value;
 248                 break;
 249
 250         case lwu_op:
 251 #ifdef CONFIG_64BIT
 252                 /*
 253                  * A 32-bit kernel might be running on a 64-bit processor.  But
 254                  * if we're on a 32-bit processor and an i-cache incoherency
 255                  * or race makes us see a 64-bit instruction here the sdl/sdr
 256                  * would blow up, so for now we don't handle unaligned 64-bit
 257                  * instructions on 32-bit kernels.
 258                  */
 259                 if (!access_ok(VERIFY_READ, addr, 4))
 260                         goto sigbus;
 261
 262                 __asm__ __volatile__ (
 263 #ifdef __BIG_ENDIAN
 264                         "1:\tlwl\t%0, (%2)\n"
 265                         "2:\tlwr\t%0, 3(%2)\n\t"
 266 #endif
 267 #ifdef __LITTLE_ENDIAN
 268                         "1:\tlwl\t%0, 3(%2)\n"
 269                         "2:\tlwr\t%0, (%2)\n\t"
 270 #endif
 271                         "dsll\t%0, %0, 32\n\t"
 272                         "dsrl\t%0, %0, 32\n\t"
 273                         "li\t%1, 0\n"
 274                         "3:\t.section\t.fixup,\"ax\"\n\t"
 275                         "4:\tli\t%1, %3\n\t"
 276                         "j\t3b\n\t"
 277                         ".previous\n\t"
 278                         ".section\t__ex_table,\"a\"\n\t"
 279                         STR(PTR)"\t1b, 4b\n\t"
 280                         STR(PTR)"\t2b, 4b\n\t"
 281                         ".previous"
 282                         : "=&r" (value), "=r" (res)
 283                         : "r" (addr), "i" (-EFAULT));
 284                 if (res)
 285                         goto fault;
 286                 compute_return_epc(regs);
 287                 regs->regs[insn.i_format.rt] = value;
 288                 break;
 289 #endif /* CONFIG_64BIT */
 290
 291                 /* Cannot handle 64-bit instructions in 32-bit kernel */
 292                 goto sigill;
 293
 294         case ld_op:
 295 #ifdef CONFIG_64BIT
 296                 /*
 297                  * A 32-bit kernel might be running on a 64-bit processor.  But
 298                  * if we're on a 32-bit processor and an i-cache incoherency
 299                  * or race makes us see a 64-bit instruction here the sdl/sdr
 300                  * would blow up, so for now we don't handle unaligned 64-bit
 301                  * instructions on 32-bit kernels.
 302                  */
 303                 if (!access_ok(VERIFY_READ, addr, 8))
 304                         goto sigbus;
 305
 306                 __asm__ __volatile__ (
 307 #ifdef __BIG_ENDIAN
 308                         "1:\tldl\t%0, (%2)\n"
 309                         "2:\tldr\t%0, 7(%2)\n\t"
 310 #endif
 311 #ifdef __LITTLE_ENDIAN
 312                         "1:\tldl\t%0, 7(%2)\n"
 313                         "2:\tldr\t%0, (%2)\n\t"
 314 #endif
 315                         "li\t%1, 0\n"
 316                         "3:\t.section\t.fixup,\"ax\"\n\t"
 317                         "4:\tli\t%1, %3\n\t"
 318                         "j\t3b\n\t"
 319                         ".previous\n\t"
 320                         ".section\t__ex_table,\"a\"\n\t"
 321                         STR(PTR)"\t1b, 4b\n\t"
 322                         STR(PTR)"\t2b, 4b\n\t"
 323                         ".previous"
 324                         : "=&r" (value), "=r" (res)
 325                         : "r" (addr), "i" (-EFAULT));
 326                 if (res)
 327                         goto fault;
 328                 compute_return_epc(regs);
 329                 regs->regs[insn.i_format.rt] = value;
 330                 break;
 331 #endif /* CONFIG_64BIT */
 332
 333                 /* Cannot handle 64-bit instructions in 32-bit kernel */
 334                 goto sigill;
 335
 336         case sh_op:
 337                 if (!access_ok(VERIFY_WRITE, addr, 2))
 338                         goto sigbus;
 339
 340                 value = regs->regs[insn.i_format.rt];
 341                 __asm__ __volatile__ (
 342 #ifdef __BIG_ENDIAN
 343                         ".set\tnoat\n"
 344                         "1:\tsb\t%1, 1(%2)\n\t"
 345                         "srl\t$1, %1, 0x8\n"
 346                         "2:\tsb\t$1, 0(%2)\n\t"
 347                         ".set\tat\n\t"
 348 #endif
 349 #ifdef __LITTLE_ENDIAN
 350                         ".set\tnoat\n"
 351                         "1:\tsb\t%1, 0(%2)\n\t"
 352                         "srl\t$1,%1, 0x8\n"
 353                         "2:\tsb\t$1, 1(%2)\n\t"
 354                         ".set\tat\n\t"
 355 #endif
 356                         "li\t%0, 0\n"
 357                         "3:\n\t"
 358                         ".section\t.fixup,\"ax\"\n\t"
 359                         "4:\tli\t%0, %3\n\t"
 360                         "j\t3b\n\t"
 361                         ".previous\n\t"
 362                         ".section\t__ex_table,\"a\"\n\t"
 363                         STR(PTR)"\t1b, 4b\n\t"
 364                         STR(PTR)"\t2b, 4b\n\t"
 365                         ".previous"
 366                         : "=r" (res)
 367                         : "r" (value), "r" (addr), "i" (-EFAULT));
 368                 if (res)
 369                         goto fault;
 370                 compute_return_epc(regs);
 371                 break;
 372
 373         case sw_op:
 374                 if (!access_ok(VERIFY_WRITE, addr, 4))
 375                         goto sigbus;
 376
 377                 value = regs->regs[insn.i_format.rt];
 378                 __asm__ __volatile__ (
 379 #ifdef __BIG_ENDIAN
 380                         "1:\tswl\t%1,(%2)\n"
 381                         "2:\tswr\t%1, 3(%2)\n\t"
 382 #endif
 383 #ifdef __LITTLE_ENDIAN
 384                         "1:\tswl\t%1, 3(%2)\n"
 385                         "2:\tswr\t%1, (%2)\n\t"
 386 #endif
 387                         "li\t%0, 0\n"
 388                         "3:\n\t"
 389                         ".section\t.fixup,\"ax\"\n\t"
 390                         "4:\tli\t%0, %3\n\t"
 391                         "j\t3b\n\t"
 392                         ".previous\n\t"
 393                         ".section\t__ex_table,\"a\"\n\t"
 394                         STR(PTR)"\t1b, 4b\n\t"
 395                         STR(PTR)"\t2b, 4b\n\t"
 396                         ".previous"
 397                 : "=r" (res)
 398                 : "r" (value), "r" (addr), "i" (-EFAULT));
 399                 if (res)
 400                         goto fault;
 401                 compute_return_epc(regs);
 402                 break;
 403
 404         case sd_op:
 405 #ifdef CONFIG_64BIT
 406                 /*
 407                  * A 32-bit kernel might be running on a 64-bit processor.  But
 408                  * if we're on a 32-bit processor and an i-cache incoherency
 409                  * or race makes us see a 64-bit instruction here the sdl/sdr
 410                  * would blow up, so for now we don't handle unaligned 64-bit
 411                  * instructions on 32-bit kernels.
 412                  */
 413                 if (!access_ok(VERIFY_WRITE, addr, 8))
 414                         goto sigbus;
 415
 416                 value = regs->regs[insn.i_format.rt];
 417                 __asm__ __volatile__ (
 418 #ifdef __BIG_ENDIAN
 419                         "1:\tsdl\t%1,(%2)\n"
 420                         "2:\tsdr\t%1, 7(%2)\n\t"
 421 #endif
 422 #ifdef __LITTLE_ENDIAN
 423                         "1:\tsdl\t%1, 7(%2)\n"
 424                         "2:\tsdr\t%1, (%2)\n\t"
 425 #endif
 426                         "li\t%0, 0\n"
 427                         "3:\n\t"
 428                         ".section\t.fixup,\"ax\"\n\t"
 429                         "4:\tli\t%0, %3\n\t"
 430                         "j\t3b\n\t"
 431                         ".previous\n\t"
 432                         ".section\t__ex_table,\"a\"\n\t"
 433                         STR(PTR)"\t1b, 4b\n\t"
 434                         STR(PTR)"\t2b, 4b\n\t"
 435                         ".previous"
 436                 : "=r" (res)
 437                 : "r" (value), "r" (addr), "i" (-EFAULT));
 438                 if (res)
 439                         goto fault;
 440                 compute_return_epc(regs);
 441                 break;
 442 #endif /* CONFIG_64BIT */
 443
 444                 /* Cannot handle 64-bit instructions in 32-bit kernel */
 445                 goto sigill;
 446
 447         case lwc1_op:
 448         case ldc1_op:
 449         case swc1_op:
 450         case sdc1_op:
 451                 /*
 452                  * I herewith declare: this does not happen.  So send SIGBUS.
 453                  */
 454                 goto sigbus;
 455
 456         /*
 457          * COP2 is available to implementor for application specific use.
 458          * It's up to applications to register a notifier chain and do
 459          * whatever they have to do, including possible sending of signals.
 460          */
 461         case lwc2_op:
 462                 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
 463                 break;
 464
 465         case ldc2_op:
 466                 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
 467                 break;
 468
 469         case swc2_op:
 470                 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
 471                 break;
 472
 473         case sdc2_op:
 474                 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
 475                 break;
 476
 477         default:
 478                 /*
 479                  * Pheeee...  We encountered an yet unknown instruction or
 480                  * cache coherence problem.  Die sucker, die ...
 481                  */
 482                 goto sigill;
 483         }
 484
 485 #ifdef CONFIG_DEBUG_FS
 486         unaligned_instructions++;
 487 #endif
 488
 489         return;
 490
 491 fault:
 492         /* Did we have an exception handler installed? */
 493         if (fixup_exception(regs))
 494                 return;
 495
 496         die_if_kernel("Unhandled kernel unaligned access", regs);
 497         force_sig(SIGSEGV, current);
 498
 499         return;
 500
 501 sigbus:
 502         die_if_kernel("Unhandled kernel unaligned access", regs);
 503         force_sig(SIGBUS, current);
 504
 505         return;
 506
 507 sigill:
 508         die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
 509         force_sig(SIGILL, current);
 510 }
 511
 512 asmlinkage void do_ade(struct pt_regs *regs)
 513 {
 514         unsigned int __user *pc;
 515         mm_segment_t seg;
 516
 517         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
 518                         1, regs, regs->cp0_badvaddr);
 519         /*
 520          * Did we catch a fault trying to load an instruction?
 521          * Or are we running in MIPS16 mode?
 522          */
 523         if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
 524                 goto sigbus;
 525
 526         pc = (unsigned int __user *) exception_epc(regs);
 527         if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
 528                 goto sigbus;
 529         if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
 530                 goto sigbus;
 531         else if (unaligned_action == UNALIGNED_ACTION_SHOW)
 532                 show_registers(regs);
 533
 534         /*
 535          * Do branch emulation only if we didn't forward the exception.
 536          * This is all so but ugly ...
 537          */
 538         seg = get_fs();
 539         if (!user_mode(regs))
 540                 set_fs(KERNEL_DS);
 541         emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
 542         set_fs(seg);
 543
 544         return;
 545
 546 sigbus:
 547         die_if_kernel("Kernel unaligned instruction access", regs);
 548         force_sig(SIGBUS, current);
 549
 550         /*
 551          * XXX On return from the signal handler we should advance the epc
 552          */
 553 }
 554
 555 #ifdef CONFIG_DEBUG_FS
 556 extern struct dentry *mips_debugfs_dir;
 557 static int __init debugfs_unaligned(void)
 558 {
 559         struct dentry *d;
 560
 561         if (!mips_debugfs_dir)
 562                 return -ENODEV;
 563         d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
 564                                mips_debugfs_dir, &unaligned_instructions);
 565         if (!d)
 566                 return -ENOMEM;
 567         d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
 568                                mips_debugfs_dir, &unaligned_action);
 569         if (!d)
 570                 return -ENOMEM;
 571         return 0;
 572 }
 573 __initcall(debugfs_unaligned);
 574 #endif