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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / arch / powerpc / kernel / ptrace.c
blob9f2ac70d20c0284ad20e35bb2d7445b5658846d8
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #ifdef CONFIG_PPC32
34 #endif
35 #include <linux/hw_breakpoint.h>
36 #include <linux/perf_event.h>
37
38 #include <asm/uaccess.h>
39 #include <asm/page.h>
40 #include <asm/pgtable.h>
41 #include <asm/system.h>
42
43 #define CREATE_TRACE_POINTS
44 #include <trace/events/syscalls.h>
45
46 /*
47 * The parameter save area on the stack is used to store arguments being passed
48 * to callee function and is located at fixed offset from stack pointer.
49 */
50 #ifdef CONFIG_PPC32
51 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
52 #else /* CONFIG_PPC32 */
53 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
54 #endif
55
56 struct pt_regs_offset {
57 const char *name;
58 int offset;
59 };
60
61 #define STR(s) #s /* convert to string */
62 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
63 #define GPR_OFFSET_NAME(num) \
64 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
65 #define REG_OFFSET_END {.name = NULL, .offset = 0}
66
67 static const struct pt_regs_offset regoffset_table[] = {
68 GPR_OFFSET_NAME(0),
69 GPR_OFFSET_NAME(1),
70 GPR_OFFSET_NAME(2),
71 GPR_OFFSET_NAME(3),
72 GPR_OFFSET_NAME(4),
73 GPR_OFFSET_NAME(5),
74 GPR_OFFSET_NAME(6),
75 GPR_OFFSET_NAME(7),
76 GPR_OFFSET_NAME(8),
77 GPR_OFFSET_NAME(9),
78 GPR_OFFSET_NAME(10),
79 GPR_OFFSET_NAME(11),
80 GPR_OFFSET_NAME(12),
81 GPR_OFFSET_NAME(13),
82 GPR_OFFSET_NAME(14),
83 GPR_OFFSET_NAME(15),
84 GPR_OFFSET_NAME(16),
85 GPR_OFFSET_NAME(17),
86 GPR_OFFSET_NAME(18),
87 GPR_OFFSET_NAME(19),
88 GPR_OFFSET_NAME(20),
89 GPR_OFFSET_NAME(21),
90 GPR_OFFSET_NAME(22),
91 GPR_OFFSET_NAME(23),
92 GPR_OFFSET_NAME(24),
93 GPR_OFFSET_NAME(25),
94 GPR_OFFSET_NAME(26),
95 GPR_OFFSET_NAME(27),
96 GPR_OFFSET_NAME(28),
97 GPR_OFFSET_NAME(29),
98 GPR_OFFSET_NAME(30),
99 GPR_OFFSET_NAME(31),
100 REG_OFFSET_NAME(nip),
101 REG_OFFSET_NAME(msr),
102 REG_OFFSET_NAME(ctr),
103 REG_OFFSET_NAME(link),
104 REG_OFFSET_NAME(xer),
105 REG_OFFSET_NAME(ccr),
106 #ifdef CONFIG_PPC64
107 REG_OFFSET_NAME(softe),
108 #else
109 REG_OFFSET_NAME(mq),
110 #endif
111 REG_OFFSET_NAME(trap),
112 REG_OFFSET_NAME(dar),
113 REG_OFFSET_NAME(dsisr),
114 REG_OFFSET_END,
115 };
116
117 /**
118 * regs_query_register_offset() - query register offset from its name
119 * @name: the name of a register
120 *
121 * regs_query_register_offset() returns the offset of a register in struct
122 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
123 */
124 int regs_query_register_offset(const char *name)
125 {
126 const struct pt_regs_offset *roff;
127 for (roff = regoffset_table; roff->name != NULL; roff++)
128 if (!strcmp(roff->name, name))
129 return roff->offset;
130 return -EINVAL;
131 }
132
133 /**
134 * regs_query_register_name() - query register name from its offset
135 * @offset: the offset of a register in struct pt_regs.
136 *
137 * regs_query_register_name() returns the name of a register from its
138 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
139 */
140 const char *regs_query_register_name(unsigned int offset)
141 {
142 const struct pt_regs_offset *roff;
143 for (roff = regoffset_table; roff->name != NULL; roff++)
144 if (roff->offset == offset)
145 return roff->name;
146 return NULL;
147 }
148
149 /*
150 * does not yet catch signals sent when the child dies.
151 * in exit.c or in signal.c.
152 */
153
154 /*
155 * Set of msr bits that gdb can change on behalf of a process.
156 */
157 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
158 #define MSR_DEBUGCHANGE 0
159 #else
160 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
161 #endif
162
163 /*
164 * Max register writeable via put_reg
165 */
166 #ifdef CONFIG_PPC32
167 #define PT_MAX_PUT_REG PT_MQ
168 #else
169 #define PT_MAX_PUT_REG PT_CCR
170 #endif
171
172 static unsigned long get_user_msr(struct task_struct *task)
173 {
174 return task->thread.regs->msr | task->thread.fpexc_mode;
175 }
176
177 static int set_user_msr(struct task_struct *task, unsigned long msr)
178 {
179 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
180 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
181 return 0;
182 }
183
184 /*
185 * We prevent mucking around with the reserved area of trap
186 * which are used internally by the kernel.
187 */
188 static int set_user_trap(struct task_struct *task, unsigned long trap)
189 {
190 task->thread.regs->trap = trap & 0xfff0;
191 return 0;
192 }
193
194 /*
195 * Get contents of register REGNO in task TASK.
196 */
197 unsigned long ptrace_get_reg(struct task_struct *task, int regno)
198 {
199 if (task->thread.regs == NULL)
200 return -EIO;
201
202 if (regno == PT_MSR)
203 return get_user_msr(task);
204
205 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
206 return ((unsigned long *)task->thread.regs)[regno];
207
208 return -EIO;
209 }
210
211 /*
212 * Write contents of register REGNO in task TASK.
213 */
214 int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
215 {
216 if (task->thread.regs == NULL)
217 return -EIO;
218
219 if (regno == PT_MSR)
220 return set_user_msr(task, data);
221 if (regno == PT_TRAP)
222 return set_user_trap(task, data);
223
224 if (regno <= PT_MAX_PUT_REG) {
225 ((unsigned long *)task->thread.regs)[regno] = data;
226 return 0;
227 }
228 return -EIO;
229 }
230
231 static int gpr_get(struct task_struct *target, const struct user_regset *regset,
232 unsigned int pos, unsigned int count,
233 void *kbuf, void __user *ubuf)
234 {
235 int i, ret;
236
237 if (target->thread.regs == NULL)
238 return -EIO;
239
240 if (!FULL_REGS(target->thread.regs)) {
241 /* We have a partial register set. Fill 14-31 with bogus values */
242 for (i = 14; i < 32; i++)
243 target->thread.regs->gpr[i] = NV_REG_POISON;
244 }
245
246 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
247 target->thread.regs,
248 0, offsetof(struct pt_regs, msr));
249 if (!ret) {
250 unsigned long msr = get_user_msr(target);
251 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
252 offsetof(struct pt_regs, msr),
253 offsetof(struct pt_regs, msr) +
254 sizeof(msr));
255 }
256
257 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
258 offsetof(struct pt_regs, msr) + sizeof(long));
259
260 if (!ret)
261 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
262 &target->thread.regs->orig_gpr3,
263 offsetof(struct pt_regs, orig_gpr3),
264 sizeof(struct pt_regs));
265 if (!ret)
266 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
267 sizeof(struct pt_regs), -1);
268
269 return ret;
270 }
271
272 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
273 unsigned int pos, unsigned int count,
274 const void *kbuf, const void __user *ubuf)
275 {
276 unsigned long reg;
277 int ret;
278
279 if (target->thread.regs == NULL)
280 return -EIO;
281
282 CHECK_FULL_REGS(target->thread.regs);
283
284 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
285 target->thread.regs,
286 0, PT_MSR * sizeof(reg));
287
288 if (!ret && count > 0) {
289 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
290 PT_MSR * sizeof(reg),
291 (PT_MSR + 1) * sizeof(reg));
292 if (!ret)
293 ret = set_user_msr(target, reg);
294 }
295
296 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
297 offsetof(struct pt_regs, msr) + sizeof(long));
298
299 if (!ret)
300 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
301 &target->thread.regs->orig_gpr3,
302 PT_ORIG_R3 * sizeof(reg),
303 (PT_MAX_PUT_REG + 1) * sizeof(reg));
304
305 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
306 ret = user_regset_copyin_ignore(
307 &pos, &count, &kbuf, &ubuf,
308 (PT_MAX_PUT_REG + 1) * sizeof(reg),
309 PT_TRAP * sizeof(reg));
310
311 if (!ret && count > 0) {
312 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
313 PT_TRAP * sizeof(reg),
314 (PT_TRAP + 1) * sizeof(reg));
315 if (!ret)
316 ret = set_user_trap(target, reg);
317 }
318
319 if (!ret)
320 ret = user_regset_copyin_ignore(
321 &pos, &count, &kbuf, &ubuf,
322 (PT_TRAP + 1) * sizeof(reg), -1);
323
324 return ret;
325 }
326
327 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
328 unsigned int pos, unsigned int count,
329 void *kbuf, void __user *ubuf)
330 {
331 #ifdef CONFIG_VSX
332 double buf[33];
333 int i;
334 #endif
335 flush_fp_to_thread(target);
336
337 #ifdef CONFIG_VSX
338 /* copy to local buffer then write that out */
339 for (i = 0; i < 32 ; i++)
340 buf[i] = target->thread.TS_FPR(i);
341 memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
342 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
343
344 #else
345 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
346 offsetof(struct thread_struct, TS_FPR(32)));
347
348 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
349 &target->thread.fpr, 0, -1);
350 #endif
351 }
352
353 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
354 unsigned int pos, unsigned int count,
355 const void *kbuf, const void __user *ubuf)
356 {
357 #ifdef CONFIG_VSX
358 double buf[33];
359 int i;
360 #endif
361 flush_fp_to_thread(target);
362
363 #ifdef CONFIG_VSX
364 /* copy to local buffer then write that out */
365 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
366 if (i)
367 return i;
368 for (i = 0; i < 32 ; i++)
369 target->thread.TS_FPR(i) = buf[i];
370 memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
371 return 0;
372 #else
373 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
374 offsetof(struct thread_struct, TS_FPR(32)));
375
376 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
377 &target->thread.fpr, 0, -1);
378 #endif
379 }
380
381 #ifdef CONFIG_ALTIVEC
382 /*
383 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
384 * The transfer totals 34 quadword. Quadwords 0-31 contain the
385 * corresponding vector registers. Quadword 32 contains the vscr as the
386 * last word (offset 12) within that quadword. Quadword 33 contains the
387 * vrsave as the first word (offset 0) within the quadword.
388 *
389 * This definition of the VMX state is compatible with the current PPC32
390 * ptrace interface. This allows signal handling and ptrace to use the
391 * same structures. This also simplifies the implementation of a bi-arch
392 * (combined (32- and 64-bit) gdb.
393 */
394
395 static int vr_active(struct task_struct *target,
396 const struct user_regset *regset)
397 {
398 flush_altivec_to_thread(target);
399 return target->thread.used_vr ? regset->n : 0;
400 }
401
402 static int vr_get(struct task_struct *target, const struct user_regset *regset,
403 unsigned int pos, unsigned int count,
404 void *kbuf, void __user *ubuf)
405 {
406 int ret;
407
408 flush_altivec_to_thread(target);
409
410 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
411 offsetof(struct thread_struct, vr[32]));
412
413 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
414 &target->thread.vr, 0,
415 33 * sizeof(vector128));
416 if (!ret) {
417 /*
418 * Copy out only the low-order word of vrsave.
419 */
420 union {
421 elf_vrreg_t reg;
422 u32 word;
423 } vrsave;
424 memset(&vrsave, 0, sizeof(vrsave));
425 vrsave.word = target->thread.vrsave;
426 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
427 33 * sizeof(vector128), -1);
428 }
429
430 return ret;
431 }
432
433 static int vr_set(struct task_struct *target, const struct user_regset *regset,
434 unsigned int pos, unsigned int count,
435 const void *kbuf, const void __user *ubuf)
436 {
437 int ret;
438
439 flush_altivec_to_thread(target);
440
441 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
442 offsetof(struct thread_struct, vr[32]));
443
444 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
445 &target->thread.vr, 0, 33 * sizeof(vector128));
446 if (!ret && count > 0) {
447 /*
448 * We use only the first word of vrsave.
449 */
450 union {
451 elf_vrreg_t reg;
452 u32 word;
453 } vrsave;
454 memset(&vrsave, 0, sizeof(vrsave));
455 vrsave.word = target->thread.vrsave;
456 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
457 33 * sizeof(vector128), -1);
458 if (!ret)
459 target->thread.vrsave = vrsave.word;
460 }
461
462 return ret;
463 }
464 #endif /* CONFIG_ALTIVEC */
465
466 #ifdef CONFIG_VSX
467 /*
468 * Currently to set and and get all the vsx state, you need to call
469 * the fp and VMX calls as well. This only get/sets the lower 32
470 * 128bit VSX registers.
471 */
472
473 static int vsr_active(struct task_struct *target,
474 const struct user_regset *regset)
475 {
476 flush_vsx_to_thread(target);
477 return target->thread.used_vsr ? regset->n : 0;
478 }
479
480 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
481 unsigned int pos, unsigned int count,
482 void *kbuf, void __user *ubuf)
483 {
484 double buf[32];
485 int ret, i;
486
487 flush_vsx_to_thread(target);
488
489 for (i = 0; i < 32 ; i++)
490 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
491 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
492 buf, 0, 32 * sizeof(double));
493
494 return ret;
495 }
496
497 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
498 unsigned int pos, unsigned int count,
499 const void *kbuf, const void __user *ubuf)
500 {
501 double buf[32];
502 int ret,i;
503
504 flush_vsx_to_thread(target);
505
506 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
507 buf, 0, 32 * sizeof(double));
508 for (i = 0; i < 32 ; i++)
509 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
510
511
512 return ret;
513 }
514 #endif /* CONFIG_VSX */
515
516 #ifdef CONFIG_SPE
517
518 /*
519 * For get_evrregs/set_evrregs functions 'data' has the following layout:
520 *
521 * struct {
522 * u32 evr[32];
523 * u64 acc;
524 * u32 spefscr;
525 * }
526 */
527
528 static int evr_active(struct task_struct *target,
529 const struct user_regset *regset)
530 {
531 flush_spe_to_thread(target);
532 return target->thread.used_spe ? regset->n : 0;
533 }
534
535 static int evr_get(struct task_struct *target, const struct user_regset *regset,
536 unsigned int pos, unsigned int count,
537 void *kbuf, void __user *ubuf)
538 {
539 int ret;
540
541 flush_spe_to_thread(target);
542
543 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
544 &target->thread.evr,
545 0, sizeof(target->thread.evr));
546
547 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
548 offsetof(struct thread_struct, spefscr));
549
550 if (!ret)
551 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
552 &target->thread.acc,
553 sizeof(target->thread.evr), -1);
554
555 return ret;
556 }
557
558 static int evr_set(struct task_struct *target, const struct user_regset *regset,
559 unsigned int pos, unsigned int count,
560 const void *kbuf, const void __user *ubuf)
561 {
562 int ret;
563
564 flush_spe_to_thread(target);
565
566 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
567 &target->thread.evr,
568 0, sizeof(target->thread.evr));
569
570 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
571 offsetof(struct thread_struct, spefscr));
572
573 if (!ret)
574 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
575 &target->thread.acc,
576 sizeof(target->thread.evr), -1);
577
578 return ret;
579 }
580 #endif /* CONFIG_SPE */
581
582
583 /*
584 * These are our native regset flavors.
585 */
586 enum powerpc_regset {
587 REGSET_GPR,
588 REGSET_FPR,
589 #ifdef CONFIG_ALTIVEC
590 REGSET_VMX,
591 #endif
592 #ifdef CONFIG_VSX
593 REGSET_VSX,
594 #endif
595 #ifdef CONFIG_SPE
596 REGSET_SPE,
597 #endif
598 };
599
600 static const struct user_regset native_regsets[] = {
601 [REGSET_GPR] = {
602 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
603 .size = sizeof(long), .align = sizeof(long),
604 .get = gpr_get, .set = gpr_set
605 },
606 [REGSET_FPR] = {
607 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
608 .size = sizeof(double), .align = sizeof(double),
609 .get = fpr_get, .set = fpr_set
610 },
611 #ifdef CONFIG_ALTIVEC
612 [REGSET_VMX] = {
613 .core_note_type = NT_PPC_VMX, .n = 34,
614 .size = sizeof(vector128), .align = sizeof(vector128),
615 .active = vr_active, .get = vr_get, .set = vr_set
616 },
617 #endif
618 #ifdef CONFIG_VSX
619 [REGSET_VSX] = {
620 .core_note_type = NT_PPC_VSX, .n = 32,
621 .size = sizeof(double), .align = sizeof(double),
622 .active = vsr_active, .get = vsr_get, .set = vsr_set
623 },
624 #endif
625 #ifdef CONFIG_SPE
626 [REGSET_SPE] = {
627 .n = 35,
628 .size = sizeof(u32), .align = sizeof(u32),
629 .active = evr_active, .get = evr_get, .set = evr_set
630 },
631 #endif
632 };
633
634 static const struct user_regset_view user_ppc_native_view = {
635 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
636 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
637 };
638
639 #ifdef CONFIG_PPC64
640 #include <linux/compat.h>
641
642 static int gpr32_get(struct task_struct *target,
643 const struct user_regset *regset,
644 unsigned int pos, unsigned int count,
645 void *kbuf, void __user *ubuf)
646 {
647 const unsigned long *regs = &target->thread.regs->gpr[0];
648 compat_ulong_t *k = kbuf;
649 compat_ulong_t __user *u = ubuf;
650 compat_ulong_t reg;
651 int i;
652
653 if (target->thread.regs == NULL)
654 return -EIO;
655
656 if (!FULL_REGS(target->thread.regs)) {
657 /* We have a partial register set. Fill 14-31 with bogus values */
658 for (i = 14; i < 32; i++)
659 target->thread.regs->gpr[i] = NV_REG_POISON;
660 }
661
662 pos /= sizeof(reg);
663 count /= sizeof(reg);
664
665 if (kbuf)
666 for (; count > 0 && pos < PT_MSR; --count)
667 *k++ = regs[pos++];
668 else
669 for (; count > 0 && pos < PT_MSR; --count)
670 if (__put_user((compat_ulong_t) regs[pos++], u++))
671 return -EFAULT;
672
673 if (count > 0 && pos == PT_MSR) {
674 reg = get_user_msr(target);
675 if (kbuf)
676 *k++ = reg;
677 else if (__put_user(reg, u++))
678 return -EFAULT;
679 ++pos;
680 --count;
681 }
682
683 if (kbuf)
684 for (; count > 0 && pos < PT_REGS_COUNT; --count)
685 *k++ = regs[pos++];
686 else
687 for (; count > 0 && pos < PT_REGS_COUNT; --count)
688 if (__put_user((compat_ulong_t) regs[pos++], u++))
689 return -EFAULT;
690
691 kbuf = k;
692 ubuf = u;
693 pos *= sizeof(reg);
694 count *= sizeof(reg);
695 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
696 PT_REGS_COUNT * sizeof(reg), -1);
697 }
698
699 static int gpr32_set(struct task_struct *target,
700 const struct user_regset *regset,
701 unsigned int pos, unsigned int count,
702 const void *kbuf, const void __user *ubuf)
703 {
704 unsigned long *regs = &target->thread.regs->gpr[0];
705 const compat_ulong_t *k = kbuf;
706 const compat_ulong_t __user *u = ubuf;
707 compat_ulong_t reg;
708
709 if (target->thread.regs == NULL)
710 return -EIO;
711
712 CHECK_FULL_REGS(target->thread.regs);
713
714 pos /= sizeof(reg);
715 count /= sizeof(reg);
716
717 if (kbuf)
718 for (; count > 0 && pos < PT_MSR; --count)
719 regs[pos++] = *k++;
720 else
721 for (; count > 0 && pos < PT_MSR; --count) {
722 if (__get_user(reg, u++))
723 return -EFAULT;
724 regs[pos++] = reg;
725 }
726
727
728 if (count > 0 && pos == PT_MSR) {
729 if (kbuf)
730 reg = *k++;
731 else if (__get_user(reg, u++))
732 return -EFAULT;
733 set_user_msr(target, reg);
734 ++pos;
735 --count;
736 }
737
738 if (kbuf) {
739 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
740 regs[pos++] = *k++;
741 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
742 ++k;
743 } else {
744 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
745 if (__get_user(reg, u++))
746 return -EFAULT;
747 regs[pos++] = reg;
748 }
749 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
750 if (__get_user(reg, u++))
751 return -EFAULT;
752 }
753
754 if (count > 0 && pos == PT_TRAP) {
755 if (kbuf)
756 reg = *k++;
757 else if (__get_user(reg, u++))
758 return -EFAULT;
759 set_user_trap(target, reg);
760 ++pos;
761 --count;
762 }
763
764 kbuf = k;
765 ubuf = u;
766 pos *= sizeof(reg);
767 count *= sizeof(reg);
768 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
769 (PT_TRAP + 1) * sizeof(reg), -1);
770 }
771
772 /*
773 * These are the regset flavors matching the CONFIG_PPC32 native set.
774 */
775 static const struct user_regset compat_regsets[] = {
776 [REGSET_GPR] = {
777 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
778 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
779 .get = gpr32_get, .set = gpr32_set
780 },
781 [REGSET_FPR] = {
782 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
783 .size = sizeof(double), .align = sizeof(double),
784 .get = fpr_get, .set = fpr_set
785 },
786 #ifdef CONFIG_ALTIVEC
787 [REGSET_VMX] = {
788 .core_note_type = NT_PPC_VMX, .n = 34,
789 .size = sizeof(vector128), .align = sizeof(vector128),
790 .active = vr_active, .get = vr_get, .set = vr_set
791 },
792 #endif
793 #ifdef CONFIG_SPE
794 [REGSET_SPE] = {
795 .core_note_type = NT_PPC_SPE, .n = 35,
796 .size = sizeof(u32), .align = sizeof(u32),
797 .active = evr_active, .get = evr_get, .set = evr_set
798 },
799 #endif
800 };
801
802 static const struct user_regset_view user_ppc_compat_view = {
803 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
804 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
805 };
806 #endif /* CONFIG_PPC64 */
807
808 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
809 {
810 #ifdef CONFIG_PPC64
811 if (test_tsk_thread_flag(task, TIF_32BIT))
812 return &user_ppc_compat_view;
813 #endif
814 return &user_ppc_native_view;
815 }
816
817
818 void user_enable_single_step(struct task_struct *task)
819 {
820 struct pt_regs *regs = task->thread.regs;
821
822 if (regs != NULL) {
823 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
824 task->thread.dbcr0 &= ~DBCR0_BT;
825 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
826 regs->msr |= MSR_DE;
827 #else
828 regs->msr &= ~MSR_BE;
829 regs->msr |= MSR_SE;
830 #endif
831 }
832 set_tsk_thread_flag(task, TIF_SINGLESTEP);
833 }
834
835 void user_enable_block_step(struct task_struct *task)
836 {
837 struct pt_regs *regs = task->thread.regs;
838
839 if (regs != NULL) {
840 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
841 task->thread.dbcr0 &= ~DBCR0_IC;
842 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
843 regs->msr |= MSR_DE;
844 #else
845 regs->msr &= ~MSR_SE;
846 regs->msr |= MSR_BE;
847 #endif
848 }
849 set_tsk_thread_flag(task, TIF_SINGLESTEP);
850 }
851
852 void user_disable_single_step(struct task_struct *task)
853 {
854 struct pt_regs *regs = task->thread.regs;
855
856 if (regs != NULL) {
857 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
858 /*
859 * The logic to disable single stepping should be as
860 * simple as turning off the Instruction Complete flag.
861 * And, after doing so, if all debug flags are off, turn
862 * off DBCR0(IDM) and MSR(DE) .... Torez
863 */
864 task->thread.dbcr0 &= ~DBCR0_IC;
865 /*
866 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
867 */
868 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
869 task->thread.dbcr1)) {
870 /*
871 * All debug events were off.....
872 */
873 task->thread.dbcr0 &= ~DBCR0_IDM;
874 regs->msr &= ~MSR_DE;
875 }
876 #else
877 regs->msr &= ~(MSR_SE | MSR_BE);
878 #endif
879 }
880 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
881 }
882
883 #ifdef CONFIG_HAVE_HW_BREAKPOINT
884 void ptrace_triggered(struct perf_event *bp,
885 struct perf_sample_data *data, struct pt_regs *regs)
886 {
887 struct perf_event_attr attr;
888
889 /*
890 * Disable the breakpoint request here since ptrace has defined a
891 * one-shot behaviour for breakpoint exceptions in PPC64.
892 * The SIGTRAP signal is generated automatically for us in do_dabr().
893 * We don't have to do anything about that here
894 */
895 attr = bp->attr;
896 attr.disabled = true;
897 modify_user_hw_breakpoint(bp, &attr);
898 }
899 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
900
901 int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
902 unsigned long data)
903 {
904 #ifdef CONFIG_HAVE_HW_BREAKPOINT
905 int ret;
906 struct thread_struct *thread = &(task->thread);
907 struct perf_event *bp;
908 struct perf_event_attr attr;
909 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
910
911 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
912 * For embedded processors we support one DAC and no IAC's at the
913 * moment.
914 */
915 if (addr > 0)
916 return -EINVAL;
917
918 /* The bottom 3 bits in dabr are flags */
919 if ((data & ~0x7UL) >= TASK_SIZE)
920 return -EIO;
921
922 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
923 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
924 * It was assumed, on previous implementations, that 3 bits were
925 * passed together with the data address, fitting the design of the
926 * DABR register, as follows:
927 *
928 * bit 0: Read flag
929 * bit 1: Write flag
930 * bit 2: Breakpoint translation
931 *
932 * Thus, we use them here as so.
933 */
934
935 /* Ensure breakpoint translation bit is set */
936 if (data && !(data & DABR_TRANSLATION))
937 return -EIO;
938 #ifdef CONFIG_HAVE_HW_BREAKPOINT
939 if (ptrace_get_breakpoints(task) < 0)
940 return -ESRCH;
941
942 bp = thread->ptrace_bps[0];
943 if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
944 if (bp) {
945 unregister_hw_breakpoint(bp);
946 thread->ptrace_bps[0] = NULL;
947 }
948 ptrace_put_breakpoints(task);
949 return 0;
950 }
951 if (bp) {
952 attr = bp->attr;
953 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
954 arch_bp_generic_fields(data &
955 (DABR_DATA_WRITE | DABR_DATA_READ),
956 &attr.bp_type);
957 ret = modify_user_hw_breakpoint(bp, &attr);
958 if (ret) {
959 ptrace_put_breakpoints(task);
960 return ret;
961 }
962 thread->ptrace_bps[0] = bp;
963 ptrace_put_breakpoints(task);
964 thread->dabr = data;
965 return 0;
966 }
967
968 /* Create a new breakpoint request if one doesn't exist already */
969 hw_breakpoint_init(&attr);
970 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
971 arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
972 &attr.bp_type);
973
974 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
975 ptrace_triggered, NULL, task);
976 if (IS_ERR(bp)) {
977 thread->ptrace_bps[0] = NULL;
978 ptrace_put_breakpoints(task);
979 return PTR_ERR(bp);
980 }
981
982 ptrace_put_breakpoints(task);
983
984 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
985
986 /* Move contents to the DABR register */
987 task->thread.dabr = data;
988 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
989 /* As described above, it was assumed 3 bits were passed with the data
990 * address, but we will assume only the mode bits will be passed
991 * as to not cause alignment restrictions for DAC-based processors.
992 */
993
994 /* DAC's hold the whole address without any mode flags */
995 task->thread.dac1 = data & ~0x3UL;
996
997 if (task->thread.dac1 == 0) {
998 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
999 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
1000 task->thread.dbcr1)) {
1001 task->thread.regs->msr &= ~MSR_DE;
1002 task->thread.dbcr0 &= ~DBCR0_IDM;
1003 }
1004 return 0;
1005 }
1006
1007 /* Read or Write bits must be set */
1008
1009 if (!(data & 0x3UL))
1010 return -EINVAL;
1011
1012 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1013 register */
1014 task->thread.dbcr0 |= DBCR0_IDM;
1015
1016 /* Check for write and read flags and set DBCR0
1017 accordingly */
1018 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
1019 if (data & 0x1UL)
1020 dbcr_dac(task) |= DBCR_DAC1R;
1021 if (data & 0x2UL)
1022 dbcr_dac(task) |= DBCR_DAC1W;
1023 task->thread.regs->msr |= MSR_DE;
1024 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1025 return 0;
1026 }
1027
1028 /*
1029 * Called by kernel/ptrace.c when detaching..
1030 *
1031 * Make sure single step bits etc are not set.
1032 */
1033 void ptrace_disable(struct task_struct *child)
1034 {
1035 /* make sure the single step bit is not set. */
1036 user_disable_single_step(child);
1037 }
1038
1039 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1040 static long set_intruction_bp(struct task_struct *child,
1041 struct ppc_hw_breakpoint *bp_info)
1042 {
1043 int slot;
1044 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
1045 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
1046 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
1047 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
1048
1049 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1050 slot2_in_use = 1;
1051 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1052 slot4_in_use = 1;
1053
1054 if (bp_info->addr >= TASK_SIZE)
1055 return -EIO;
1056
1057 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1058
1059 /* Make sure range is valid. */
1060 if (bp_info->addr2 >= TASK_SIZE)
1061 return -EIO;
1062
1063 /* We need a pair of IAC regsisters */
1064 if ((!slot1_in_use) && (!slot2_in_use)) {
1065 slot = 1;
1066 child->thread.iac1 = bp_info->addr;
1067 child->thread.iac2 = bp_info->addr2;
1068 child->thread.dbcr0 |= DBCR0_IAC1;
1069 if (bp_info->addr_mode ==
1070 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1071 dbcr_iac_range(child) |= DBCR_IAC12X;
1072 else
1073 dbcr_iac_range(child) |= DBCR_IAC12I;
1074 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1075 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1076 slot = 3;
1077 child->thread.iac3 = bp_info->addr;
1078 child->thread.iac4 = bp_info->addr2;
1079 child->thread.dbcr0 |= DBCR0_IAC3;
1080 if (bp_info->addr_mode ==
1081 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1082 dbcr_iac_range(child) |= DBCR_IAC34X;
1083 else
1084 dbcr_iac_range(child) |= DBCR_IAC34I;
1085 #endif
1086 } else
1087 return -ENOSPC;
1088 } else {
1089 /* We only need one. If possible leave a pair free in
1090 * case a range is needed later
1091 */
1092 if (!slot1_in_use) {
1093 /*
1094 * Don't use iac1 if iac1-iac2 are free and either
1095 * iac3 or iac4 (but not both) are free
1096 */
1097 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1098 slot = 1;
1099 child->thread.iac1 = bp_info->addr;
1100 child->thread.dbcr0 |= DBCR0_IAC1;
1101 goto out;
1102 }
1103 }
1104 if (!slot2_in_use) {
1105 slot = 2;
1106 child->thread.iac2 = bp_info->addr;
1107 child->thread.dbcr0 |= DBCR0_IAC2;
1108 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1109 } else if (!slot3_in_use) {
1110 slot = 3;
1111 child->thread.iac3 = bp_info->addr;
1112 child->thread.dbcr0 |= DBCR0_IAC3;
1113 } else if (!slot4_in_use) {
1114 slot = 4;
1115 child->thread.iac4 = bp_info->addr;
1116 child->thread.dbcr0 |= DBCR0_IAC4;
1117 #endif
1118 } else
1119 return -ENOSPC;
1120 }
1121 out:
1122 child->thread.dbcr0 |= DBCR0_IDM;
1123 child->thread.regs->msr |= MSR_DE;
1124
1125 return slot;
1126 }
1127
1128 static int del_instruction_bp(struct task_struct *child, int slot)
1129 {
1130 switch (slot) {
1131 case 1:
1132 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
1133 return -ENOENT;
1134
1135 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1136 /* address range - clear slots 1 & 2 */
1137 child->thread.iac2 = 0;
1138 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1139 }
1140 child->thread.iac1 = 0;
1141 child->thread.dbcr0 &= ~DBCR0_IAC1;
1142 break;
1143 case 2:
1144 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
1145 return -ENOENT;
1146
1147 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1148 /* used in a range */
1149 return -EINVAL;
1150 child->thread.iac2 = 0;
1151 child->thread.dbcr0 &= ~DBCR0_IAC2;
1152 break;
1153 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1154 case 3:
1155 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
1156 return -ENOENT;
1157
1158 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1159 /* address range - clear slots 3 & 4 */
1160 child->thread.iac4 = 0;
1161 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1162 }
1163 child->thread.iac3 = 0;
1164 child->thread.dbcr0 &= ~DBCR0_IAC3;
1165 break;
1166 case 4:
1167 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
1168 return -ENOENT;
1169
1170 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1171 /* Used in a range */
1172 return -EINVAL;
1173 child->thread.iac4 = 0;
1174 child->thread.dbcr0 &= ~DBCR0_IAC4;
1175 break;
1176 #endif
1177 default:
1178 return -EINVAL;
1179 }
1180 return 0;
1181 }
1182
1183 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1184 {
1185 int byte_enable =
1186 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
1187 & 0xf;
1188 int condition_mode =
1189 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
1190 int slot;
1191
1192 if (byte_enable && (condition_mode == 0))
1193 return -EINVAL;
1194
1195 if (bp_info->addr >= TASK_SIZE)
1196 return -EIO;
1197
1198 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
1199 slot = 1;
1200 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1201 dbcr_dac(child) |= DBCR_DAC1R;
1202 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1203 dbcr_dac(child) |= DBCR_DAC1W;
1204 child->thread.dac1 = (unsigned long)bp_info->addr;
1205 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1206 if (byte_enable) {
1207 child->thread.dvc1 =
1208 (unsigned long)bp_info->condition_value;
1209 child->thread.dbcr2 |=
1210 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1211 (condition_mode << DBCR2_DVC1M_SHIFT));
1212 }
1213 #endif
1214 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1215 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1216 /* Both dac1 and dac2 are part of a range */
1217 return -ENOSPC;
1218 #endif
1219 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
1220 slot = 2;
1221 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1222 dbcr_dac(child) |= DBCR_DAC2R;
1223 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1224 dbcr_dac(child) |= DBCR_DAC2W;
1225 child->thread.dac2 = (unsigned long)bp_info->addr;
1226 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1227 if (byte_enable) {
1228 child->thread.dvc2 =
1229 (unsigned long)bp_info->condition_value;
1230 child->thread.dbcr2 |=
1231 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1232 (condition_mode << DBCR2_DVC2M_SHIFT));
1233 }
1234 #endif
1235 } else
1236 return -ENOSPC;
1237 child->thread.dbcr0 |= DBCR0_IDM;
1238 child->thread.regs->msr |= MSR_DE;
1239
1240 return slot + 4;
1241 }
1242
1243 static int del_dac(struct task_struct *child, int slot)
1244 {
1245 if (slot == 1) {
1246 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
1247 return -ENOENT;
1248
1249 child->thread.dac1 = 0;
1250 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1251 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1252 if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1253 child->thread.dac2 = 0;
1254 child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1255 }
1256 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1257 #endif
1258 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1259 child->thread.dvc1 = 0;
1260 #endif
1261 } else if (slot == 2) {
1262 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
1263 return -ENOENT;
1264
1265 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1266 if (child->thread.dbcr2 & DBCR2_DAC12MODE)
1267 /* Part of a range */
1268 return -EINVAL;
1269 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1270 #endif
1271 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1272 child->thread.dvc2 = 0;
1273 #endif
1274 child->thread.dac2 = 0;
1275 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1276 } else
1277 return -EINVAL;
1278
1279 return 0;
1280 }
1281 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1282
1283 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1284 static int set_dac_range(struct task_struct *child,
1285 struct ppc_hw_breakpoint *bp_info)
1286 {
1287 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
1288
1289 /* We don't allow range watchpoints to be used with DVC */
1290 if (bp_info->condition_mode)
1291 return -EINVAL;
1292
1293 /*
1294 * Best effort to verify the address range. The user/supervisor bits
1295 * prevent trapping in kernel space, but let's fail on an obvious bad
1296 * range. The simple test on the mask is not fool-proof, and any
1297 * exclusive range will spill over into kernel space.
1298 */
1299 if (bp_info->addr >= TASK_SIZE)
1300 return -EIO;
1301 if (mode == PPC_BREAKPOINT_MODE_MASK) {
1302 /*
1303 * dac2 is a bitmask. Don't allow a mask that makes a
1304 * kernel space address from a valid dac1 value
1305 */
1306 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
1307 return -EIO;
1308 } else {
1309 /*
1310 * For range breakpoints, addr2 must also be a valid address
1311 */
1312 if (bp_info->addr2 >= TASK_SIZE)
1313 return -EIO;
1314 }
1315
1316 if (child->thread.dbcr0 &
1317 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1318 return -ENOSPC;
1319
1320 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1321 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1322 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1323 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1324 child->thread.dac1 = bp_info->addr;
1325 child->thread.dac2 = bp_info->addr2;
1326 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1327 child->thread.dbcr2 |= DBCR2_DAC12M;
1328 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1329 child->thread.dbcr2 |= DBCR2_DAC12MX;
1330 else /* PPC_BREAKPOINT_MODE_MASK */
1331 child->thread.dbcr2 |= DBCR2_DAC12MM;
1332 child->thread.regs->msr |= MSR_DE;
1333
1334 return 5;
1335 }
1336 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
1337
1338 static long ppc_set_hwdebug(struct task_struct *child,
1339 struct ppc_hw_breakpoint *bp_info)
1340 {
1341 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
1342 unsigned long dabr;
1343 #endif
1344
1345 if (bp_info->version != 1)
1346 return -ENOTSUPP;
1347 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1348 /*
1349 * Check for invalid flags and combinations
1350 */
1351 if ((bp_info->trigger_type == 0) ||
1352 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
1353 PPC_BREAKPOINT_TRIGGER_RW)) ||
1354 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
1355 (bp_info->condition_mode &
1356 ~(PPC_BREAKPOINT_CONDITION_MODE |
1357 PPC_BREAKPOINT_CONDITION_BE_ALL)))
1358 return -EINVAL;
1359 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
1360 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1361 return -EINVAL;
1362 #endif
1363
1364 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
1365 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
1366 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1367 return -EINVAL;
1368 return set_intruction_bp(child, bp_info);
1369 }
1370 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1371 return set_dac(child, bp_info);
1372
1373 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1374 return set_dac_range(child, bp_info);
1375 #else
1376 return -EINVAL;
1377 #endif
1378 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1379 /*
1380 * We only support one data breakpoint
1381 */
1382 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1383 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
1384 bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT ||
1385 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1386 return -EINVAL;
1387
1388 if (child->thread.dabr)
1389 return -ENOSPC;
1390
1391 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1392 return -EIO;
1393
1394 dabr = (unsigned long)bp_info->addr & ~7UL;
1395 dabr |= DABR_TRANSLATION;
1396 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1397 dabr |= DABR_DATA_READ;
1398 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1399 dabr |= DABR_DATA_WRITE;
1400
1401 child->thread.dabr = dabr;
1402
1403 return 1;
1404 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1405 }
1406
1407 static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
1408 {
1409 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1410 int rc;
1411
1412 if (data <= 4)
1413 rc = del_instruction_bp(child, (int)data);
1414 else
1415 rc = del_dac(child, (int)data - 4);
1416
1417 if (!rc) {
1418 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
1419 child->thread.dbcr1)) {
1420 child->thread.dbcr0 &= ~DBCR0_IDM;
1421 child->thread.regs->msr &= ~MSR_DE;
1422 }
1423 }
1424 return rc;
1425 #else
1426 if (data != 1)
1427 return -EINVAL;
1428 if (child->thread.dabr == 0)
1429 return -ENOENT;
1430
1431 child->thread.dabr = 0;
1432
1433 return 0;
1434 #endif
1435 }
1436
1437 /*
1438 * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
1439 * we mark them as obsolete now, they will be removed in a future version
1440 */
1441 static long arch_ptrace_old(struct task_struct *child, long request,
1442 unsigned long addr, unsigned long data)
1443 {
1444 void __user *datavp = (void __user *) data;
1445
1446 switch (request) {
1447 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
1448 return copy_regset_to_user(child, &user_ppc_native_view,
1449 REGSET_GPR, 0, 32 * sizeof(long),
1450 datavp);
1451
1452 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
1453 return copy_regset_from_user(child, &user_ppc_native_view,
1454 REGSET_GPR, 0, 32 * sizeof(long),
1455 datavp);
1456
1457 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
1458 return copy_regset_to_user(child, &user_ppc_native_view,
1459 REGSET_FPR, 0, 32 * sizeof(double),
1460 datavp);
1461
1462 case PPC_PTRACE_SETFPREGS: /* Set FPRs 0 - 31. */
1463 return copy_regset_from_user(child, &user_ppc_native_view,
1464 REGSET_FPR, 0, 32 * sizeof(double),
1465 datavp);
1466 }
1467
1468 return -EPERM;
1469 }
1470
1471 long arch_ptrace(struct task_struct *child, long request,
1472 unsigned long addr, unsigned long data)
1473 {
1474 int ret = -EPERM;
1475 void __user *datavp = (void __user *) data;
1476 unsigned long __user *datalp = datavp;
1477
1478 switch (request) {
1479 /* read the word at location addr in the USER area. */
1480 case PTRACE_PEEKUSR: {
1481 unsigned long index, tmp;
1482
1483 ret = -EIO;
1484 /* convert to index and check */
1485 #ifdef CONFIG_PPC32
1486 index = addr >> 2;
1487 if ((addr & 3) || (index > PT_FPSCR)
1488 || (child->thread.regs == NULL))
1489 #else
1490 index = addr >> 3;
1491 if ((addr & 7) || (index > PT_FPSCR))
1492 #endif
1493 break;
1494
1495 CHECK_FULL_REGS(child->thread.regs);
1496 if (index < PT_FPR0) {
1497 tmp = ptrace_get_reg(child, (int) index);
1498 } else {
1499 flush_fp_to_thread(child);
1500 tmp = ((unsigned long *)child->thread.fpr)
1501 [TS_FPRWIDTH * (index - PT_FPR0)];
1502 }
1503 ret = put_user(tmp, datalp);
1504 break;
1505 }
1506
1507 /* write the word at location addr in the USER area */
1508 case PTRACE_POKEUSR: {
1509 unsigned long index;
1510
1511 ret = -EIO;
1512 /* convert to index and check */
1513 #ifdef CONFIG_PPC32
1514 index = addr >> 2;
1515 if ((addr & 3) || (index > PT_FPSCR)
1516 || (child->thread.regs == NULL))
1517 #else
1518 index = addr >> 3;
1519 if ((addr & 7) || (index > PT_FPSCR))
1520 #endif
1521 break;
1522
1523 CHECK_FULL_REGS(child->thread.regs);
1524 if (index < PT_FPR0) {
1525 ret = ptrace_put_reg(child, index, data);
1526 } else {
1527 flush_fp_to_thread(child);
1528 ((unsigned long *)child->thread.fpr)
1529 [TS_FPRWIDTH * (index - PT_FPR0)] = data;
1530 ret = 0;
1531 }
1532 break;
1533 }
1534
1535 case PPC_PTRACE_GETHWDBGINFO: {
1536 struct ppc_debug_info dbginfo;
1537
1538 dbginfo.version = 1;
1539 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1540 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
1541 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
1542 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
1543 dbginfo.data_bp_alignment = 4;
1544 dbginfo.sizeof_condition = 4;
1545 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
1546 PPC_DEBUG_FEATURE_INSN_BP_MASK;
1547 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1548 dbginfo.features |=
1549 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1550 PPC_DEBUG_FEATURE_DATA_BP_MASK;
1551 #endif
1552 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
1553 dbginfo.num_instruction_bps = 0;
1554 dbginfo.num_data_bps = 1;
1555 dbginfo.num_condition_regs = 0;
1556 #ifdef CONFIG_PPC64
1557 dbginfo.data_bp_alignment = 8;
1558 #else
1559 dbginfo.data_bp_alignment = 4;
1560 #endif
1561 dbginfo.sizeof_condition = 0;
1562 dbginfo.features = 0;
1563 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1564
1565 if (!access_ok(VERIFY_WRITE, datavp,
1566 sizeof(struct ppc_debug_info)))
1567 return -EFAULT;
1568 ret = __copy_to_user(datavp, &dbginfo,
1569 sizeof(struct ppc_debug_info)) ?
1570 -EFAULT : 0;
1571 break;
1572 }
1573
1574 case PPC_PTRACE_SETHWDEBUG: {
1575 struct ppc_hw_breakpoint bp_info;
1576
1577 if (!access_ok(VERIFY_READ, datavp,
1578 sizeof(struct ppc_hw_breakpoint)))
1579 return -EFAULT;
1580 ret = __copy_from_user(&bp_info, datavp,
1581 sizeof(struct ppc_hw_breakpoint)) ?
1582 -EFAULT : 0;
1583 if (!ret)
1584 ret = ppc_set_hwdebug(child, &bp_info);
1585 break;
1586 }
1587
1588 case PPC_PTRACE_DELHWDEBUG: {
1589 ret = ppc_del_hwdebug(child, addr, data);
1590 break;
1591 }
1592
1593 case PTRACE_GET_DEBUGREG: {
1594 ret = -EINVAL;
1595 /* We only support one DABR and no IABRS at the moment */
1596 if (addr > 0)
1597 break;
1598 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1599 ret = put_user(child->thread.dac1, datalp);
1600 #else
1601 ret = put_user(child->thread.dabr, datalp);
1602 #endif
1603 break;
1604 }
1605
1606 case PTRACE_SET_DEBUGREG:
1607 ret = ptrace_set_debugreg(child, addr, data);
1608 break;
1609
1610 #ifdef CONFIG_PPC64
1611 case PTRACE_GETREGS64:
1612 #endif
1613 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
1614 return copy_regset_to_user(child, &user_ppc_native_view,
1615 REGSET_GPR,
1616 0, sizeof(struct pt_regs),
1617 datavp);
1618
1619 #ifdef CONFIG_PPC64
1620 case PTRACE_SETREGS64:
1621 #endif
1622 case PTRACE_SETREGS: /* Set all gp regs in the child. */
1623 return copy_regset_from_user(child, &user_ppc_native_view,
1624 REGSET_GPR,
1625 0, sizeof(struct pt_regs),
1626 datavp);
1627
1628 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
1629 return copy_regset_to_user(child, &user_ppc_native_view,
1630 REGSET_FPR,
1631 0, sizeof(elf_fpregset_t),
1632 datavp);
1633
1634 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
1635 return copy_regset_from_user(child, &user_ppc_native_view,
1636 REGSET_FPR,
1637 0, sizeof(elf_fpregset_t),
1638 datavp);
1639
1640 #ifdef CONFIG_ALTIVEC
1641 case PTRACE_GETVRREGS:
1642 return copy_regset_to_user(child, &user_ppc_native_view,
1643 REGSET_VMX,
1644 0, (33 * sizeof(vector128) +
1645 sizeof(u32)),
1646 datavp);
1647
1648 case PTRACE_SETVRREGS:
1649 return copy_regset_from_user(child, &user_ppc_native_view,
1650 REGSET_VMX,
1651 0, (33 * sizeof(vector128) +
1652 sizeof(u32)),
1653 datavp);
1654 #endif
1655 #ifdef CONFIG_VSX
1656 case PTRACE_GETVSRREGS:
1657 return copy_regset_to_user(child, &user_ppc_native_view,
1658 REGSET_VSX,
1659 0, 32 * sizeof(double),
1660 datavp);
1661
1662 case PTRACE_SETVSRREGS:
1663 return copy_regset_from_user(child, &user_ppc_native_view,
1664 REGSET_VSX,
1665 0, 32 * sizeof(double),
1666 datavp);
1667 #endif
1668 #ifdef CONFIG_SPE
1669 case PTRACE_GETEVRREGS:
1670 /* Get the child spe register state. */
1671 return copy_regset_to_user(child, &user_ppc_native_view,
1672 REGSET_SPE, 0, 35 * sizeof(u32),
1673 datavp);
1674
1675 case PTRACE_SETEVRREGS:
1676 /* Set the child spe register state. */
1677 return copy_regset_from_user(child, &user_ppc_native_view,
1678 REGSET_SPE, 0, 35 * sizeof(u32),
1679 datavp);
1680 #endif
1681
1682 /* Old reverse args ptrace callss */
1683 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
1684 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
1685 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
1686 case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */
1687 ret = arch_ptrace_old(child, request, addr, data);
1688 break;
1689
1690 default:
1691 ret = ptrace_request(child, request, addr, data);
1692 break;
1693 }
1694 return ret;
1695 }
1696
1697 /*
1698 * We must return the syscall number to actually look up in the table.
1699 * This can be -1L to skip running any syscall at all.
1700 */
1701 long do_syscall_trace_enter(struct pt_regs *regs)
1702 {
1703 long ret = 0;
1704
1705 secure_computing(regs->gpr[0]);
1706
1707 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1708 tracehook_report_syscall_entry(regs))
1709 /*
1710 * Tracing decided this syscall should not happen.
1711 * We'll return a bogus call number to get an ENOSYS
1712 * error, but leave the original number in regs->gpr[0].
1713 */
1714 ret = -1L;
1715
1716 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1717 trace_sys_enter(regs, regs->gpr[0]);
1718
1719 if (unlikely(current->audit_context)) {
1720 #ifdef CONFIG_PPC64
1721 if (!is_32bit_task())
1722 audit_syscall_entry(AUDIT_ARCH_PPC64,
1723 regs->gpr[0],
1724 regs->gpr[3], regs->gpr[4],
1725 regs->gpr[5], regs->gpr[6]);
1726 else
1727 #endif
1728 audit_syscall_entry(AUDIT_ARCH_PPC,
1729 regs->gpr[0],
1730 regs->gpr[3] & 0xffffffff,
1731 regs->gpr[4] & 0xffffffff,
1732 regs->gpr[5] & 0xffffffff,
1733 regs->gpr[6] & 0xffffffff);
1734 }
1735
1736 return ret ?: regs->gpr[0];
1737 }
1738
1739 void do_syscall_trace_leave(struct pt_regs *regs)
1740 {
1741 int step;
1742
1743 if (unlikely(current->audit_context))
1744 audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
1745 regs->result);
1746
1747 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1748 trace_sys_exit(regs, regs->result);
1749
1750 step = test_thread_flag(TIF_SINGLESTEP);
1751 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1752 tracehook_report_syscall_exit(regs, step);
1753 }
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