2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
28 #include <asm/sections.h>
32 #include <asm/pci-bridge.h>
34 #include <asm/pmac_feature.h>
48 /* Workaround flags for 32bit powermac machines */
49 unsigned int of_irq_workarounds
;
50 struct device_node
*of_irq_dflt_pic
;
52 /* Default addresses */
53 static volatile struct pmac_irq_hw __iomem
*pmac_irq_hw
[4];
55 #define GC_LEVEL_MASK 0x3ff00000
56 #define OHARE_LEVEL_MASK 0x1ff00000
57 #define HEATHROW_LEVEL_MASK 0x1ff00000
60 static int max_real_irqs
;
61 static u32 level_mask
[4];
63 static DEFINE_RAW_SPINLOCK(pmac_pic_lock
);
65 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
66 static unsigned long ppc_lost_interrupts
[NR_MASK_WORDS
];
67 static unsigned long ppc_cached_irq_mask
[NR_MASK_WORDS
];
68 static int pmac_irq_cascade
= -1;
69 static struct irq_host
*pmac_pic_host
;
71 static void __pmac_retrigger(unsigned int irq_nr
)
73 if (irq_nr
>= max_real_irqs
&& pmac_irq_cascade
> 0) {
74 __set_bit(irq_nr
, ppc_lost_interrupts
);
75 irq_nr
= pmac_irq_cascade
;
78 if (!__test_and_set_bit(irq_nr
, ppc_lost_interrupts
)) {
79 atomic_inc(&ppc_n_lost_interrupts
);
84 static void pmac_mask_and_ack_irq(struct irq_data
*d
)
86 unsigned int src
= irqd_to_hwirq(d
);
87 unsigned long bit
= 1UL << (src
& 0x1f);
91 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
92 __clear_bit(src
, ppc_cached_irq_mask
);
93 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
94 atomic_dec(&ppc_n_lost_interrupts
);
95 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
96 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
98 /* make sure ack gets to controller before we enable
101 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
102 != (ppc_cached_irq_mask
[i
] & bit
));
103 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
106 static void pmac_ack_irq(struct irq_data
*d
)
108 unsigned int src
= irqd_to_hwirq(d
);
109 unsigned long bit
= 1UL << (src
& 0x1f);
113 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
114 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
115 atomic_dec(&ppc_n_lost_interrupts
);
116 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
117 (void)in_le32(&pmac_irq_hw
[i
]->ack
);
118 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
121 static void __pmac_set_irq_mask(unsigned int irq_nr
, int nokicklost
)
123 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
126 if ((unsigned)irq_nr
>= max_irqs
)
129 /* enable unmasked interrupts */
130 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
133 /* make sure mask gets to controller before we
136 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
137 != (ppc_cached_irq_mask
[i
] & bit
));
140 * Unfortunately, setting the bit in the enable register
141 * when the device interrupt is already on *doesn't* set
142 * the bit in the flag register or request another interrupt.
144 if (bit
& ppc_cached_irq_mask
[i
] & in_le32(&pmac_irq_hw
[i
]->level
))
145 __pmac_retrigger(irq_nr
);
148 /* When an irq gets requested for the first client, if it's an
149 * edge interrupt, we clear any previous one on the controller
151 static unsigned int pmac_startup_irq(struct irq_data
*d
)
154 unsigned int src
= irqd_to_hwirq(d
);
155 unsigned long bit
= 1UL << (src
& 0x1f);
158 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
159 if (!irqd_is_level_type(d
))
160 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
161 __set_bit(src
, ppc_cached_irq_mask
);
162 __pmac_set_irq_mask(src
, 0);
163 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
168 static void pmac_mask_irq(struct irq_data
*d
)
171 unsigned int src
= irqd_to_hwirq(d
);
173 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
174 __clear_bit(src
, ppc_cached_irq_mask
);
175 __pmac_set_irq_mask(src
, 1);
176 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
179 static void pmac_unmask_irq(struct irq_data
*d
)
182 unsigned int src
= irqd_to_hwirq(d
);
184 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
185 __set_bit(src
, ppc_cached_irq_mask
);
186 __pmac_set_irq_mask(src
, 0);
187 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
190 static int pmac_retrigger(struct irq_data
*d
)
194 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
195 __pmac_retrigger(irqd_to_hwirq(d
));
196 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
200 static struct irq_chip pmac_pic
= {
202 .irq_startup
= pmac_startup_irq
,
203 .irq_mask
= pmac_mask_irq
,
204 .irq_ack
= pmac_ack_irq
,
205 .irq_mask_ack
= pmac_mask_and_ack_irq
,
206 .irq_unmask
= pmac_unmask_irq
,
207 .irq_retrigger
= pmac_retrigger
,
210 static irqreturn_t
gatwick_action(int cpl
, void *dev_id
)
216 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
217 for (irq
= max_irqs
; (irq
-= 32) >= max_real_irqs
; ) {
219 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
220 /* We must read level interrupts from the level register */
221 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
222 bits
&= ppc_cached_irq_mask
[i
];
225 irq
+= __ilog2(bits
);
226 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
227 generic_handle_irq(irq
);
228 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
231 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
235 static unsigned int pmac_pic_get_irq(void)
238 unsigned long bits
= 0;
241 #ifdef CONFIG_PPC_PMAC32_PSURGE
242 /* IPI's are a hack on the powersurge -- Cort */
243 if (smp_processor_id() != 0) {
244 return psurge_secondary_virq
;
246 #endif /* CONFIG_PPC_PMAC32_PSURGE */
247 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
248 for (irq
= max_real_irqs
; (irq
-= 32) >= 0; ) {
250 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
251 /* We must read level interrupts from the level register */
252 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
253 bits
&= ppc_cached_irq_mask
[i
];
256 irq
+= __ilog2(bits
);
259 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
260 if (unlikely(irq
< 0))
262 return irq_linear_revmap(pmac_pic_host
, irq
);
266 static struct irqaction xmon_action
= {
273 static struct irqaction gatwick_cascade_action
= {
274 .handler
= gatwick_action
,
275 .flags
= IRQF_DISABLED
,
279 static int pmac_pic_host_match(struct irq_host
*h
, struct device_node
*node
)
281 /* We match all, we don't always have a node anyway */
285 static int pmac_pic_host_map(struct irq_host
*h
, unsigned int virq
,
293 /* Mark level interrupts, set delayed disable for edge ones and set
296 level
= !!(level_mask
[hw
>> 5] & (1UL << (hw
& 0x1f)));
298 irq_set_status_flags(virq
, IRQ_LEVEL
);
299 irq_set_chip_and_handler(virq
, &pmac_pic
,
300 level
? handle_level_irq
: handle_edge_irq
);
304 static int pmac_pic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
305 const u32
*intspec
, unsigned int intsize
,
306 irq_hw_number_t
*out_hwirq
,
307 unsigned int *out_flags
)
310 *out_flags
= IRQ_TYPE_NONE
;
311 *out_hwirq
= *intspec
;
315 static struct irq_host_ops pmac_pic_host_ops
= {
316 .match
= pmac_pic_host_match
,
317 .map
= pmac_pic_host_map
,
318 .xlate
= pmac_pic_host_xlate
,
321 static void __init
pmac_pic_probe_oldstyle(void)
324 struct device_node
*master
= NULL
;
325 struct device_node
*slave
= NULL
;
329 /* Set our get_irq function */
330 ppc_md
.get_irq
= pmac_pic_get_irq
;
333 * Find the interrupt controller type & node
336 if ((master
= of_find_node_by_name(NULL
, "gc")) != NULL
) {
337 max_irqs
= max_real_irqs
= 32;
338 level_mask
[0] = GC_LEVEL_MASK
;
339 } else if ((master
= of_find_node_by_name(NULL
, "ohare")) != NULL
) {
340 max_irqs
= max_real_irqs
= 32;
341 level_mask
[0] = OHARE_LEVEL_MASK
;
343 /* We might have a second cascaded ohare */
344 slave
= of_find_node_by_name(NULL
, "pci106b,7");
347 level_mask
[1] = OHARE_LEVEL_MASK
;
349 } else if ((master
= of_find_node_by_name(NULL
, "mac-io")) != NULL
) {
350 max_irqs
= max_real_irqs
= 64;
351 level_mask
[0] = HEATHROW_LEVEL_MASK
;
354 /* We might have a second cascaded heathrow */
355 slave
= of_find_node_by_name(master
, "mac-io");
357 /* Check ordering of master & slave */
358 if (of_device_is_compatible(master
, "gatwick")) {
359 struct device_node
*tmp
;
360 BUG_ON(slave
== NULL
);
366 /* We found a slave */
369 level_mask
[2] = HEATHROW_LEVEL_MASK
;
373 BUG_ON(master
== NULL
);
376 * Allocate an irq host
378 pmac_pic_host
= irq_alloc_host(master
, IRQ_HOST_MAP_LINEAR
, max_irqs
,
381 BUG_ON(pmac_pic_host
== NULL
);
382 irq_set_default_host(pmac_pic_host
);
384 /* Get addresses of first controller if we have a node for it */
385 BUG_ON(of_address_to_resource(master
, 0, &r
));
387 /* Map interrupts of primary controller */
388 addr
= (u8 __iomem
*) ioremap(r
.start
, 0x40);
390 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
392 if (max_real_irqs
> 32)
393 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
397 printk(KERN_INFO
"irq: Found primary Apple PIC %s for %d irqs\n",
398 master
->full_name
, max_real_irqs
);
400 /* Map interrupts of cascaded controller */
401 if (slave
&& !of_address_to_resource(slave
, 0, &r
)) {
402 addr
= (u8 __iomem
*)ioremap(r
.start
, 0x40);
403 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
407 (volatile struct pmac_irq_hw __iomem
*)
409 pmac_irq_cascade
= irq_of_parse_and_map(slave
, 0);
411 printk(KERN_INFO
"irq: Found slave Apple PIC %s for %d irqs"
412 " cascade: %d\n", slave
->full_name
,
413 max_irqs
- max_real_irqs
, pmac_irq_cascade
);
417 /* Disable all interrupts in all controllers */
418 for (i
= 0; i
* 32 < max_irqs
; ++i
)
419 out_le32(&pmac_irq_hw
[i
]->enable
, 0);
421 /* Hookup cascade irq */
422 if (slave
&& pmac_irq_cascade
!= NO_IRQ
)
423 setup_irq(pmac_irq_cascade
, &gatwick_cascade_action
);
425 printk(KERN_INFO
"irq: System has %d possible interrupts\n", max_irqs
);
427 setup_irq(irq_create_mapping(NULL
, 20), &xmon_action
);
431 int of_irq_map_oldworld(struct device_node
*device
, int index
,
432 struct of_irq
*out_irq
)
434 const u32
*ints
= NULL
;
438 * Old machines just have a list of interrupt numbers
439 * and no interrupt-controller nodes. We also have dodgy
440 * cases where the APPL,interrupts property is completely
441 * missing behind pci-pci bridges and we have to get it
442 * from the parent (the bridge itself, as apple just wired
443 * everything together on these)
446 ints
= of_get_property(device
, "AAPL,interrupts", &intlen
);
449 device
= device
->parent
;
450 if (device
&& strcmp(device
->type
, "pci") != 0)
455 intlen
/= sizeof(u32
);
460 out_irq
->controller
= NULL
;
461 out_irq
->specifier
[0] = ints
[index
];
466 #endif /* CONFIG_PPC32 */
468 static void pmac_u3_cascade(unsigned int irq
, struct irq_desc
*desc
)
470 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
471 struct mpic
*mpic
= irq_desc_get_handler_data(desc
);
472 unsigned int cascade_irq
= mpic_get_one_irq(mpic
);
474 if (cascade_irq
!= NO_IRQ
)
475 generic_handle_irq(cascade_irq
);
477 chip
->irq_eoi(&desc
->irq_data
);
480 static void __init
pmac_pic_setup_mpic_nmi(struct mpic
*mpic
)
482 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
483 struct device_node
* pswitch
;
486 pswitch
= of_find_node_by_name(NULL
, "programmer-switch");
488 nmi_irq
= irq_of_parse_and_map(pswitch
, 0);
489 if (nmi_irq
!= NO_IRQ
) {
490 mpic_irq_set_priority(nmi_irq
, 9);
491 setup_irq(nmi_irq
, &xmon_action
);
493 of_node_put(pswitch
);
495 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
498 static struct mpic
* __init
pmac_setup_one_mpic(struct device_node
*np
,
501 const char *name
= master
? " MPIC 1 " : " MPIC 2 ";
504 unsigned int flags
= master
? MPIC_PRIMARY
: 0;
507 rc
= of_address_to_resource(np
, 0, &r
);
511 pmac_call_feature(PMAC_FTR_ENABLE_MPIC
, np
, 0, 0);
513 flags
|= MPIC_WANTS_RESET
;
514 if (of_get_property(np
, "big-endian", NULL
))
515 flags
|= MPIC_BIG_ENDIAN
;
517 /* Primary Big Endian means HT interrupts. This is quite dodgy
518 * but works until I find a better way
520 if (master
&& (flags
& MPIC_BIG_ENDIAN
))
521 flags
|= MPIC_U3_HT_IRQS
;
523 mpic
= mpic_alloc(np
, r
.start
, flags
, 0, 0, name
);
532 static int __init
pmac_pic_probe_mpic(void)
534 struct mpic
*mpic1
, *mpic2
;
535 struct device_node
*np
, *master
= NULL
, *slave
= NULL
;
536 unsigned int cascade
;
538 /* We can have up to 2 MPICs cascaded */
539 for (np
= NULL
; (np
= of_find_node_by_type(np
, "open-pic"))
541 if (master
== NULL
&&
542 of_get_property(np
, "interrupts", NULL
) == NULL
)
543 master
= of_node_get(np
);
544 else if (slave
== NULL
)
545 slave
= of_node_get(np
);
550 /* Check for bogus setups */
551 if (master
== NULL
&& slave
!= NULL
) {
556 /* Not found, default to good old pmac pic */
560 /* Set master handler */
561 ppc_md
.get_irq
= mpic_get_irq
;
564 mpic1
= pmac_setup_one_mpic(master
, 1);
565 BUG_ON(mpic1
== NULL
);
567 /* Install NMI if any */
568 pmac_pic_setup_mpic_nmi(mpic1
);
572 /* No slave, let's go out */
576 /* Get/Map slave interrupt */
577 cascade
= irq_of_parse_and_map(slave
, 0);
578 if (cascade
== NO_IRQ
) {
579 printk(KERN_ERR
"Failed to map cascade IRQ\n");
583 mpic2
= pmac_setup_one_mpic(slave
, 0);
585 printk(KERN_ERR
"Failed to setup slave MPIC\n");
589 irq_set_handler_data(cascade
, mpic2
);
590 irq_set_chained_handler(cascade
, pmac_u3_cascade
);
597 void __init
pmac_pic_init(void)
599 /* We configure the OF parsing based on our oldworld vs. newworld
600 * platform type and wether we were booted by BootX.
604 of_irq_workarounds
|= OF_IMAP_OLDWORLD_MAC
;
605 if (of_get_property(of_chosen
, "linux,bootx", NULL
) != NULL
)
606 of_irq_workarounds
|= OF_IMAP_NO_PHANDLE
;
608 /* If we don't have phandles on a newworld, then try to locate a
609 * default interrupt controller (happens when booting with BootX).
610 * We do a first match here, hopefully, that only ever happens on
611 * machines with one controller.
613 if (pmac_newworld
&& (of_irq_workarounds
& OF_IMAP_NO_PHANDLE
)) {
614 struct device_node
*np
;
616 for_each_node_with_property(np
, "interrupt-controller") {
617 /* Skip /chosen/interrupt-controller */
618 if (strcmp(np
->name
, "chosen") == 0)
620 /* It seems like at least one person wants
621 * to use BootX on a machine with an AppleKiwi
622 * controller which happens to pretend to be an
623 * interrupt controller too. */
624 if (strcmp(np
->name
, "AppleKiwi") == 0)
626 /* I think we found one ! */
627 of_irq_dflt_pic
= np
;
631 #endif /* CONFIG_PPC32 */
633 /* We first try to detect Apple's new Core99 chipset, since mac-io
634 * is quite different on those machines and contains an IBM MPIC2.
636 if (pmac_pic_probe_mpic() == 0)
640 pmac_pic_probe_oldstyle();
644 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
646 * These procedures are used in implementing sleep on the powerbooks.
647 * sleep_save_intrs() saves the states of all interrupt enables
648 * and disables all interrupts except for the nominated one.
649 * sleep_restore_intrs() restores the states of all interrupt enables.
651 unsigned long sleep_save_mask
[2];
653 /* This used to be passed by the PMU driver but that link got
654 * broken with the new driver model. We use this tweak for now...
655 * We really want to do things differently though...
657 static int pmacpic_find_viaint(void)
661 #ifdef CONFIG_ADB_PMU
662 struct device_node
*np
;
664 if (pmu_get_model() != PMU_OHARE_BASED
)
666 np
= of_find_node_by_name(NULL
, "via-pmu");
669 viaint
= irq_of_parse_and_map(np
, 0);
672 #endif /* CONFIG_ADB_PMU */
676 static int pmacpic_suspend(void)
678 int viaint
= pmacpic_find_viaint();
680 sleep_save_mask
[0] = ppc_cached_irq_mask
[0];
681 sleep_save_mask
[1] = ppc_cached_irq_mask
[1];
682 ppc_cached_irq_mask
[0] = 0;
683 ppc_cached_irq_mask
[1] = 0;
685 set_bit(viaint
, ppc_cached_irq_mask
);
686 out_le32(&pmac_irq_hw
[0]->enable
, ppc_cached_irq_mask
[0]);
687 if (max_real_irqs
> 32)
688 out_le32(&pmac_irq_hw
[1]->enable
, ppc_cached_irq_mask
[1]);
689 (void)in_le32(&pmac_irq_hw
[0]->event
);
690 /* make sure mask gets to controller before we return to caller */
692 (void)in_le32(&pmac_irq_hw
[0]->enable
);
697 static void pmacpic_resume(void)
701 out_le32(&pmac_irq_hw
[0]->enable
, 0);
702 if (max_real_irqs
> 32)
703 out_le32(&pmac_irq_hw
[1]->enable
, 0);
705 for (i
= 0; i
< max_real_irqs
; ++i
)
706 if (test_bit(i
, sleep_save_mask
))
707 pmac_unmask_irq(irq_get_irq_data(i
));
710 static struct syscore_ops pmacpic_syscore_ops
= {
711 .suspend
= pmacpic_suspend
,
712 .resume
= pmacpic_resume
,
715 static int __init
init_pmacpic_syscore(void)
718 register_syscore_ops(&pmacpic_syscore_ops
);
722 machine_subsys_initcall(powermac
, init_pmacpic_syscore
);
724 #endif /* CONFIG_PM && CONFIG_PPC32 */