arch/tile/include/asm/opcode_constants_64.h

   1 /*
   2  * Copyright 2011 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 /* This file is machine-generated; DO NOT EDIT! */
  16
  17
  18 #ifndef _TILE_OPCODE_CONSTANTS_H
  19 #define _TILE_OPCODE_CONSTANTS_H
  20 enum
  21 {
  22   ADDI_IMM8_OPCODE_X0 = 1,
  23   ADDI_IMM8_OPCODE_X1 = 1,
  24   ADDI_OPCODE_Y0 = 0,
  25   ADDI_OPCODE_Y1 = 1,
  26   ADDLI_OPCODE_X0 = 1,
  27   ADDLI_OPCODE_X1 = 0,
  28   ADDXI_IMM8_OPCODE_X0 = 2,
  29   ADDXI_IMM8_OPCODE_X1 = 2,
  30   ADDXI_OPCODE_Y0 = 1,
  31   ADDXI_OPCODE_Y1 = 2,
  32   ADDXLI_OPCODE_X0 = 2,
  33   ADDXLI_OPCODE_X1 = 1,
  34   ADDXSC_RRR_0_OPCODE_X0 = 1,
  35   ADDXSC_RRR_0_OPCODE_X1 = 1,
  36   ADDX_RRR_0_OPCODE_X0 = 2,
  37   ADDX_RRR_0_OPCODE_X1 = 2,
  38   ADDX_RRR_0_OPCODE_Y0 = 0,
  39   ADDX_SPECIAL_0_OPCODE_Y1 = 0,
  40   ADD_RRR_0_OPCODE_X0 = 3,
  41   ADD_RRR_0_OPCODE_X1 = 3,
  42   ADD_RRR_0_OPCODE_Y0 = 1,
  43   ADD_SPECIAL_0_OPCODE_Y1 = 1,
  44   ANDI_IMM8_OPCODE_X0 = 3,
  45   ANDI_IMM8_OPCODE_X1 = 3,
  46   ANDI_OPCODE_Y0 = 2,
  47   ANDI_OPCODE_Y1 = 3,
  48   AND_RRR_0_OPCODE_X0 = 4,
  49   AND_RRR_0_OPCODE_X1 = 4,
  50   AND_RRR_5_OPCODE_Y0 = 0,
  51   AND_RRR_5_OPCODE_Y1 = 0,
  52   BEQZT_BRANCH_OPCODE_X1 = 16,
  53   BEQZ_BRANCH_OPCODE_X1 = 17,
  54   BFEXTS_BF_OPCODE_X0 = 4,
  55   BFEXTU_BF_OPCODE_X0 = 5,
  56   BFINS_BF_OPCODE_X0 = 6,
  57   BF_OPCODE_X0 = 3,
  58   BGEZT_BRANCH_OPCODE_X1 = 18,
  59   BGEZ_BRANCH_OPCODE_X1 = 19,
  60   BGTZT_BRANCH_OPCODE_X1 = 20,
  61   BGTZ_BRANCH_OPCODE_X1 = 21,
  62   BLBCT_BRANCH_OPCODE_X1 = 22,
  63   BLBC_BRANCH_OPCODE_X1 = 23,
  64   BLBST_BRANCH_OPCODE_X1 = 24,
  65   BLBS_BRANCH_OPCODE_X1 = 25,
  66   BLEZT_BRANCH_OPCODE_X1 = 26,
  67   BLEZ_BRANCH_OPCODE_X1 = 27,
  68   BLTZT_BRANCH_OPCODE_X1 = 28,
  69   BLTZ_BRANCH_OPCODE_X1 = 29,
  70   BNEZT_BRANCH_OPCODE_X1 = 30,
  71   BNEZ_BRANCH_OPCODE_X1 = 31,
  72   BRANCH_OPCODE_X1 = 2,
  73   CMOVEQZ_RRR_0_OPCODE_X0 = 5,
  74   CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
  75   CMOVNEZ_RRR_0_OPCODE_X0 = 6,
  76   CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
  77   CMPEQI_IMM8_OPCODE_X0 = 4,
  78   CMPEQI_IMM8_OPCODE_X1 = 4,
  79   CMPEQI_OPCODE_Y0 = 3,
  80   CMPEQI_OPCODE_Y1 = 4,
  81   CMPEQ_RRR_0_OPCODE_X0 = 7,
  82   CMPEQ_RRR_0_OPCODE_X1 = 5,
  83   CMPEQ_RRR_3_OPCODE_Y0 = 0,
  84   CMPEQ_RRR_3_OPCODE_Y1 = 2,
  85   CMPEXCH4_RRR_0_OPCODE_X1 = 6,
  86   CMPEXCH_RRR_0_OPCODE_X1 = 7,
  87   CMPLES_RRR_0_OPCODE_X0 = 8,
  88   CMPLES_RRR_0_OPCODE_X1 = 8,
  89   CMPLES_RRR_2_OPCODE_Y0 = 0,
  90   CMPLES_RRR_2_OPCODE_Y1 = 0,
  91   CMPLEU_RRR_0_OPCODE_X0 = 9,
  92   CMPLEU_RRR_0_OPCODE_X1 = 9,
  93   CMPLEU_RRR_2_OPCODE_Y0 = 1,
  94   CMPLEU_RRR_2_OPCODE_Y1 = 1,
  95   CMPLTSI_IMM8_OPCODE_X0 = 5,
  96   CMPLTSI_IMM8_OPCODE_X1 = 5,
  97   CMPLTSI_OPCODE_Y0 = 4,
  98   CMPLTSI_OPCODE_Y1 = 5,
  99   CMPLTS_RRR_0_OPCODE_X0 = 10,
 100   CMPLTS_RRR_0_OPCODE_X1 = 10,
 101   CMPLTS_RRR_2_OPCODE_Y0 = 2,
 102   CMPLTS_RRR_2_OPCODE_Y1 = 2,
 103   CMPLTUI_IMM8_OPCODE_X0 = 6,
 104   CMPLTUI_IMM8_OPCODE_X1 = 6,
 105   CMPLTU_RRR_0_OPCODE_X0 = 11,
 106   CMPLTU_RRR_0_OPCODE_X1 = 11,
 107   CMPLTU_RRR_2_OPCODE_Y0 = 3,
 108   CMPLTU_RRR_2_OPCODE_Y1 = 3,
 109   CMPNE_RRR_0_OPCODE_X0 = 12,
 110   CMPNE_RRR_0_OPCODE_X1 = 12,
 111   CMPNE_RRR_3_OPCODE_Y0 = 1,
 112   CMPNE_RRR_3_OPCODE_Y1 = 3,
 113   CMULAF_RRR_0_OPCODE_X0 = 13,
 114   CMULA_RRR_0_OPCODE_X0 = 14,
 115   CMULFR_RRR_0_OPCODE_X0 = 15,
 116   CMULF_RRR_0_OPCODE_X0 = 16,
 117   CMULHR_RRR_0_OPCODE_X0 = 17,
 118   CMULH_RRR_0_OPCODE_X0 = 18,
 119   CMUL_RRR_0_OPCODE_X0 = 19,
 120   CNTLZ_UNARY_OPCODE_X0 = 1,
 121   CNTLZ_UNARY_OPCODE_Y0 = 1,
 122   CNTTZ_UNARY_OPCODE_X0 = 2,
 123   CNTTZ_UNARY_OPCODE_Y0 = 2,
 124   CRC32_32_RRR_0_OPCODE_X0 = 20,
 125   CRC32_8_RRR_0_OPCODE_X0 = 21,
 126   DBLALIGN2_RRR_0_OPCODE_X0 = 22,
 127   DBLALIGN2_RRR_0_OPCODE_X1 = 13,
 128   DBLALIGN4_RRR_0_OPCODE_X0 = 23,
 129   DBLALIGN4_RRR_0_OPCODE_X1 = 14,
 130   DBLALIGN6_RRR_0_OPCODE_X0 = 24,
 131   DBLALIGN6_RRR_0_OPCODE_X1 = 15,
 132   DBLALIGN_RRR_0_OPCODE_X0 = 25,
 133   DRAIN_UNARY_OPCODE_X1 = 1,
 134   DTLBPR_UNARY_OPCODE_X1 = 2,
 135   EXCH4_RRR_0_OPCODE_X1 = 16,
 136   EXCH_RRR_0_OPCODE_X1 = 17,
 137   FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
 138   FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
 139   FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
 140   FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
 141   FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
 142   FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
 143   FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
 144   FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
 145   FETCHADD4_RRR_0_OPCODE_X1 = 18,
 146   FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
 147   FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
 148   FETCHADD_RRR_0_OPCODE_X1 = 21,
 149   FETCHAND4_RRR_0_OPCODE_X1 = 22,
 150   FETCHAND_RRR_0_OPCODE_X1 = 23,
 151   FETCHOR4_RRR_0_OPCODE_X1 = 24,
 152   FETCHOR_RRR_0_OPCODE_X1 = 25,
 153   FINV_UNARY_OPCODE_X1 = 3,
 154   FLUSHWB_UNARY_OPCODE_X1 = 4,
 155   FLUSH_UNARY_OPCODE_X1 = 5,
 156   FNOP_UNARY_OPCODE_X0 = 3,
 157   FNOP_UNARY_OPCODE_X1 = 6,
 158   FNOP_UNARY_OPCODE_Y0 = 3,
 159   FNOP_UNARY_OPCODE_Y1 = 8,
 160   FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
 161   FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
 162   FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
 163   FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
 164   FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
 165   FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
 166   FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
 167   FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
 168   ICOH_UNARY_OPCODE_X1 = 7,
 169   ILL_UNARY_OPCODE_X1 = 8,
 170   ILL_UNARY_OPCODE_Y1 = 9,
 171   IMM8_OPCODE_X0 = 4,
 172   IMM8_OPCODE_X1 = 3,
 173   INV_UNARY_OPCODE_X1 = 9,
 174   IRET_UNARY_OPCODE_X1 = 10,
 175   JALRP_UNARY_OPCODE_X1 = 11,
 176   JALRP_UNARY_OPCODE_Y1 = 10,
 177   JALR_UNARY_OPCODE_X1 = 12,
 178   JALR_UNARY_OPCODE_Y1 = 11,
 179   JAL_JUMP_OPCODE_X1 = 0,
 180   JRP_UNARY_OPCODE_X1 = 13,
 181   JRP_UNARY_OPCODE_Y1 = 12,
 182   JR_UNARY_OPCODE_X1 = 14,
 183   JR_UNARY_OPCODE_Y1 = 13,
 184   JUMP_OPCODE_X1 = 4,
 185   J_JUMP_OPCODE_X1 = 1,
 186   LD1S_ADD_IMM8_OPCODE_X1 = 7,
 187   LD1S_OPCODE_Y2 = 0,
 188   LD1S_UNARY_OPCODE_X1 = 15,
 189   LD1U_ADD_IMM8_OPCODE_X1 = 8,
 190   LD1U_OPCODE_Y2 = 1,
 191   LD1U_UNARY_OPCODE_X1 = 16,
 192   LD2S_ADD_IMM8_OPCODE_X1 = 9,
 193   LD2S_OPCODE_Y2 = 2,
 194   LD2S_UNARY_OPCODE_X1 = 17,
 195   LD2U_ADD_IMM8_OPCODE_X1 = 10,
 196   LD2U_OPCODE_Y2 = 3,
 197   LD2U_UNARY_OPCODE_X1 = 18,
 198   LD4S_ADD_IMM8_OPCODE_X1 = 11,
 199   LD4S_OPCODE_Y2 = 1,
 200   LD4S_UNARY_OPCODE_X1 = 19,
 201   LD4U_ADD_IMM8_OPCODE_X1 = 12,
 202   LD4U_OPCODE_Y2 = 2,
 203   LD4U_UNARY_OPCODE_X1 = 20,
 204   LDNA_UNARY_OPCODE_X1 = 21,
 205   LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
 206   LDNT1S_UNARY_OPCODE_X1 = 22,
 207   LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
 208   LDNT1U_UNARY_OPCODE_X1 = 23,
 209   LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
 210   LDNT2S_UNARY_OPCODE_X1 = 24,
 211   LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
 212   LDNT2U_UNARY_OPCODE_X1 = 25,
 213   LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
 214   LDNT4S_UNARY_OPCODE_X1 = 26,
 215   LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
 216   LDNT4U_UNARY_OPCODE_X1 = 27,
 217   LDNT_ADD_IMM8_OPCODE_X1 = 19,
 218   LDNT_UNARY_OPCODE_X1 = 28,
 219   LD_ADD_IMM8_OPCODE_X1 = 20,
 220   LD_OPCODE_Y2 = 3,
 221   LD_UNARY_OPCODE_X1 = 29,
 222   LNK_UNARY_OPCODE_X1 = 30,
 223   LNK_UNARY_OPCODE_Y1 = 14,
 224   LWNA_ADD_IMM8_OPCODE_X1 = 21,
 225   MFSPR_IMM8_OPCODE_X1 = 22,
 226   MF_UNARY_OPCODE_X1 = 31,
 227   MM_BF_OPCODE_X0 = 7,
 228   MNZ_RRR_0_OPCODE_X0 = 40,
 229   MNZ_RRR_0_OPCODE_X1 = 26,
 230   MNZ_RRR_4_OPCODE_Y0 = 2,
 231   MNZ_RRR_4_OPCODE_Y1 = 2,
 232   MODE_OPCODE_YA2 = 1,
 233   MODE_OPCODE_YB2 = 2,
 234   MODE_OPCODE_YC2 = 3,
 235   MTSPR_IMM8_OPCODE_X1 = 23,
 236   MULAX_RRR_0_OPCODE_X0 = 41,
 237   MULAX_RRR_3_OPCODE_Y0 = 2,
 238   MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
 239   MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
 240   MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
 241   MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
 242   MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
 243   MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
 244   MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
 245   MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
 246   MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
 247   MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
 248   MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
 249   MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
 250   MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
 251   MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
 252   MULX_RRR_0_OPCODE_X0 = 52,
 253   MULX_RRR_3_OPCODE_Y0 = 3,
 254   MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
 255   MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
 256   MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
 257   MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
 258   MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
 259   MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
 260   MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
 261   MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
 262   MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
 263   MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
 264   MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
 265   MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
 266   MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
 267   MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
 268   MZ_RRR_0_OPCODE_X0 = 63,
 269   MZ_RRR_0_OPCODE_X1 = 27,
 270   MZ_RRR_4_OPCODE_Y0 = 3,
 271   MZ_RRR_4_OPCODE_Y1 = 3,
 272   NAP_UNARY_OPCODE_X1 = 32,
 273   NOP_UNARY_OPCODE_X0 = 5,
 274   NOP_UNARY_OPCODE_X1 = 33,
 275   NOP_UNARY_OPCODE_Y0 = 5,
 276   NOP_UNARY_OPCODE_Y1 = 15,
 277   NOR_RRR_0_OPCODE_X0 = 64,
 278   NOR_RRR_0_OPCODE_X1 = 28,
 279   NOR_RRR_5_OPCODE_Y0 = 1,
 280   NOR_RRR_5_OPCODE_Y1 = 1,
 281   ORI_IMM8_OPCODE_X0 = 7,
 282   ORI_IMM8_OPCODE_X1 = 24,
 283   OR_RRR_0_OPCODE_X0 = 65,
 284   OR_RRR_0_OPCODE_X1 = 29,
 285   OR_RRR_5_OPCODE_Y0 = 2,
 286   OR_RRR_5_OPCODE_Y1 = 2,
 287   PCNT_UNARY_OPCODE_X0 = 6,
 288   PCNT_UNARY_OPCODE_Y0 = 6,
 289   REVBITS_UNARY_OPCODE_X0 = 7,
 290   REVBITS_UNARY_OPCODE_Y0 = 7,
 291   REVBYTES_UNARY_OPCODE_X0 = 8,
 292   REVBYTES_UNARY_OPCODE_Y0 = 8,
 293   ROTLI_SHIFT_OPCODE_X0 = 1,
 294   ROTLI_SHIFT_OPCODE_X1 = 1,
 295   ROTLI_SHIFT_OPCODE_Y0 = 0,
 296   ROTLI_SHIFT_OPCODE_Y1 = 0,
 297   ROTL_RRR_0_OPCODE_X0 = 66,
 298   ROTL_RRR_0_OPCODE_X1 = 30,
 299   ROTL_RRR_6_OPCODE_Y0 = 0,
 300   ROTL_RRR_6_OPCODE_Y1 = 0,
 301   RRR_0_OPCODE_X0 = 5,
 302   RRR_0_OPCODE_X1 = 5,
 303   RRR_0_OPCODE_Y0 = 5,
 304   RRR_0_OPCODE_Y1 = 6,
 305   RRR_1_OPCODE_Y0 = 6,
 306   RRR_1_OPCODE_Y1 = 7,
 307   RRR_2_OPCODE_Y0 = 7,
 308   RRR_2_OPCODE_Y1 = 8,
 309   RRR_3_OPCODE_Y0 = 8,
 310   RRR_3_OPCODE_Y1 = 9,
 311   RRR_4_OPCODE_Y0 = 9,
 312   RRR_4_OPCODE_Y1 = 10,
 313   RRR_5_OPCODE_Y0 = 10,
 314   RRR_5_OPCODE_Y1 = 11,
 315   RRR_6_OPCODE_Y0 = 11,
 316   RRR_6_OPCODE_Y1 = 12,
 317   RRR_7_OPCODE_Y0 = 12,
 318   RRR_7_OPCODE_Y1 = 13,
 319   RRR_8_OPCODE_Y0 = 13,
 320   RRR_9_OPCODE_Y0 = 14,
 321   SHIFT_OPCODE_X0 = 6,
 322   SHIFT_OPCODE_X1 = 6,
 323   SHIFT_OPCODE_Y0 = 15,
 324   SHIFT_OPCODE_Y1 = 14,
 325   SHL16INSLI_OPCODE_X0 = 7,
 326   SHL16INSLI_OPCODE_X1 = 7,
 327   SHL1ADDX_RRR_0_OPCODE_X0 = 67,
 328   SHL1ADDX_RRR_0_OPCODE_X1 = 31,
 329   SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
 330   SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
 331   SHL1ADD_RRR_0_OPCODE_X0 = 68,
 332   SHL1ADD_RRR_0_OPCODE_X1 = 32,
 333   SHL1ADD_RRR_1_OPCODE_Y0 = 0,
 334   SHL1ADD_RRR_1_OPCODE_Y1 = 0,
 335   SHL2ADDX_RRR_0_OPCODE_X0 = 69,
 336   SHL2ADDX_RRR_0_OPCODE_X1 = 33,
 337   SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
 338   SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
 339   SHL2ADD_RRR_0_OPCODE_X0 = 70,
 340   SHL2ADD_RRR_0_OPCODE_X1 = 34,
 341   SHL2ADD_RRR_1_OPCODE_Y0 = 1,
 342   SHL2ADD_RRR_1_OPCODE_Y1 = 1,
 343   SHL3ADDX_RRR_0_OPCODE_X0 = 71,
 344   SHL3ADDX_RRR_0_OPCODE_X1 = 35,
 345   SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
 346   SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
 347   SHL3ADD_RRR_0_OPCODE_X0 = 72,
 348   SHL3ADD_RRR_0_OPCODE_X1 = 36,
 349   SHL3ADD_RRR_1_OPCODE_Y0 = 2,
 350   SHL3ADD_RRR_1_OPCODE_Y1 = 2,
 351   SHLI_SHIFT_OPCODE_X0 = 2,
 352   SHLI_SHIFT_OPCODE_X1 = 2,
 353   SHLI_SHIFT_OPCODE_Y0 = 1,
 354   SHLI_SHIFT_OPCODE_Y1 = 1,
 355   SHLXI_SHIFT_OPCODE_X0 = 3,
 356   SHLXI_SHIFT_OPCODE_X1 = 3,
 357   SHLX_RRR_0_OPCODE_X0 = 73,
 358   SHLX_RRR_0_OPCODE_X1 = 37,
 359   SHL_RRR_0_OPCODE_X0 = 74,
 360   SHL_RRR_0_OPCODE_X1 = 38,
 361   SHL_RRR_6_OPCODE_Y0 = 1,
 362   SHL_RRR_6_OPCODE_Y1 = 1,
 363   SHRSI_SHIFT_OPCODE_X0 = 4,
 364   SHRSI_SHIFT_OPCODE_X1 = 4,
 365   SHRSI_SHIFT_OPCODE_Y0 = 2,
 366   SHRSI_SHIFT_OPCODE_Y1 = 2,
 367   SHRS_RRR_0_OPCODE_X0 = 75,
 368   SHRS_RRR_0_OPCODE_X1 = 39,
 369   SHRS_RRR_6_OPCODE_Y0 = 2,
 370   SHRS_RRR_6_OPCODE_Y1 = 2,
 371   SHRUI_SHIFT_OPCODE_X0 = 5,
 372   SHRUI_SHIFT_OPCODE_X1 = 5,
 373   SHRUI_SHIFT_OPCODE_Y0 = 3,
 374   SHRUI_SHIFT_OPCODE_Y1 = 3,
 375   SHRUXI_SHIFT_OPCODE_X0 = 6,
 376   SHRUXI_SHIFT_OPCODE_X1 = 6,
 377   SHRUX_RRR_0_OPCODE_X0 = 76,
 378   SHRUX_RRR_0_OPCODE_X1 = 40,
 379   SHRU_RRR_0_OPCODE_X0 = 77,
 380   SHRU_RRR_0_OPCODE_X1 = 41,
 381   SHRU_RRR_6_OPCODE_Y0 = 3,
 382   SHRU_RRR_6_OPCODE_Y1 = 3,
 383   SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
 384   ST1_ADD_IMM8_OPCODE_X1 = 25,
 385   ST1_OPCODE_Y2 = 0,
 386   ST1_RRR_0_OPCODE_X1 = 42,
 387   ST2_ADD_IMM8_OPCODE_X1 = 26,
 388   ST2_OPCODE_Y2 = 1,
 389   ST2_RRR_0_OPCODE_X1 = 43,
 390   ST4_ADD_IMM8_OPCODE_X1 = 27,
 391   ST4_OPCODE_Y2 = 2,
 392   ST4_RRR_0_OPCODE_X1 = 44,
 393   STNT1_ADD_IMM8_OPCODE_X1 = 28,
 394   STNT1_RRR_0_OPCODE_X1 = 45,
 395   STNT2_ADD_IMM8_OPCODE_X1 = 29,
 396   STNT2_RRR_0_OPCODE_X1 = 46,
 397   STNT4_ADD_IMM8_OPCODE_X1 = 30,
 398   STNT4_RRR_0_OPCODE_X1 = 47,
 399   STNT_ADD_IMM8_OPCODE_X1 = 31,
 400   STNT_RRR_0_OPCODE_X1 = 48,
 401   ST_ADD_IMM8_OPCODE_X1 = 32,
 402   ST_OPCODE_Y2 = 3,
 403   ST_RRR_0_OPCODE_X1 = 49,
 404   SUBXSC_RRR_0_OPCODE_X0 = 79,
 405   SUBXSC_RRR_0_OPCODE_X1 = 50,
 406   SUBX_RRR_0_OPCODE_X0 = 80,
 407   SUBX_RRR_0_OPCODE_X1 = 51,
 408   SUBX_RRR_0_OPCODE_Y0 = 2,
 409   SUBX_RRR_0_OPCODE_Y1 = 2,
 410   SUB_RRR_0_OPCODE_X0 = 81,
 411   SUB_RRR_0_OPCODE_X1 = 52,
 412   SUB_RRR_0_OPCODE_Y0 = 3,
 413   SUB_RRR_0_OPCODE_Y1 = 3,
 414   SWINT0_UNARY_OPCODE_X1 = 34,
 415   SWINT1_UNARY_OPCODE_X1 = 35,
 416   SWINT2_UNARY_OPCODE_X1 = 36,
 417   SWINT3_UNARY_OPCODE_X1 = 37,
 418   TBLIDXB0_UNARY_OPCODE_X0 = 9,
 419   TBLIDXB0_UNARY_OPCODE_Y0 = 9,
 420   TBLIDXB1_UNARY_OPCODE_X0 = 10,
 421   TBLIDXB1_UNARY_OPCODE_Y0 = 10,
 422   TBLIDXB2_UNARY_OPCODE_X0 = 11,
 423   TBLIDXB2_UNARY_OPCODE_Y0 = 11,
 424   TBLIDXB3_UNARY_OPCODE_X0 = 12,
 425   TBLIDXB3_UNARY_OPCODE_Y0 = 12,
 426   UNARY_RRR_0_OPCODE_X0 = 82,
 427   UNARY_RRR_0_OPCODE_X1 = 53,
 428   UNARY_RRR_1_OPCODE_Y0 = 3,
 429   UNARY_RRR_1_OPCODE_Y1 = 3,
 430   V1ADDI_IMM8_OPCODE_X0 = 8,
 431   V1ADDI_IMM8_OPCODE_X1 = 33,
 432   V1ADDUC_RRR_0_OPCODE_X0 = 83,
 433   V1ADDUC_RRR_0_OPCODE_X1 = 54,
 434   V1ADD_RRR_0_OPCODE_X0 = 84,
 435   V1ADD_RRR_0_OPCODE_X1 = 55,
 436   V1ADIFFU_RRR_0_OPCODE_X0 = 85,
 437   V1AVGU_RRR_0_OPCODE_X0 = 86,
 438   V1CMPEQI_IMM8_OPCODE_X0 = 9,
 439   V1CMPEQI_IMM8_OPCODE_X1 = 34,
 440   V1CMPEQ_RRR_0_OPCODE_X0 = 87,
 441   V1CMPEQ_RRR_0_OPCODE_X1 = 56,
 442   V1CMPLES_RRR_0_OPCODE_X0 = 88,
 443   V1CMPLES_RRR_0_OPCODE_X1 = 57,
 444   V1CMPLEU_RRR_0_OPCODE_X0 = 89,
 445   V1CMPLEU_RRR_0_OPCODE_X1 = 58,
 446   V1CMPLTSI_IMM8_OPCODE_X0 = 10,
 447   V1CMPLTSI_IMM8_OPCODE_X1 = 35,
 448   V1CMPLTS_RRR_0_OPCODE_X0 = 90,
 449   V1CMPLTS_RRR_0_OPCODE_X1 = 59,
 450   V1CMPLTUI_IMM8_OPCODE_X0 = 11,
 451   V1CMPLTUI_IMM8_OPCODE_X1 = 36,
 452   V1CMPLTU_RRR_0_OPCODE_X0 = 91,
 453   V1CMPLTU_RRR_0_OPCODE_X1 = 60,
 454   V1CMPNE_RRR_0_OPCODE_X0 = 92,
 455   V1CMPNE_RRR_0_OPCODE_X1 = 61,
 456   V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
 457   V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
 458   V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
 459   V1DDOTPU_RRR_0_OPCODE_X0 = 162,
 460   V1DOTPA_RRR_0_OPCODE_X0 = 95,
 461   V1DOTPUA_RRR_0_OPCODE_X0 = 163,
 462   V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
 463   V1DOTPUS_RRR_0_OPCODE_X0 = 97,
 464   V1DOTPU_RRR_0_OPCODE_X0 = 164,
 465   V1DOTP_RRR_0_OPCODE_X0 = 98,
 466   V1INT_H_RRR_0_OPCODE_X0 = 99,
 467   V1INT_H_RRR_0_OPCODE_X1 = 62,
 468   V1INT_L_RRR_0_OPCODE_X0 = 100,
 469   V1INT_L_RRR_0_OPCODE_X1 = 63,
 470   V1MAXUI_IMM8_OPCODE_X0 = 12,
 471   V1MAXUI_IMM8_OPCODE_X1 = 37,
 472   V1MAXU_RRR_0_OPCODE_X0 = 101,
 473   V1MAXU_RRR_0_OPCODE_X1 = 64,
 474   V1MINUI_IMM8_OPCODE_X0 = 13,
 475   V1MINUI_IMM8_OPCODE_X1 = 38,
 476   V1MINU_RRR_0_OPCODE_X0 = 102,
 477   V1MINU_RRR_0_OPCODE_X1 = 65,
 478   V1MNZ_RRR_0_OPCODE_X0 = 103,
 479   V1MNZ_RRR_0_OPCODE_X1 = 66,
 480   V1MULTU_RRR_0_OPCODE_X0 = 104,
 481   V1MULUS_RRR_0_OPCODE_X0 = 105,
 482   V1MULU_RRR_0_OPCODE_X0 = 106,
 483   V1MZ_RRR_0_OPCODE_X0 = 107,
 484   V1MZ_RRR_0_OPCODE_X1 = 67,
 485   V1SADAU_RRR_0_OPCODE_X0 = 108,
 486   V1SADU_RRR_0_OPCODE_X0 = 109,
 487   V1SHLI_SHIFT_OPCODE_X0 = 7,
 488   V1SHLI_SHIFT_OPCODE_X1 = 7,
 489   V1SHL_RRR_0_OPCODE_X0 = 110,
 490   V1SHL_RRR_0_OPCODE_X1 = 68,
 491   V1SHRSI_SHIFT_OPCODE_X0 = 8,
 492   V1SHRSI_SHIFT_OPCODE_X1 = 8,
 493   V1SHRS_RRR_0_OPCODE_X0 = 111,
 494   V1SHRS_RRR_0_OPCODE_X1 = 69,
 495   V1SHRUI_SHIFT_OPCODE_X0 = 9,
 496   V1SHRUI_SHIFT_OPCODE_X1 = 9,
 497   V1SHRU_RRR_0_OPCODE_X0 = 112,
 498   V1SHRU_RRR_0_OPCODE_X1 = 70,
 499   V1SUBUC_RRR_0_OPCODE_X0 = 113,
 500   V1SUBUC_RRR_0_OPCODE_X1 = 71,
 501   V1SUB_RRR_0_OPCODE_X0 = 114,
 502   V1SUB_RRR_0_OPCODE_X1 = 72,
 503   V2ADDI_IMM8_OPCODE_X0 = 14,
 504   V2ADDI_IMM8_OPCODE_X1 = 39,
 505   V2ADDSC_RRR_0_OPCODE_X0 = 115,
 506   V2ADDSC_RRR_0_OPCODE_X1 = 73,
 507   V2ADD_RRR_0_OPCODE_X0 = 116,
 508   V2ADD_RRR_0_OPCODE_X1 = 74,
 509   V2ADIFFS_RRR_0_OPCODE_X0 = 117,
 510   V2AVGS_RRR_0_OPCODE_X0 = 118,
 511   V2CMPEQI_IMM8_OPCODE_X0 = 15,
 512   V2CMPEQI_IMM8_OPCODE_X1 = 40,
 513   V2CMPEQ_RRR_0_OPCODE_X0 = 119,
 514   V2CMPEQ_RRR_0_OPCODE_X1 = 75,
 515   V2CMPLES_RRR_0_OPCODE_X0 = 120,
 516   V2CMPLES_RRR_0_OPCODE_X1 = 76,
 517   V2CMPLEU_RRR_0_OPCODE_X0 = 121,
 518   V2CMPLEU_RRR_0_OPCODE_X1 = 77,
 519   V2CMPLTSI_IMM8_OPCODE_X0 = 16,
 520   V2CMPLTSI_IMM8_OPCODE_X1 = 41,
 521   V2CMPLTS_RRR_0_OPCODE_X0 = 122,
 522   V2CMPLTS_RRR_0_OPCODE_X1 = 78,
 523   V2CMPLTUI_IMM8_OPCODE_X0 = 17,
 524   V2CMPLTUI_IMM8_OPCODE_X1 = 42,
 525   V2CMPLTU_RRR_0_OPCODE_X0 = 123,
 526   V2CMPLTU_RRR_0_OPCODE_X1 = 79,
 527   V2CMPNE_RRR_0_OPCODE_X0 = 124,
 528   V2CMPNE_RRR_0_OPCODE_X1 = 80,
 529   V2DOTPA_RRR_0_OPCODE_X0 = 125,
 530   V2DOTP_RRR_0_OPCODE_X0 = 126,
 531   V2INT_H_RRR_0_OPCODE_X0 = 127,
 532   V2INT_H_RRR_0_OPCODE_X1 = 81,
 533   V2INT_L_RRR_0_OPCODE_X0 = 128,
 534   V2INT_L_RRR_0_OPCODE_X1 = 82,
 535   V2MAXSI_IMM8_OPCODE_X0 = 18,
 536   V2MAXSI_IMM8_OPCODE_X1 = 43,
 537   V2MAXS_RRR_0_OPCODE_X0 = 129,
 538   V2MAXS_RRR_0_OPCODE_X1 = 83,
 539   V2MINSI_IMM8_OPCODE_X0 = 19,
 540   V2MINSI_IMM8_OPCODE_X1 = 44,
 541   V2MINS_RRR_0_OPCODE_X0 = 130,
 542   V2MINS_RRR_0_OPCODE_X1 = 84,
 543   V2MNZ_RRR_0_OPCODE_X0 = 131,
 544   V2MNZ_RRR_0_OPCODE_X1 = 85,
 545   V2MULFSC_RRR_0_OPCODE_X0 = 132,
 546   V2MULS_RRR_0_OPCODE_X0 = 133,
 547   V2MULTS_RRR_0_OPCODE_X0 = 134,
 548   V2MZ_RRR_0_OPCODE_X0 = 135,
 549   V2MZ_RRR_0_OPCODE_X1 = 86,
 550   V2PACKH_RRR_0_OPCODE_X0 = 136,
 551   V2PACKH_RRR_0_OPCODE_X1 = 87,
 552   V2PACKL_RRR_0_OPCODE_X0 = 137,
 553   V2PACKL_RRR_0_OPCODE_X1 = 88,
 554   V2PACKUC_RRR_0_OPCODE_X0 = 138,
 555   V2PACKUC_RRR_0_OPCODE_X1 = 89,
 556   V2SADAS_RRR_0_OPCODE_X0 = 139,
 557   V2SADAU_RRR_0_OPCODE_X0 = 140,
 558   V2SADS_RRR_0_OPCODE_X0 = 141,
 559   V2SADU_RRR_0_OPCODE_X0 = 142,
 560   V2SHLI_SHIFT_OPCODE_X0 = 10,
 561   V2SHLI_SHIFT_OPCODE_X1 = 10,
 562   V2SHLSC_RRR_0_OPCODE_X0 = 143,
 563   V2SHLSC_RRR_0_OPCODE_X1 = 90,
 564   V2SHL_RRR_0_OPCODE_X0 = 144,
 565   V2SHL_RRR_0_OPCODE_X1 = 91,
 566   V2SHRSI_SHIFT_OPCODE_X0 = 11,
 567   V2SHRSI_SHIFT_OPCODE_X1 = 11,
 568   V2SHRS_RRR_0_OPCODE_X0 = 145,
 569   V2SHRS_RRR_0_OPCODE_X1 = 92,
 570   V2SHRUI_SHIFT_OPCODE_X0 = 12,
 571   V2SHRUI_SHIFT_OPCODE_X1 = 12,
 572   V2SHRU_RRR_0_OPCODE_X0 = 146,
 573   V2SHRU_RRR_0_OPCODE_X1 = 93,
 574   V2SUBSC_RRR_0_OPCODE_X0 = 147,
 575   V2SUBSC_RRR_0_OPCODE_X1 = 94,
 576   V2SUB_RRR_0_OPCODE_X0 = 148,
 577   V2SUB_RRR_0_OPCODE_X1 = 95,
 578   V4ADDSC_RRR_0_OPCODE_X0 = 149,
 579   V4ADDSC_RRR_0_OPCODE_X1 = 96,
 580   V4ADD_RRR_0_OPCODE_X0 = 150,
 581   V4ADD_RRR_0_OPCODE_X1 = 97,
 582   V4INT_H_RRR_0_OPCODE_X0 = 151,
 583   V4INT_H_RRR_0_OPCODE_X1 = 98,
 584   V4INT_L_RRR_0_OPCODE_X0 = 152,
 585   V4INT_L_RRR_0_OPCODE_X1 = 99,
 586   V4PACKSC_RRR_0_OPCODE_X0 = 153,
 587   V4PACKSC_RRR_0_OPCODE_X1 = 100,
 588   V4SHLSC_RRR_0_OPCODE_X0 = 154,
 589   V4SHLSC_RRR_0_OPCODE_X1 = 101,
 590   V4SHL_RRR_0_OPCODE_X0 = 155,
 591   V4SHL_RRR_0_OPCODE_X1 = 102,
 592   V4SHRS_RRR_0_OPCODE_X0 = 156,
 593   V4SHRS_RRR_0_OPCODE_X1 = 103,
 594   V4SHRU_RRR_0_OPCODE_X0 = 157,
 595   V4SHRU_RRR_0_OPCODE_X1 = 104,
 596   V4SUBSC_RRR_0_OPCODE_X0 = 158,
 597   V4SUBSC_RRR_0_OPCODE_X1 = 105,
 598   V4SUB_RRR_0_OPCODE_X0 = 159,
 599   V4SUB_RRR_0_OPCODE_X1 = 106,
 600   WH64_UNARY_OPCODE_X1 = 38,
 601   XORI_IMM8_OPCODE_X0 = 20,
 602   XORI_IMM8_OPCODE_X1 = 45,
 603   XOR_RRR_0_OPCODE_X0 = 160,
 604   XOR_RRR_0_OPCODE_X1 = 107,
 605   XOR_RRR_5_OPCODE_Y0 = 3,
 606   XOR_RRR_5_OPCODE_Y1 = 3
 607 };
 608
 609 #endif /* !_TILE_OPCODE_CONSTANTS_H */