2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
14 * This code maintains the "home" for each page in the system.
17 #include <linux/kernel.h>
19 #include <linux/spinlock.h>
20 #include <linux/list.h>
21 #include <linux/bootmem.h>
22 #include <linux/rmap.h>
23 #include <linux/pagemap.h>
24 #include <linux/mutex.h>
25 #include <linux/interrupt.h>
26 #include <linux/sysctl.h>
27 #include <linux/pagevec.h>
28 #include <linux/ptrace.h>
29 #include <linux/timex.h>
30 #include <linux/cache.h>
31 #include <linux/smp.h>
32 #include <linux/module.h>
35 #include <asm/sections.h>
36 #include <asm/tlbflush.h>
37 #include <asm/pgalloc.h>
38 #include <asm/homecache.h>
45 #if CHIP_HAS_COHERENT_LOCAL_CACHE()
48 * The noallocl2 option suppresses all use of the L2 cache to cache
49 * locally from a remote home. There's no point in using it if we
50 * don't have coherent local caching, though.
52 static int __write_once noallocl2
;
53 static int __init
set_noallocl2(char *str
)
58 early_param("noallocl2", set_noallocl2
);
66 /* Provide no-op versions of these routines to keep flush_remote() cleaner. */
67 #define mark_caches_evicted_start() 0
68 #define mark_caches_evicted_finish(mask, timestamp) do {} while (0)
72 * Update the irq_stat for cpus that we are going to interrupt
73 * with TLB or cache flushes. Also handle removing dataplane cpus
74 * from the TLB flush set, and setting dataplane_tlb_state instead.
76 static void hv_flush_update(const struct cpumask
*cache_cpumask
,
77 struct cpumask
*tlb_cpumask
,
78 unsigned long tlb_va
, unsigned long tlb_length
,
79 HV_Remote_ASID
*asids
, int asidcount
)
86 cpumask_or(&mask
, &mask
, cache_cpumask
);
87 if (tlb_cpumask
&& tlb_length
) {
88 cpumask_or(&mask
, &mask
, tlb_cpumask
);
91 for (i
= 0; i
< asidcount
; ++i
)
92 cpumask_set_cpu(asids
[i
].y
* smp_width
+ asids
[i
].x
, &mask
);
95 * Don't bother to update atomically; losing a count
96 * here is not that critical.
98 for_each_cpu(cpu
, &mask
)
99 ++per_cpu(irq_stat
, cpu
).irq_hv_flush_count
;
103 * This wrapper function around hv_flush_remote() does several things:
105 * - Provides a return value error-checking panic path, since
106 * there's never any good reason for hv_flush_remote() to fail.
107 * - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
108 * is the type that Linux wants to pass around anyway.
109 * - Centralizes the mark_caches_evicted() handling.
110 * - Canonicalizes that lengths of zero make cpumasks NULL.
111 * - Handles deferring TLB flushes for dataplane tiles.
112 * - Tracks remote interrupts in the per-cpu irq_cpustat_t.
114 * Note that we have to wait until the cache flush completes before
115 * updating the per-cpu last_cache_flush word, since otherwise another
116 * concurrent flush can race, conclude the flush has already
117 * completed, and start to use the page while it's still dirty
118 * remotely (running concurrently with the actual evict, presumably).
120 void flush_remote(unsigned long cache_pfn
, unsigned long cache_control
,
121 const struct cpumask
*cache_cpumask_orig
,
122 HV_VirtAddr tlb_va
, unsigned long tlb_length
,
123 unsigned long tlb_pgsize
,
124 const struct cpumask
*tlb_cpumask_orig
,
125 HV_Remote_ASID
*asids
, int asidcount
)
128 int timestamp
= 0; /* happy compiler */
129 struct cpumask cache_cpumask_copy
, tlb_cpumask_copy
;
130 struct cpumask
*cache_cpumask
, *tlb_cpumask
;
131 HV_PhysAddr cache_pa
;
132 char cache_buf
[NR_CPUS
*5], tlb_buf
[NR_CPUS
*5];
134 mb(); /* provided just to simplify "magic hypervisor" mode */
137 * Canonicalize and copy the cpumasks.
139 if (cache_cpumask_orig
&& cache_control
) {
140 cpumask_copy(&cache_cpumask_copy
, cache_cpumask_orig
);
141 cache_cpumask
= &cache_cpumask_copy
;
143 cpumask_clear(&cache_cpumask_copy
);
144 cache_cpumask
= NULL
;
146 if (cache_cpumask
== NULL
)
148 if (tlb_cpumask_orig
&& tlb_length
) {
149 cpumask_copy(&tlb_cpumask_copy
, tlb_cpumask_orig
);
150 tlb_cpumask
= &tlb_cpumask_copy
;
152 cpumask_clear(&tlb_cpumask_copy
);
156 hv_flush_update(cache_cpumask
, tlb_cpumask
, tlb_va
, tlb_length
,
158 cache_pa
= (HV_PhysAddr
)cache_pfn
<< PAGE_SHIFT
;
159 if (cache_control
& HV_FLUSH_EVICT_L2
)
160 timestamp
= mark_caches_evicted_start();
161 rc
= hv_flush_remote(cache_pa
, cache_control
,
162 cpumask_bits(cache_cpumask
),
163 tlb_va
, tlb_length
, tlb_pgsize
,
164 cpumask_bits(tlb_cpumask
),
166 if (cache_control
& HV_FLUSH_EVICT_L2
)
167 mark_caches_evicted_finish(cache_cpumask
, timestamp
);
170 cpumask_scnprintf(cache_buf
, sizeof(cache_buf
), &cache_cpumask_copy
);
171 cpumask_scnprintf(tlb_buf
, sizeof(tlb_buf
), &tlb_cpumask_copy
);
173 pr_err("hv_flush_remote(%#llx, %#lx, %p [%s],"
174 " %#lx, %#lx, %#lx, %p [%s], %p, %d) = %d\n",
175 cache_pa
, cache_control
, cache_cpumask
, cache_buf
,
176 (unsigned long)tlb_va
, tlb_length
, tlb_pgsize
,
177 tlb_cpumask
, tlb_buf
,
178 asids
, asidcount
, rc
);
179 panic("Unsafe to continue.");
182 void flush_remote_page(struct page
*page
, int order
)
184 int i
, pages
= (1 << order
);
185 for (i
= 0; i
< pages
; ++i
, ++page
) {
186 void *p
= kmap_atomic(page
);
188 int home
= page_home(page
);
189 #if CHIP_HAS_CBOX_HOME_MAP()
190 if (home
== PAGE_HOME_HASH
)
194 BUG_ON(home
< 0 || home
>= NR_CPUS
);
195 finv_buffer_remote(p
, PAGE_SIZE
, hfh
);
200 void homecache_evict(const struct cpumask
*mask
)
202 flush_remote(0, HV_FLUSH_EVICT_L2
, mask
, 0, 0, 0, NULL
, NULL
, 0);
206 * Return a mask of the cpus whose caches currently own these pages.
207 * The return value is whether the pages are all coherently cached
208 * (i.e. none are immutable, incoherent, or uncached).
210 static int homecache_mask(struct page
*page
, int pages
,
211 struct cpumask
*home_mask
)
214 int cached_coherently
= 1;
215 cpumask_clear(home_mask
);
216 for (i
= 0; i
< pages
; ++i
) {
217 int home
= page_home(&page
[i
]);
218 if (home
== PAGE_HOME_IMMUTABLE
||
219 home
== PAGE_HOME_INCOHERENT
) {
220 cpumask_copy(home_mask
, cpu_possible_mask
);
223 #if CHIP_HAS_CBOX_HOME_MAP()
224 if (home
== PAGE_HOME_HASH
) {
225 cpumask_or(home_mask
, home_mask
, &hash_for_home_map
);
229 if (home
== PAGE_HOME_UNCACHED
) {
230 cached_coherently
= 0;
233 BUG_ON(home
< 0 || home
>= NR_CPUS
);
234 cpumask_set_cpu(home
, home_mask
);
236 return cached_coherently
;
240 * Return the passed length, or zero if it's long enough that we
241 * believe we should evict the whole L2 cache.
243 static unsigned long cache_flush_length(unsigned long length
)
245 return (length
>= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2
: length
;
248 /* Flush a page out of whatever cache(s) it is in. */
249 void homecache_flush_cache(struct page
*page
, int order
)
251 int pages
= 1 << order
;
252 int length
= cache_flush_length(pages
* PAGE_SIZE
);
253 unsigned long pfn
= page_to_pfn(page
);
254 struct cpumask home_mask
;
256 homecache_mask(page
, pages
, &home_mask
);
257 flush_remote(pfn
, length
, &home_mask
, 0, 0, 0, NULL
, NULL
, 0);
258 sim_validate_lines_evicted(PFN_PHYS(pfn
), pages
* PAGE_SIZE
);
262 /* Report the home corresponding to a given PTE. */
263 static int pte_to_home(pte_t pte
)
265 if (hv_pte_get_nc(pte
))
266 return PAGE_HOME_IMMUTABLE
;
267 switch (hv_pte_get_mode(pte
)) {
268 case HV_PTE_MODE_CACHE_TILE_L3
:
269 return get_remote_cache_cpu(pte
);
270 case HV_PTE_MODE_CACHE_NO_L3
:
271 return PAGE_HOME_INCOHERENT
;
272 case HV_PTE_MODE_UNCACHED
:
273 return PAGE_HOME_UNCACHED
;
274 #if CHIP_HAS_CBOX_HOME_MAP()
275 case HV_PTE_MODE_CACHE_HASH_L3
:
276 return PAGE_HOME_HASH
;
279 panic("Bad PTE %#llx\n", pte
.val
);
282 /* Update the home of a PTE if necessary (can also be used for a pgprot_t). */
283 pte_t
pte_set_home(pte_t pte
, int home
)
285 /* Check for non-linear file mapping "PTEs" and pass them through. */
290 /* Check for MMIO mappings and pass them through. */
291 if (hv_pte_get_mode(pte
) == HV_PTE_MODE_MMIO
)
297 * Only immutable pages get NC mappings. If we have a
298 * non-coherent PTE, but the underlying page is not
299 * immutable, it's likely the result of a forced
300 * caching setting running up against ptrace setting
301 * the page to be writable underneath. In this case,
302 * just keep the PTE coherent.
304 if (hv_pte_get_nc(pte
) && home
!= PAGE_HOME_IMMUTABLE
) {
305 pte
= hv_pte_clear_nc(pte
);
306 pr_err("non-immutable page incoherently referenced: %#llx\n",
312 case PAGE_HOME_UNCACHED
:
313 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_UNCACHED
);
316 case PAGE_HOME_INCOHERENT
:
317 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_CACHE_NO_L3
);
320 case PAGE_HOME_IMMUTABLE
:
322 * We could home this page anywhere, since it's immutable,
323 * but by default just home it to follow "hash_default".
325 BUG_ON(hv_pte_get_writable(pte
));
326 if (pte_get_forcecache(pte
)) {
327 /* Upgrade "force any cpu" to "No L3" for immutable. */
328 if (hv_pte_get_mode(pte
) == HV_PTE_MODE_CACHE_TILE_L3
329 && pte_get_anyhome(pte
)) {
330 pte
= hv_pte_set_mode(pte
,
331 HV_PTE_MODE_CACHE_NO_L3
);
334 #if CHIP_HAS_CBOX_HOME_MAP()
336 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_CACHE_HASH_L3
);
339 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_CACHE_NO_L3
);
340 pte
= hv_pte_set_nc(pte
);
343 #if CHIP_HAS_CBOX_HOME_MAP()
345 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_CACHE_HASH_L3
);
350 BUG_ON(home
< 0 || home
>= NR_CPUS
||
351 !cpu_is_valid_lotar(home
));
352 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_CACHE_TILE_L3
);
353 pte
= set_remote_cache_cpu(pte
, home
);
357 #if CHIP_HAS_NC_AND_NOALLOC_BITS()
359 pte
= hv_pte_set_no_alloc_l2(pte
);
361 /* Simplify "no local and no l3" to "uncached" */
362 if (hv_pte_get_no_alloc_l2(pte
) && hv_pte_get_no_alloc_l1(pte
) &&
363 hv_pte_get_mode(pte
) == HV_PTE_MODE_CACHE_NO_L3
) {
364 pte
= hv_pte_set_mode(pte
, HV_PTE_MODE_UNCACHED
);
368 /* Checking this case here gives a better panic than from the hv. */
369 BUG_ON(hv_pte_get_mode(pte
) == 0);
373 EXPORT_SYMBOL(pte_set_home
);
376 * The routines in this section are the "static" versions of the normal
377 * dynamic homecaching routines; they just set the home cache
378 * of a kernel page once, and require a full-chip cache/TLB flush,
379 * so they're not suitable for anything but infrequent use.
382 #if CHIP_HAS_CBOX_HOME_MAP()
383 static inline int initial_page_home(void) { return PAGE_HOME_HASH
; }
385 static inline int initial_page_home(void) { return 0; }
388 int page_home(struct page
*page
)
390 if (PageHighMem(page
)) {
391 return initial_page_home();
393 unsigned long kva
= (unsigned long)page_address(page
);
394 return pte_to_home(*virt_to_pte(NULL
, kva
));
398 void homecache_change_page_home(struct page
*page
, int order
, int home
)
400 int i
, pages
= (1 << order
);
403 BUG_ON(PageHighMem(page
));
404 BUG_ON(page_count(page
) > 1);
405 BUG_ON(page_mapcount(page
) != 0);
406 kva
= (unsigned long) page_address(page
);
407 flush_remote(0, HV_FLUSH_EVICT_L2
, &cpu_cacheable_map
,
408 kva
, pages
* PAGE_SIZE
, PAGE_SIZE
, cpu_online_mask
,
411 for (i
= 0; i
< pages
; ++i
, kva
+= PAGE_SIZE
) {
412 pte_t
*ptep
= virt_to_pte(NULL
, kva
);
413 pte_t pteval
= *ptep
;
414 BUG_ON(!pte_present(pteval
) || pte_huge(pteval
));
415 __set_pte(ptep
, pte_set_home(pteval
, home
));
419 struct page
*homecache_alloc_pages(gfp_t gfp_mask
,
420 unsigned int order
, int home
)
423 BUG_ON(gfp_mask
& __GFP_HIGHMEM
); /* must be lowmem */
424 page
= alloc_pages(gfp_mask
, order
);
426 homecache_change_page_home(page
, order
, home
);
429 EXPORT_SYMBOL(homecache_alloc_pages
);
431 struct page
*homecache_alloc_pages_node(int nid
, gfp_t gfp_mask
,
432 unsigned int order
, int home
)
435 BUG_ON(gfp_mask
& __GFP_HIGHMEM
); /* must be lowmem */
436 page
= alloc_pages_node(nid
, gfp_mask
, order
);
438 homecache_change_page_home(page
, order
, home
);
442 void homecache_free_pages(unsigned long addr
, unsigned int order
)
449 VM_BUG_ON(!virt_addr_valid((void *)addr
));
450 page
= virt_to_page((void *)addr
);
451 if (put_page_testzero(page
)) {
452 int pages
= (1 << order
);
453 homecache_change_page_home(page
, order
, initial_page_home());