2 * intel_mid_dma.c - Intel Langwell DMA Drivers
4 * Copyright (C) 2008-10 Intel Corp
5 * Author: Vinod Koul <vinod.koul@intel.com>
6 * The driver design is based on dw_dmac driver
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
26 #include <linux/pci.h>
27 #include <linux/interrupt.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/intel_mid_dma.h>
30 #include <linux/module.h>
32 #define MAX_CHAN 4 /*max ch across controllers*/
33 #include "intel_mid_dma_regs.h"
35 #define INTEL_MID_DMAC1_ID 0x0814
36 #define INTEL_MID_DMAC2_ID 0x0813
37 #define INTEL_MID_GP_DMAC2_ID 0x0827
38 #define INTEL_MFLD_DMAC1_ID 0x0830
39 #define LNW_PERIPHRAL_MASK_BASE 0xFFAE8008
40 #define LNW_PERIPHRAL_MASK_SIZE 0x10
41 #define LNW_PERIPHRAL_STATUS 0x0
42 #define LNW_PERIPHRAL_MASK 0x8
44 struct intel_mid_dma_probe_info
{
51 #define INFO(_max_chan, _ch_base, _block_size, _pimr_mask) \
52 ((kernel_ulong_t)&(struct intel_mid_dma_probe_info) { \
53 .max_chan = (_max_chan), \
54 .ch_base = (_ch_base), \
55 .block_size = (_block_size), \
56 .pimr_mask = (_pimr_mask), \
59 /*****************************************************************************
62 * get_ch_index - convert status to channel
63 * @status: status mask
64 * @base: dma ch base value
66 * Modify the status mask and return the channel index needing
67 * attention (or -1 if neither)
69 static int get_ch_index(int *status
, unsigned int base
)
72 for (i
= 0; i
< MAX_CHAN
; i
++) {
73 if (*status
& (1 << (i
+ base
))) {
74 *status
= *status
& ~(1 << (i
+ base
));
75 pr_debug("MDMA: index %d New status %x\n", i
, *status
);
83 * get_block_ts - calculates dma transaction length
84 * @len: dma transfer length
85 * @tx_width: dma transfer src width
86 * @block_size: dma controller max block size
88 * Based on src width calculate the DMA trsaction length in data items
89 * return data items or FFFF if exceeds max length for block
91 static int get_block_ts(int len
, int tx_width
, int block_size
)
93 int byte_width
= 0, block_ts
= 0;
96 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
99 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
102 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
108 block_ts
= len
/byte_width
;
109 if (block_ts
> block_size
)
114 /*****************************************************************************
115 DMAC1 interrupt Functions*/
118 * dmac1_mask_periphral_intr - mask the periphral interrupt
119 * @midc: dma channel for which masking is required
121 * Masks the DMA periphral interrupt
122 * this is valid for DMAC1 family controllers only
123 * This controller should have periphral mask registers already mapped
125 static void dmac1_mask_periphral_intr(struct intel_mid_dma_chan
*midc
)
128 struct middma_device
*mid
= to_middma_device(midc
->chan
.device
);
130 if (mid
->pimr_mask
) {
131 pimr
= readl(mid
->mask_reg
+ LNW_PERIPHRAL_MASK
);
132 pimr
|= mid
->pimr_mask
;
133 writel(pimr
, mid
->mask_reg
+ LNW_PERIPHRAL_MASK
);
139 * dmac1_unmask_periphral_intr - unmask the periphral interrupt
140 * @midc: dma channel for which masking is required
142 * UnMasks the DMA periphral interrupt,
143 * this is valid for DMAC1 family controllers only
144 * This controller should have periphral mask registers already mapped
146 static void dmac1_unmask_periphral_intr(struct intel_mid_dma_chan
*midc
)
149 struct middma_device
*mid
= to_middma_device(midc
->chan
.device
);
151 if (mid
->pimr_mask
) {
152 pimr
= readl(mid
->mask_reg
+ LNW_PERIPHRAL_MASK
);
153 pimr
&= ~mid
->pimr_mask
;
154 writel(pimr
, mid
->mask_reg
+ LNW_PERIPHRAL_MASK
);
160 * enable_dma_interrupt - enable the periphral interrupt
161 * @midc: dma channel for which enable interrupt is required
163 * Enable the DMA periphral interrupt,
164 * this is valid for DMAC1 family controllers only
165 * This controller should have periphral mask registers already mapped
167 static void enable_dma_interrupt(struct intel_mid_dma_chan
*midc
)
169 dmac1_unmask_periphral_intr(midc
);
172 iowrite32(UNMASK_INTR_REG(midc
->ch_id
), midc
->dma_base
+ MASK_TFR
);
173 iowrite32(UNMASK_INTR_REG(midc
->ch_id
), midc
->dma_base
+ MASK_ERR
);
178 * disable_dma_interrupt - disable the periphral interrupt
179 * @midc: dma channel for which disable interrupt is required
181 * Disable the DMA periphral interrupt,
182 * this is valid for DMAC1 family controllers only
183 * This controller should have periphral mask registers already mapped
185 static void disable_dma_interrupt(struct intel_mid_dma_chan
*midc
)
187 /*Check LPE PISR, make sure fwd is disabled*/
188 dmac1_mask_periphral_intr(midc
);
189 iowrite32(MASK_INTR_REG(midc
->ch_id
), midc
->dma_base
+ MASK_BLOCK
);
190 iowrite32(MASK_INTR_REG(midc
->ch_id
), midc
->dma_base
+ MASK_TFR
);
191 iowrite32(MASK_INTR_REG(midc
->ch_id
), midc
->dma_base
+ MASK_ERR
);
195 /*****************************************************************************
196 DMA channel helper Functions*/
198 * mid_desc_get - get a descriptor
199 * @midc: dma channel for which descriptor is required
201 * Obtain a descriptor for the channel. Returns NULL if none are free.
202 * Once the descriptor is returned it is private until put on another
205 static struct intel_mid_dma_desc
*midc_desc_get(struct intel_mid_dma_chan
*midc
)
207 struct intel_mid_dma_desc
*desc
, *_desc
;
208 struct intel_mid_dma_desc
*ret
= NULL
;
210 spin_lock_bh(&midc
->lock
);
211 list_for_each_entry_safe(desc
, _desc
, &midc
->free_list
, desc_node
) {
212 if (async_tx_test_ack(&desc
->txd
)) {
213 list_del(&desc
->desc_node
);
218 spin_unlock_bh(&midc
->lock
);
223 * mid_desc_put - put a descriptor
224 * @midc: dma channel for which descriptor is required
225 * @desc: descriptor to put
227 * Return a descriptor from lwn_desc_get back to the free pool
229 static void midc_desc_put(struct intel_mid_dma_chan
*midc
,
230 struct intel_mid_dma_desc
*desc
)
233 spin_lock_bh(&midc
->lock
);
234 list_add_tail(&desc
->desc_node
, &midc
->free_list
);
235 spin_unlock_bh(&midc
->lock
);
239 * midc_dostart - begin a DMA transaction
240 * @midc: channel for which txn is to be started
241 * @first: first descriptor of series
243 * Load a transaction into the engine. This must be called with midc->lock
244 * held and bh disabled.
246 static void midc_dostart(struct intel_mid_dma_chan
*midc
,
247 struct intel_mid_dma_desc
*first
)
249 struct middma_device
*mid
= to_middma_device(midc
->chan
.device
);
251 /* channel is idle */
252 if (midc
->busy
&& test_ch_en(midc
->dma_base
, midc
->ch_id
)) {
254 pr_err("ERR_MDMA: channel is busy in start\n");
255 /* The tasklet will hopefully advance the queue... */
259 /*write registers and en*/
260 iowrite32(first
->sar
, midc
->ch_regs
+ SAR
);
261 iowrite32(first
->dar
, midc
->ch_regs
+ DAR
);
262 iowrite32(first
->lli_phys
, midc
->ch_regs
+ LLP
);
263 iowrite32(first
->cfg_hi
, midc
->ch_regs
+ CFG_HIGH
);
264 iowrite32(first
->cfg_lo
, midc
->ch_regs
+ CFG_LOW
);
265 iowrite32(first
->ctl_lo
, midc
->ch_regs
+ CTL_LOW
);
266 iowrite32(first
->ctl_hi
, midc
->ch_regs
+ CTL_HIGH
);
267 pr_debug("MDMA:TX SAR %x,DAR %x,CFGL %x,CFGH %x,CTLH %x, CTLL %x\n",
268 (int)first
->sar
, (int)first
->dar
, first
->cfg_hi
,
269 first
->cfg_lo
, first
->ctl_hi
, first
->ctl_lo
);
270 first
->status
= DMA_IN_PROGRESS
;
272 iowrite32(ENABLE_CHANNEL(midc
->ch_id
), mid
->dma_base
+ DMA_CHAN_EN
);
276 * midc_descriptor_complete - process completed descriptor
277 * @midc: channel owning the descriptor
278 * @desc: the descriptor itself
280 * Process a completed descriptor and perform any callbacks upon
281 * the completion. The completion handling drops the lock during the
282 * callbacks but must be called with the lock held.
284 static void midc_descriptor_complete(struct intel_mid_dma_chan
*midc
,
285 struct intel_mid_dma_desc
*desc
)
287 struct dma_async_tx_descriptor
*txd
= &desc
->txd
;
288 dma_async_tx_callback callback_txd
= NULL
;
289 struct intel_mid_dma_lli
*llitem
;
290 void *param_txd
= NULL
;
292 midc
->completed
= txd
->cookie
;
293 callback_txd
= txd
->callback
;
294 param_txd
= txd
->callback_param
;
296 if (desc
->lli
!= NULL
) {
297 /*clear the DONE bit of completed LLI in memory*/
298 llitem
= desc
->lli
+ desc
->current_lli
;
299 llitem
->ctl_hi
&= CLEAR_DONE
;
300 if (desc
->current_lli
< desc
->lli_length
-1)
301 (desc
->current_lli
)++;
303 desc
->current_lli
= 0;
305 spin_unlock_bh(&midc
->lock
);
307 pr_debug("MDMA: TXD callback set ... calling\n");
308 callback_txd(param_txd
);
311 desc
->status
= DMA_SUCCESS
;
312 if (desc
->lli
!= NULL
) {
313 pci_pool_free(desc
->lli_pool
, desc
->lli
,
315 pci_pool_destroy(desc
->lli_pool
);
317 list_move(&desc
->desc_node
, &midc
->free_list
);
320 spin_lock_bh(&midc
->lock
);
324 * midc_scan_descriptors - check the descriptors in channel
325 * mark completed when tx is completete
327 * @midc: channel to scan
329 * Walk the descriptor chain for the device and process any entries
332 static void midc_scan_descriptors(struct middma_device
*mid
,
333 struct intel_mid_dma_chan
*midc
)
335 struct intel_mid_dma_desc
*desc
= NULL
, *_desc
= NULL
;
338 list_for_each_entry_safe(desc
, _desc
, &midc
->active_list
, desc_node
) {
339 if (desc
->status
== DMA_IN_PROGRESS
)
340 midc_descriptor_complete(midc
, desc
);
345 * midc_lli_fill_sg - Helper function to convert
346 * SG list to Linked List Items.
348 *@desc: DMA descriptor
349 *@sglist: Pointer to SG list
350 *@sglen: SG list length
351 *@flags: DMA transaction flags
353 * Walk through the SG list and convert the SG list into Linked
356 static int midc_lli_fill_sg(struct intel_mid_dma_chan
*midc
,
357 struct intel_mid_dma_desc
*desc
,
358 struct scatterlist
*sglist
,
362 struct intel_mid_dma_slave
*mids
;
363 struct scatterlist
*sg
;
364 dma_addr_t lli_next
, sg_phy_addr
;
365 struct intel_mid_dma_lli
*lli_bloc_desc
;
366 union intel_mid_dma_ctl_lo ctl_lo
;
367 union intel_mid_dma_ctl_hi ctl_hi
;
370 pr_debug("MDMA: Entered midc_lli_fill_sg\n");
371 mids
= midc
->mid_slave
;
373 lli_bloc_desc
= desc
->lli
;
374 lli_next
= desc
->lli_phys
;
376 ctl_lo
.ctl_lo
= desc
->ctl_lo
;
377 ctl_hi
.ctl_hi
= desc
->ctl_hi
;
378 for_each_sg(sglist
, sg
, sglen
, i
) {
379 /*Populate CTL_LOW and LLI values*/
380 if (i
!= sglen
- 1) {
381 lli_next
= lli_next
+
382 sizeof(struct intel_mid_dma_lli
);
384 /*Check for circular list, otherwise terminate LLI to ZERO*/
385 if (flags
& DMA_PREP_CIRCULAR_LIST
) {
386 pr_debug("MDMA: LLI is configured in circular mode\n");
387 lli_next
= desc
->lli_phys
;
390 ctl_lo
.ctlx
.llp_dst_en
= 0;
391 ctl_lo
.ctlx
.llp_src_en
= 0;
394 /*Populate CTL_HI values*/
395 ctl_hi
.ctlx
.block_ts
= get_block_ts(sg
->length
,
397 midc
->dma
->block_size
);
398 /*Populate SAR and DAR values*/
399 sg_phy_addr
= sg_phys(sg
);
400 if (desc
->dirn
== DMA_TO_DEVICE
) {
401 lli_bloc_desc
->sar
= sg_phy_addr
;
402 lli_bloc_desc
->dar
= mids
->dma_slave
.dst_addr
;
403 } else if (desc
->dirn
== DMA_FROM_DEVICE
) {
404 lli_bloc_desc
->sar
= mids
->dma_slave
.src_addr
;
405 lli_bloc_desc
->dar
= sg_phy_addr
;
407 /*Copy values into block descriptor in system memroy*/
408 lli_bloc_desc
->llp
= lli_next
;
409 lli_bloc_desc
->ctl_lo
= ctl_lo
.ctl_lo
;
410 lli_bloc_desc
->ctl_hi
= ctl_hi
.ctl_hi
;
414 /*Copy very first LLI values to descriptor*/
415 desc
->ctl_lo
= desc
->lli
->ctl_lo
;
416 desc
->ctl_hi
= desc
->lli
->ctl_hi
;
417 desc
->sar
= desc
->lli
->sar
;
418 desc
->dar
= desc
->lli
->dar
;
422 /*****************************************************************************
423 DMA engine callback Functions*/
425 * intel_mid_dma_tx_submit - callback to submit DMA transaction
426 * @tx: dma engine descriptor
428 * Submit the DMA trasaction for this descriptor, start if ch idle
430 static dma_cookie_t
intel_mid_dma_tx_submit(struct dma_async_tx_descriptor
*tx
)
432 struct intel_mid_dma_desc
*desc
= to_intel_mid_dma_desc(tx
);
433 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(tx
->chan
);
436 spin_lock_bh(&midc
->lock
);
437 cookie
= midc
->chan
.cookie
;
442 midc
->chan
.cookie
= cookie
;
443 desc
->txd
.cookie
= cookie
;
446 if (list_empty(&midc
->active_list
))
447 list_add_tail(&desc
->desc_node
, &midc
->active_list
);
449 list_add_tail(&desc
->desc_node
, &midc
->queue
);
451 midc_dostart(midc
, desc
);
452 spin_unlock_bh(&midc
->lock
);
458 * intel_mid_dma_issue_pending - callback to issue pending txn
459 * @chan: chan where pending trascation needs to be checked and submitted
461 * Call for scan to issue pending descriptors
463 static void intel_mid_dma_issue_pending(struct dma_chan
*chan
)
465 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(chan
);
467 spin_lock_bh(&midc
->lock
);
468 if (!list_empty(&midc
->queue
))
469 midc_scan_descriptors(to_middma_device(chan
->device
), midc
);
470 spin_unlock_bh(&midc
->lock
);
474 * intel_mid_dma_tx_status - Return status of txn
475 * @chan: chan for where status needs to be checked
476 * @cookie: cookie for txn
477 * @txstate: DMA txn state
479 * Return status of DMA txn
481 static enum dma_status
intel_mid_dma_tx_status(struct dma_chan
*chan
,
483 struct dma_tx_state
*txstate
)
485 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(chan
);
486 dma_cookie_t last_used
;
487 dma_cookie_t last_complete
;
490 last_complete
= midc
->completed
;
491 last_used
= chan
->cookie
;
493 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
494 if (ret
!= DMA_SUCCESS
) {
495 midc_scan_descriptors(to_middma_device(chan
->device
), midc
);
497 last_complete
= midc
->completed
;
498 last_used
= chan
->cookie
;
500 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
504 txstate
->last
= last_complete
;
505 txstate
->used
= last_used
;
506 txstate
->residue
= 0;
511 static int dma_slave_control(struct dma_chan
*chan
, unsigned long arg
)
513 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(chan
);
514 struct dma_slave_config
*slave
= (struct dma_slave_config
*)arg
;
515 struct intel_mid_dma_slave
*mid_slave
;
519 pr_debug("MDMA: slave control called\n");
521 mid_slave
= to_intel_mid_dma_slave(slave
);
525 midc
->mid_slave
= mid_slave
;
529 * intel_mid_dma_device_control - DMA device control
530 * @chan: chan for DMA control
532 * @arg: cmd arg value
534 * Perform DMA control command
536 static int intel_mid_dma_device_control(struct dma_chan
*chan
,
537 enum dma_ctrl_cmd cmd
, unsigned long arg
)
539 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(chan
);
540 struct middma_device
*mid
= to_middma_device(chan
->device
);
541 struct intel_mid_dma_desc
*desc
, *_desc
;
542 union intel_mid_dma_cfg_lo cfg_lo
;
544 if (cmd
== DMA_SLAVE_CONFIG
)
545 return dma_slave_control(chan
, arg
);
547 if (cmd
!= DMA_TERMINATE_ALL
)
550 spin_lock_bh(&midc
->lock
);
551 if (midc
->busy
== false) {
552 spin_unlock_bh(&midc
->lock
);
555 /*Suspend and disable the channel*/
556 cfg_lo
.cfg_lo
= ioread32(midc
->ch_regs
+ CFG_LOW
);
557 cfg_lo
.cfgx
.ch_susp
= 1;
558 iowrite32(cfg_lo
.cfg_lo
, midc
->ch_regs
+ CFG_LOW
);
559 iowrite32(DISABLE_CHANNEL(midc
->ch_id
), mid
->dma_base
+ DMA_CHAN_EN
);
561 /* Disable interrupts */
562 disable_dma_interrupt(midc
);
563 midc
->descs_allocated
= 0;
565 spin_unlock_bh(&midc
->lock
);
566 list_for_each_entry_safe(desc
, _desc
, &midc
->active_list
, desc_node
) {
567 if (desc
->lli
!= NULL
) {
568 pci_pool_free(desc
->lli_pool
, desc
->lli
,
570 pci_pool_destroy(desc
->lli_pool
);
572 list_move(&desc
->desc_node
, &midc
->free_list
);
579 * intel_mid_dma_prep_memcpy - Prep memcpy txn
580 * @chan: chan for DMA transfer
581 * @dest: destn address
583 * @len: DMA transfer len
586 * Perform a DMA memcpy. Note we support slave periphral DMA transfers only
587 * The periphral txn details should be filled in slave structure properly
588 * Returns the descriptor for this txn
590 static struct dma_async_tx_descriptor
*intel_mid_dma_prep_memcpy(
591 struct dma_chan
*chan
, dma_addr_t dest
,
592 dma_addr_t src
, size_t len
, unsigned long flags
)
594 struct intel_mid_dma_chan
*midc
;
595 struct intel_mid_dma_desc
*desc
= NULL
;
596 struct intel_mid_dma_slave
*mids
;
597 union intel_mid_dma_ctl_lo ctl_lo
;
598 union intel_mid_dma_ctl_hi ctl_hi
;
599 union intel_mid_dma_cfg_lo cfg_lo
;
600 union intel_mid_dma_cfg_hi cfg_hi
;
601 enum dma_slave_buswidth width
;
603 pr_debug("MDMA: Prep for memcpy\n");
608 midc
= to_intel_mid_dma_chan(chan
);
611 mids
= midc
->mid_slave
;
614 pr_debug("MDMA:called for DMA %x CH %d Length %zu\n",
615 midc
->dma
->pci_id
, midc
->ch_id
, len
);
616 pr_debug("MDMA:Cfg passed Mode %x, Dirn %x, HS %x, Width %x\n",
617 mids
->cfg_mode
, mids
->dma_slave
.direction
,
618 mids
->hs_mode
, mids
->dma_slave
.src_addr_width
);
621 if (mids
->hs_mode
== LNW_DMA_SW_HS
) {
623 cfg_lo
.cfgx
.hs_sel_dst
= 1;
624 cfg_lo
.cfgx
.hs_sel_src
= 1;
625 } else if (mids
->hs_mode
== LNW_DMA_HW_HS
)
626 cfg_lo
.cfg_lo
= 0x00000;
629 if (mids
->cfg_mode
== LNW_DMA_MEM_TO_MEM
) {
634 if (midc
->dma
->pimr_mask
) {
635 cfg_hi
.cfgx
.protctl
= 0x0; /*default value*/
636 cfg_hi
.cfgx
.fifo_mode
= 1;
637 if (mids
->dma_slave
.direction
== DMA_TO_DEVICE
) {
638 cfg_hi
.cfgx
.src_per
= 0;
639 if (mids
->device_instance
== 0)
640 cfg_hi
.cfgx
.dst_per
= 3;
641 if (mids
->device_instance
== 1)
642 cfg_hi
.cfgx
.dst_per
= 1;
643 } else if (mids
->dma_slave
.direction
== DMA_FROM_DEVICE
) {
644 if (mids
->device_instance
== 0)
645 cfg_hi
.cfgx
.src_per
= 2;
646 if (mids
->device_instance
== 1)
647 cfg_hi
.cfgx
.src_per
= 0;
648 cfg_hi
.cfgx
.dst_per
= 0;
651 cfg_hi
.cfgx
.protctl
= 0x1; /*default value*/
652 cfg_hi
.cfgx
.src_per
= cfg_hi
.cfgx
.dst_per
=
653 midc
->ch_id
- midc
->dma
->chan_base
;
658 ctl_hi
.ctlx
.reser
= 0;
659 ctl_hi
.ctlx
.done
= 0;
660 width
= mids
->dma_slave
.src_addr_width
;
662 ctl_hi
.ctlx
.block_ts
= get_block_ts(len
, width
, midc
->dma
->block_size
);
663 pr_debug("MDMA:calc len %d for block size %d\n",
664 ctl_hi
.ctlx
.block_ts
, midc
->dma
->block_size
);
667 ctl_lo
.ctlx
.int_en
= 1;
668 ctl_lo
.ctlx
.dst_msize
= mids
->dma_slave
.src_maxburst
;
669 ctl_lo
.ctlx
.src_msize
= mids
->dma_slave
.dst_maxburst
;
672 * Here we need some translation from "enum dma_slave_buswidth"
673 * to the format for our dma controller
674 * standard intel_mid_dmac's format
679 ctl_lo
.ctlx
.dst_tr_width
= mids
->dma_slave
.dst_addr_width
/ 2;
680 ctl_lo
.ctlx
.src_tr_width
= mids
->dma_slave
.src_addr_width
/ 2;
682 if (mids
->cfg_mode
== LNW_DMA_MEM_TO_MEM
) {
683 ctl_lo
.ctlx
.tt_fc
= 0;
684 ctl_lo
.ctlx
.sinc
= 0;
685 ctl_lo
.ctlx
.dinc
= 0;
687 if (mids
->dma_slave
.direction
== DMA_TO_DEVICE
) {
688 ctl_lo
.ctlx
.sinc
= 0;
689 ctl_lo
.ctlx
.dinc
= 2;
690 ctl_lo
.ctlx
.tt_fc
= 1;
691 } else if (mids
->dma_slave
.direction
== DMA_FROM_DEVICE
) {
692 ctl_lo
.ctlx
.sinc
= 2;
693 ctl_lo
.ctlx
.dinc
= 0;
694 ctl_lo
.ctlx
.tt_fc
= 2;
698 pr_debug("MDMA:Calc CTL LO %x, CTL HI %x, CFG LO %x, CFG HI %x\n",
699 ctl_lo
.ctl_lo
, ctl_hi
.ctl_hi
, cfg_lo
.cfg_lo
, cfg_hi
.cfg_hi
);
701 enable_dma_interrupt(midc
);
703 desc
= midc_desc_get(midc
);
709 desc
->cfg_hi
= cfg_hi
.cfg_hi
;
710 desc
->cfg_lo
= cfg_lo
.cfg_lo
;
711 desc
->ctl_lo
= ctl_lo
.ctl_lo
;
712 desc
->ctl_hi
= ctl_hi
.ctl_hi
;
714 desc
->dirn
= mids
->dma_slave
.direction
;
717 desc
->lli_pool
= NULL
;
721 pr_err("ERR_MDMA: Failed to get desc\n");
722 midc_desc_put(midc
, desc
);
726 * intel_mid_dma_prep_slave_sg - Prep slave sg txn
727 * @chan: chan for DMA transfer
728 * @sgl: scatter gather list
729 * @sg_len: length of sg txn
730 * @direction: DMA transfer dirtn
733 * Prepares LLI based periphral transfer
735 static struct dma_async_tx_descriptor
*intel_mid_dma_prep_slave_sg(
736 struct dma_chan
*chan
, struct scatterlist
*sgl
,
737 unsigned int sg_len
, enum dma_data_direction direction
,
740 struct intel_mid_dma_chan
*midc
= NULL
;
741 struct intel_mid_dma_slave
*mids
= NULL
;
742 struct intel_mid_dma_desc
*desc
= NULL
;
743 struct dma_async_tx_descriptor
*txd
= NULL
;
744 union intel_mid_dma_ctl_lo ctl_lo
;
746 pr_debug("MDMA: Prep for slave SG\n");
749 pr_err("MDMA: Invalid SG length\n");
752 midc
= to_intel_mid_dma_chan(chan
);
755 mids
= midc
->mid_slave
;
758 if (!midc
->dma
->pimr_mask
) {
759 /* We can still handle sg list with only one item */
761 txd
= intel_mid_dma_prep_memcpy(chan
,
762 mids
->dma_slave
.dst_addr
,
763 mids
->dma_slave
.src_addr
,
768 pr_warn("MDMA: SG list is not supported by this controller\n");
773 pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
774 sg_len
, direction
, flags
);
776 txd
= intel_mid_dma_prep_memcpy(chan
, 0, 0, sgl
->length
, flags
);
778 pr_err("MDMA: Prep memcpy failed\n");
782 desc
= to_intel_mid_dma_desc(txd
);
783 desc
->dirn
= direction
;
784 ctl_lo
.ctl_lo
= desc
->ctl_lo
;
785 ctl_lo
.ctlx
.llp_dst_en
= 1;
786 ctl_lo
.ctlx
.llp_src_en
= 1;
787 desc
->ctl_lo
= ctl_lo
.ctl_lo
;
788 desc
->lli_length
= sg_len
;
789 desc
->current_lli
= 0;
790 /* DMA coherent memory pool for LLI descriptors*/
791 desc
->lli_pool
= pci_pool_create("intel_mid_dma_lli_pool",
793 (sizeof(struct intel_mid_dma_lli
)*sg_len
),
795 if (NULL
== desc
->lli_pool
) {
796 pr_err("MID_DMA:LLI pool create failed\n");
800 desc
->lli
= pci_pool_alloc(desc
->lli_pool
, GFP_KERNEL
, &desc
->lli_phys
);
802 pr_err("MID_DMA: LLI alloc failed\n");
803 pci_pool_destroy(desc
->lli_pool
);
807 midc_lli_fill_sg(midc
, desc
, sgl
, sg_len
, flags
);
808 if (flags
& DMA_PREP_INTERRUPT
) {
809 iowrite32(UNMASK_INTR_REG(midc
->ch_id
),
810 midc
->dma_base
+ MASK_BLOCK
);
811 pr_debug("MDMA:Enabled Block interrupt\n");
817 * intel_mid_dma_free_chan_resources - Frees dma resources
818 * @chan: chan requiring attention
820 * Frees the allocated resources on this DMA chan
822 static void intel_mid_dma_free_chan_resources(struct dma_chan
*chan
)
824 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(chan
);
825 struct middma_device
*mid
= to_middma_device(chan
->device
);
826 struct intel_mid_dma_desc
*desc
, *_desc
;
828 if (true == midc
->busy
) {
829 /*trying to free ch in use!!!!!*/
830 pr_err("ERR_MDMA: trying to free ch in use\n");
832 pm_runtime_put(&mid
->pdev
->dev
);
833 spin_lock_bh(&midc
->lock
);
834 midc
->descs_allocated
= 0;
835 list_for_each_entry_safe(desc
, _desc
, &midc
->active_list
, desc_node
) {
836 list_del(&desc
->desc_node
);
837 pci_pool_free(mid
->dma_pool
, desc
, desc
->txd
.phys
);
839 list_for_each_entry_safe(desc
, _desc
, &midc
->free_list
, desc_node
) {
840 list_del(&desc
->desc_node
);
841 pci_pool_free(mid
->dma_pool
, desc
, desc
->txd
.phys
);
843 list_for_each_entry_safe(desc
, _desc
, &midc
->queue
, desc_node
) {
844 list_del(&desc
->desc_node
);
845 pci_pool_free(mid
->dma_pool
, desc
, desc
->txd
.phys
);
847 spin_unlock_bh(&midc
->lock
);
848 midc
->in_use
= false;
850 /* Disable CH interrupts */
851 iowrite32(MASK_INTR_REG(midc
->ch_id
), mid
->dma_base
+ MASK_BLOCK
);
852 iowrite32(MASK_INTR_REG(midc
->ch_id
), mid
->dma_base
+ MASK_ERR
);
856 * intel_mid_dma_alloc_chan_resources - Allocate dma resources
857 * @chan: chan requiring attention
859 * Allocates DMA resources on this chan
860 * Return the descriptors allocated
862 static int intel_mid_dma_alloc_chan_resources(struct dma_chan
*chan
)
864 struct intel_mid_dma_chan
*midc
= to_intel_mid_dma_chan(chan
);
865 struct middma_device
*mid
= to_middma_device(chan
->device
);
866 struct intel_mid_dma_desc
*desc
;
870 pm_runtime_get_sync(&mid
->pdev
->dev
);
872 if (mid
->state
== SUSPENDED
) {
873 if (dma_resume(mid
->pdev
)) {
874 pr_err("ERR_MDMA: resume failed");
879 /* ASSERT: channel is idle */
880 if (test_ch_en(mid
->dma_base
, midc
->ch_id
)) {
882 pr_err("ERR_MDMA: ch not idle\n");
883 pm_runtime_put(&mid
->pdev
->dev
);
886 midc
->completed
= chan
->cookie
= 1;
888 spin_lock_bh(&midc
->lock
);
889 while (midc
->descs_allocated
< DESCS_PER_CHANNEL
) {
890 spin_unlock_bh(&midc
->lock
);
891 desc
= pci_pool_alloc(mid
->dma_pool
, GFP_KERNEL
, &phys
);
893 pr_err("ERR_MDMA: desc failed\n");
894 pm_runtime_put(&mid
->pdev
->dev
);
898 dma_async_tx_descriptor_init(&desc
->txd
, chan
);
899 desc
->txd
.tx_submit
= intel_mid_dma_tx_submit
;
900 desc
->txd
.flags
= DMA_CTRL_ACK
;
901 desc
->txd
.phys
= phys
;
902 spin_lock_bh(&midc
->lock
);
903 i
= ++midc
->descs_allocated
;
904 list_add_tail(&desc
->desc_node
, &midc
->free_list
);
906 spin_unlock_bh(&midc
->lock
);
909 pr_debug("MID_DMA: Desc alloc done ret: %d desc\n", i
);
914 * midc_handle_error - Handle DMA txn error
915 * @mid: controller where error occurred
916 * @midc: chan where error occurred
918 * Scan the descriptor for error
920 static void midc_handle_error(struct middma_device
*mid
,
921 struct intel_mid_dma_chan
*midc
)
923 midc_scan_descriptors(mid
, midc
);
927 * dma_tasklet - DMA interrupt tasklet
928 * @data: tasklet arg (the controller structure)
930 * Scan the controller for interrupts for completion/error
931 * Clear the interrupt and call for handling completion/error
933 static void dma_tasklet(unsigned long data
)
935 struct middma_device
*mid
= NULL
;
936 struct intel_mid_dma_chan
*midc
= NULL
;
937 u32 status
, raw_tfr
, raw_block
;
940 mid
= (struct middma_device
*)data
;
942 pr_err("ERR_MDMA: tasklet Null param\n");
945 pr_debug("MDMA: in tasklet for device %x\n", mid
->pci_id
);
946 raw_tfr
= ioread32(mid
->dma_base
+ RAW_TFR
);
947 raw_block
= ioread32(mid
->dma_base
+ RAW_BLOCK
);
948 status
= raw_tfr
| raw_block
;
949 status
&= mid
->intr_mask
;
952 i
= get_ch_index(&status
, mid
->chan_base
);
954 pr_err("ERR_MDMA:Invalid ch index %x\n", i
);
959 pr_err("ERR_MDMA:Null param midc\n");
962 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
963 status
, midc
->ch_id
, i
);
964 midc
->raw_tfr
= raw_tfr
;
965 midc
->raw_block
= raw_block
;
966 spin_lock_bh(&midc
->lock
);
967 /*clearing this interrupts first*/
968 iowrite32((1 << midc
->ch_id
), mid
->dma_base
+ CLEAR_TFR
);
970 iowrite32((1 << midc
->ch_id
),
971 mid
->dma_base
+ CLEAR_BLOCK
);
973 midc_scan_descriptors(mid
, midc
);
974 pr_debug("MDMA:Scan of desc... complete, unmasking\n");
975 iowrite32(UNMASK_INTR_REG(midc
->ch_id
),
976 mid
->dma_base
+ MASK_TFR
);
978 iowrite32(UNMASK_INTR_REG(midc
->ch_id
),
979 mid
->dma_base
+ MASK_BLOCK
);
981 spin_unlock_bh(&midc
->lock
);
984 status
= ioread32(mid
->dma_base
+ RAW_ERR
);
985 status
&= mid
->intr_mask
;
988 i
= get_ch_index(&status
, mid
->chan_base
);
990 pr_err("ERR_MDMA:Invalid ch index %x\n", i
);
995 pr_err("ERR_MDMA:Null param midc\n");
998 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
999 status
, midc
->ch_id
, i
);
1001 iowrite32((1 << midc
->ch_id
), mid
->dma_base
+ CLEAR_ERR
);
1002 spin_lock_bh(&midc
->lock
);
1003 midc_handle_error(mid
, midc
);
1004 iowrite32(UNMASK_INTR_REG(midc
->ch_id
),
1005 mid
->dma_base
+ MASK_ERR
);
1006 spin_unlock_bh(&midc
->lock
);
1008 pr_debug("MDMA:Exiting takslet...\n");
1012 static void dma_tasklet1(unsigned long data
)
1014 pr_debug("MDMA:in takslet1...\n");
1015 return dma_tasklet(data
);
1018 static void dma_tasklet2(unsigned long data
)
1020 pr_debug("MDMA:in takslet2...\n");
1021 return dma_tasklet(data
);
1025 * intel_mid_dma_interrupt - DMA ISR
1026 * @irq: IRQ where interrupt occurred
1027 * @data: ISR cllback data (the controller structure)
1029 * See if this is our interrupt if so then schedule the tasklet
1032 static irqreturn_t
intel_mid_dma_interrupt(int irq
, void *data
)
1034 struct middma_device
*mid
= data
;
1035 u32 tfr_status
, err_status
;
1036 int call_tasklet
= 0;
1038 tfr_status
= ioread32(mid
->dma_base
+ RAW_TFR
);
1039 err_status
= ioread32(mid
->dma_base
+ RAW_ERR
);
1040 if (!tfr_status
&& !err_status
)
1044 pr_debug("MDMA:Got an interrupt on irq %d\n", irq
);
1045 pr_debug("MDMA: Status %x, Mask %x\n", tfr_status
, mid
->intr_mask
);
1046 tfr_status
&= mid
->intr_mask
;
1048 /*need to disable intr*/
1049 iowrite32((tfr_status
<< INT_MASK_WE
), mid
->dma_base
+ MASK_TFR
);
1050 iowrite32((tfr_status
<< INT_MASK_WE
), mid
->dma_base
+ MASK_BLOCK
);
1051 pr_debug("MDMA: Calling tasklet %x\n", tfr_status
);
1054 err_status
&= mid
->intr_mask
;
1056 iowrite32(MASK_INTR_REG(err_status
), mid
->dma_base
+ MASK_ERR
);
1060 tasklet_schedule(&mid
->tasklet
);
1065 static irqreturn_t
intel_mid_dma_interrupt1(int irq
, void *data
)
1067 return intel_mid_dma_interrupt(irq
, data
);
1070 static irqreturn_t
intel_mid_dma_interrupt2(int irq
, void *data
)
1072 return intel_mid_dma_interrupt(irq
, data
);
1076 * mid_setup_dma - Setup the DMA controller
1077 * @pdev: Controller PCI device structure
1079 * Initialize the DMA controller, channels, registers with DMA engine,
1080 * ISR. Initialize DMA controller channels.
1082 static int mid_setup_dma(struct pci_dev
*pdev
)
1084 struct middma_device
*dma
= pci_get_drvdata(pdev
);
1087 /* DMA coherent memory pool for DMA descriptor allocations */
1088 dma
->dma_pool
= pci_pool_create("intel_mid_dma_desc_pool", pdev
,
1089 sizeof(struct intel_mid_dma_desc
),
1091 if (NULL
== dma
->dma_pool
) {
1092 pr_err("ERR_MDMA:pci_pool_create failed\n");
1097 INIT_LIST_HEAD(&dma
->common
.channels
);
1098 dma
->pci_id
= pdev
->device
;
1099 if (dma
->pimr_mask
) {
1100 dma
->mask_reg
= ioremap(LNW_PERIPHRAL_MASK_BASE
,
1101 LNW_PERIPHRAL_MASK_SIZE
);
1102 if (dma
->mask_reg
== NULL
) {
1103 pr_err("ERR_MDMA:Can't map periphral intr space !!\n");
1107 dma
->mask_reg
= NULL
;
1109 pr_debug("MDMA:Adding %d channel for this controller\n", dma
->max_chan
);
1110 /*init CH structures*/
1112 dma
->state
= RUNNING
;
1113 for (i
= 0; i
< dma
->max_chan
; i
++) {
1114 struct intel_mid_dma_chan
*midch
= &dma
->ch
[i
];
1116 midch
->chan
.device
= &dma
->common
;
1117 midch
->chan
.cookie
= 1;
1118 midch
->chan
.chan_id
= i
;
1119 midch
->ch_id
= dma
->chan_base
+ i
;
1120 pr_debug("MDMA:Init CH %d, ID %d\n", i
, midch
->ch_id
);
1122 midch
->dma_base
= dma
->dma_base
;
1123 midch
->ch_regs
= dma
->dma_base
+ DMA_CH_SIZE
* midch
->ch_id
;
1125 dma
->intr_mask
|= 1 << (dma
->chan_base
+ i
);
1126 spin_lock_init(&midch
->lock
);
1128 INIT_LIST_HEAD(&midch
->active_list
);
1129 INIT_LIST_HEAD(&midch
->queue
);
1130 INIT_LIST_HEAD(&midch
->free_list
);
1132 iowrite32(MASK_INTR_REG(midch
->ch_id
),
1133 dma
->dma_base
+ MASK_BLOCK
);
1134 iowrite32(MASK_INTR_REG(midch
->ch_id
),
1135 dma
->dma_base
+ MASK_SRC_TRAN
);
1136 iowrite32(MASK_INTR_REG(midch
->ch_id
),
1137 dma
->dma_base
+ MASK_DST_TRAN
);
1138 iowrite32(MASK_INTR_REG(midch
->ch_id
),
1139 dma
->dma_base
+ MASK_ERR
);
1140 iowrite32(MASK_INTR_REG(midch
->ch_id
),
1141 dma
->dma_base
+ MASK_TFR
);
1143 disable_dma_interrupt(midch
);
1144 list_add_tail(&midch
->chan
.device_node
, &dma
->common
.channels
);
1146 pr_debug("MDMA: Calc Mask as %x for this controller\n", dma
->intr_mask
);
1148 /*init dma structure*/
1149 dma_cap_zero(dma
->common
.cap_mask
);
1150 dma_cap_set(DMA_MEMCPY
, dma
->common
.cap_mask
);
1151 dma_cap_set(DMA_SLAVE
, dma
->common
.cap_mask
);
1152 dma_cap_set(DMA_PRIVATE
, dma
->common
.cap_mask
);
1153 dma
->common
.dev
= &pdev
->dev
;
1154 dma
->common
.chancnt
= dma
->max_chan
;
1156 dma
->common
.device_alloc_chan_resources
=
1157 intel_mid_dma_alloc_chan_resources
;
1158 dma
->common
.device_free_chan_resources
=
1159 intel_mid_dma_free_chan_resources
;
1161 dma
->common
.device_tx_status
= intel_mid_dma_tx_status
;
1162 dma
->common
.device_prep_dma_memcpy
= intel_mid_dma_prep_memcpy
;
1163 dma
->common
.device_issue_pending
= intel_mid_dma_issue_pending
;
1164 dma
->common
.device_prep_slave_sg
= intel_mid_dma_prep_slave_sg
;
1165 dma
->common
.device_control
= intel_mid_dma_device_control
;
1167 /*enable dma cntrl*/
1168 iowrite32(REG_BIT0
, dma
->dma_base
+ DMA_CFG
);
1171 if (dma
->pimr_mask
) {
1172 pr_debug("MDMA:Requesting irq shared for DMAC1\n");
1173 err
= request_irq(pdev
->irq
, intel_mid_dma_interrupt1
,
1174 IRQF_SHARED
, "INTEL_MID_DMAC1", dma
);
1178 dma
->intr_mask
= 0x03;
1179 pr_debug("MDMA:Requesting irq for DMAC2\n");
1180 err
= request_irq(pdev
->irq
, intel_mid_dma_interrupt2
,
1181 IRQF_SHARED
, "INTEL_MID_DMAC2", dma
);
1185 /*register device w/ engine*/
1186 err
= dma_async_device_register(&dma
->common
);
1188 pr_err("ERR_MDMA:device_register failed: %d\n", err
);
1191 if (dma
->pimr_mask
) {
1192 pr_debug("setting up tasklet1 for DMAC1\n");
1193 tasklet_init(&dma
->tasklet
, dma_tasklet1
, (unsigned long)dma
);
1195 pr_debug("setting up tasklet2 for DMAC2\n");
1196 tasklet_init(&dma
->tasklet
, dma_tasklet2
, (unsigned long)dma
);
1201 free_irq(pdev
->irq
, dma
);
1203 pci_pool_destroy(dma
->dma_pool
);
1205 pr_err("ERR_MDMA:setup_dma failed: %d\n", err
);
1211 * middma_shutdown - Shutdown the DMA controller
1212 * @pdev: Controller PCI device structure
1215 * Unregister DMa controller, clear all structures and free interrupt
1217 static void middma_shutdown(struct pci_dev
*pdev
)
1219 struct middma_device
*device
= pci_get_drvdata(pdev
);
1221 dma_async_device_unregister(&device
->common
);
1222 pci_pool_destroy(device
->dma_pool
);
1223 if (device
->mask_reg
)
1224 iounmap(device
->mask_reg
);
1225 if (device
->dma_base
)
1226 iounmap(device
->dma_base
);
1227 free_irq(pdev
->irq
, device
);
1232 * intel_mid_dma_probe - PCI Probe
1233 * @pdev: Controller PCI device structure
1234 * @id: pci device id structure
1236 * Initialize the PCI device, map BARs, query driver data.
1237 * Call setup_dma to complete contoller and chan initilzation
1239 static int __devinit
intel_mid_dma_probe(struct pci_dev
*pdev
,
1240 const struct pci_device_id
*id
)
1242 struct middma_device
*device
;
1243 u32 base_addr
, bar_size
;
1244 struct intel_mid_dma_probe_info
*info
;
1247 pr_debug("MDMA: probe for %x\n", pdev
->device
);
1248 info
= (void *)id
->driver_data
;
1249 pr_debug("MDMA: CH %d, base %d, block len %d, Periphral mask %x\n",
1250 info
->max_chan
, info
->ch_base
,
1251 info
->block_size
, info
->pimr_mask
);
1253 err
= pci_enable_device(pdev
);
1255 goto err_enable_device
;
1257 err
= pci_request_regions(pdev
, "intel_mid_dmac");
1259 goto err_request_regions
;
1261 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1263 goto err_set_dma_mask
;
1265 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
1267 goto err_set_dma_mask
;
1269 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
1271 pr_err("ERR_MDMA:kzalloc failed probe\n");
1275 device
->pdev
= pci_dev_get(pdev
);
1277 base_addr
= pci_resource_start(pdev
, 0);
1278 bar_size
= pci_resource_len(pdev
, 0);
1279 device
->dma_base
= ioremap_nocache(base_addr
, DMA_REG_SIZE
);
1280 if (!device
->dma_base
) {
1281 pr_err("ERR_MDMA:ioremap failed\n");
1285 pci_set_drvdata(pdev
, device
);
1286 pci_set_master(pdev
);
1287 device
->max_chan
= info
->max_chan
;
1288 device
->chan_base
= info
->ch_base
;
1289 device
->block_size
= info
->block_size
;
1290 device
->pimr_mask
= info
->pimr_mask
;
1292 err
= mid_setup_dma(pdev
);
1296 pm_runtime_put_noidle(&pdev
->dev
);
1297 pm_runtime_allow(&pdev
->dev
);
1301 iounmap(device
->dma_base
);
1307 pci_release_regions(pdev
);
1308 pci_disable_device(pdev
);
1309 err_request_regions
:
1311 pr_err("ERR_MDMA:Probe failed %d\n", err
);
1316 * intel_mid_dma_remove - PCI remove
1317 * @pdev: Controller PCI device structure
1319 * Free up all resources and data
1320 * Call shutdown_dma to complete contoller and chan cleanup
1322 static void __devexit
intel_mid_dma_remove(struct pci_dev
*pdev
)
1324 struct middma_device
*device
= pci_get_drvdata(pdev
);
1326 pm_runtime_get_noresume(&pdev
->dev
);
1327 pm_runtime_forbid(&pdev
->dev
);
1328 middma_shutdown(pdev
);
1331 pci_release_regions(pdev
);
1332 pci_disable_device(pdev
);
1335 /* Power Management */
1337 * dma_suspend - PCI suspend function
1339 * @pci: PCI device structure
1340 * @state: PM message
1342 * This function is called by OS when a power event occurs
1344 int dma_suspend(struct pci_dev
*pci
, pm_message_t state
)
1347 struct middma_device
*device
= pci_get_drvdata(pci
);
1348 pr_debug("MDMA: dma_suspend called\n");
1350 for (i
= 0; i
< device
->max_chan
; i
++) {
1351 if (device
->ch
[i
].in_use
)
1354 device
->state
= SUSPENDED
;
1355 pci_save_state(pci
);
1356 pci_disable_device(pci
);
1357 pci_set_power_state(pci
, PCI_D3hot
);
1362 * dma_resume - PCI resume function
1364 * @pci: PCI device structure
1366 * This function is called by OS when a power event occurs
1368 int dma_resume(struct pci_dev
*pci
)
1371 struct middma_device
*device
= pci_get_drvdata(pci
);
1373 pr_debug("MDMA: dma_resume called\n");
1374 pci_set_power_state(pci
, PCI_D0
);
1375 pci_restore_state(pci
);
1376 ret
= pci_enable_device(pci
);
1378 pr_err("MDMA: device can't be enabled for %x\n", pci
->device
);
1381 device
->state
= RUNNING
;
1382 iowrite32(REG_BIT0
, device
->dma_base
+ DMA_CFG
);
1386 static int dma_runtime_suspend(struct device
*dev
)
1388 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1389 struct middma_device
*device
= pci_get_drvdata(pci_dev
);
1391 device
->state
= SUSPENDED
;
1395 static int dma_runtime_resume(struct device
*dev
)
1397 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1398 struct middma_device
*device
= pci_get_drvdata(pci_dev
);
1400 device
->state
= RUNNING
;
1401 iowrite32(REG_BIT0
, device
->dma_base
+ DMA_CFG
);
1405 static int dma_runtime_idle(struct device
*dev
)
1407 struct pci_dev
*pdev
= to_pci_dev(dev
);
1408 struct middma_device
*device
= pci_get_drvdata(pdev
);
1411 for (i
= 0; i
< device
->max_chan
; i
++) {
1412 if (device
->ch
[i
].in_use
)
1416 return pm_schedule_suspend(dev
, 0);
1419 /******************************************************************************
1422 static struct pci_device_id intel_mid_dma_ids
[] = {
1423 { PCI_VDEVICE(INTEL
, INTEL_MID_DMAC1_ID
), INFO(2, 6, 4095, 0x200020)},
1424 { PCI_VDEVICE(INTEL
, INTEL_MID_DMAC2_ID
), INFO(2, 0, 2047, 0)},
1425 { PCI_VDEVICE(INTEL
, INTEL_MID_GP_DMAC2_ID
), INFO(2, 0, 2047, 0)},
1426 { PCI_VDEVICE(INTEL
, INTEL_MFLD_DMAC1_ID
), INFO(4, 0, 4095, 0x400040)},
1429 MODULE_DEVICE_TABLE(pci
, intel_mid_dma_ids
);
1431 static const struct dev_pm_ops intel_mid_dma_pm
= {
1432 .runtime_suspend
= dma_runtime_suspend
,
1433 .runtime_resume
= dma_runtime_resume
,
1434 .runtime_idle
= dma_runtime_idle
,
1437 static struct pci_driver intel_mid_dma_pci_driver
= {
1438 .name
= "Intel MID DMA",
1439 .id_table
= intel_mid_dma_ids
,
1440 .probe
= intel_mid_dma_probe
,
1441 .remove
= __devexit_p(intel_mid_dma_remove
),
1443 .suspend
= dma_suspend
,
1444 .resume
= dma_resume
,
1446 .pm
= &intel_mid_dma_pm
,
1451 static int __init
intel_mid_dma_init(void)
1453 pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n",
1454 INTEL_MID_DMA_DRIVER_VERSION
);
1455 return pci_register_driver(&intel_mid_dma_pci_driver
);
1457 fs_initcall(intel_mid_dma_init
);
1459 static void __exit
intel_mid_dma_exit(void)
1461 pci_unregister_driver(&intel_mid_dma_pci_driver
);
1463 module_exit(intel_mid_dma_exit
);
1465 MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
1466 MODULE_DESCRIPTION("Intel (R) MID DMAC Driver");
1467 MODULE_LICENSE("GPL v2");
1468 MODULE_VERSION(INTEL_MID_DMA_DRIVER_VERSION
);