drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/basic_mmio_gpio.h>
  31 #include <linux/module.h>
  32 #include <mach/mxs.h>
  33
  34 #define MXS_SET         0x4
  35 #define MXS_CLR         0x8
  36
  37 #define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
  38 #define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
  39 #define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
  40 #define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
  41 #define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
  42 #define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
  43 #define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
  44 #define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
  45
  46 #define GPIO_INT_FALL_EDGE      0x0
  47 #define GPIO_INT_LOW_LEV        0x1
  48 #define GPIO_INT_RISE_EDGE      0x2
  49 #define GPIO_INT_HIGH_LEV       0x3
  50 #define GPIO_INT_LEV_MASK       (1 << 0)
  51 #define GPIO_INT_POL_MASK       (1 << 1)
  52
  53 struct mxs_gpio_port {
  54         void __iomem *base;
  55         int id;
  56         int irq;
  57         int virtual_irq_start;
  58         struct bgpio_chip bgc;
  59 };
  60
  61 /* Note: This driver assumes 32 GPIOs are handled in one register */
  62
  63 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  64 {
  65         u32 gpio = irq_to_gpio(d->irq);
  66         u32 pin_mask = 1 << (gpio & 31);
  67         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  68         struct mxs_gpio_port *port = gc->private;
  69         void __iomem *pin_addr;
  70         int edge;
  71
  72         switch (type) {
  73         case IRQ_TYPE_EDGE_RISING:
  74                 edge = GPIO_INT_RISE_EDGE;
  75                 break;
  76         case IRQ_TYPE_EDGE_FALLING:
  77                 edge = GPIO_INT_FALL_EDGE;
  78                 break;
  79         case IRQ_TYPE_LEVEL_LOW:
  80                 edge = GPIO_INT_LOW_LEV;
  81                 break;
  82         case IRQ_TYPE_LEVEL_HIGH:
  83                 edge = GPIO_INT_HIGH_LEV;
  84                 break;
  85         default:
  86                 return -EINVAL;
  87         }
  88
  89         /* set level or edge */
  90         pin_addr = port->base + PINCTRL_IRQLEV(port->id);
  91         if (edge & GPIO_INT_LEV_MASK)
  92                 writel(pin_mask, pin_addr + MXS_SET);
  93         else
  94                 writel(pin_mask, pin_addr + MXS_CLR);
  95
  96         /* set polarity */
  97         pin_addr = port->base + PINCTRL_IRQPOL(port->id);
  98         if (edge & GPIO_INT_POL_MASK)
  99                 writel(pin_mask, pin_addr + MXS_SET);
 100         else
 101                 writel(pin_mask, pin_addr + MXS_CLR);
 102
 103         writel(1 << (gpio & 0x1f),
 104                port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 105
 106         return 0;
 107 }
 108
 109 /* MXS has one interrupt *per* gpio port */
 110 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 111 {
 112         u32 irq_stat;
 113         struct mxs_gpio_port *port = irq_get_handler_data(irq);
 114         u32 gpio_irq_no_base = port->virtual_irq_start;
 115
 116         desc->irq_data.chip->irq_ack(&desc->irq_data);
 117
 118         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
 119                         readl(port->base + PINCTRL_IRQEN(port->id));
 120
 121         while (irq_stat != 0) {
 122                 int irqoffset = fls(irq_stat) - 1;
 123                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 124                 irq_stat &= ~(1 << irqoffset);
 125         }
 126 }
 127
 128 /*
 129  * Set interrupt number "irq" in the GPIO as a wake-up source.
 130  * While system is running, all registered GPIO interrupts need to have
 131  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 132  * need to have wake-up enabled.
 133  * @param  irq          interrupt source number
 134  * @param  enable       enable as wake-up if equal to non-zero
 135  * @return       This function returns 0 on success.
 136  */
 137 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 138 {
 139         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 140         struct mxs_gpio_port *port = gc->private;
 141
 142         if (enable)
 143                 enable_irq_wake(port->irq);
 144         else
 145                 disable_irq_wake(port->irq);
 146
 147         return 0;
 148 }
 149
 150 static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
 151 {
 152         struct irq_chip_generic *gc;
 153         struct irq_chip_type *ct;
 154
 155         gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
 156                                     port->base, handle_level_irq);
 157         gc->private = port;
 158
 159         ct = gc->chip_types;
 160         ct->chip.irq_ack = irq_gc_ack_set_bit;
 161         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 162         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 163         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 164         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 165         ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR;
 166         ct->regs.mask = PINCTRL_IRQEN(port->id);
 167
 168         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 169 }
 170
 171 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 172 {
 173         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 174         struct mxs_gpio_port *port =
 175                 container_of(bgc, struct mxs_gpio_port, bgc);
 176
 177         return port->virtual_irq_start + offset;
 178 }
 179
 180 static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 181 {
 182         static void __iomem *base;
 183         struct mxs_gpio_port *port;
 184         struct resource *iores = NULL;
 185         int err;
 186
 187         port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
 188         if (!port)
 189                 return -ENOMEM;
 190
 191         port->id = pdev->id;
 192         port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 193
 194         /*
 195          * map memory region only once, as all the gpio ports
 196          * share the same one
 197          */
 198         if (!base) {
 199                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 200                 if (!iores) {
 201                         err = -ENODEV;
 202                         goto out_kfree;
 203                 }
 204
 205                 if (!request_mem_region(iores->start, resource_size(iores),
 206                                         pdev->name)) {
 207                         err = -EBUSY;
 208                         goto out_kfree;
 209                 }
 210
 211                 base = ioremap(iores->start, resource_size(iores));
 212                 if (!base) {
 213                         err = -ENOMEM;
 214                         goto out_release_mem;
 215                 }
 216         }
 217         port->base = base;
 218
 219         port->irq = platform_get_irq(pdev, 0);
 220         if (port->irq < 0) {
 221                 err = -EINVAL;
 222                 goto out_iounmap;
 223         }
 224
 225         /*
 226          * select the pin interrupt functionality but initially
 227          * disable the interrupts
 228          */
 229         writel(~0U, port->base + PINCTRL_PIN2IRQ(port->id));
 230         writel(0, port->base + PINCTRL_IRQEN(port->id));
 231
 232         /* clear address has to be used to clear IRQSTAT bits */
 233         writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 234
 235         /* gpio-mxs can be a generic irq chip */
 236         mxs_gpio_init_gc(port);
 237
 238         /* setup one handler for each entry */
 239         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 240         irq_set_handler_data(port->irq, port);
 241
 242         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 243                          port->base + PINCTRL_DIN(port->id),
 244                          port->base + PINCTRL_DOUT(port->id), NULL,
 245                          port->base + PINCTRL_DOE(port->id), NULL, false);
 246         if (err)
 247                 goto out_iounmap;
 248
 249         port->bgc.gc.to_irq = mxs_gpio_to_irq;
 250         port->bgc.gc.base = port->id * 32;
 251
 252         err = gpiochip_add(&port->bgc.gc);
 253         if (err)
 254                 goto out_bgpio_remove;
 255
 256         return 0;
 257
 258 out_bgpio_remove:
 259         bgpio_remove(&port->bgc);
 260 out_iounmap:
 261         if (iores)
 262                 iounmap(port->base);
 263 out_release_mem:
 264         if (iores)
 265                 release_mem_region(iores->start, resource_size(iores));
 266 out_kfree:
 267         kfree(port);
 268         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 269         return err;
 270 }
 271
 272 static struct platform_driver mxs_gpio_driver = {
 273         .driver         = {
 274                 .name   = "gpio-mxs",
 275                 .owner  = THIS_MODULE,
 276         },
 277         .probe          = mxs_gpio_probe,
 278 };
 279
 280 static int __init mxs_gpio_init(void)
 281 {
 282         return platform_driver_register(&mxs_gpio_driver);
 283 }
 284 postcore_initcall(mxs_gpio_init);
 285
 286 MODULE_AUTHOR("Freescale Semiconductor, "
 287               "Daniel Mack <danielncaiaq.de>, "
 288               "Juergen Beisert <kernel@pengutronix.de>");
 289 MODULE_DESCRIPTION("Freescale MXS GPIO");
 290 MODULE_LICENSE("GPL");