2 * Copyright 2007-2008 Nouveau Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #ifndef __NOUVEAU_BIOS_H__
25 #define __NOUVEAU_BIOS_H__
28 #include "nouveau_i2c.h"
30 #define DCB_MAX_NUM_ENTRIES 16
31 #define DCB_MAX_NUM_I2C_ENTRIES 16
32 #define DCB_MAX_NUM_GPIO_ENTRIES 32
33 #define DCB_MAX_NUM_CONNECTOR_ENTRIES 16
35 #define DCB_LOC_ON_CHIP 0
37 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
38 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
39 #define ROMPTR(bios, x) (ROM16(x) ? &(bios)->data[ROM16(x)] : NULL)
49 int bit_table(struct drm_device
*, u8 id
, struct bit_entry
*);
51 struct dcb_i2c_entry
{
55 struct nouveau_i2c_chan
*chan
;
59 DCB_GPIO_TVDAC0
= 0xc,
60 DCB_GPIO_TVDAC1
= 0x2d,
63 struct dcb_gpio_entry
{
64 enum dcb_gpio_tag tag
;
68 uint8_t state_default
;
72 struct dcb_gpio_table
{
74 struct dcb_gpio_entry entry
[DCB_MAX_NUM_GPIO_ENTRIES
];
77 enum dcb_connector_type
{
78 DCB_CONNECTOR_VGA
= 0x00,
79 DCB_CONNECTOR_TV_0
= 0x10,
80 DCB_CONNECTOR_TV_1
= 0x11,
81 DCB_CONNECTOR_TV_3
= 0x13,
82 DCB_CONNECTOR_DVI_I
= 0x30,
83 DCB_CONNECTOR_DVI_D
= 0x31,
84 DCB_CONNECTOR_LVDS
= 0x40,
85 DCB_CONNECTOR_LVDS_SPWG
= 0x41,
86 DCB_CONNECTOR_DP
= 0x46,
87 DCB_CONNECTOR_eDP
= 0x47,
88 DCB_CONNECTOR_HDMI_0
= 0x60,
89 DCB_CONNECTOR_HDMI_1
= 0x61,
90 DCB_CONNECTOR_NONE
= 0xff
93 struct dcb_connector_table_entry
{
96 enum dcb_connector_type type
;
102 struct dcb_connector_table
{
104 struct dcb_connector_table_entry entry
[DCB_MAX_NUM_CONNECTOR_ENTRIES
];
113 OUTPUT_EOL
= 14, /* DCB 4.0+, appears to be end-of-list */
118 int index
; /* may not be raw dcb index if merging has happened */
126 bool duallink_possible
;
136 bool use_straps_for_mode
;
137 bool use_acpi_for_edid
;
138 bool use_power_scripts
;
141 bool has_component_output
;
153 bool i2c_upper_default
;
160 struct dcb_entry entry
[DCB_MAX_NUM_ENTRIES
];
163 uint8_t i2c_default_indices
;
164 struct dcb_i2c_entry i2c
[DCB_MAX_NUM_I2C_ENTRIES
];
166 uint16_t gpio_table_ptr
;
167 struct dcb_gpio_table gpio
;
168 uint16_t connector_table_ptr
;
169 struct dcb_connector_table connector
;
179 /* Order *does* matter here */
188 /* these match types in pll limits table version 0x40,
189 * nouveau uses them on all chipsets internally where a
190 * specific pll needs to be referenced, but the exact
191 * register isn't known.
224 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
225 * value) is no different to 6 (at least for vplls) so allowing the MNP
226 * calc to use 7 causes the generated clock to be out by a factor of 2.
227 * however, max_log2p cannot be fixed-up during parsing as the
228 * unmodified max_log2p value is still needed for setting mplls, hence
229 * an additional max_usable_log2p member
231 uint8_t max_usable_log2p
;
241 struct drm_device
*dev
;
248 uint8_t chip_version
;
251 uint32_t tvdactestval
;
252 uint8_t digital_min_front_porch
;
257 uint8_t data
[NV_PROM_SIZE
];
261 uint8_t major_version
;
262 uint8_t feature_byte
;
265 uint32_t fmaxvco
, fminvco
;
268 uint16_t init_script_tbls_ptr
;
269 uint16_t extra_init_script_tbl_ptr
;
270 uint16_t macro_index_tbl_ptr
;
271 uint16_t macro_tbl_ptr
;
272 uint16_t condition_tbl_ptr
;
273 uint16_t io_condition_tbl_ptr
;
274 uint16_t io_flag_condition_tbl_ptr
;
275 uint16_t init_function_tbl_ptr
;
277 uint16_t pll_limit_tbl_ptr
;
278 uint16_t ram_restrict_tbl_ptr
;
279 uint8_t ram_restrict_group_count
;
281 uint16_t some_script_ptr
; /* BIT I + 14 */
282 uint16_t init96_tbl_ptr
; /* BIT I + 16 */
284 struct dcb_table dcb
;
291 struct dcb_entry
*output
;
292 uint16_t script_table_ptr
;
293 uint16_t dp_table_ptr
;
297 uint16_t fptablepointer
; /* also used by tmds */
298 uint16_t fpxlatetableptr
;
300 uint16_t lvdsmanufacturerpointer
;
301 uint16_t fpxlatemanufacturertableptr
;
303 uint16_t xlated_entry
;
304 bool power_off_for_reset
;
305 bool reset_after_pclk_change
;
307 bool link_c_increment
;
309 int duallink_transition_clk
;
310 uint8_t strapless_is_24bit
;
313 /* will need resetting after suspend */
314 int last_script_invoc
;
319 uint16_t output0_script_ptr
;
320 uint16_t output1_script_ptr
;
324 uint16_t mem_init_tbl_ptr
;
325 uint16_t sdr_seq_tbl_ptr
;
326 uint16_t ddr_seq_tbl_ptr
;
329 uint8_t crt
, tv
, panel
;
332 uint16_t lvds_single_a_script_ptr
;