1 /* fuc microcode for nvc0 PGRAPH/GPC
3 * Copyright 2011 Red Hat Inc.
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6 * copy of this software and associated documentation files (the "Software"),
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10 * Software is furnished to do so, subject to the following conditions:
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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27 * m4 nvc0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grgpc.fuc.h
31 * - bracket certain functions with scratch writes, useful for debugging
32 * - watchdog timer around ctx operations
35 .section nvc0_grgpc_data
36 include(`nvc0_graph.fuc')
38 gpc_mmio_list_head: .b32 0
39 gpc_mmio_list_tail: .b32 0
43 tpc_mmio_list_head: .b32 0
44 tpc_mmio_list_tail: .b32 0
48 // chipset descriptions
51 .b16 nvc0_gpc_mmio_head
52 .b16 nvc0_gpc_mmio_tail
53 .b16 nvc0_tpc_mmio_head
54 .b16 nvc0_tpc_mmio_tail
56 .b16 nvc0_gpc_mmio_head
57 .b16 nvc1_gpc_mmio_tail
58 .b16 nvc0_tpc_mmio_head
59 .b16 nvc1_tpc_mmio_tail
61 .b16 nvc0_gpc_mmio_head
62 .b16 nvc0_gpc_mmio_tail
63 .b16 nvc0_tpc_mmio_head
64 .b16 nvc3_tpc_mmio_tail
66 .b16 nvc0_gpc_mmio_head
67 .b16 nvc0_gpc_mmio_tail
68 .b16 nvc0_tpc_mmio_head
69 .b16 nvc3_tpc_mmio_tail
71 .b16 nvc0_gpc_mmio_head
72 .b16 nvc0_gpc_mmio_tail
73 .b16 nvc0_tpc_mmio_head
74 .b16 nvc0_tpc_mmio_tail
76 .b16 nvc0_gpc_mmio_head
77 .b16 nvc0_gpc_mmio_tail
78 .b16 nvc0_tpc_mmio_head
79 .b16 nvc3_tpc_mmio_tail
84 mmctx_data(0x000380, 1)
85 mmctx_data(0x000400, 6)
86 mmctx_data(0x000450, 9)
87 mmctx_data(0x000600, 1)
88 mmctx_data(0x000684, 1)
89 mmctx_data(0x000700, 5)
90 mmctx_data(0x000800, 1)
91 mmctx_data(0x000808, 3)
92 mmctx_data(0x000828, 1)
93 mmctx_data(0x000830, 1)
94 mmctx_data(0x0008d8, 1)
95 mmctx_data(0x0008e0, 1)
96 mmctx_data(0x0008e8, 6)
97 mmctx_data(0x00091c, 1)
98 mmctx_data(0x000924, 3)
99 mmctx_data(0x000b00, 1)
100 mmctx_data(0x000b08, 6)
101 mmctx_data(0x000bb8, 1)
102 mmctx_data(0x000c08, 1)
103 mmctx_data(0x000c10, 8)
104 mmctx_data(0x000c80, 1)
105 mmctx_data(0x000c8c, 1)
106 mmctx_data(0x001000, 3)
107 mmctx_data(0x001014, 1)
109 mmctx_data(0x000c6c, 1);
114 mmctx_data(0x000018, 1)
115 mmctx_data(0x00003c, 1)
116 mmctx_data(0x000048, 1)
117 mmctx_data(0x000064, 1)
118 mmctx_data(0x000088, 1)
119 mmctx_data(0x000200, 6)
120 mmctx_data(0x00021c, 2)
121 mmctx_data(0x000300, 6)
122 mmctx_data(0x0003d0, 1)
123 mmctx_data(0x0003e0, 2)
124 mmctx_data(0x000400, 3)
125 mmctx_data(0x000420, 1)
126 mmctx_data(0x0004b0, 1)
127 mmctx_data(0x0004e8, 1)
128 mmctx_data(0x0004f4, 1)
129 mmctx_data(0x000520, 2)
130 mmctx_data(0x000604, 4)
131 mmctx_data(0x000644, 20)
132 mmctx_data(0x000698, 1)
133 mmctx_data(0x000750, 2)
135 mmctx_data(0x000758, 1)
136 mmctx_data(0x0002c4, 1)
137 mmctx_data(0x0004bc, 1)
138 mmctx_data(0x0006e0, 1)
140 mmctx_data(0x000544, 1)
144 .section nvc0_grgpc_code
146 define(`include_code')
147 include(`nvc0_graph.fuc')
149 // reports an exception to the host
151 // In: $r15 error code (see nvc0_graph.fuc)
155 mov $r14 -0x67ec // 0x9814
157 call nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
160 call nv_wr32 // HUB_CTXCTL_INTR_UP_SET
164 // GPC fuc initialisation, executed by triggering ucode start, will
165 // fall through to main loop after completion.
168 // CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
169 // CC_SCRATCH[1]: context base
173 // 31:31: set to signal completion
175 // 31:0: GPC context size
181 // enable fifo access
184 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
186 // setup i0 handler, and route all interrupts to it
190 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
192 // enable fifo interrupt
194 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
199 // figure out which GPC we are, and how many TPCs we have
202 iord $r2 I[$r1 + 0x000] // UNITS
207 st b32 D[$r0 + tpc_count] $r2
208 st b32 D[$r0 + tpc_mask] $r3
210 iord $r2 I[$r1 + 0x000] // MYINDEX
211 st b32 D[$r0 + gpc_id] $r2
213 // find context data for this chipset
216 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
217 mov $r1 chipsets - 12
220 ld b32 $r3 D[$r1 + 0x00]
224 bra ne init_find_chipset
228 // initialise context base, and size tracking
232 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
233 clear b32 $r3 // track GPC context size here
235 // set mmctx base addresses now so we don't have to do it later,
236 // they don't currently ever change
240 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
241 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
243 // calculate GPC mmio context size, store the chipset-specific
244 // mmio list pointers somewhere we can get at them later without
245 // re-parsing the chipset list
248 ld b16 $r14 D[$r1 + 4]
249 ld b16 $r15 D[$r1 + 6]
250 st b16 D[$r0 + gpc_mmio_list_head] $r14
251 st b16 D[$r0 + gpc_mmio_list_tail] $r15
256 // calculate per-TPC mmio context size, store the list pointers
257 ld b16 $r14 D[$r1 + 8]
258 ld b16 $r15 D[$r1 + 10]
259 st b16 D[$r0 + tpc_mmio_list_head] $r14
260 st b16 D[$r0 + tpc_mmio_list_tail] $r15
262 ld b32 $r14 D[$r0 + tpc_count]
267 // round up base/size to 256 byte boundary (for strand SWBASE)
270 iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
278 // calculate size of strand context data
283 // save context size, and tell HUB we're done
286 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
290 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
292 // Main program loop, very simple, sleeps until woken up by the interrupt
293 // handler, pulls a command from the queue and executes its handler
302 // 0x0000-0x0003 are all context transfers
304 bra nc main_not_ctx_xfer
305 // fetch $flags and mask off $p1/$p2
310 // set $p1/$p2 according to transfer type
314 // transfer context data
320 or $r15 E_BAD_COMMAND
336 // incoming fifo command?
337 iord $r10 I[$r0 + 0x200] // INTR
338 and $r11 $r10 0x00000004
340 // queue incoming fifo command for later processing
343 iord $r14 I[$r11 + 0x100] // FIFO_CMD
344 iord $r15 I[$r11 + 0x000] // FIFO_DATA
348 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
350 // ack, and wake up main()
352 iowr I[$r0 + 0x100] $r10 // INTR_ACK
366 // Set this GPC's bit in HUB_BAR, used to signal completion of various
367 // activities to the HUB fuc
371 ld b32 $r14 D[$r0 + gpc_id]
373 mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
378 // Disables various things, waits a bit, and re-enables them..
380 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
381 // good description for the bits we turn off? Anyways, without this,
382 // funny things happen.
388 iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
392 bra ne ctx_redswitch_delay
394 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
397 // Transfer GPC context data between GPU and storage area
399 // In: $r15 context base address
400 // $p1 clear on save, set on load
401 // $p2 set if opposite direction done/will be done, so:
402 // on save it means: "a load will follow this save"
403 // on load it means: "a save preceeded this load"
406 // set context base address
409 iowr I[$r1 + 0x000] $r15// MEM_BASE
410 bra not $p1 ctx_xfer_not_load
418 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
422 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
425 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
428 xbit $r10 $flags $p1 // direction
432 ld b32 $r12 D[$r0 + gpc_id]
434 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
435 ld b32 $r12 D[$r0 + gpc_mmio_list_head]
436 ld b32 $r13 D[$r0 + gpc_mmio_list_tail]
437 mov $r14 0 // not multi
440 // per-TPC mmio context
441 xbit $r10 $flags $p1 // direction
444 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
445 ld b32 $r12 D[$r0 + gpc_id]
447 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
448 ld b32 $r12 D[$r0 + tpc_mmio_list_head]
449 ld b32 $r13 D[$r0 + tpc_mmio_list_tail]
450 ld b32 $r15 D[$r0 + tpc_mask]
451 mov $r14 0x800 // stride = 0x800
454 // wait for strands to finish
457 // if load, or a save without a load following, do some
458 // unknown stuff that's done after finishing a block of
460 bra $p1 ctx_xfer_post
461 bra not $p2 ctx_xfer_done
466 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
469 // mark completion in HUB's barrier
471 call hub_barrier_done