2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
31 #include "radeon_drm.h"
32 #include "radeon_drv.h"
34 #define PFP_UCODE_SIZE 576
35 #define PM4_UCODE_SIZE 1792
36 #define R700_PFP_UCODE_SIZE 848
37 #define R700_PM4_UCODE_SIZE 1360
40 MODULE_FIRMWARE("radeon/R600_pfp.bin");
41 MODULE_FIRMWARE("radeon/R600_me.bin");
42 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
43 MODULE_FIRMWARE("radeon/RV610_me.bin");
44 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
45 MODULE_FIRMWARE("radeon/RV630_me.bin");
46 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
47 MODULE_FIRMWARE("radeon/RV620_me.bin");
48 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
49 MODULE_FIRMWARE("radeon/RV635_me.bin");
50 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
51 MODULE_FIRMWARE("radeon/RV670_me.bin");
52 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
53 MODULE_FIRMWARE("radeon/RS780_me.bin");
54 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV770_me.bin");
56 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV730_me.bin");
58 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV710_me.bin");
62 int r600_cs_legacy(struct drm_device
*dev
, void *data
, struct drm_file
*filp
,
63 unsigned family
, u32
*ib
, int *l
);
64 void r600_cs_legacy_init(void);
67 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
68 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
70 #define R600_PTE_VALID (1 << 0)
71 #define R600_PTE_SYSTEM (1 << 1)
72 #define R600_PTE_SNOOPED (1 << 2)
73 #define R600_PTE_READABLE (1 << 5)
74 #define R600_PTE_WRITEABLE (1 << 6)
76 /* MAX values used for gfx init */
77 #define R6XX_MAX_SH_GPRS 256
78 #define R6XX_MAX_TEMP_GPRS 16
79 #define R6XX_MAX_SH_THREADS 256
80 #define R6XX_MAX_SH_STACK_ENTRIES 4096
81 #define R6XX_MAX_BACKENDS 8
82 #define R6XX_MAX_BACKENDS_MASK 0xff
83 #define R6XX_MAX_SIMDS 8
84 #define R6XX_MAX_SIMDS_MASK 0xff
85 #define R6XX_MAX_PIPES 8
86 #define R6XX_MAX_PIPES_MASK 0xff
88 #define R7XX_MAX_SH_GPRS 256
89 #define R7XX_MAX_TEMP_GPRS 16
90 #define R7XX_MAX_SH_THREADS 256
91 #define R7XX_MAX_SH_STACK_ENTRIES 4096
92 #define R7XX_MAX_BACKENDS 8
93 #define R7XX_MAX_BACKENDS_MASK 0xff
94 #define R7XX_MAX_SIMDS 16
95 #define R7XX_MAX_SIMDS_MASK 0xffff
96 #define R7XX_MAX_PIPES 8
97 #define R7XX_MAX_PIPES_MASK 0xff
99 static int r600_do_wait_for_fifo(drm_radeon_private_t
*dev_priv
, int entries
)
103 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
105 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
107 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
108 slots
= (RADEON_READ(R600_GRBM_STATUS
)
109 & R700_CMDFIFO_AVAIL_MASK
);
111 slots
= (RADEON_READ(R600_GRBM_STATUS
)
112 & R600_CMDFIFO_AVAIL_MASK
);
113 if (slots
>= entries
)
117 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
118 RADEON_READ(R600_GRBM_STATUS
),
119 RADEON_READ(R600_GRBM_STATUS2
));
124 static int r600_do_wait_for_idle(drm_radeon_private_t
*dev_priv
)
128 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
130 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
131 ret
= r600_do_wait_for_fifo(dev_priv
, 8);
133 ret
= r600_do_wait_for_fifo(dev_priv
, 16);
136 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
137 if (!(RADEON_READ(R600_GRBM_STATUS
) & R600_GUI_ACTIVE
))
141 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
142 RADEON_READ(R600_GRBM_STATUS
),
143 RADEON_READ(R600_GRBM_STATUS2
));
148 void r600_page_table_cleanup(struct drm_device
*dev
, struct drm_ati_pcigart_info
*gart_info
)
150 struct drm_sg_mem
*entry
= dev
->sg
;
158 if (gart_info
->bus_addr
) {
159 max_pages
= (gart_info
->table_size
/ sizeof(u64
));
160 pages
= (entry
->pages
<= max_pages
)
161 ? entry
->pages
: max_pages
;
163 for (i
= 0; i
< pages
; i
++) {
164 if (!entry
->busaddr
[i
])
166 pci_unmap_page(dev
->pdev
, entry
->busaddr
[i
],
167 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
169 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
)
170 gart_info
->bus_addr
= 0;
174 /* R600 has page table setup */
175 int r600_page_table_init(struct drm_device
*dev
)
177 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
178 struct drm_ati_pcigart_info
*gart_info
= &dev_priv
->gart_info
;
179 struct drm_local_map
*map
= &gart_info
->mapping
;
180 struct drm_sg_mem
*entry
= dev
->sg
;
185 dma_addr_t entry_addr
;
186 int max_ati_pages
, max_real_pages
, gart_idx
;
188 /* okay page table is available - lets rock */
189 max_ati_pages
= (gart_info
->table_size
/ sizeof(u64
));
190 max_real_pages
= max_ati_pages
/ (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
);
192 pages
= (entry
->pages
<= max_real_pages
) ?
193 entry
->pages
: max_real_pages
;
195 memset_io((void __iomem
*)map
->handle
, 0, max_ati_pages
* sizeof(u64
));
198 for (i
= 0; i
< pages
; i
++) {
199 entry
->busaddr
[i
] = pci_map_page(dev
->pdev
,
200 entry
->pagelist
[i
], 0,
202 PCI_DMA_BIDIRECTIONAL
);
203 if (pci_dma_mapping_error(dev
->pdev
, entry
->busaddr
[i
])) {
204 DRM_ERROR("unable to map PCIGART pages!\n");
205 r600_page_table_cleanup(dev
, gart_info
);
208 entry_addr
= entry
->busaddr
[i
];
209 for (j
= 0; j
< (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
); j
++) {
210 page_base
= (u64
) entry_addr
& ATI_PCIGART_PAGE_MASK
;
211 page_base
|= R600_PTE_VALID
| R600_PTE_SYSTEM
| R600_PTE_SNOOPED
;
212 page_base
|= R600_PTE_READABLE
| R600_PTE_WRITEABLE
;
214 DRM_WRITE64(map
, gart_idx
* sizeof(u64
), page_base
);
219 DRM_DEBUG("page entry %d: 0x%016llx\n",
220 i
, (unsigned long long)page_base
);
221 entry_addr
+= ATI_PCIGART_PAGE_SIZE
;
229 static void r600_vm_flush_gart_range(struct drm_device
*dev
)
231 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
232 u32 resp
, countdown
= 1000;
233 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
235 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE
, 2);
238 resp
= RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE
);
241 } while (((resp
& 0xf0) == 0) && countdown
);
244 static void r600_vm_init(struct drm_device
*dev
)
246 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
247 /* initialise the VM to use the page table we constructed up there */
250 u32 vm_l2_cntl
, vm_l2_cntl3
;
251 /* okay set up the PCIE aperture type thingo */
252 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
257 mc_rd_a
= R600_MCD_L1_TLB
| R600_MCD_L1_FRAG_PROC
| R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS
|
258 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
| R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
259 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY
;
261 RADEON_WRITE(R600_MCD_RD_A_CNTL
, mc_rd_a
);
262 RADEON_WRITE(R600_MCD_RD_B_CNTL
, mc_rd_a
);
264 RADEON_WRITE(R600_MCD_WR_A_CNTL
, mc_rd_a
);
265 RADEON_WRITE(R600_MCD_WR_B_CNTL
, mc_rd_a
);
267 RADEON_WRITE(R600_MCD_RD_GFX_CNTL
, mc_rd_a
);
268 RADEON_WRITE(R600_MCD_WR_GFX_CNTL
, mc_rd_a
);
270 RADEON_WRITE(R600_MCD_RD_SYS_CNTL
, mc_rd_a
);
271 RADEON_WRITE(R600_MCD_WR_SYS_CNTL
, mc_rd_a
);
273 RADEON_WRITE(R600_MCD_RD_HDP_CNTL
, mc_rd_a
| R600_MCD_L1_STRICT_ORDERING
);
274 RADEON_WRITE(R600_MCD_WR_HDP_CNTL
, mc_rd_a
/*| R600_MCD_L1_STRICT_ORDERING*/);
276 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL
, mc_rd_a
);
277 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL
, mc_rd_a
);
279 RADEON_WRITE(R600_MCD_RD_SEM_CNTL
, mc_rd_a
| R600_MCD_SEMAPHORE_MODE
);
280 RADEON_WRITE(R600_MCD_WR_SEM_CNTL
, mc_rd_a
);
282 vm_l2_cntl
= R600_VM_L2_CACHE_EN
| R600_VM_L2_FRAG_PROC
| R600_VM_ENABLE_PTE_CACHE_LRU_W
;
283 vm_l2_cntl
|= R600_VM_L2_CNTL_QUEUE_SIZE(7);
284 RADEON_WRITE(R600_VM_L2_CNTL
, vm_l2_cntl
);
286 RADEON_WRITE(R600_VM_L2_CNTL2
, 0);
287 vm_l2_cntl3
= (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
288 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
289 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
290 RADEON_WRITE(R600_VM_L2_CNTL3
, vm_l2_cntl3
);
292 vm_c0
= R600_VM_ENABLE_CONTEXT
| R600_VM_PAGE_TABLE_DEPTH_FLAT
;
294 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
, vm_c0
);
296 vm_c0
&= ~R600_VM_ENABLE_CONTEXT
;
298 /* disable all other contexts */
299 for (i
= 1; i
< 8; i
++)
300 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
+ (i
* 4), vm_c0
);
302 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, dev_priv
->gart_info
.bus_addr
>> 12);
303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR
, dev_priv
->gart_vm_start
>> 12);
304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
306 r600_vm_flush_gart_range(dev
);
309 static int r600_cp_init_microcode(drm_radeon_private_t
*dev_priv
)
311 struct platform_device
*pdev
;
312 const char *chip_name
;
313 size_t pfp_req_size
, me_req_size
;
317 pdev
= platform_device_register_simple("r600_cp", 0, NULL
, 0);
320 printk(KERN_ERR
"r600_cp: Failed to register firmware\n");
324 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
325 case CHIP_R600
: chip_name
= "R600"; break;
326 case CHIP_RV610
: chip_name
= "RV610"; break;
327 case CHIP_RV630
: chip_name
= "RV630"; break;
328 case CHIP_RV620
: chip_name
= "RV620"; break;
329 case CHIP_RV635
: chip_name
= "RV635"; break;
330 case CHIP_RV670
: chip_name
= "RV670"; break;
332 case CHIP_RS880
: chip_name
= "RS780"; break;
333 case CHIP_RV770
: chip_name
= "RV770"; break;
335 case CHIP_RV740
: chip_name
= "RV730"; break;
336 case CHIP_RV710
: chip_name
= "RV710"; break;
340 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
) {
341 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
342 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
344 pfp_req_size
= PFP_UCODE_SIZE
* 4;
345 me_req_size
= PM4_UCODE_SIZE
* 12;
348 DRM_INFO("Loading %s CP Microcode\n", chip_name
);
350 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
351 err
= request_firmware(&dev_priv
->pfp_fw
, fw_name
, &pdev
->dev
);
354 if (dev_priv
->pfp_fw
->size
!= pfp_req_size
) {
356 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
357 dev_priv
->pfp_fw
->size
, fw_name
);
362 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
363 err
= request_firmware(&dev_priv
->me_fw
, fw_name
, &pdev
->dev
);
366 if (dev_priv
->me_fw
->size
!= me_req_size
) {
368 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
369 dev_priv
->me_fw
->size
, fw_name
);
373 platform_device_unregister(pdev
);
378 "r600_cp: Failed to load firmware \"%s\"\n",
380 release_firmware(dev_priv
->pfp_fw
);
381 dev_priv
->pfp_fw
= NULL
;
382 release_firmware(dev_priv
->me_fw
);
383 dev_priv
->me_fw
= NULL
;
388 static void r600_cp_load_microcode(drm_radeon_private_t
*dev_priv
)
390 const __be32
*fw_data
;
393 if (!dev_priv
->me_fw
|| !dev_priv
->pfp_fw
)
396 r600_do_cp_stop(dev_priv
);
398 RADEON_WRITE(R600_CP_RB_CNTL
,
400 R600_BUF_SWAP_32BIT
|
406 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
407 RADEON_READ(R600_GRBM_SOFT_RESET
);
409 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
411 fw_data
= (const __be32
*)dev_priv
->me_fw
->data
;
412 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
413 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
414 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
415 be32_to_cpup(fw_data
++));
417 fw_data
= (const __be32
*)dev_priv
->pfp_fw
->data
;
418 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
419 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
420 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
,
421 be32_to_cpup(fw_data
++));
423 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
424 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
425 RADEON_WRITE(R600_CP_ME_RAM_RADDR
, 0);
429 static void r700_vm_init(struct drm_device
*dev
)
431 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
432 /* initialise the VM to use the page table we constructed up there */
435 u32 vm_l2_cntl
, vm_l2_cntl3
;
436 /* okay set up the PCIE aperture type thingo */
437 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
438 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
439 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
441 mc_vm_md_l1
= R700_ENABLE_L1_TLB
|
442 R700_ENABLE_L1_FRAGMENT_PROCESSING
|
443 R700_SYSTEM_ACCESS_MODE_IN_SYS
|
444 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
445 R700_EFFECTIVE_L1_TLB_SIZE(5) |
446 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
448 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL
, mc_vm_md_l1
);
449 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL
, mc_vm_md_l1
);
450 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL
, mc_vm_md_l1
);
451 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL
, mc_vm_md_l1
);
452 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL
, mc_vm_md_l1
);
453 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL
, mc_vm_md_l1
);
454 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL
, mc_vm_md_l1
);
456 vm_l2_cntl
= R600_VM_L2_CACHE_EN
| R600_VM_L2_FRAG_PROC
| R600_VM_ENABLE_PTE_CACHE_LRU_W
;
457 vm_l2_cntl
|= R700_VM_L2_CNTL_QUEUE_SIZE(7);
458 RADEON_WRITE(R600_VM_L2_CNTL
, vm_l2_cntl
);
460 RADEON_WRITE(R600_VM_L2_CNTL2
, 0);
461 vm_l2_cntl3
= R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
462 RADEON_WRITE(R600_VM_L2_CNTL3
, vm_l2_cntl3
);
464 vm_c0
= R600_VM_ENABLE_CONTEXT
| R600_VM_PAGE_TABLE_DEPTH_FLAT
;
466 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
, vm_c0
);
468 vm_c0
&= ~R600_VM_ENABLE_CONTEXT
;
470 /* disable all other contexts */
471 for (i
= 1; i
< 8; i
++)
472 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
+ (i
* 4), vm_c0
);
474 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, dev_priv
->gart_info
.bus_addr
>> 12);
475 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR
, dev_priv
->gart_vm_start
>> 12);
476 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
478 r600_vm_flush_gart_range(dev
);
481 static void r700_cp_load_microcode(drm_radeon_private_t
*dev_priv
)
483 const __be32
*fw_data
;
486 if (!dev_priv
->me_fw
|| !dev_priv
->pfp_fw
)
489 r600_do_cp_stop(dev_priv
);
491 RADEON_WRITE(R600_CP_RB_CNTL
,
493 R600_BUF_SWAP_32BIT
|
499 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
500 RADEON_READ(R600_GRBM_SOFT_RESET
);
502 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
504 fw_data
= (const __be32
*)dev_priv
->pfp_fw
->data
;
505 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
506 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
507 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
508 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
510 fw_data
= (const __be32
*)dev_priv
->me_fw
->data
;
511 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
512 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
513 RADEON_WRITE(R600_CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
514 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
516 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
517 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
518 RADEON_WRITE(R600_CP_ME_RAM_RADDR
, 0);
522 static void r600_test_writeback(drm_radeon_private_t
*dev_priv
)
526 /* Start with assuming that writeback doesn't work */
527 dev_priv
->writeback_works
= 0;
529 /* Writeback doesn't seem to work everywhere, test it here and possibly
530 * enable it if it appears to work
532 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(1), 0);
534 RADEON_WRITE(R600_SCRATCH_REG1
, 0xdeadbeef);
536 for (tmp
= 0; tmp
< dev_priv
->usec_timeout
; tmp
++) {
539 val
= radeon_read_ring_rptr(dev_priv
, R600_SCRATCHOFF(1));
540 if (val
== 0xdeadbeef)
545 if (tmp
< dev_priv
->usec_timeout
) {
546 dev_priv
->writeback_works
= 1;
547 DRM_INFO("writeback test succeeded in %d usecs\n", tmp
);
549 dev_priv
->writeback_works
= 0;
550 DRM_INFO("writeback test failed\n");
552 if (radeon_no_wb
== 1) {
553 dev_priv
->writeback_works
= 0;
554 DRM_INFO("writeback forced off\n");
557 if (!dev_priv
->writeback_works
) {
558 /* Disable writeback to avoid unnecessary bus master transfer */
559 RADEON_WRITE(R600_CP_RB_CNTL
,
561 R600_BUF_SWAP_32BIT
|
563 RADEON_READ(R600_CP_RB_CNTL
) |
565 RADEON_WRITE(R600_SCRATCH_UMSK
, 0);
569 int r600_do_engine_reset(struct drm_device
*dev
)
571 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
572 u32 cp_ptr
, cp_me_cntl
, cp_rb_cntl
;
574 DRM_INFO("Resetting GPU\n");
576 cp_ptr
= RADEON_READ(R600_CP_RB_WPTR
);
577 cp_me_cntl
= RADEON_READ(R600_CP_ME_CNTL
);
578 RADEON_WRITE(R600_CP_ME_CNTL
, R600_CP_ME_HALT
);
580 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0x7fff);
581 RADEON_READ(R600_GRBM_SOFT_RESET
);
583 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
584 RADEON_READ(R600_GRBM_SOFT_RESET
);
586 RADEON_WRITE(R600_CP_RB_WPTR_DELAY
, 0);
587 cp_rb_cntl
= RADEON_READ(R600_CP_RB_CNTL
);
588 RADEON_WRITE(R600_CP_RB_CNTL
,
590 R600_BUF_SWAP_32BIT
|
592 R600_RB_RPTR_WR_ENA
);
594 RADEON_WRITE(R600_CP_RB_RPTR_WR
, cp_ptr
);
595 RADEON_WRITE(R600_CP_RB_WPTR
, cp_ptr
);
596 RADEON_WRITE(R600_CP_RB_CNTL
, cp_rb_cntl
);
597 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me_cntl
);
599 /* Reset the CP ring */
600 r600_do_cp_reset(dev_priv
);
602 /* The CP is no longer running after an engine reset */
603 dev_priv
->cp_running
= 0;
605 /* Reset any pending vertex, indirect buffers */
606 radeon_freelist_reset(dev
);
612 static u32
r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
614 u32 backend_disable_mask
)
617 u32 enabled_backends_mask
;
618 u32 enabled_backends_count
;
620 u32 swizzle_pipe
[R6XX_MAX_PIPES
];
624 if (num_tile_pipes
> R6XX_MAX_PIPES
)
625 num_tile_pipes
= R6XX_MAX_PIPES
;
626 if (num_tile_pipes
< 1)
628 if (num_backends
> R6XX_MAX_BACKENDS
)
629 num_backends
= R6XX_MAX_BACKENDS
;
630 if (num_backends
< 1)
633 enabled_backends_mask
= 0;
634 enabled_backends_count
= 0;
635 for (i
= 0; i
< R6XX_MAX_BACKENDS
; ++i
) {
636 if (((backend_disable_mask
>> i
) & 1) == 0) {
637 enabled_backends_mask
|= (1 << i
);
638 ++enabled_backends_count
;
640 if (enabled_backends_count
== num_backends
)
644 if (enabled_backends_count
== 0) {
645 enabled_backends_mask
= 1;
646 enabled_backends_count
= 1;
649 if (enabled_backends_count
!= num_backends
)
650 num_backends
= enabled_backends_count
;
652 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R6XX_MAX_PIPES
);
653 switch (num_tile_pipes
) {
709 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
710 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
711 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
713 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
715 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
721 static int r600_count_pipe_bits(uint32_t val
)
724 for (i
= 0; i
< 32; i
++) {
731 static void r600_gfx_init(struct drm_device
*dev
,
732 drm_radeon_private_t
*dev_priv
)
734 int i
, j
, num_qd_pipes
;
738 u32 num_gs_verts_per_thread
;
740 u32 gs_prim_buffer_depth
= 0;
741 u32 sq_ms_fifo_sizes
;
743 u32 sq_gpr_resource_mgmt_1
= 0;
744 u32 sq_gpr_resource_mgmt_2
= 0;
745 u32 sq_thread_resource_mgmt
= 0;
746 u32 sq_stack_resource_mgmt_1
= 0;
747 u32 sq_stack_resource_mgmt_2
= 0;
748 u32 hdp_host_path_cntl
;
750 u32 gb_tiling_config
= 0;
751 u32 cc_rb_backend_disable
;
752 u32 cc_gc_shader_pipe_config
;
755 /* setup chip specs */
756 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
758 dev_priv
->r600_max_pipes
= 4;
759 dev_priv
->r600_max_tile_pipes
= 8;
760 dev_priv
->r600_max_simds
= 4;
761 dev_priv
->r600_max_backends
= 4;
762 dev_priv
->r600_max_gprs
= 256;
763 dev_priv
->r600_max_threads
= 192;
764 dev_priv
->r600_max_stack_entries
= 256;
765 dev_priv
->r600_max_hw_contexts
= 8;
766 dev_priv
->r600_max_gs_threads
= 16;
767 dev_priv
->r600_sx_max_export_size
= 128;
768 dev_priv
->r600_sx_max_export_pos_size
= 16;
769 dev_priv
->r600_sx_max_export_smx_size
= 128;
770 dev_priv
->r600_sq_num_cf_insts
= 2;
774 dev_priv
->r600_max_pipes
= 2;
775 dev_priv
->r600_max_tile_pipes
= 2;
776 dev_priv
->r600_max_simds
= 3;
777 dev_priv
->r600_max_backends
= 1;
778 dev_priv
->r600_max_gprs
= 128;
779 dev_priv
->r600_max_threads
= 192;
780 dev_priv
->r600_max_stack_entries
= 128;
781 dev_priv
->r600_max_hw_contexts
= 8;
782 dev_priv
->r600_max_gs_threads
= 4;
783 dev_priv
->r600_sx_max_export_size
= 128;
784 dev_priv
->r600_sx_max_export_pos_size
= 16;
785 dev_priv
->r600_sx_max_export_smx_size
= 128;
786 dev_priv
->r600_sq_num_cf_insts
= 2;
792 dev_priv
->r600_max_pipes
= 1;
793 dev_priv
->r600_max_tile_pipes
= 1;
794 dev_priv
->r600_max_simds
= 2;
795 dev_priv
->r600_max_backends
= 1;
796 dev_priv
->r600_max_gprs
= 128;
797 dev_priv
->r600_max_threads
= 192;
798 dev_priv
->r600_max_stack_entries
= 128;
799 dev_priv
->r600_max_hw_contexts
= 4;
800 dev_priv
->r600_max_gs_threads
= 4;
801 dev_priv
->r600_sx_max_export_size
= 128;
802 dev_priv
->r600_sx_max_export_pos_size
= 16;
803 dev_priv
->r600_sx_max_export_smx_size
= 128;
804 dev_priv
->r600_sq_num_cf_insts
= 1;
807 dev_priv
->r600_max_pipes
= 4;
808 dev_priv
->r600_max_tile_pipes
= 4;
809 dev_priv
->r600_max_simds
= 4;
810 dev_priv
->r600_max_backends
= 4;
811 dev_priv
->r600_max_gprs
= 192;
812 dev_priv
->r600_max_threads
= 192;
813 dev_priv
->r600_max_stack_entries
= 256;
814 dev_priv
->r600_max_hw_contexts
= 8;
815 dev_priv
->r600_max_gs_threads
= 16;
816 dev_priv
->r600_sx_max_export_size
= 128;
817 dev_priv
->r600_sx_max_export_pos_size
= 16;
818 dev_priv
->r600_sx_max_export_smx_size
= 128;
819 dev_priv
->r600_sq_num_cf_insts
= 2;
827 for (i
= 0; i
< 32; i
++) {
828 RADEON_WRITE((0x2c14 + j
), 0x00000000);
829 RADEON_WRITE((0x2c18 + j
), 0x00000000);
830 RADEON_WRITE((0x2c1c + j
), 0x00000000);
831 RADEON_WRITE((0x2c20 + j
), 0x00000000);
832 RADEON_WRITE((0x2c24 + j
), 0x00000000);
836 RADEON_WRITE(R600_GRBM_CNTL
, R600_GRBM_READ_TIMEOUT(0xff));
838 /* setup tiling, simd, pipe config */
839 ramcfg
= RADEON_READ(R600_RAMCFG
);
841 switch (dev_priv
->r600_max_tile_pipes
) {
843 gb_tiling_config
|= R600_PIPE_TILING(0);
846 gb_tiling_config
|= R600_PIPE_TILING(1);
849 gb_tiling_config
|= R600_PIPE_TILING(2);
852 gb_tiling_config
|= R600_PIPE_TILING(3);
858 gb_tiling_config
|= R600_BANK_TILING((ramcfg
>> R600_NOOFBANK_SHIFT
) & R600_NOOFBANK_MASK
);
860 gb_tiling_config
|= R600_GROUP_SIZE(0);
862 if (((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
) > 3) {
863 gb_tiling_config
|= R600_ROW_TILING(3);
864 gb_tiling_config
|= R600_SAMPLE_SPLIT(3);
867 R600_ROW_TILING(((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
));
869 R600_SAMPLE_SPLIT(((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
));
872 gb_tiling_config
|= R600_BANK_SWAPS(1);
874 cc_rb_backend_disable
= RADEON_READ(R600_CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
875 cc_rb_backend_disable
|=
876 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK
<< dev_priv
->r600_max_backends
) & R6XX_MAX_BACKENDS_MASK
);
878 cc_gc_shader_pipe_config
= RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
879 cc_gc_shader_pipe_config
|=
880 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK
<< dev_priv
->r600_max_pipes
) & R6XX_MAX_PIPES_MASK
);
881 cc_gc_shader_pipe_config
|=
882 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK
<< dev_priv
->r600_max_simds
) & R6XX_MAX_SIMDS_MASK
);
884 backend_map
= r600_get_tile_pipe_to_backend_map(dev_priv
->r600_max_tile_pipes
,
886 r600_count_pipe_bits((cc_rb_backend_disable
&
887 R6XX_MAX_BACKENDS_MASK
) >> 16)),
888 (cc_rb_backend_disable
>> 16));
889 gb_tiling_config
|= R600_BACKEND_MAP(backend_map
);
891 RADEON_WRITE(R600_GB_TILING_CONFIG
, gb_tiling_config
);
892 RADEON_WRITE(R600_DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
893 RADEON_WRITE(R600_HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
894 if (gb_tiling_config
& 0xc0) {
895 dev_priv
->r600_group_size
= 512;
897 dev_priv
->r600_group_size
= 256;
899 dev_priv
->r600_npipes
= 1 << ((gb_tiling_config
>> 1) & 0x7);
900 if (gb_tiling_config
& 0x30) {
901 dev_priv
->r600_nbanks
= 8;
903 dev_priv
->r600_nbanks
= 4;
906 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
907 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
908 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
911 R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& R600_INACTIVE_QD_PIPES_MASK
) >> 8);
912 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & R600_DEALLOC_DIST_MASK
);
913 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & R600_VTX_REUSE_DEPTH_MASK
);
915 /* set HW defaults for 3D engine */
916 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS
, (R600_ROQ_IB1_START(0x16) |
917 R600_ROQ_IB2_START(0x2b)));
919 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS
, (R600_MEQ_END(0x40) |
920 R600_ROQ_END(0x40)));
922 RADEON_WRITE(R600_TA_CNTL_AUX
, (R600_DISABLE_CUBE_ANISO
|
927 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
)
928 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL
, 0x00000021);
930 sx_debug_1
= RADEON_READ(R600_SX_DEBUG_1
);
931 sx_debug_1
|= R600_SMX_EVENT_RELEASE
;
932 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_R600
))
933 sx_debug_1
|= R600_ENABLE_NEW_SMX_ADDRESS
;
934 RADEON_WRITE(R600_SX_DEBUG_1
, sx_debug_1
);
936 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) ||
937 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
) ||
938 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
939 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
940 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
941 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
))
942 RADEON_WRITE(R600_DB_DEBUG
, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
944 RADEON_WRITE(R600_DB_DEBUG
, 0);
946 RADEON_WRITE(R600_DB_WATERMARKS
, (R600_DEPTH_FREE(4) |
947 R600_DEPTH_FLUSH(16) |
948 R600_DEPTH_PENDING_FREE(4) |
949 R600_DEPTH_CACHELINE_FREE(16)));
950 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
951 RADEON_WRITE(R600_VGT_NUM_INSTANCES
, 0);
953 RADEON_WRITE(R600_SPI_CONFIG_CNTL
, R600_GPR_WRITE_PRIORITY(0));
954 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1
, R600_VTX_DONE_DELAY(0));
956 sq_ms_fifo_sizes
= RADEON_READ(R600_SQ_MS_FIFO_SIZES
);
957 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
958 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
959 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
960 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
)) {
961 sq_ms_fifo_sizes
= (R600_CACHE_FIFO_SIZE(0xa) |
962 R600_FETCH_FIFO_HIWATER(0xa) |
963 R600_DONE_FIFO_HIWATER(0xe0) |
964 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
965 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) ||
966 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
)) {
967 sq_ms_fifo_sizes
&= ~R600_DONE_FIFO_HIWATER(0xff);
968 sq_ms_fifo_sizes
|= R600_DONE_FIFO_HIWATER(0x4);
970 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
972 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
973 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
975 sq_config
= RADEON_READ(R600_SQ_CONFIG
);
976 sq_config
&= ~(R600_PS_PRIO(3) |
980 sq_config
|= (R600_DX9_CONSTS
|
987 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) {
988 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(124) |
989 R600_NUM_VS_GPRS(124) |
990 R600_NUM_CLAUSE_TEMP_GPRS(4));
991 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(0) |
992 R600_NUM_ES_GPRS(0));
993 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(136) |
994 R600_NUM_VS_THREADS(48) |
995 R600_NUM_GS_THREADS(4) |
996 R600_NUM_ES_THREADS(4));
997 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(128) |
998 R600_NUM_VS_STACK_ENTRIES(128));
999 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(0) |
1000 R600_NUM_ES_STACK_ENTRIES(0));
1001 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
1002 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
1003 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
1004 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
)) {
1005 /* no vertex cache */
1006 sq_config
&= ~R600_VC_ENABLE
;
1008 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1009 R600_NUM_VS_GPRS(44) |
1010 R600_NUM_CLAUSE_TEMP_GPRS(2));
1011 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(17) |
1012 R600_NUM_ES_GPRS(17));
1013 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1014 R600_NUM_VS_THREADS(78) |
1015 R600_NUM_GS_THREADS(4) |
1016 R600_NUM_ES_THREADS(31));
1017 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(40) |
1018 R600_NUM_VS_STACK_ENTRIES(40));
1019 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(32) |
1020 R600_NUM_ES_STACK_ENTRIES(16));
1021 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
) ||
1022 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV635
)) {
1023 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1024 R600_NUM_VS_GPRS(44) |
1025 R600_NUM_CLAUSE_TEMP_GPRS(2));
1026 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(18) |
1027 R600_NUM_ES_GPRS(18));
1028 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1029 R600_NUM_VS_THREADS(78) |
1030 R600_NUM_GS_THREADS(4) |
1031 R600_NUM_ES_THREADS(31));
1032 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(40) |
1033 R600_NUM_VS_STACK_ENTRIES(40));
1034 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(32) |
1035 R600_NUM_ES_STACK_ENTRIES(16));
1036 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
) {
1037 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1038 R600_NUM_VS_GPRS(44) |
1039 R600_NUM_CLAUSE_TEMP_GPRS(2));
1040 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(17) |
1041 R600_NUM_ES_GPRS(17));
1042 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1043 R600_NUM_VS_THREADS(78) |
1044 R600_NUM_GS_THREADS(4) |
1045 R600_NUM_ES_THREADS(31));
1046 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(64) |
1047 R600_NUM_VS_STACK_ENTRIES(64));
1048 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(64) |
1049 R600_NUM_ES_STACK_ENTRIES(64));
1052 RADEON_WRITE(R600_SQ_CONFIG
, sq_config
);
1053 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1054 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1055 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1056 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1057 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1059 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
1060 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
1061 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
1062 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
))
1063 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, R600_CACHE_INVALIDATION(R600_TC_ONLY
));
1065 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, R600_CACHE_INVALIDATION(R600_VC_AND_TC
));
1067 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S
, (R600_S0_X(0xc) |
1071 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S
, (R600_S0_X(0xe) |
1079 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (R600_S0_X(0xe) |
1087 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (R600_S4_X(0x6) |
1097 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1101 gs_prim_buffer_depth
= 0;
1107 gs_prim_buffer_depth
= 32;
1110 gs_prim_buffer_depth
= 128;
1116 num_gs_verts_per_thread
= dev_priv
->r600_max_pipes
* 16;
1117 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
1118 /* Max value for this is 256 */
1119 if (vgt_gs_per_es
> 256)
1120 vgt_gs_per_es
= 256;
1122 RADEON_WRITE(R600_VGT_ES_PER_GS
, 128);
1123 RADEON_WRITE(R600_VGT_GS_PER_ES
, vgt_gs_per_es
);
1124 RADEON_WRITE(R600_VGT_GS_PER_VS
, 2);
1125 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE
, 16);
1127 /* more default values. 2D/3D driver should adjust as needed */
1128 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE
, 0);
1129 RADEON_WRITE(R600_VGT_STRMOUT_EN
, 0);
1130 RADEON_WRITE(R600_SX_MISC
, 0);
1131 RADEON_WRITE(R600_PA_SC_MODE_CNTL
, 0);
1132 RADEON_WRITE(R600_PA_SC_AA_CONFIG
, 0);
1133 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE
, 0);
1134 RADEON_WRITE(R600_SPI_INPUT_Z
, 0);
1135 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0
, R600_NUM_INTERP(2));
1136 RADEON_WRITE(R600_CB_COLOR7_FRAG
, 0);
1138 /* clear render buffer base addresses */
1139 RADEON_WRITE(R600_CB_COLOR0_BASE
, 0);
1140 RADEON_WRITE(R600_CB_COLOR1_BASE
, 0);
1141 RADEON_WRITE(R600_CB_COLOR2_BASE
, 0);
1142 RADEON_WRITE(R600_CB_COLOR3_BASE
, 0);
1143 RADEON_WRITE(R600_CB_COLOR4_BASE
, 0);
1144 RADEON_WRITE(R600_CB_COLOR5_BASE
, 0);
1145 RADEON_WRITE(R600_CB_COLOR6_BASE
, 0);
1146 RADEON_WRITE(R600_CB_COLOR7_BASE
, 0);
1148 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1153 tc_cntl
= R600_TC_L2_SIZE(8);
1157 tc_cntl
= R600_TC_L2_SIZE(4);
1160 tc_cntl
= R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT
;
1163 tc_cntl
= R600_TC_L2_SIZE(0);
1167 RADEON_WRITE(R600_TC_CNTL
, tc_cntl
);
1169 hdp_host_path_cntl
= RADEON_READ(R600_HDP_HOST_PATH_CNTL
);
1170 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1172 arb_pop
= RADEON_READ(R600_ARB_POP
);
1173 arb_pop
|= R600_ENABLE_TC128
;
1174 RADEON_WRITE(R600_ARB_POP
, arb_pop
);
1176 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1177 RADEON_WRITE(R600_PA_CL_ENHANCE
, (R600_CLIP_VTX_REORDER_ENA
|
1178 R600_NUM_CLIP_SEQ(3)));
1179 RADEON_WRITE(R600_PA_SC_ENHANCE
, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1183 static u32
r700_get_tile_pipe_to_backend_map(drm_radeon_private_t
*dev_priv
,
1186 u32 backend_disable_mask
)
1188 u32 backend_map
= 0;
1189 u32 enabled_backends_mask
;
1190 u32 enabled_backends_count
;
1192 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
1195 bool force_no_swizzle
;
1197 if (num_tile_pipes
> R7XX_MAX_PIPES
)
1198 num_tile_pipes
= R7XX_MAX_PIPES
;
1199 if (num_tile_pipes
< 1)
1201 if (num_backends
> R7XX_MAX_BACKENDS
)
1202 num_backends
= R7XX_MAX_BACKENDS
;
1203 if (num_backends
< 1)
1206 enabled_backends_mask
= 0;
1207 enabled_backends_count
= 0;
1208 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
1209 if (((backend_disable_mask
>> i
) & 1) == 0) {
1210 enabled_backends_mask
|= (1 << i
);
1211 ++enabled_backends_count
;
1213 if (enabled_backends_count
== num_backends
)
1217 if (enabled_backends_count
== 0) {
1218 enabled_backends_mask
= 1;
1219 enabled_backends_count
= 1;
1222 if (enabled_backends_count
!= num_backends
)
1223 num_backends
= enabled_backends_count
;
1225 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1228 force_no_swizzle
= false;
1233 force_no_swizzle
= true;
1237 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
1238 switch (num_tile_pipes
) {
1240 swizzle_pipe
[0] = 0;
1243 swizzle_pipe
[0] = 0;
1244 swizzle_pipe
[1] = 1;
1247 if (force_no_swizzle
) {
1248 swizzle_pipe
[0] = 0;
1249 swizzle_pipe
[1] = 1;
1250 swizzle_pipe
[2] = 2;
1252 swizzle_pipe
[0] = 0;
1253 swizzle_pipe
[1] = 2;
1254 swizzle_pipe
[2] = 1;
1258 if (force_no_swizzle
) {
1259 swizzle_pipe
[0] = 0;
1260 swizzle_pipe
[1] = 1;
1261 swizzle_pipe
[2] = 2;
1262 swizzle_pipe
[3] = 3;
1264 swizzle_pipe
[0] = 0;
1265 swizzle_pipe
[1] = 2;
1266 swizzle_pipe
[2] = 3;
1267 swizzle_pipe
[3] = 1;
1271 if (force_no_swizzle
) {
1272 swizzle_pipe
[0] = 0;
1273 swizzle_pipe
[1] = 1;
1274 swizzle_pipe
[2] = 2;
1275 swizzle_pipe
[3] = 3;
1276 swizzle_pipe
[4] = 4;
1278 swizzle_pipe
[0] = 0;
1279 swizzle_pipe
[1] = 2;
1280 swizzle_pipe
[2] = 4;
1281 swizzle_pipe
[3] = 1;
1282 swizzle_pipe
[4] = 3;
1286 if (force_no_swizzle
) {
1287 swizzle_pipe
[0] = 0;
1288 swizzle_pipe
[1] = 1;
1289 swizzle_pipe
[2] = 2;
1290 swizzle_pipe
[3] = 3;
1291 swizzle_pipe
[4] = 4;
1292 swizzle_pipe
[5] = 5;
1294 swizzle_pipe
[0] = 0;
1295 swizzle_pipe
[1] = 2;
1296 swizzle_pipe
[2] = 4;
1297 swizzle_pipe
[3] = 5;
1298 swizzle_pipe
[4] = 3;
1299 swizzle_pipe
[5] = 1;
1303 if (force_no_swizzle
) {
1304 swizzle_pipe
[0] = 0;
1305 swizzle_pipe
[1] = 1;
1306 swizzle_pipe
[2] = 2;
1307 swizzle_pipe
[3] = 3;
1308 swizzle_pipe
[4] = 4;
1309 swizzle_pipe
[5] = 5;
1310 swizzle_pipe
[6] = 6;
1312 swizzle_pipe
[0] = 0;
1313 swizzle_pipe
[1] = 2;
1314 swizzle_pipe
[2] = 4;
1315 swizzle_pipe
[3] = 6;
1316 swizzle_pipe
[4] = 3;
1317 swizzle_pipe
[5] = 1;
1318 swizzle_pipe
[6] = 5;
1322 if (force_no_swizzle
) {
1323 swizzle_pipe
[0] = 0;
1324 swizzle_pipe
[1] = 1;
1325 swizzle_pipe
[2] = 2;
1326 swizzle_pipe
[3] = 3;
1327 swizzle_pipe
[4] = 4;
1328 swizzle_pipe
[5] = 5;
1329 swizzle_pipe
[6] = 6;
1330 swizzle_pipe
[7] = 7;
1332 swizzle_pipe
[0] = 0;
1333 swizzle_pipe
[1] = 2;
1334 swizzle_pipe
[2] = 4;
1335 swizzle_pipe
[3] = 6;
1336 swizzle_pipe
[4] = 3;
1337 swizzle_pipe
[5] = 1;
1338 swizzle_pipe
[6] = 7;
1339 swizzle_pipe
[7] = 5;
1345 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1346 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1347 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
1349 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
1351 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
1357 static void r700_gfx_init(struct drm_device
*dev
,
1358 drm_radeon_private_t
*dev_priv
)
1360 int i
, j
, num_qd_pipes
;
1365 u32 num_gs_verts_per_thread
;
1367 u32 gs_prim_buffer_depth
= 0;
1368 u32 sq_ms_fifo_sizes
;
1370 u32 sq_thread_resource_mgmt
;
1371 u32 hdp_host_path_cntl
;
1372 u32 sq_dyn_gpr_size_simd_ab_0
;
1374 u32 gb_tiling_config
= 0;
1375 u32 cc_rb_backend_disable
;
1376 u32 cc_gc_shader_pipe_config
;
1380 /* setup chip specs */
1381 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1383 dev_priv
->r600_max_pipes
= 4;
1384 dev_priv
->r600_max_tile_pipes
= 8;
1385 dev_priv
->r600_max_simds
= 10;
1386 dev_priv
->r600_max_backends
= 4;
1387 dev_priv
->r600_max_gprs
= 256;
1388 dev_priv
->r600_max_threads
= 248;
1389 dev_priv
->r600_max_stack_entries
= 512;
1390 dev_priv
->r600_max_hw_contexts
= 8;
1391 dev_priv
->r600_max_gs_threads
= 16 * 2;
1392 dev_priv
->r600_sx_max_export_size
= 128;
1393 dev_priv
->r600_sx_max_export_pos_size
= 16;
1394 dev_priv
->r600_sx_max_export_smx_size
= 112;
1395 dev_priv
->r600_sq_num_cf_insts
= 2;
1397 dev_priv
->r700_sx_num_of_sets
= 7;
1398 dev_priv
->r700_sc_prim_fifo_size
= 0xF9;
1399 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1400 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1403 dev_priv
->r600_max_pipes
= 2;
1404 dev_priv
->r600_max_tile_pipes
= 4;
1405 dev_priv
->r600_max_simds
= 8;
1406 dev_priv
->r600_max_backends
= 2;
1407 dev_priv
->r600_max_gprs
= 128;
1408 dev_priv
->r600_max_threads
= 248;
1409 dev_priv
->r600_max_stack_entries
= 256;
1410 dev_priv
->r600_max_hw_contexts
= 8;
1411 dev_priv
->r600_max_gs_threads
= 16 * 2;
1412 dev_priv
->r600_sx_max_export_size
= 256;
1413 dev_priv
->r600_sx_max_export_pos_size
= 32;
1414 dev_priv
->r600_sx_max_export_smx_size
= 224;
1415 dev_priv
->r600_sq_num_cf_insts
= 2;
1417 dev_priv
->r700_sx_num_of_sets
= 7;
1418 dev_priv
->r700_sc_prim_fifo_size
= 0xf9;
1419 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1420 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1421 if (dev_priv
->r600_sx_max_export_pos_size
> 16) {
1422 dev_priv
->r600_sx_max_export_pos_size
-= 16;
1423 dev_priv
->r600_sx_max_export_smx_size
+= 16;
1427 dev_priv
->r600_max_pipes
= 2;
1428 dev_priv
->r600_max_tile_pipes
= 2;
1429 dev_priv
->r600_max_simds
= 2;
1430 dev_priv
->r600_max_backends
= 1;
1431 dev_priv
->r600_max_gprs
= 256;
1432 dev_priv
->r600_max_threads
= 192;
1433 dev_priv
->r600_max_stack_entries
= 256;
1434 dev_priv
->r600_max_hw_contexts
= 4;
1435 dev_priv
->r600_max_gs_threads
= 8 * 2;
1436 dev_priv
->r600_sx_max_export_size
= 128;
1437 dev_priv
->r600_sx_max_export_pos_size
= 16;
1438 dev_priv
->r600_sx_max_export_smx_size
= 112;
1439 dev_priv
->r600_sq_num_cf_insts
= 1;
1441 dev_priv
->r700_sx_num_of_sets
= 7;
1442 dev_priv
->r700_sc_prim_fifo_size
= 0x40;
1443 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1444 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1447 dev_priv
->r600_max_pipes
= 4;
1448 dev_priv
->r600_max_tile_pipes
= 4;
1449 dev_priv
->r600_max_simds
= 8;
1450 dev_priv
->r600_max_backends
= 4;
1451 dev_priv
->r600_max_gprs
= 256;
1452 dev_priv
->r600_max_threads
= 248;
1453 dev_priv
->r600_max_stack_entries
= 512;
1454 dev_priv
->r600_max_hw_contexts
= 8;
1455 dev_priv
->r600_max_gs_threads
= 16 * 2;
1456 dev_priv
->r600_sx_max_export_size
= 256;
1457 dev_priv
->r600_sx_max_export_pos_size
= 32;
1458 dev_priv
->r600_sx_max_export_smx_size
= 224;
1459 dev_priv
->r600_sq_num_cf_insts
= 2;
1461 dev_priv
->r700_sx_num_of_sets
= 7;
1462 dev_priv
->r700_sc_prim_fifo_size
= 0x100;
1463 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1464 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1466 if (dev_priv
->r600_sx_max_export_pos_size
> 16) {
1467 dev_priv
->r600_sx_max_export_pos_size
-= 16;
1468 dev_priv
->r600_sx_max_export_smx_size
+= 16;
1475 /* Initialize HDP */
1477 for (i
= 0; i
< 32; i
++) {
1478 RADEON_WRITE((0x2c14 + j
), 0x00000000);
1479 RADEON_WRITE((0x2c18 + j
), 0x00000000);
1480 RADEON_WRITE((0x2c1c + j
), 0x00000000);
1481 RADEON_WRITE((0x2c20 + j
), 0x00000000);
1482 RADEON_WRITE((0x2c24 + j
), 0x00000000);
1486 RADEON_WRITE(R600_GRBM_CNTL
, R600_GRBM_READ_TIMEOUT(0xff));
1488 /* setup tiling, simd, pipe config */
1489 mc_arb_ramcfg
= RADEON_READ(R700_MC_ARB_RAMCFG
);
1491 switch (dev_priv
->r600_max_tile_pipes
) {
1493 gb_tiling_config
|= R600_PIPE_TILING(0);
1496 gb_tiling_config
|= R600_PIPE_TILING(1);
1499 gb_tiling_config
|= R600_PIPE_TILING(2);
1502 gb_tiling_config
|= R600_PIPE_TILING(3);
1508 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV770
)
1509 gb_tiling_config
|= R600_BANK_TILING(1);
1511 gb_tiling_config
|= R600_BANK_TILING((mc_arb_ramcfg
>> R700_NOOFBANK_SHIFT
) & R700_NOOFBANK_MASK
);
1513 gb_tiling_config
|= R600_GROUP_SIZE(0);
1515 if (((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
) > 3) {
1516 gb_tiling_config
|= R600_ROW_TILING(3);
1517 gb_tiling_config
|= R600_SAMPLE_SPLIT(3);
1520 R600_ROW_TILING(((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
));
1522 R600_SAMPLE_SPLIT(((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
));
1525 gb_tiling_config
|= R600_BANK_SWAPS(1);
1527 cc_rb_backend_disable
= RADEON_READ(R600_CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1528 cc_rb_backend_disable
|=
1529 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< dev_priv
->r600_max_backends
) & R7XX_MAX_BACKENDS_MASK
);
1531 cc_gc_shader_pipe_config
= RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
1532 cc_gc_shader_pipe_config
|=
1533 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< dev_priv
->r600_max_pipes
) & R7XX_MAX_PIPES_MASK
);
1534 cc_gc_shader_pipe_config
|=
1535 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< dev_priv
->r600_max_simds
) & R7XX_MAX_SIMDS_MASK
);
1537 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV740
)
1540 backend_map
= r700_get_tile_pipe_to_backend_map(dev_priv
,
1541 dev_priv
->r600_max_tile_pipes
,
1542 (R7XX_MAX_BACKENDS
-
1543 r600_count_pipe_bits((cc_rb_backend_disable
&
1544 R7XX_MAX_BACKENDS_MASK
) >> 16)),
1545 (cc_rb_backend_disable
>> 16));
1546 gb_tiling_config
|= R600_BACKEND_MAP(backend_map
);
1548 RADEON_WRITE(R600_GB_TILING_CONFIG
, gb_tiling_config
);
1549 RADEON_WRITE(R600_DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
1550 RADEON_WRITE(R600_HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
1551 if (gb_tiling_config
& 0xc0) {
1552 dev_priv
->r600_group_size
= 512;
1554 dev_priv
->r600_group_size
= 256;
1556 dev_priv
->r600_npipes
= 1 << ((gb_tiling_config
>> 1) & 0x7);
1557 if (gb_tiling_config
& 0x30) {
1558 dev_priv
->r600_nbanks
= 8;
1560 dev_priv
->r600_nbanks
= 4;
1563 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1564 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1565 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1567 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1568 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE
, 0);
1569 RADEON_WRITE(R700_CGTS_TCC_DISABLE
, 0);
1570 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE
, 0);
1571 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE
, 0);
1574 R7XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& R600_INACTIVE_QD_PIPES_MASK
) >> 8);
1575 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & R600_DEALLOC_DIST_MASK
);
1576 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & R600_VTX_REUSE_DEPTH_MASK
);
1578 /* set HW defaults for 3D engine */
1579 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS
, (R600_ROQ_IB1_START(0x16) |
1580 R600_ROQ_IB2_START(0x2b)));
1582 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS
, R700_STQ_SPLIT(0x30));
1584 ta_aux_cntl
= RADEON_READ(R600_TA_CNTL_AUX
);
1585 RADEON_WRITE(R600_TA_CNTL_AUX
, ta_aux_cntl
| R600_DISABLE_CUBE_ANISO
);
1587 sx_debug_1
= RADEON_READ(R700_SX_DEBUG_1
);
1588 sx_debug_1
|= R700_ENABLE_NEW_SMX_ADDRESS
;
1589 RADEON_WRITE(R700_SX_DEBUG_1
, sx_debug_1
);
1591 smx_dc_ctl0
= RADEON_READ(R600_SMX_DC_CTL0
);
1592 smx_dc_ctl0
&= ~R700_CACHE_DEPTH(0x1ff);
1593 smx_dc_ctl0
|= R700_CACHE_DEPTH((dev_priv
->r700_sx_num_of_sets
* 64) - 1);
1594 RADEON_WRITE(R600_SMX_DC_CTL0
, smx_dc_ctl0
);
1596 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) != CHIP_RV740
)
1597 RADEON_WRITE(R700_SMX_EVENT_CTL
, (R700_ES_FLUSH_CTL(4) |
1598 R700_GS_FLUSH_CTL(4) |
1599 R700_ACK_FLUSH_CTL(3) |
1600 R700_SYNC_FLUSH_CTL
));
1602 db_debug3
= RADEON_READ(R700_DB_DEBUG3
);
1603 db_debug3
&= ~R700_DB_CLK_OFF_DELAY(0x1f);
1604 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1607 db_debug3
|= R700_DB_CLK_OFF_DELAY(0x1f);
1612 db_debug3
|= R700_DB_CLK_OFF_DELAY(2);
1615 RADEON_WRITE(R700_DB_DEBUG3
, db_debug3
);
1617 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) != CHIP_RV770
) {
1618 db_debug4
= RADEON_READ(RV700_DB_DEBUG4
);
1619 db_debug4
|= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER
;
1620 RADEON_WRITE(RV700_DB_DEBUG4
, db_debug4
);
1623 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES
, (R600_COLOR_BUFFER_SIZE((dev_priv
->r600_sx_max_export_size
/ 4) - 1) |
1624 R600_POSITION_BUFFER_SIZE((dev_priv
->r600_sx_max_export_pos_size
/ 4) - 1) |
1625 R600_SMX_BUFFER_SIZE((dev_priv
->r600_sx_max_export_smx_size
/ 4) - 1)));
1627 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX
, (R700_SC_PRIM_FIFO_SIZE(dev_priv
->r700_sc_prim_fifo_size
) |
1628 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv
->r700_sc_hiz_tile_fifo_size
) |
1629 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv
->r700_sc_earlyz_tile_fifo_fize
)));
1631 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1633 RADEON_WRITE(R600_VGT_NUM_INSTANCES
, 1);
1635 RADEON_WRITE(R600_SPI_CONFIG_CNTL
, R600_GPR_WRITE_PRIORITY(0));
1637 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1
, R600_VTX_DONE_DELAY(4));
1639 RADEON_WRITE(R600_CP_PERFMON_CNTL
, 0);
1641 sq_ms_fifo_sizes
= (R600_CACHE_FIFO_SIZE(16 * dev_priv
->r600_sq_num_cf_insts
) |
1642 R600_DONE_FIFO_HIWATER(0xe0) |
1643 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1644 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1648 sq_ms_fifo_sizes
|= R600_FETCH_FIFO_HIWATER(0x1);
1652 sq_ms_fifo_sizes
|= R600_FETCH_FIFO_HIWATER(0x4);
1655 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
1657 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1658 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1660 sq_config
= RADEON_READ(R600_SQ_CONFIG
);
1661 sq_config
&= ~(R600_PS_PRIO(3) |
1665 sq_config
|= (R600_DX9_CONSTS
|
1672 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)
1673 /* no vertex cache */
1674 sq_config
&= ~R600_VC_ENABLE
;
1676 RADEON_WRITE(R600_SQ_CONFIG
, sq_config
);
1678 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1
, (R600_NUM_PS_GPRS((dev_priv
->r600_max_gprs
* 24)/64) |
1679 R600_NUM_VS_GPRS((dev_priv
->r600_max_gprs
* 24)/64) |
1680 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv
->r600_max_gprs
* 24)/64)/2)));
1682 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2
, (R600_NUM_GS_GPRS((dev_priv
->r600_max_gprs
* 7)/64) |
1683 R600_NUM_ES_GPRS((dev_priv
->r600_max_gprs
* 7)/64)));
1685 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS((dev_priv
->r600_max_threads
* 4)/8) |
1686 R600_NUM_VS_THREADS((dev_priv
->r600_max_threads
* 2)/8) |
1687 R600_NUM_ES_THREADS((dev_priv
->r600_max_threads
* 1)/8));
1688 if (((dev_priv
->r600_max_threads
* 1) / 8) > dev_priv
->r600_max_gs_threads
)
1689 sq_thread_resource_mgmt
|= R600_NUM_GS_THREADS(dev_priv
->r600_max_gs_threads
);
1691 sq_thread_resource_mgmt
|= R600_NUM_GS_THREADS((dev_priv
->r600_max_gs_threads
* 1)/8);
1692 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1694 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1
, (R600_NUM_PS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4) |
1695 R600_NUM_VS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4)));
1697 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2
, (R600_NUM_GS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4) |
1698 R600_NUM_ES_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4)));
1700 sq_dyn_gpr_size_simd_ab_0
= (R700_SIMDA_RING0((dev_priv
->r600_max_gprs
* 38)/64) |
1701 R700_SIMDA_RING1((dev_priv
->r600_max_gprs
* 38)/64) |
1702 R700_SIMDB_RING0((dev_priv
->r600_max_gprs
* 38)/64) |
1703 R700_SIMDB_RING1((dev_priv
->r600_max_gprs
* 38)/64));
1705 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
1706 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
1707 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
1708 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
1709 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
1710 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
1711 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
1712 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
1714 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS
, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1715 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1717 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)
1718 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, (R600_CACHE_INVALIDATION(R600_TC_ONLY
) |
1719 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO
)));
1721 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, (R600_CACHE_INVALIDATION(R600_VC_AND_TC
) |
1722 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO
)));
1724 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1728 gs_prim_buffer_depth
= 384;
1731 gs_prim_buffer_depth
= 128;
1737 num_gs_verts_per_thread
= dev_priv
->r600_max_pipes
* 16;
1738 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
1739 /* Max value for this is 256 */
1740 if (vgt_gs_per_es
> 256)
1741 vgt_gs_per_es
= 256;
1743 RADEON_WRITE(R600_VGT_ES_PER_GS
, 128);
1744 RADEON_WRITE(R600_VGT_GS_PER_ES
, vgt_gs_per_es
);
1745 RADEON_WRITE(R600_VGT_GS_PER_VS
, 2);
1747 /* more default values. 2D/3D driver should adjust as needed */
1748 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE
, 16);
1749 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE
, 0);
1750 RADEON_WRITE(R600_VGT_STRMOUT_EN
, 0);
1751 RADEON_WRITE(R600_SX_MISC
, 0);
1752 RADEON_WRITE(R600_PA_SC_MODE_CNTL
, 0);
1753 RADEON_WRITE(R700_PA_SC_EDGERULE
, 0xaaaaaaaa);
1754 RADEON_WRITE(R600_PA_SC_AA_CONFIG
, 0);
1755 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE
, 0xffff);
1756 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE
, 0);
1757 RADEON_WRITE(R600_SPI_INPUT_Z
, 0);
1758 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0
, R600_NUM_INTERP(2));
1759 RADEON_WRITE(R600_CB_COLOR7_FRAG
, 0);
1761 /* clear render buffer base addresses */
1762 RADEON_WRITE(R600_CB_COLOR0_BASE
, 0);
1763 RADEON_WRITE(R600_CB_COLOR1_BASE
, 0);
1764 RADEON_WRITE(R600_CB_COLOR2_BASE
, 0);
1765 RADEON_WRITE(R600_CB_COLOR3_BASE
, 0);
1766 RADEON_WRITE(R600_CB_COLOR4_BASE
, 0);
1767 RADEON_WRITE(R600_CB_COLOR5_BASE
, 0);
1768 RADEON_WRITE(R600_CB_COLOR6_BASE
, 0);
1769 RADEON_WRITE(R600_CB_COLOR7_BASE
, 0);
1771 RADEON_WRITE(R700_TCP_CNTL
, 0);
1773 hdp_host_path_cntl
= RADEON_READ(R600_HDP_HOST_PATH_CNTL
);
1774 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1776 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1778 RADEON_WRITE(R600_PA_CL_ENHANCE
, (R600_CLIP_VTX_REORDER_ENA
|
1779 R600_NUM_CLIP_SEQ(3)));
1783 static void r600_cp_init_ring_buffer(struct drm_device
*dev
,
1784 drm_radeon_private_t
*dev_priv
,
1785 struct drm_file
*file_priv
)
1787 struct drm_radeon_master_private
*master_priv
;
1791 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
1792 r700_gfx_init(dev
, dev_priv
);
1794 r600_gfx_init(dev
, dev_priv
);
1796 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
1797 RADEON_READ(R600_GRBM_SOFT_RESET
);
1799 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
1802 /* Set ring buffer size */
1804 RADEON_WRITE(R600_CP_RB_CNTL
,
1805 R600_BUF_SWAP_32BIT
|
1807 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1808 dev_priv
->ring
.size_l2qw
);
1810 RADEON_WRITE(R600_CP_RB_CNTL
,
1811 RADEON_RB_NO_UPDATE
|
1812 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1813 dev_priv
->ring
.size_l2qw
);
1816 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER
, 0x4);
1818 /* Set the write pointer delay */
1819 RADEON_WRITE(R600_CP_RB_WPTR_DELAY
, 0);
1822 RADEON_WRITE(R600_CP_RB_CNTL
,
1823 R600_BUF_SWAP_32BIT
|
1825 R600_RB_RPTR_WR_ENA
|
1826 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1827 dev_priv
->ring
.size_l2qw
);
1829 RADEON_WRITE(R600_CP_RB_CNTL
,
1831 R600_RB_RPTR_WR_ENA
|
1832 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1833 dev_priv
->ring
.size_l2qw
);
1836 /* Initialize the ring buffer's read and write pointers */
1837 RADEON_WRITE(R600_CP_RB_RPTR_WR
, 0);
1838 RADEON_WRITE(R600_CP_RB_WPTR
, 0);
1839 SET_RING_HEAD(dev_priv
, 0);
1840 dev_priv
->ring
.tail
= 0;
1843 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1844 rptr_addr
= dev_priv
->ring_rptr
->offset
1846 dev_priv
->gart_vm_start
;
1850 rptr_addr
= dev_priv
->ring_rptr
->offset
1851 - ((unsigned long) dev
->sg
->virtual)
1852 + dev_priv
->gart_vm_start
;
1854 RADEON_WRITE(R600_CP_RB_RPTR_ADDR
, (rptr_addr
& 0xfffffffc));
1855 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI
, upper_32_bits(rptr_addr
));
1858 RADEON_WRITE(R600_CP_RB_CNTL
,
1859 RADEON_BUF_SWAP_32BIT
|
1860 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1861 dev_priv
->ring
.size_l2qw
);
1863 RADEON_WRITE(R600_CP_RB_CNTL
,
1864 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1865 dev_priv
->ring
.size_l2qw
);
1869 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1871 radeon_write_agp_base(dev_priv
, dev
->agp
->base
);
1874 radeon_write_agp_location(dev_priv
,
1875 (((dev_priv
->gart_vm_start
- 1 +
1876 dev_priv
->gart_size
) & 0xffff0000) |
1877 (dev_priv
->gart_vm_start
>> 16)));
1879 ring_start
= (dev_priv
->cp_ring
->offset
1881 + dev_priv
->gart_vm_start
);
1884 ring_start
= (dev_priv
->cp_ring
->offset
1885 - (unsigned long)dev
->sg
->virtual
1886 + dev_priv
->gart_vm_start
);
1888 RADEON_WRITE(R600_CP_RB_BASE
, ring_start
>> 8);
1890 RADEON_WRITE(R600_CP_ME_CNTL
, 0xff);
1892 RADEON_WRITE(R600_CP_DEBUG
, (1 << 27) | (1 << 28));
1894 /* Initialize the scratch register pointer. This will cause
1895 * the scratch register values to be written out to memory
1896 * whenever they are updated.
1898 * We simply put this behind the ring read pointer, this works
1899 * with PCI GART as well as (whatever kind of) AGP GART
1904 scratch_addr
= RADEON_READ(R600_CP_RB_RPTR_ADDR
) & 0xFFFFFFFC;
1905 scratch_addr
|= ((u64
)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI
)) << 32;
1906 scratch_addr
+= R600_SCRATCH_REG_OFFSET
;
1908 scratch_addr
&= 0xffffffff;
1910 RADEON_WRITE(R600_SCRATCH_ADDR
, (uint32_t)scratch_addr
);
1913 RADEON_WRITE(R600_SCRATCH_UMSK
, 0x7);
1915 /* Turn on bus mastering */
1916 radeon_enable_bm(dev_priv
);
1918 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(0), 0);
1919 RADEON_WRITE(R600_LAST_FRAME_REG
, 0);
1921 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(1), 0);
1922 RADEON_WRITE(R600_LAST_DISPATCH_REG
, 0);
1924 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(2), 0);
1925 RADEON_WRITE(R600_LAST_CLEAR_REG
, 0);
1927 /* reset sarea copies of these */
1928 master_priv
= file_priv
->master
->driver_priv
;
1929 if (master_priv
->sarea_priv
) {
1930 master_priv
->sarea_priv
->last_frame
= 0;
1931 master_priv
->sarea_priv
->last_dispatch
= 0;
1932 master_priv
->sarea_priv
->last_clear
= 0;
1935 r600_do_wait_for_idle(dev_priv
);
1939 int r600_do_cleanup_cp(struct drm_device
*dev
)
1941 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1944 /* Make sure interrupts are disabled here because the uninstall ioctl
1945 * may not have been called from userspace and after dev_private
1946 * is freed, it's too late.
1948 if (dev
->irq_enabled
)
1949 drm_irq_uninstall(dev
);
1952 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1953 if (dev_priv
->cp_ring
!= NULL
) {
1954 drm_core_ioremapfree(dev_priv
->cp_ring
, dev
);
1955 dev_priv
->cp_ring
= NULL
;
1957 if (dev_priv
->ring_rptr
!= NULL
) {
1958 drm_core_ioremapfree(dev_priv
->ring_rptr
, dev
);
1959 dev_priv
->ring_rptr
= NULL
;
1961 if (dev
->agp_buffer_map
!= NULL
) {
1962 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
1963 dev
->agp_buffer_map
= NULL
;
1969 if (dev_priv
->gart_info
.bus_addr
)
1970 r600_page_table_cleanup(dev
, &dev_priv
->gart_info
);
1972 if (dev_priv
->gart_info
.gart_table_location
== DRM_ATI_GART_FB
) {
1973 drm_core_ioremapfree(&dev_priv
->gart_info
.mapping
, dev
);
1974 dev_priv
->gart_info
.addr
= NULL
;
1977 /* only clear to the start of flags */
1978 memset(dev_priv
, 0, offsetof(drm_radeon_private_t
, flags
));
1983 int r600_do_init_cp(struct drm_device
*dev
, drm_radeon_init_t
*init
,
1984 struct drm_file
*file_priv
)
1986 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1987 struct drm_radeon_master_private
*master_priv
= file_priv
->master
->driver_priv
;
1991 mutex_init(&dev_priv
->cs_mutex
);
1992 r600_cs_legacy_init();
1993 /* if we require new memory map but we don't have it fail */
1994 if ((dev_priv
->flags
& RADEON_NEW_MEMMAP
) && !dev_priv
->new_memmap
) {
1995 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1996 r600_do_cleanup_cp(dev
);
2000 if (init
->is_pci
&& (dev_priv
->flags
& RADEON_IS_AGP
)) {
2001 DRM_DEBUG("Forcing AGP card to PCI mode\n");
2002 dev_priv
->flags
&= ~RADEON_IS_AGP
;
2003 /* The writeback test succeeds, but when writeback is enabled,
2004 * the ring buffer read ptr update fails after first 128 bytes.
2007 } else if (!(dev_priv
->flags
& (RADEON_IS_AGP
| RADEON_IS_PCI
| RADEON_IS_PCIE
))
2009 DRM_DEBUG("Restoring AGP flag\n");
2010 dev_priv
->flags
|= RADEON_IS_AGP
;
2013 dev_priv
->usec_timeout
= init
->usec_timeout
;
2014 if (dev_priv
->usec_timeout
< 1 ||
2015 dev_priv
->usec_timeout
> RADEON_MAX_USEC_TIMEOUT
) {
2016 DRM_DEBUG("TIMEOUT problem!\n");
2017 r600_do_cleanup_cp(dev
);
2021 /* Enable vblank on CRTC1 for older X servers
2023 dev_priv
->vblank_crtc
= DRM_RADEON_VBLANK_CRTC1
;
2024 dev_priv
->do_boxes
= 0;
2025 dev_priv
->cp_mode
= init
->cp_mode
;
2027 /* We don't support anything other than bus-mastering ring mode,
2028 * but the ring can be in either AGP or PCI space for the ring
2031 if ((init
->cp_mode
!= RADEON_CSQ_PRIBM_INDDIS
) &&
2032 (init
->cp_mode
!= RADEON_CSQ_PRIBM_INDBM
)) {
2033 DRM_DEBUG("BAD cp_mode (%x)!\n", init
->cp_mode
);
2034 r600_do_cleanup_cp(dev
);
2038 switch (init
->fb_bpp
) {
2040 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
2044 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
2047 dev_priv
->front_offset
= init
->front_offset
;
2048 dev_priv
->front_pitch
= init
->front_pitch
;
2049 dev_priv
->back_offset
= init
->back_offset
;
2050 dev_priv
->back_pitch
= init
->back_pitch
;
2052 dev_priv
->ring_offset
= init
->ring_offset
;
2053 dev_priv
->ring_rptr_offset
= init
->ring_rptr_offset
;
2054 dev_priv
->buffers_offset
= init
->buffers_offset
;
2055 dev_priv
->gart_textures_offset
= init
->gart_textures_offset
;
2057 master_priv
->sarea
= drm_getsarea(dev
);
2058 if (!master_priv
->sarea
) {
2059 DRM_ERROR("could not find sarea!\n");
2060 r600_do_cleanup_cp(dev
);
2064 dev_priv
->cp_ring
= drm_core_findmap(dev
, init
->ring_offset
);
2065 if (!dev_priv
->cp_ring
) {
2066 DRM_ERROR("could not find cp ring region!\n");
2067 r600_do_cleanup_cp(dev
);
2070 dev_priv
->ring_rptr
= drm_core_findmap(dev
, init
->ring_rptr_offset
);
2071 if (!dev_priv
->ring_rptr
) {
2072 DRM_ERROR("could not find ring read pointer!\n");
2073 r600_do_cleanup_cp(dev
);
2076 dev
->agp_buffer_token
= init
->buffers_offset
;
2077 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
2078 if (!dev
->agp_buffer_map
) {
2079 DRM_ERROR("could not find dma buffer region!\n");
2080 r600_do_cleanup_cp(dev
);
2084 if (init
->gart_textures_offset
) {
2085 dev_priv
->gart_textures
=
2086 drm_core_findmap(dev
, init
->gart_textures_offset
);
2087 if (!dev_priv
->gart_textures
) {
2088 DRM_ERROR("could not find GART texture region!\n");
2089 r600_do_cleanup_cp(dev
);
2096 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2097 drm_core_ioremap_wc(dev_priv
->cp_ring
, dev
);
2098 drm_core_ioremap_wc(dev_priv
->ring_rptr
, dev
);
2099 drm_core_ioremap_wc(dev
->agp_buffer_map
, dev
);
2100 if (!dev_priv
->cp_ring
->handle
||
2101 !dev_priv
->ring_rptr
->handle
||
2102 !dev
->agp_buffer_map
->handle
) {
2103 DRM_ERROR("could not find ioremap agp regions!\n");
2104 r600_do_cleanup_cp(dev
);
2110 dev_priv
->cp_ring
->handle
= (void *)(unsigned long)dev_priv
->cp_ring
->offset
;
2111 dev_priv
->ring_rptr
->handle
=
2112 (void *)(unsigned long)dev_priv
->ring_rptr
->offset
;
2113 dev
->agp_buffer_map
->handle
=
2114 (void *)(unsigned long)dev
->agp_buffer_map
->offset
;
2116 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2117 dev_priv
->cp_ring
->handle
);
2118 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2119 dev_priv
->ring_rptr
->handle
);
2120 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2121 dev
->agp_buffer_map
->handle
);
2124 dev_priv
->fb_location
= (radeon_read_fb_location(dev_priv
) & 0xffff) << 24;
2126 (((radeon_read_fb_location(dev_priv
) & 0xffff0000u
) << 8) + 0x1000000)
2127 - dev_priv
->fb_location
;
2129 dev_priv
->front_pitch_offset
= (((dev_priv
->front_pitch
/ 64) << 22) |
2130 ((dev_priv
->front_offset
2131 + dev_priv
->fb_location
) >> 10));
2133 dev_priv
->back_pitch_offset
= (((dev_priv
->back_pitch
/ 64) << 22) |
2134 ((dev_priv
->back_offset
2135 + dev_priv
->fb_location
) >> 10));
2137 dev_priv
->depth_pitch_offset
= (((dev_priv
->depth_pitch
/ 64) << 22) |
2138 ((dev_priv
->depth_offset
2139 + dev_priv
->fb_location
) >> 10));
2141 dev_priv
->gart_size
= init
->gart_size
;
2143 /* New let's set the memory map ... */
2144 if (dev_priv
->new_memmap
) {
2147 DRM_INFO("Setting GART location based on new memory map\n");
2149 /* If using AGP, try to locate the AGP aperture at the same
2150 * location in the card and on the bus, though we have to
2155 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2156 base
= dev
->agp
->base
;
2157 /* Check if valid */
2158 if ((base
+ dev_priv
->gart_size
- 1) >= dev_priv
->fb_location
&&
2159 base
< (dev_priv
->fb_location
+ dev_priv
->fb_size
- 1)) {
2160 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2166 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2168 base
= dev_priv
->fb_location
+ dev_priv
->fb_size
;
2169 if (base
< dev_priv
->fb_location
||
2170 ((base
+ dev_priv
->gart_size
) & 0xfffffffful
) < base
)
2171 base
= dev_priv
->fb_location
2172 - dev_priv
->gart_size
;
2174 dev_priv
->gart_vm_start
= base
& 0xffc00000u
;
2175 if (dev_priv
->gart_vm_start
!= base
)
2176 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2177 base
, dev_priv
->gart_vm_start
);
2182 if (dev_priv
->flags
& RADEON_IS_AGP
)
2183 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
2185 + dev_priv
->gart_vm_start
);
2188 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
2189 - (unsigned long)dev
->sg
->virtual
2190 + dev_priv
->gart_vm_start
);
2192 DRM_DEBUG("fb 0x%08x size %d\n",
2193 (unsigned int) dev_priv
->fb_location
,
2194 (unsigned int) dev_priv
->fb_size
);
2195 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv
->gart_size
);
2196 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2197 (unsigned int) dev_priv
->gart_vm_start
);
2198 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2199 dev_priv
->gart_buffers_offset
);
2201 dev_priv
->ring
.start
= (u32
*) dev_priv
->cp_ring
->handle
;
2202 dev_priv
->ring
.end
= ((u32
*) dev_priv
->cp_ring
->handle
2203 + init
->ring_size
/ sizeof(u32
));
2204 dev_priv
->ring
.size
= init
->ring_size
;
2205 dev_priv
->ring
.size_l2qw
= drm_order(init
->ring_size
/ 8);
2207 dev_priv
->ring
.rptr_update
= /* init->rptr_update */ 4096;
2208 dev_priv
->ring
.rptr_update_l2qw
= drm_order(/* init->rptr_update */ 4096 / 8);
2210 dev_priv
->ring
.fetch_size
= /* init->fetch_size */ 32;
2211 dev_priv
->ring
.fetch_size_l2ow
= drm_order(/* init->fetch_size */ 32 / 16);
2213 dev_priv
->ring
.tail_mask
= (dev_priv
->ring
.size
/ sizeof(u32
)) - 1;
2215 dev_priv
->ring
.high_mark
= RADEON_RING_HIGH_MARK
;
2218 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2219 /* XXX turn off pcie gart */
2223 dev_priv
->gart_info
.table_mask
= DMA_BIT_MASK(32);
2224 /* if we have an offset set from userspace */
2225 if (!dev_priv
->pcigart_offset_set
) {
2226 DRM_ERROR("Need gart offset from userspace\n");
2227 r600_do_cleanup_cp(dev
);
2231 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv
->pcigart_offset
);
2233 dev_priv
->gart_info
.bus_addr
=
2234 dev_priv
->pcigart_offset
+ dev_priv
->fb_location
;
2235 dev_priv
->gart_info
.mapping
.offset
=
2236 dev_priv
->pcigart_offset
+ dev_priv
->fb_aper_offset
;
2237 dev_priv
->gart_info
.mapping
.size
=
2238 dev_priv
->gart_info
.table_size
;
2240 drm_core_ioremap_wc(&dev_priv
->gart_info
.mapping
, dev
);
2241 if (!dev_priv
->gart_info
.mapping
.handle
) {
2242 DRM_ERROR("ioremap failed.\n");
2243 r600_do_cleanup_cp(dev
);
2247 dev_priv
->gart_info
.addr
=
2248 dev_priv
->gart_info
.mapping
.handle
;
2250 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2251 dev_priv
->gart_info
.addr
,
2252 dev_priv
->pcigart_offset
);
2254 if (!r600_page_table_init(dev
)) {
2255 DRM_ERROR("Failed to init GART table\n");
2256 r600_do_cleanup_cp(dev
);
2260 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
2266 if (!dev_priv
->me_fw
|| !dev_priv
->pfp_fw
) {
2267 int err
= r600_cp_init_microcode(dev_priv
);
2269 DRM_ERROR("Failed to load firmware!\n");
2270 r600_do_cleanup_cp(dev
);
2274 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
2275 r700_cp_load_microcode(dev_priv
);
2277 r600_cp_load_microcode(dev_priv
);
2279 r600_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
2281 dev_priv
->last_buf
= 0;
2283 r600_do_engine_reset(dev
);
2284 r600_test_writeback(dev_priv
);
2289 int r600_do_resume_cp(struct drm_device
*dev
, struct drm_file
*file_priv
)
2291 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2294 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)) {
2296 r700_cp_load_microcode(dev_priv
);
2299 r600_cp_load_microcode(dev_priv
);
2301 r600_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
2302 r600_do_engine_reset(dev
);
2307 /* Wait for the CP to go idle.
2309 int r600_do_cp_idle(drm_radeon_private_t
*dev_priv
)
2315 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
2316 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT
);
2317 /* wait for 3D idle clean */
2318 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
2319 OUT_RING((R600_WAIT_UNTIL
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
2320 OUT_RING(RADEON_WAIT_3D_IDLE
| RADEON_WAIT_3D_IDLECLEAN
);
2325 return r600_do_wait_for_idle(dev_priv
);
2328 /* Start the Command Processor.
2330 void r600_do_cp_start(drm_radeon_private_t
*dev_priv
)
2337 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE
, 5));
2338 OUT_RING(0x00000001);
2339 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) < CHIP_RV770
))
2340 OUT_RING(0x00000003);
2342 OUT_RING(0x00000000);
2343 OUT_RING((dev_priv
->r600_max_hw_contexts
- 1));
2344 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2345 OUT_RING(0x00000000);
2346 OUT_RING(0x00000000);
2350 /* set the mux and reset the halt bit */
2352 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me
);
2354 dev_priv
->cp_running
= 1;
2358 void r600_do_cp_reset(drm_radeon_private_t
*dev_priv
)
2363 cur_read_ptr
= RADEON_READ(R600_CP_RB_RPTR
);
2364 RADEON_WRITE(R600_CP_RB_WPTR
, cur_read_ptr
);
2365 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
2366 dev_priv
->ring
.tail
= cur_read_ptr
;
2369 void r600_do_cp_stop(drm_radeon_private_t
*dev_priv
)
2375 cp_me
= 0xff | R600_CP_ME_HALT
;
2377 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me
);
2379 dev_priv
->cp_running
= 0;
2382 int r600_cp_dispatch_indirect(struct drm_device
*dev
,
2383 struct drm_buf
*buf
, int start
, int end
)
2385 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2389 unsigned long offset
= (dev_priv
->gart_buffers_offset
2390 + buf
->offset
+ start
);
2391 int dwords
= (end
- start
+ 3) / sizeof(u32
);
2393 DRM_DEBUG("dwords:%d\n", dwords
);
2394 DRM_DEBUG("offset 0x%lx\n", offset
);
2397 /* Indirect buffer data must be a multiple of 16 dwords.
2398 * pad the data with a Type-2 CP packet.
2400 while (dwords
& 0xf) {
2402 ((char *)dev
->agp_buffer_map
->handle
2403 + buf
->offset
+ start
);
2404 data
[dwords
++] = RADEON_CP_PACKET2
;
2407 /* Fire off the indirect buffer */
2409 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER
, 2));
2410 OUT_RING((offset
& 0xfffffffc));
2411 OUT_RING((upper_32_bits(offset
) & 0xff));
2419 void r600_cp_dispatch_swap(struct drm_device
*dev
, struct drm_file
*file_priv
)
2421 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2422 struct drm_master
*master
= file_priv
->master
;
2423 struct drm_radeon_master_private
*master_priv
= master
->driver_priv
;
2424 drm_radeon_sarea_t
*sarea_priv
= master_priv
->sarea_priv
;
2425 int nbox
= sarea_priv
->nbox
;
2426 struct drm_clip_rect
*pbox
= sarea_priv
->boxes
;
2427 int i
, cpp
, src_pitch
, dst_pitch
;
2432 if (dev_priv
->color_fmt
== RADEON_COLOR_FORMAT_ARGB8888
)
2437 if (sarea_priv
->pfCurrentPage
== 0) {
2438 src_pitch
= dev_priv
->back_pitch
;
2439 dst_pitch
= dev_priv
->front_pitch
;
2440 src
= dev_priv
->back_offset
+ dev_priv
->fb_location
;
2441 dst
= dev_priv
->front_offset
+ dev_priv
->fb_location
;
2443 src_pitch
= dev_priv
->front_pitch
;
2444 dst_pitch
= dev_priv
->back_pitch
;
2445 src
= dev_priv
->front_offset
+ dev_priv
->fb_location
;
2446 dst
= dev_priv
->back_offset
+ dev_priv
->fb_location
;
2449 if (r600_prepare_blit_copy(dev
, file_priv
)) {
2450 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2453 for (i
= 0; i
< nbox
; i
++) {
2456 int w
= pbox
[i
].x2
- x
;
2457 int h
= pbox
[i
].y2
- y
;
2459 DRM_DEBUG("%d,%d-%d,%d\n", x
, y
, w
, h
);
2464 src_pitch
, dst_pitch
, cpp
);
2466 r600_done_blit_copy(dev
);
2468 /* Increment the frame counter. The client-side 3D driver must
2469 * throttle the framerate by waiting for this value before
2470 * performing the swapbuffer ioctl.
2472 sarea_priv
->last_frame
++;
2475 R600_FRAME_AGE(sarea_priv
->last_frame
);
2479 int r600_cp_dispatch_texture(struct drm_device
*dev
,
2480 struct drm_file
*file_priv
,
2481 drm_radeon_texture_t
*tex
,
2482 drm_radeon_tex_image_t
*image
)
2484 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2485 struct drm_buf
*buf
;
2487 const u8 __user
*data
;
2488 int size
, pass_size
;
2489 u64 src_offset
, dst_offset
;
2491 if (!radeon_check_offset(dev_priv
, tex
->offset
)) {
2492 DRM_ERROR("Invalid destination offset\n");
2496 /* this might fail for zero-sized uploads - are those illegal? */
2497 if (!radeon_check_offset(dev_priv
, tex
->offset
+ tex
->height
* tex
->pitch
- 1)) {
2498 DRM_ERROR("Invalid final destination offset\n");
2502 size
= tex
->height
* tex
->pitch
;
2507 dst_offset
= tex
->offset
;
2509 if (r600_prepare_blit_copy(dev
, file_priv
)) {
2510 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2514 data
= (const u8 __user
*)image
->data
;
2517 buf
= radeon_freelist_get(dev
);
2519 DRM_DEBUG("EAGAIN\n");
2520 if (DRM_COPY_TO_USER(tex
->image
, image
, sizeof(*image
)))
2525 if (pass_size
> buf
->total
)
2526 pass_size
= buf
->total
;
2528 /* Dispatch the indirect buffer.
2531 (u32
*) ((char *)dev
->agp_buffer_map
->handle
+ buf
->offset
);
2533 if (DRM_COPY_FROM_USER(buffer
, data
, pass_size
)) {
2534 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size
);
2538 buf
->file_priv
= file_priv
;
2539 buf
->used
= pass_size
;
2540 src_offset
= dev_priv
->gart_buffers_offset
+ buf
->offset
;
2542 r600_blit_copy(dev
, src_offset
, dst_offset
, pass_size
);
2544 radeon_cp_discard_buffer(dev
, file_priv
->master
, buf
);
2546 /* Update the input parameters for next time */
2547 image
->data
= (const u8 __user
*)image
->data
+ pass_size
;
2548 dst_offset
+= pass_size
;
2551 r600_done_blit_copy(dev
);
2559 static u32
radeon_cs_id_get(struct drm_radeon_private
*radeon
)
2561 /* FIXME: check if wrap affect last reported wrap & sequence */
2562 radeon
->cs_id_scnt
= (radeon
->cs_id_scnt
+ 1) & 0x00FFFFFF;
2563 if (!radeon
->cs_id_scnt
) {
2564 /* increment wrap counter */
2565 radeon
->cs_id_wcnt
+= 0x01000000;
2566 /* valid sequence counter start at 1 */
2567 radeon
->cs_id_scnt
= 1;
2569 return (radeon
->cs_id_scnt
| radeon
->cs_id_wcnt
);
2572 static void r600_cs_id_emit(drm_radeon_private_t
*dev_priv
, u32
*id
)
2576 *id
= radeon_cs_id_get(dev_priv
);
2580 R600_CLEAR_AGE(*id
);
2585 static int r600_ib_get(struct drm_device
*dev
,
2586 struct drm_file
*fpriv
,
2587 struct drm_buf
**buffer
)
2589 struct drm_buf
*buf
;
2592 buf
= radeon_freelist_get(dev
);
2596 buf
->file_priv
= fpriv
;
2601 static void r600_ib_free(struct drm_device
*dev
, struct drm_buf
*buf
,
2602 struct drm_file
*fpriv
, int l
, int r
)
2604 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2608 r600_cp_dispatch_indirect(dev
, buf
, 0, l
* 4);
2609 radeon_cp_discard_buffer(dev
, fpriv
->master
, buf
);
2614 int r600_cs_legacy_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*fpriv
)
2616 struct drm_radeon_private
*dev_priv
= dev
->dev_private
;
2617 struct drm_radeon_cs
*cs
= data
;
2618 struct drm_buf
*buf
;
2623 if (dev_priv
== NULL
) {
2624 DRM_ERROR("called with no initialization\n");
2627 family
= dev_priv
->flags
& RADEON_FAMILY_MASK
;
2628 if (family
< CHIP_R600
) {
2629 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2632 mutex_lock(&dev_priv
->cs_mutex
);
2634 r
= r600_ib_get(dev
, fpriv
, &buf
);
2636 DRM_ERROR("ib_get failed\n");
2639 ib
= dev
->agp_buffer_map
->handle
+ buf
->offset
;
2640 /* now parse command stream */
2641 r
= r600_cs_legacy(dev
, data
, fpriv
, family
, ib
, &l
);
2647 r600_ib_free(dev
, buf
, fpriv
, l
, r
);
2648 /* emit cs id sequence */
2649 r600_cs_id_emit(dev_priv
, &cs_id
);
2651 mutex_unlock(&dev_priv
->cs_mutex
);
2655 void r600_cs_legacy_get_tiling_conf(struct drm_device
*dev
, u32
*npipes
, u32
*nbanks
, u32
*group_size
)
2657 struct drm_radeon_private
*dev_priv
= dev
->dev_private
;
2659 *npipes
= dev_priv
->r600_npipes
;
2660 *nbanks
= dev_priv
->r600_nbanks
;
2661 *group_size
= dev_priv
->r600_group_size
;