2 #include "drm_crtc_helper.h"
6 * Integrated TV out support based on the GATOS code by
7 * Federico Ulivi <fulivi@lycos.com>
12 * Limits of h/v positions (hPos & vPos)
14 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
15 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
18 * Unit for hPos (in TV clock periods)
23 * Indexes in h. code timing table for horizontal line position adjustment
25 #define H_TABLE_POS1 6
26 #define H_TABLE_POS2 8
29 * Limits of hor. size (hSize)
31 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
33 /* tv standard constants */
34 #define NTSC_TV_CLOCK_T 233
35 #define NTSC_TV_VFTOTAL 1
36 #define NTSC_TV_LINES_PER_FRAME 525
37 #define NTSC_TV_ZERO_H_SIZE 479166
38 #define NTSC_TV_H_SIZE_UNIT 9478
40 #define PAL_TV_CLOCK_T 188
41 #define PAL_TV_VFTOTAL 3
42 #define PAL_TV_LINES_PER_FRAME 625
43 #define PAL_TV_ZERO_H_SIZE 473200
44 #define PAL_TV_H_SIZE_UNIT 9360
46 /* tv pll setting for 27 mhz ref clk */
47 #define NTSC_TV_PLL_M_27 22
48 #define NTSC_TV_PLL_N_27 175
49 #define NTSC_TV_PLL_P_27 5
51 #define PAL_TV_PLL_M_27 113
52 #define PAL_TV_PLL_N_27 668
53 #define PAL_TV_PLL_P_27 3
55 /* tv pll setting for 14 mhz ref clk */
56 #define NTSC_TV_PLL_M_14 33
57 #define NTSC_TV_PLL_N_14 693
58 #define NTSC_TV_PLL_P_14 7
60 #define PAL_TV_PLL_M_14 19
61 #define PAL_TV_PLL_N_14 353
62 #define PAL_TV_PLL_P_14 5
64 #define VERT_LEAD_IN_LINES 2
66 #define FRAC_MASK 0x3fff
68 struct radeon_tv_mode_constants
{
69 uint16_t hor_resolution
;
70 uint16_t ver_resolution
;
71 enum radeon_tv_std standard
;
75 uint16_t hor_syncstart
;
76 uint16_t ver_syncstart
;
80 uint8_t crtcPLL_post_div
;
84 static const uint16_t hor_timing_NTSC
[MAX_H_CODE_TIMING_LEN
] = {
91 0x126d, /* H_TABLE_POS1 */
93 0x1a8f, /* H_TABLE_POS2 */
105 static const uint16_t vert_timing_NTSC
[MAX_V_CODE_TIMING_LEN
] = {
122 static const uint16_t hor_timing_PAL
[MAX_H_CODE_TIMING_LEN
] = {
129 0x124f, /* H_TABLE_POS1 */
131 0x1b22, /* H_TABLE_POS2 */
143 static const uint16_t vert_timing_PAL
[MAX_V_CODE_TIMING_LEN
] = {
162 /**********************************************************************
166 * Table of all allowed modes for tv output
168 **********************************************************************/
169 static const struct radeon_tv_mode_constants available_tv_modes
[] = {
170 { /* NTSC timing for 27 Mhz ref clk */
171 800, /* horResolution */
172 600, /* verResolution */
173 TV_STD_NTSC
, /* standard */
177 824, /* horSyncStart */
178 632, /* verSyncStart */
179 625592, /* defRestart */
182 4, /* crtcPLL_postDiv */
185 { /* PAL timing for 27 Mhz ref clk */
186 800, /* horResolution */
187 600, /* verResolution */
188 TV_STD_PAL
, /* standard */
192 824, /* horSyncStart */
193 669, /* verSyncStart */
194 696700, /* defRestart */
195 1382, /* crtcPLL_N */
197 4, /* crtcPLL_postDiv */
200 { /* NTSC timing for 14 Mhz ref clk */
201 800, /* horResolution */
202 600, /* verResolution */
203 TV_STD_NTSC
, /* standard */
207 840, /* horSyncStart */
208 633, /* verSyncStart */
209 630627, /* defRestart */
212 8, /* crtcPLL_postDiv */
215 { /* PAL timing for 14 Mhz ref clk */
216 800, /* horResolution */
217 600, /* verResolution */
218 TV_STD_PAL
, /* standard */
222 840, /* horSyncStart */
223 633, /* verSyncStart */
224 708369, /* defRestart */
227 8, /* crtcPLL_postDiv */
232 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
234 static const struct radeon_tv_mode_constants
*radeon_legacy_tv_get_std_mode(struct radeon_encoder
*radeon_encoder
,
235 uint16_t *pll_ref_freq
)
237 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
238 struct radeon_device
*rdev
= dev
->dev_private
;
239 struct radeon_crtc
*radeon_crtc
;
240 struct radeon_encoder_tv_dac
*tv_dac
= radeon_encoder
->enc_priv
;
241 const struct radeon_tv_mode_constants
*const_ptr
;
242 struct radeon_pll
*pll
;
244 radeon_crtc
= to_radeon_crtc(radeon_encoder
->base
.crtc
);
245 if (radeon_crtc
->crtc_id
== 1)
246 pll
= &rdev
->clock
.p2pll
;
248 pll
= &rdev
->clock
.p1pll
;
251 *pll_ref_freq
= pll
->reference_freq
;
253 if (tv_dac
->tv_std
== TV_STD_NTSC
||
254 tv_dac
->tv_std
== TV_STD_NTSC_J
||
255 tv_dac
->tv_std
== TV_STD_PAL_M
) {
256 if (pll
->reference_freq
== 2700)
257 const_ptr
= &available_tv_modes
[0];
259 const_ptr
= &available_tv_modes
[2];
261 if (pll
->reference_freq
== 2700)
262 const_ptr
= &available_tv_modes
[1];
264 const_ptr
= &available_tv_modes
[3];
269 static long YCOEF_value
[5] = { 2, 2, 0, 4, 0 };
270 static long YCOEF_EN_value
[5] = { 1, 1, 0, 1, 0 };
271 static long SLOPE_value
[5] = { 1, 2, 2, 4, 8 };
272 static long SLOPE_limit
[5] = { 6, 5, 4, 3, 2 };
274 static void radeon_wait_pll_lock(struct drm_encoder
*encoder
, unsigned n_tests
,
275 unsigned n_wait_loops
, unsigned cnt_threshold
)
277 struct drm_device
*dev
= encoder
->dev
;
278 struct radeon_device
*rdev
= dev
->dev_private
;
279 uint32_t save_pll_test
;
282 WREG32(RADEON_TEST_DEBUG_MUX
, (RREG32(RADEON_TEST_DEBUG_MUX
) & 0xffff60ff) | 0x100);
283 save_pll_test
= RREG32_PLL(RADEON_PLL_TEST_CNTL
);
284 WREG32_PLL(RADEON_PLL_TEST_CNTL
, save_pll_test
& ~RADEON_PLL_MASK_READ_B
);
286 WREG8(RADEON_CLOCK_CNTL_INDEX
, RADEON_PLL_TEST_CNTL
);
287 for (i
= 0; i
< n_tests
; i
++) {
288 WREG8(RADEON_CLOCK_CNTL_DATA
+ 3, 0);
289 for (j
= 0; j
< n_wait_loops
; j
++)
290 if (RREG8(RADEON_CLOCK_CNTL_DATA
+ 3) >= cnt_threshold
)
293 WREG32_PLL(RADEON_PLL_TEST_CNTL
, save_pll_test
);
294 WREG32(RADEON_TEST_DEBUG_MUX
, RREG32(RADEON_TEST_DEBUG_MUX
) & 0xffffe0ff);
298 static void radeon_legacy_tv_write_fifo(struct radeon_encoder
*radeon_encoder
,
299 uint16_t addr
, uint32_t value
)
301 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
302 struct radeon_device
*rdev
= dev
->dev_private
;
306 WREG32(RADEON_TV_HOST_WRITE_DATA
, value
);
308 WREG32(RADEON_TV_HOST_RD_WT_CNTL
, addr
);
309 WREG32(RADEON_TV_HOST_RD_WT_CNTL
, addr
| RADEON_HOST_FIFO_WT
);
312 tmp
= RREG32(RADEON_TV_HOST_RD_WT_CNTL
);
313 if ((tmp
& RADEON_HOST_FIFO_WT_ACK
) == 0)
317 WREG32(RADEON_TV_HOST_RD_WT_CNTL
, 0);
320 #if 0 /* included for completeness */
321 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder
*radeon_encoder
, uint16_t addr
)
323 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
324 struct radeon_device
*rdev
= dev
->dev_private
;
328 WREG32(RADEON_TV_HOST_RD_WT_CNTL
, addr
);
329 WREG32(RADEON_TV_HOST_RD_WT_CNTL
, addr
| RADEON_HOST_FIFO_RD
);
332 tmp
= RREG32(RADEON_TV_HOST_RD_WT_CNTL
);
333 if ((tmp
& RADEON_HOST_FIFO_RD_ACK
) == 0)
337 WREG32(RADEON_TV_HOST_RD_WT_CNTL
, 0);
338 return RREG32(RADEON_TV_HOST_READ_DATA
);
342 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr
)
346 switch ((tv_uv_adr
& RADEON_HCODE_TABLE_SEL_MASK
) >> RADEON_HCODE_TABLE_SEL_SHIFT
) {
348 h_table
= RADEON_TV_MAX_FIFO_ADDR_INTERNAL
;
351 h_table
= ((tv_uv_adr
& RADEON_TABLE1_BOT_ADR_MASK
) >> RADEON_TABLE1_BOT_ADR_SHIFT
) * 2;
354 h_table
= ((tv_uv_adr
& RADEON_TABLE3_TOP_ADR_MASK
) >> RADEON_TABLE3_TOP_ADR_SHIFT
) * 2;
363 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr
)
367 switch ((tv_uv_adr
& RADEON_VCODE_TABLE_SEL_MASK
) >> RADEON_VCODE_TABLE_SEL_SHIFT
) {
369 v_table
= ((tv_uv_adr
& RADEON_MAX_UV_ADR_MASK
) >> RADEON_MAX_UV_ADR_SHIFT
) * 2 + 1;
372 v_table
= ((tv_uv_adr
& RADEON_TABLE1_BOT_ADR_MASK
) >> RADEON_TABLE1_BOT_ADR_SHIFT
) * 2 + 1;
375 v_table
= ((tv_uv_adr
& RADEON_TABLE3_TOP_ADR_MASK
) >> RADEON_TABLE3_TOP_ADR_SHIFT
) * 2 + 1;
384 static void radeon_restore_tv_timing_tables(struct radeon_encoder
*radeon_encoder
)
386 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
387 struct radeon_device
*rdev
= dev
->dev_private
;
388 struct radeon_encoder_tv_dac
*tv_dac
= radeon_encoder
->enc_priv
;
389 uint16_t h_table
, v_table
;
393 WREG32(RADEON_TV_UV_ADR
, tv_dac
->tv
.tv_uv_adr
);
394 h_table
= radeon_get_htiming_tables_addr(tv_dac
->tv
.tv_uv_adr
);
395 v_table
= radeon_get_vtiming_tables_addr(tv_dac
->tv
.tv_uv_adr
);
397 for (i
= 0; i
< MAX_H_CODE_TIMING_LEN
; i
+= 2, h_table
--) {
398 tmp
= ((uint32_t)tv_dac
->tv
.h_code_timing
[i
] << 14) | ((uint32_t)tv_dac
->tv
.h_code_timing
[i
+1]);
399 radeon_legacy_tv_write_fifo(radeon_encoder
, h_table
, tmp
);
400 if (tv_dac
->tv
.h_code_timing
[i
] == 0 || tv_dac
->tv
.h_code_timing
[i
+ 1] == 0)
403 for (i
= 0; i
< MAX_V_CODE_TIMING_LEN
; i
+= 2, v_table
++) {
404 tmp
= ((uint32_t)tv_dac
->tv
.v_code_timing
[i
+1] << 14) | ((uint32_t)tv_dac
->tv
.v_code_timing
[i
]);
405 radeon_legacy_tv_write_fifo(radeon_encoder
, v_table
, tmp
);
406 if (tv_dac
->tv
.v_code_timing
[i
] == 0 || tv_dac
->tv
.v_code_timing
[i
+ 1] == 0)
411 static void radeon_legacy_write_tv_restarts(struct radeon_encoder
*radeon_encoder
)
413 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
414 struct radeon_device
*rdev
= dev
->dev_private
;
415 struct radeon_encoder_tv_dac
*tv_dac
= radeon_encoder
->enc_priv
;
416 WREG32(RADEON_TV_FRESTART
, tv_dac
->tv
.frestart
);
417 WREG32(RADEON_TV_HRESTART
, tv_dac
->tv
.hrestart
);
418 WREG32(RADEON_TV_VRESTART
, tv_dac
->tv
.vrestart
);
421 static bool radeon_legacy_tv_init_restarts(struct drm_encoder
*encoder
)
423 struct drm_device
*dev
= encoder
->dev
;
424 struct radeon_device
*rdev
= dev
->dev_private
;
425 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
426 struct radeon_encoder_tv_dac
*tv_dac
= radeon_encoder
->enc_priv
;
427 struct radeon_crtc
*radeon_crtc
;
429 unsigned int h_total
, v_total
, f_total
;
430 int v_offset
, h_offset
;
433 const struct radeon_tv_mode_constants
*const_ptr
;
434 struct radeon_pll
*pll
;
436 radeon_crtc
= to_radeon_crtc(radeon_encoder
->base
.crtc
);
437 if (radeon_crtc
->crtc_id
== 1)
438 pll
= &rdev
->clock
.p2pll
;
440 pll
= &rdev
->clock
.p1pll
;
442 const_ptr
= radeon_legacy_tv_get_std_mode(radeon_encoder
, NULL
);
446 h_total
= const_ptr
->hor_total
;
447 v_total
= const_ptr
->ver_total
;
449 if (tv_dac
->tv_std
== TV_STD_NTSC
||
450 tv_dac
->tv_std
== TV_STD_NTSC_J
||
451 tv_dac
->tv_std
== TV_STD_PAL_M
||
452 tv_dac
->tv_std
== TV_STD_PAL_60
)
453 f_total
= NTSC_TV_VFTOTAL
+ 1;
455 f_total
= PAL_TV_VFTOTAL
+ 1;
457 /* adjust positions 1&2 in hor. cod timing table */
458 h_offset
= tv_dac
->h_pos
* H_POS_UNIT
;
460 if (tv_dac
->tv_std
== TV_STD_NTSC
||
461 tv_dac
->tv_std
== TV_STD_NTSC_J
||
462 tv_dac
->tv_std
== TV_STD_PAL_M
) {
464 p1
= hor_timing_NTSC
[H_TABLE_POS1
];
465 p2
= hor_timing_NTSC
[H_TABLE_POS2
];
467 p1
= hor_timing_PAL
[H_TABLE_POS1
];
468 p2
= hor_timing_PAL
[H_TABLE_POS2
];
471 p1
= (u16
)((int)p1
+ h_offset
);
472 p2
= (u16
)((int)p2
- h_offset
);
474 h_changed
= (p1
!= tv_dac
->tv
.h_code_timing
[H_TABLE_POS1
] ||
475 p2
!= tv_dac
->tv
.h_code_timing
[H_TABLE_POS2
]);
477 tv_dac
->tv
.h_code_timing
[H_TABLE_POS1
] = p1
;
478 tv_dac
->tv
.h_code_timing
[H_TABLE_POS2
] = p2
;
480 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
481 h_offset
= (h_offset
* (int)(const_ptr
->pix_to_tv
)) / 1000;
484 restart
= const_ptr
->def_restart
;
487 * convert v_pos TV lines to n. of CRTC pixels
489 if (tv_dac
->tv_std
== TV_STD_NTSC
||
490 tv_dac
->tv_std
== TV_STD_NTSC_J
||
491 tv_dac
->tv_std
== TV_STD_PAL_M
||
492 tv_dac
->tv_std
== TV_STD_PAL_60
)
493 v_offset
= ((int)(v_total
* h_total
) * 2 * tv_dac
->v_pos
) / (int)(NTSC_TV_LINES_PER_FRAME
);
495 v_offset
= ((int)(v_total
* h_total
) * 2 * tv_dac
->v_pos
) / (int)(PAL_TV_LINES_PER_FRAME
);
497 restart
-= v_offset
+ h_offset
;
499 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
500 const_ptr
->def_restart
, tv_dac
->h_pos
, tv_dac
->v_pos
, p1
, p2
, restart
);
502 tv_dac
->tv
.hrestart
= restart
% h_total
;
504 tv_dac
->tv
.vrestart
= restart
% v_total
;
506 tv_dac
->tv
.frestart
= restart
% f_total
;
508 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n",
509 (unsigned)tv_dac
->tv
.frestart
,
510 (unsigned)tv_dac
->tv
.vrestart
,
511 (unsigned)tv_dac
->tv
.hrestart
);
513 /* compute h_inc from hsize */
514 if (tv_dac
->tv_std
== TV_STD_NTSC
||
515 tv_dac
->tv_std
== TV_STD_NTSC_J
||
516 tv_dac
->tv_std
== TV_STD_PAL_M
)
517 h_inc
= (u16
)((int)(const_ptr
->hor_resolution
* 4096 * NTSC_TV_CLOCK_T
) /
518 (tv_dac
->h_size
* (int)(NTSC_TV_H_SIZE_UNIT
) + (int)(NTSC_TV_ZERO_H_SIZE
)));
520 h_inc
= (u16
)((int)(const_ptr
->hor_resolution
* 4096 * PAL_TV_CLOCK_T
) /
521 (tv_dac
->h_size
* (int)(PAL_TV_H_SIZE_UNIT
) + (int)(PAL_TV_ZERO_H_SIZE
)));
523 tv_dac
->tv
.timing_cntl
= (tv_dac
->tv
.timing_cntl
& ~RADEON_H_INC_MASK
) |
524 ((u32
)h_inc
<< RADEON_H_INC_SHIFT
);
526 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac
->h_size
, h_inc
);
531 void radeon_legacy_tv_mode_set(struct drm_encoder
*encoder
,
532 struct drm_display_mode
*mode
,
533 struct drm_display_mode
*adjusted_mode
)
535 struct drm_device
*dev
= encoder
->dev
;
536 struct radeon_device
*rdev
= dev
->dev_private
;
537 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
538 struct radeon_encoder_tv_dac
*tv_dac
= radeon_encoder
->enc_priv
;
539 const struct radeon_tv_mode_constants
*const_ptr
;
540 struct radeon_crtc
*radeon_crtc
;
542 uint16_t pll_ref_freq
;
543 uint32_t vert_space
, flicker_removal
, tmp
;
544 uint32_t tv_master_cntl
, tv_rgb_cntl
, tv_dac_cntl
;
545 uint32_t tv_modulator_cntl1
, tv_modulator_cntl2
;
546 uint32_t tv_vscaler_cntl1
, tv_vscaler_cntl2
;
547 uint32_t tv_pll_cntl
, tv_pll_cntl1
, tv_ftotal
;
548 uint32_t tv_y_fall_cntl
, tv_y_rise_cntl
, tv_y_saw_tooth_cntl
;
550 const uint16_t *hor_timing
;
551 const uint16_t *vert_timing
;
553 const_ptr
= radeon_legacy_tv_get_std_mode(radeon_encoder
, &pll_ref_freq
);
557 radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
559 tv_master_cntl
= (RADEON_VIN_ASYNC_RST
|
560 RADEON_CRT_FIFO_CE_EN
|
561 RADEON_TV_FIFO_CE_EN
|
564 if (!ASIC_IS_R300(rdev
))
565 tv_master_cntl
|= RADEON_TVCLK_ALWAYS_ONb
;
567 if (tv_dac
->tv_std
== TV_STD_NTSC
||
568 tv_dac
->tv_std
== TV_STD_NTSC_J
)
569 tv_master_cntl
|= RADEON_RESTART_PHASE_FIX
;
571 tv_modulator_cntl1
= (RADEON_SLEW_RATE_LIMIT
|
572 RADEON_SYNC_TIP_LEVEL
|
575 (6 << RADEON_CY_FILT_BLEND_SHIFT
));
577 if (tv_dac
->tv_std
== TV_STD_NTSC
||
578 tv_dac
->tv_std
== TV_STD_NTSC_J
) {
579 tv_modulator_cntl1
|= (0x46 << RADEON_SET_UP_LEVEL_SHIFT
) |
580 (0x3b << RADEON_BLANK_LEVEL_SHIFT
);
581 tv_modulator_cntl2
= (-111 & RADEON_TV_U_BURST_LEVEL_MASK
) |
582 ((0 & RADEON_TV_V_BURST_LEVEL_MASK
) << RADEON_TV_V_BURST_LEVEL_SHIFT
);
583 } else if (tv_dac
->tv_std
== TV_STD_SCART_PAL
) {
584 tv_modulator_cntl1
|= RADEON_ALT_PHASE_EN
;
585 tv_modulator_cntl2
= (0 & RADEON_TV_U_BURST_LEVEL_MASK
) |
586 ((0 & RADEON_TV_V_BURST_LEVEL_MASK
) << RADEON_TV_V_BURST_LEVEL_SHIFT
);
588 tv_modulator_cntl1
|= RADEON_ALT_PHASE_EN
|
589 (0x3b << RADEON_SET_UP_LEVEL_SHIFT
) |
590 (0x3b << RADEON_BLANK_LEVEL_SHIFT
);
591 tv_modulator_cntl2
= (-78 & RADEON_TV_U_BURST_LEVEL_MASK
) |
592 ((62 & RADEON_TV_V_BURST_LEVEL_MASK
) << RADEON_TV_V_BURST_LEVEL_SHIFT
);
596 tv_rgb_cntl
= (RADEON_RGB_DITHER_EN
597 | RADEON_TVOUT_SCALE_EN
598 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT
)
599 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT
)
600 | RADEON_RGB_ATTEN_SEL(0x3)
601 | RADEON_RGB_ATTEN_VAL(0xc));
603 if (radeon_crtc
->crtc_id
== 1)
604 tv_rgb_cntl
|= RADEON_RGB_SRC_SEL_CRTC2
;
606 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
607 tv_rgb_cntl
|= RADEON_RGB_SRC_SEL_RMX
;
609 tv_rgb_cntl
|= RADEON_RGB_SRC_SEL_CRTC1
;
612 if (tv_dac
->tv_std
== TV_STD_NTSC
||
613 tv_dac
->tv_std
== TV_STD_NTSC_J
||
614 tv_dac
->tv_std
== TV_STD_PAL_M
||
615 tv_dac
->tv_std
== TV_STD_PAL_60
)
616 vert_space
= const_ptr
->ver_total
* 2 * 10000 / NTSC_TV_LINES_PER_FRAME
;
618 vert_space
= const_ptr
->ver_total
* 2 * 10000 / PAL_TV_LINES_PER_FRAME
;
620 tmp
= RREG32(RADEON_TV_VSCALER_CNTL1
);
622 tmp
|= (vert_space
* (1 << FRAC_BITS
) / 10000);
623 tv_vscaler_cntl1
= tmp
;
625 if (pll_ref_freq
== 2700)
626 tv_vscaler_cntl1
|= RADEON_RESTART_FIELD
;
628 if (const_ptr
->hor_resolution
== 1024)
629 tv_vscaler_cntl1
|= (4 << RADEON_Y_DEL_W_SIG_SHIFT
);
631 tv_vscaler_cntl1
|= (2 << RADEON_Y_DEL_W_SIG_SHIFT
);
633 /* scale up for int divide */
634 tmp
= const_ptr
->ver_total
* 2 * 1000;
635 if (tv_dac
->tv_std
== TV_STD_NTSC
||
636 tv_dac
->tv_std
== TV_STD_NTSC_J
||
637 tv_dac
->tv_std
== TV_STD_PAL_M
||
638 tv_dac
->tv_std
== TV_STD_PAL_60
) {
639 tmp
/= NTSC_TV_LINES_PER_FRAME
;
641 tmp
/= PAL_TV_LINES_PER_FRAME
;
643 flicker_removal
= (tmp
+ 500) / 1000;
645 if (flicker_removal
< 3)
647 for (i
= 0; i
< ARRAY_SIZE(SLOPE_limit
); ++i
) {
648 if (flicker_removal
== SLOPE_limit
[i
])
652 tv_y_saw_tooth_cntl
= (vert_space
* SLOPE_value
[i
] * (1 << (FRAC_BITS
- 1)) +
653 5001) / 10000 / 8 | ((SLOPE_value
[i
] *
654 (1 << (FRAC_BITS
- 1)) / 8) << 16);
656 (YCOEF_EN_value
[i
] << 17) | ((YCOEF_value
[i
] * (1 << 8) / 8) << 24) |
657 RADEON_Y_FALL_PING_PONG
| (272 * SLOPE_value
[i
] / 8) * (1 << (FRAC_BITS
- 1)) /
659 tv_y_rise_cntl
= RADEON_Y_RISE_PING_PONG
|
660 (flicker_removal
* 1024 - 272) * SLOPE_value
[i
] / 8 * (1 << (FRAC_BITS
- 1)) / 1024;
662 tv_vscaler_cntl2
= RREG32(RADEON_TV_VSCALER_CNTL2
) & 0x00fffff0;
663 tv_vscaler_cntl2
|= (0x10 << 24) |
665 RADEON_Y_OUTPUT_DITHER_EN
|
666 RADEON_UV_OUTPUT_DITHER_EN
|
667 RADEON_UV_TO_BUF_DITHER_EN
;
669 tmp
= (tv_vscaler_cntl1
>> RADEON_UV_INC_SHIFT
) & RADEON_UV_INC_MASK
;
670 tmp
= ((16384 * 256 * 10) / tmp
+ 5) / 10;
671 tmp
= (tmp
<< RADEON_UV_OUTPUT_POST_SCALE_SHIFT
) | 0x000b0000;
672 tv_dac
->tv
.timing_cntl
= tmp
;
674 if (tv_dac
->tv_std
== TV_STD_NTSC
||
675 tv_dac
->tv_std
== TV_STD_NTSC_J
||
676 tv_dac
->tv_std
== TV_STD_PAL_M
||
677 tv_dac
->tv_std
== TV_STD_PAL_60
)
678 tv_dac_cntl
= tv_dac
->ntsc_tvdac_adj
;
680 tv_dac_cntl
= tv_dac
->pal_tvdac_adj
;
682 tv_dac_cntl
|= RADEON_TV_DAC_NBLANK
| RADEON_TV_DAC_NHOLD
;
684 if (tv_dac
->tv_std
== TV_STD_NTSC
||
685 tv_dac
->tv_std
== TV_STD_NTSC_J
)
686 tv_dac_cntl
|= RADEON_TV_DAC_STD_NTSC
;
688 tv_dac_cntl
|= RADEON_TV_DAC_STD_PAL
;
690 if (tv_dac
->tv_std
== TV_STD_NTSC
||
691 tv_dac
->tv_std
== TV_STD_NTSC_J
) {
692 if (pll_ref_freq
== 2700) {
693 m
= NTSC_TV_PLL_M_27
;
694 n
= NTSC_TV_PLL_N_27
;
695 p
= NTSC_TV_PLL_P_27
;
697 m
= NTSC_TV_PLL_M_14
;
698 n
= NTSC_TV_PLL_N_14
;
699 p
= NTSC_TV_PLL_P_14
;
702 if (pll_ref_freq
== 2700) {
713 tv_pll_cntl
= (m
& RADEON_TV_M0LO_MASK
) |
714 (((m
>> 8) & RADEON_TV_M0HI_MASK
) << RADEON_TV_M0HI_SHIFT
) |
715 ((n
& RADEON_TV_N0LO_MASK
) << RADEON_TV_N0LO_SHIFT
) |
716 (((n
>> 9) & RADEON_TV_N0HI_MASK
) << RADEON_TV_N0HI_SHIFT
) |
717 ((p
& RADEON_TV_P_MASK
) << RADEON_TV_P_SHIFT
);
719 tv_pll_cntl1
= (((4 & RADEON_TVPCP_MASK
) << RADEON_TVPCP_SHIFT
) |
720 ((4 & RADEON_TVPVG_MASK
) << RADEON_TVPVG_SHIFT
) |
721 ((1 & RADEON_TVPDC_MASK
) << RADEON_TVPDC_SHIFT
) |
722 RADEON_TVCLK_SRC_SEL_TVPLL
|
723 RADEON_TVPLL_TEST_DIS
);
725 tv_dac
->tv
.tv_uv_adr
= 0xc8;
727 if (tv_dac
->tv_std
== TV_STD_NTSC
||
728 tv_dac
->tv_std
== TV_STD_NTSC_J
||
729 tv_dac
->tv_std
== TV_STD_PAL_M
||
730 tv_dac
->tv_std
== TV_STD_PAL_60
) {
731 tv_ftotal
= NTSC_TV_VFTOTAL
;
732 hor_timing
= hor_timing_NTSC
;
733 vert_timing
= vert_timing_NTSC
;
735 hor_timing
= hor_timing_PAL
;
736 vert_timing
= vert_timing_PAL
;
737 tv_ftotal
= PAL_TV_VFTOTAL
;
740 for (i
= 0; i
< MAX_H_CODE_TIMING_LEN
; i
++) {
741 if ((tv_dac
->tv
.h_code_timing
[i
] = hor_timing
[i
]) == 0)
745 for (i
= 0; i
< MAX_V_CODE_TIMING_LEN
; i
++) {
746 if ((tv_dac
->tv
.v_code_timing
[i
] = vert_timing
[i
]) == 0)
750 radeon_legacy_tv_init_restarts(encoder
);
752 /* play with DAC_CNTL */
753 /* play with GPIOPAD_A */
754 /* DISP_OUTPUT_CNTL */
755 /* use reference freq */
757 /* program the TV registers */
758 WREG32(RADEON_TV_MASTER_CNTL
, (tv_master_cntl
| RADEON_TV_ASYNC_RST
|
759 RADEON_CRT_ASYNC_RST
| RADEON_TV_FIFO_ASYNC_RST
));
761 tmp
= RREG32(RADEON_TV_DAC_CNTL
);
762 tmp
&= ~RADEON_TV_DAC_NBLANK
;
763 tmp
|= RADEON_TV_DAC_BGSLEEP
|
764 RADEON_TV_DAC_RDACPD
|
765 RADEON_TV_DAC_GDACPD
|
766 RADEON_TV_DAC_BDACPD
;
767 WREG32(RADEON_TV_DAC_CNTL
, tmp
);
770 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL
);
771 WREG32_PLL(RADEON_TV_PLL_CNTL
, tv_pll_cntl
);
772 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, RADEON_TVPLL_RESET
, ~RADEON_TVPLL_RESET
);
774 radeon_wait_pll_lock(encoder
, 200, 800, 135);
776 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, 0, ~RADEON_TVPLL_RESET
);
778 radeon_wait_pll_lock(encoder
, 300, 160, 27);
779 radeon_wait_pll_lock(encoder
, 200, 800, 135);
781 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, 0, ~0xf);
782 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, RADEON_TVCLK_SRC_SEL_TVPLL
, ~RADEON_TVCLK_SRC_SEL_TVPLL
);
784 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, (1 << RADEON_TVPDC_SHIFT
), ~RADEON_TVPDC_MASK
);
785 WREG32_PLL_P(RADEON_TV_PLL_CNTL1
, 0, ~RADEON_TVPLL_SLEEP
);
788 WREG32(RADEON_TV_RGB_CNTL
, tv_rgb_cntl
);
789 WREG32(RADEON_TV_HTOTAL
, const_ptr
->hor_total
- 1);
790 WREG32(RADEON_TV_HDISP
, const_ptr
->hor_resolution
- 1);
791 WREG32(RADEON_TV_HSTART
, const_ptr
->hor_start
);
793 WREG32(RADEON_TV_VTOTAL
, const_ptr
->ver_total
- 1);
794 WREG32(RADEON_TV_VDISP
, const_ptr
->ver_resolution
- 1);
795 WREG32(RADEON_TV_FTOTAL
, tv_ftotal
);
796 WREG32(RADEON_TV_VSCALER_CNTL1
, tv_vscaler_cntl1
);
797 WREG32(RADEON_TV_VSCALER_CNTL2
, tv_vscaler_cntl2
);
799 WREG32(RADEON_TV_Y_FALL_CNTL
, tv_y_fall_cntl
);
800 WREG32(RADEON_TV_Y_RISE_CNTL
, tv_y_rise_cntl
);
801 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL
, tv_y_saw_tooth_cntl
);
803 WREG32(RADEON_TV_MASTER_CNTL
, (tv_master_cntl
| RADEON_TV_ASYNC_RST
|
804 RADEON_CRT_ASYNC_RST
));
807 radeon_legacy_write_tv_restarts(radeon_encoder
);
810 radeon_restore_tv_timing_tables(radeon_encoder
);
812 WREG32(RADEON_TV_MASTER_CNTL
, (tv_master_cntl
| RADEON_TV_ASYNC_RST
));
815 WREG32(RADEON_TV_SYNC_CNTL
, (RADEON_SYNC_PUB
| RADEON_TV_SYNC_IO_DRIVE
));
816 WREG32(RADEON_TV_TIMING_CNTL
, tv_dac
->tv
.timing_cntl
);
817 WREG32(RADEON_TV_MODULATOR_CNTL1
, tv_modulator_cntl1
);
818 WREG32(RADEON_TV_MODULATOR_CNTL2
, tv_modulator_cntl2
);
819 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL
, (RADEON_Y_RED_EN
|
822 RADEON_DAC_DITHER_EN
));
824 WREG32(RADEON_TV_CRC_CNTL
, 0);
826 WREG32(RADEON_TV_MASTER_CNTL
, tv_master_cntl
);
828 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS
, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT
) |
829 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT
)));
830 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS
, ((0x100 << RADEON_UV_GAIN_SHIFT
) |
831 (0x100 << RADEON_Y_GAIN_SHIFT
)));
833 WREG32(RADEON_TV_DAC_CNTL
, tv_dac_cntl
);
837 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder
*encoder
,
838 uint32_t *h_total_disp
, uint32_t *h_sync_strt_wid
,
839 uint32_t *v_total_disp
, uint32_t *v_sync_strt_wid
)
841 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
842 const struct radeon_tv_mode_constants
*const_ptr
;
845 const_ptr
= radeon_legacy_tv_get_std_mode(radeon_encoder
, NULL
);
849 *h_total_disp
= (((const_ptr
->hor_resolution
/ 8) - 1) << RADEON_CRTC_H_DISP_SHIFT
) |
850 (((const_ptr
->hor_total
/ 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT
);
852 tmp
= *h_sync_strt_wid
;
853 tmp
&= ~(RADEON_CRTC_H_SYNC_STRT_PIX
| RADEON_CRTC_H_SYNC_STRT_CHAR
);
854 tmp
|= (((const_ptr
->hor_syncstart
/ 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT
) |
855 (const_ptr
->hor_syncstart
& 7);
856 *h_sync_strt_wid
= tmp
;
858 *v_total_disp
= ((const_ptr
->ver_resolution
- 1) << RADEON_CRTC_V_DISP_SHIFT
) |
859 ((const_ptr
->ver_total
- 1) << RADEON_CRTC_V_TOTAL_SHIFT
);
861 tmp
= *v_sync_strt_wid
;
862 tmp
&= ~RADEON_CRTC_V_SYNC_STRT
;
863 tmp
|= ((const_ptr
->ver_syncstart
- 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT
);
864 *v_sync_strt_wid
= tmp
;
867 static inline int get_post_div(int value
)
871 case 1: post_div
= 0; break;
872 case 2: post_div
= 1; break;
873 case 3: post_div
= 4; break;
874 case 4: post_div
= 2; break;
875 case 6: post_div
= 6; break;
876 case 8: post_div
= 3; break;
877 case 12: post_div
= 7; break;
879 default: post_div
= 5; break;
884 void radeon_legacy_tv_adjust_pll1(struct drm_encoder
*encoder
,
885 uint32_t *htotal_cntl
, uint32_t *ppll_ref_div
,
886 uint32_t *ppll_div_3
, uint32_t *pixclks_cntl
)
888 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
889 const struct radeon_tv_mode_constants
*const_ptr
;
891 const_ptr
= radeon_legacy_tv_get_std_mode(radeon_encoder
, NULL
);
895 *htotal_cntl
= (const_ptr
->hor_total
& 0x7) | RADEON_HTOT_CNTL_VGA_EN
;
897 *ppll_ref_div
= const_ptr
->crtcPLL_M
;
899 *ppll_div_3
= (const_ptr
->crtcPLL_N
& 0x7ff) | (get_post_div(const_ptr
->crtcPLL_post_div
) << 16);
900 *pixclks_cntl
&= ~(RADEON_PIX2CLK_SRC_SEL_MASK
| RADEON_PIXCLK_TV_SRC_SEL
);
901 *pixclks_cntl
|= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK
;
904 void radeon_legacy_tv_adjust_pll2(struct drm_encoder
*encoder
,
905 uint32_t *htotal2_cntl
, uint32_t *p2pll_ref_div
,
906 uint32_t *p2pll_div_0
, uint32_t *pixclks_cntl
)
908 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
909 const struct radeon_tv_mode_constants
*const_ptr
;
911 const_ptr
= radeon_legacy_tv_get_std_mode(radeon_encoder
, NULL
);
915 *htotal2_cntl
= (const_ptr
->hor_total
& 0x7);
917 *p2pll_ref_div
= const_ptr
->crtcPLL_M
;
919 *p2pll_div_0
= (const_ptr
->crtcPLL_N
& 0x7ff) | (get_post_div(const_ptr
->crtcPLL_post_div
) << 16);
920 *pixclks_cntl
&= ~RADEON_PIX2CLK_SRC_SEL_MASK
;
921 *pixclks_cntl
|= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK
| RADEON_PIXCLK_TV_SRC_SEL
;