drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include "radeon_drm.h"
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  50 {
  51         struct radeon_bo *bo;
  52
  53         bo = container_of(tbo, struct radeon_bo, tbo);
  54         mutex_lock(&bo->rdev->gem.mutex);
  55         list_del_init(&bo->list);
  56         mutex_unlock(&bo->rdev->gem.mutex);
  57         radeon_bo_clear_surface_reg(bo);
  58         drm_gem_object_release(&bo->gem_base);
  59         kfree(bo);
  60 }
  61
  62 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  63 {
  64         if (bo->destroy == &radeon_ttm_bo_destroy)
  65                 return true;
  66         return false;
  67 }
  68
  69 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  70 {
  71         u32 c = 0;
  72
  73         rbo->placement.fpfn = 0;
  74         rbo->placement.lpfn = 0;
  75         rbo->placement.placement = rbo->placements;
  76         rbo->placement.busy_placement = rbo->placements;
  77         if (domain & RADEON_GEM_DOMAIN_VRAM)
  78                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79                                         TTM_PL_FLAG_VRAM;
  80         if (domain & RADEON_GEM_DOMAIN_GTT)
  81                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  82         if (domain & RADEON_GEM_DOMAIN_CPU)
  83                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  84         if (!c)
  85                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  86         rbo->placement.num_placement = c;
  87         rbo->placement.num_busy_placement = c;
  88 }
  89
  90 int radeon_bo_create(struct radeon_device *rdev,
  91                      unsigned long size, int byte_align, bool kernel, u32 domain,
  92                      struct radeon_bo **bo_ptr)
  93 {
  94         struct radeon_bo *bo;
  95         enum ttm_bo_type type;
  96         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
  97         unsigned long max_size = 0;
  98         int r;
  99
 100         size = ALIGN(size, PAGE_SIZE);
 101
 102         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
 103                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 104         }
 105         if (kernel) {
 106                 type = ttm_bo_type_kernel;
 107         } else {
 108                 type = ttm_bo_type_device;
 109         }
 110         *bo_ptr = NULL;
 111
 112         /* maximun bo size is the minimun btw visible vram and gtt size */
 113         max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
 114         if ((page_align << PAGE_SHIFT) >= max_size) {
 115                 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
 116                         __func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
 117                 return -ENOMEM;
 118         }
 119
 120 retry:
 121         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 122         if (bo == NULL)
 123                 return -ENOMEM;
 124         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 125         if (unlikely(r)) {
 126                 kfree(bo);
 127                 return r;
 128         }
 129         bo->rdev = rdev;
 130         bo->gem_base.driver_private = NULL;
 131         bo->surface_reg = -1;
 132         INIT_LIST_HEAD(&bo->list);
 133         radeon_ttm_placement_from_domain(bo, domain);
 134         /* Kernel allocation are uninterruptible */
 135         mutex_lock(&rdev->vram_mutex);
 136         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 137                         &bo->placement, page_align, 0, !kernel, NULL, size,
 138                         &radeon_ttm_bo_destroy);
 139         mutex_unlock(&rdev->vram_mutex);
 140         if (unlikely(r != 0)) {
 141                 if (r != -ERESTARTSYS) {
 142                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 143                                 domain |= RADEON_GEM_DOMAIN_GTT;
 144                                 goto retry;
 145                         }
 146                         dev_err(rdev->dev,
 147                                 "object_init failed for (%lu, 0x%08X)\n",
 148                                 size, domain);
 149                 }
 150                 return r;
 151         }
 152         *bo_ptr = bo;
 153
 154         trace_radeon_bo_create(bo);
 155
 156         return 0;
 157 }
 158
 159 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 160 {
 161         bool is_iomem;
 162         int r;
 163
 164         if (bo->kptr) {
 165                 if (ptr) {
 166                         *ptr = bo->kptr;
 167                 }
 168                 return 0;
 169         }
 170         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 171         if (r) {
 172                 return r;
 173         }
 174         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 175         if (ptr) {
 176                 *ptr = bo->kptr;
 177         }
 178         radeon_bo_check_tiling(bo, 0, 0);
 179         return 0;
 180 }
 181
 182 void radeon_bo_kunmap(struct radeon_bo *bo)
 183 {
 184         if (bo->kptr == NULL)
 185                 return;
 186         bo->kptr = NULL;
 187         radeon_bo_check_tiling(bo, 0, 0);
 188         ttm_bo_kunmap(&bo->kmap);
 189 }
 190
 191 void radeon_bo_unref(struct radeon_bo **bo)
 192 {
 193         struct ttm_buffer_object *tbo;
 194         struct radeon_device *rdev;
 195
 196         if ((*bo) == NULL)
 197                 return;
 198         rdev = (*bo)->rdev;
 199         tbo = &((*bo)->tbo);
 200         mutex_lock(&rdev->vram_mutex);
 201         ttm_bo_unref(&tbo);
 202         mutex_unlock(&rdev->vram_mutex);
 203         if (tbo == NULL)
 204                 *bo = NULL;
 205 }
 206
 207 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 208 {
 209         int r, i;
 210
 211         if (bo->pin_count) {
 212                 bo->pin_count++;
 213                 if (gpu_addr)
 214                         *gpu_addr = radeon_bo_gpu_offset(bo);
 215                 return 0;
 216         }
 217         radeon_ttm_placement_from_domain(bo, domain);
 218         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 219                 /* force to pin into visible video ram */
 220                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 221         }
 222         for (i = 0; i < bo->placement.num_placement; i++)
 223                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 224         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 225         if (likely(r == 0)) {
 226                 bo->pin_count = 1;
 227                 if (gpu_addr != NULL)
 228                         *gpu_addr = radeon_bo_gpu_offset(bo);
 229         }
 230         if (unlikely(r != 0))
 231                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 232         return r;
 233 }
 234
 235 int radeon_bo_unpin(struct radeon_bo *bo)
 236 {
 237         int r, i;
 238
 239         if (!bo->pin_count) {
 240                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 241                 return 0;
 242         }
 243         bo->pin_count--;
 244         if (bo->pin_count)
 245                 return 0;
 246         for (i = 0; i < bo->placement.num_placement; i++)
 247                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 248         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 249         if (unlikely(r != 0))
 250                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 251         return r;
 252 }
 253
 254 int radeon_bo_evict_vram(struct radeon_device *rdev)
 255 {
 256         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 257         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 258                 if (rdev->mc.igp_sideport_enabled == false)
 259                         /* Useless to evict on IGP chips */
 260                         return 0;
 261         }
 262         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 263 }
 264
 265 void radeon_bo_force_delete(struct radeon_device *rdev)
 266 {
 267         struct radeon_bo *bo, *n;
 268
 269         if (list_empty(&rdev->gem.objects)) {
 270                 return;
 271         }
 272         dev_err(rdev->dev, "Userspace still has active objects !\n");
 273         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 274                 mutex_lock(&rdev->ddev->struct_mutex);
 275                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 276                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 277                         *((unsigned long *)&bo->gem_base.refcount));
 278                 mutex_lock(&bo->rdev->gem.mutex);
 279                 list_del_init(&bo->list);
 280                 mutex_unlock(&bo->rdev->gem.mutex);
 281                 /* this should unref the ttm bo */
 282                 drm_gem_object_unreference(&bo->gem_base);
 283                 mutex_unlock(&rdev->ddev->struct_mutex);
 284         }
 285 }
 286
 287 int radeon_bo_init(struct radeon_device *rdev)
 288 {
 289         /* Add an MTRR for the VRAM */
 290         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 291                         MTRR_TYPE_WRCOMB, 1);
 292         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 293                 rdev->mc.mc_vram_size >> 20,
 294                 (unsigned long long)rdev->mc.aper_size >> 20);
 295         DRM_INFO("RAM width %dbits %cDR\n",
 296                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 297         return radeon_ttm_init(rdev);
 298 }
 299
 300 void radeon_bo_fini(struct radeon_device *rdev)
 301 {
 302         radeon_ttm_fini(rdev);
 303 }
 304
 305 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 306                                 struct list_head *head)
 307 {
 308         if (lobj->wdomain) {
 309                 list_add(&lobj->tv.head, head);
 310         } else {
 311                 list_add_tail(&lobj->tv.head, head);
 312         }
 313 }
 314
 315 int radeon_bo_list_validate(struct list_head *head)
 316 {
 317         struct radeon_bo_list *lobj;
 318         struct radeon_bo *bo;
 319         u32 domain;
 320         int r;
 321
 322         r = ttm_eu_reserve_buffers(head);
 323         if (unlikely(r != 0)) {
 324                 return r;
 325         }
 326         list_for_each_entry(lobj, head, tv.head) {
 327                 bo = lobj->bo;
 328                 if (!bo->pin_count) {
 329                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 330
 331                 retry:
 332                         radeon_ttm_placement_from_domain(bo, domain);
 333                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 334                                                 true, false, false);
 335                         if (unlikely(r)) {
 336                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 337                                         domain |= RADEON_GEM_DOMAIN_GTT;
 338                                         goto retry;
 339                                 }
 340                                 return r;
 341                         }
 342                 }
 343                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 344                 lobj->tiling_flags = bo->tiling_flags;
 345         }
 346         return 0;
 347 }
 348
 349 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 350                              struct vm_area_struct *vma)
 351 {
 352         return ttm_fbdev_mmap(vma, &bo->tbo);
 353 }
 354
 355 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 356 {
 357         struct radeon_device *rdev = bo->rdev;
 358         struct radeon_surface_reg *reg;
 359         struct radeon_bo *old_object;
 360         int steal;
 361         int i;
 362
 363         BUG_ON(!atomic_read(&bo->tbo.reserved));
 364
 365         if (!bo->tiling_flags)
 366                 return 0;
 367
 368         if (bo->surface_reg >= 0) {
 369                 reg = &rdev->surface_regs[bo->surface_reg];
 370                 i = bo->surface_reg;
 371                 goto out;
 372         }
 373
 374         steal = -1;
 375         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 376
 377                 reg = &rdev->surface_regs[i];
 378                 if (!reg->bo)
 379                         break;
 380
 381                 old_object = reg->bo;
 382                 if (old_object->pin_count == 0)
 383                         steal = i;
 384         }
 385
 386         /* if we are all out */
 387         if (i == RADEON_GEM_MAX_SURFACES) {
 388                 if (steal == -1)
 389                         return -ENOMEM;
 390                 /* find someone with a surface reg and nuke their BO */
 391                 reg = &rdev->surface_regs[steal];
 392                 old_object = reg->bo;
 393                 /* blow away the mapping */
 394                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 395                 ttm_bo_unmap_virtual(&old_object->tbo);
 396                 old_object->surface_reg = -1;
 397                 i = steal;
 398         }
 399
 400         bo->surface_reg = i;
 401         reg->bo = bo;
 402
 403 out:
 404         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 405                                bo->tbo.mem.start << PAGE_SHIFT,
 406                                bo->tbo.num_pages << PAGE_SHIFT);
 407         return 0;
 408 }
 409
 410 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 411 {
 412         struct radeon_device *rdev = bo->rdev;
 413         struct radeon_surface_reg *reg;
 414
 415         if (bo->surface_reg == -1)
 416                 return;
 417
 418         reg = &rdev->surface_regs[bo->surface_reg];
 419         radeon_clear_surface_reg(rdev, bo->surface_reg);
 420
 421         reg->bo = NULL;
 422         bo->surface_reg = -1;
 423 }
 424
 425 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 426                                 uint32_t tiling_flags, uint32_t pitch)
 427 {
 428         int r;
 429
 430         r = radeon_bo_reserve(bo, false);
 431         if (unlikely(r != 0))
 432                 return r;
 433         bo->tiling_flags = tiling_flags;
 434         bo->pitch = pitch;
 435         radeon_bo_unreserve(bo);
 436         return 0;
 437 }
 438
 439 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 440                                 uint32_t *tiling_flags,
 441                                 uint32_t *pitch)
 442 {
 443         BUG_ON(!atomic_read(&bo->tbo.reserved));
 444         if (tiling_flags)
 445                 *tiling_flags = bo->tiling_flags;
 446         if (pitch)
 447                 *pitch = bo->pitch;
 448 }
 449
 450 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 451                                 bool force_drop)
 452 {
 453         BUG_ON(!atomic_read(&bo->tbo.reserved));
 454
 455         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 456                 return 0;
 457
 458         if (force_drop) {
 459                 radeon_bo_clear_surface_reg(bo);
 460                 return 0;
 461         }
 462
 463         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 464                 if (!has_moved)
 465                         return 0;
 466
 467                 if (bo->surface_reg >= 0)
 468                         radeon_bo_clear_surface_reg(bo);
 469                 return 0;
 470         }
 471
 472         if ((bo->surface_reg >= 0) && !has_moved)
 473                 return 0;
 474
 475         return radeon_bo_get_surface_reg(bo);
 476 }
 477
 478 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 479                            struct ttm_mem_reg *mem)
 480 {
 481         struct radeon_bo *rbo;
 482         if (!radeon_ttm_bo_is_radeon_bo(bo))
 483                 return;
 484         rbo = container_of(bo, struct radeon_bo, tbo);
 485         radeon_bo_check_tiling(rbo, 0, 1);
 486 }
 487
 488 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 489 {
 490         struct radeon_device *rdev;
 491         struct radeon_bo *rbo;
 492         unsigned long offset, size;
 493         int r;
 494
 495         if (!radeon_ttm_bo_is_radeon_bo(bo))
 496                 return 0;
 497         rbo = container_of(bo, struct radeon_bo, tbo);
 498         radeon_bo_check_tiling(rbo, 0, 0);
 499         rdev = rbo->rdev;
 500         if (bo->mem.mem_type == TTM_PL_VRAM) {
 501                 size = bo->mem.num_pages << PAGE_SHIFT;
 502                 offset = bo->mem.start << PAGE_SHIFT;
 503                 if ((offset + size) > rdev->mc.visible_vram_size) {
 504                         /* hurrah the memory is not visible ! */
 505                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 506                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 507                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
 508                         if (unlikely(r != 0))
 509                                 return r;
 510                         offset = bo->mem.start << PAGE_SHIFT;
 511                         /* this should not happen */
 512                         if ((offset + size) > rdev->mc.visible_vram_size)
 513                                 return -EINVAL;
 514                 }
 515         }
 516         return 0;
 517 }