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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / gpu / drm / vmwgfx / svga3d_reg.h
blob77cb453310009e65ef7fd955c580d4b1ba3938b2
1 /**********************************************************
2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 /*
27 * svga3d_reg.h --
28 *
29 * SVGA 3D hardware definitions
30 */
31
32 #ifndef _SVGA3D_REG_H_
33 #define _SVGA3D_REG_H_
34
35 #include "svga_reg.h"
36
37
38 /*
39 * 3D Hardware Version
40 *
41 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
42 * register. Is set by the host and read by the guest. This lets
43 * us make new guest drivers which are backwards-compatible with old
44 * SVGA hardware revisions. It does not let us support old guest
45 * drivers. Good enough for now.
46 *
47 */
48
49 #define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
50 #define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
51 #define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
52
53 typedef enum {
54 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
55 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
56 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
57 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
58 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
59 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
60 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS65_B1,
61 } SVGA3dHardwareVersion;
62
63 /*
64 * Generic Types
65 */
66
67 typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
68 #define SVGA3D_NUM_CLIPPLANES 6
69 #define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
70
71
72 /*
73 * Surface formats.
74 *
75 * If you modify this list, be sure to keep GLUtil.c in sync. It
76 * includes the internal format definition of each surface in
77 * GLUtil_ConvertSurfaceFormat, and it contains a table of
78 * human-readable names in GLUtil_GetFormatName.
79 */
80
81 typedef enum SVGA3dSurfaceFormat {
82 SVGA3D_FORMAT_INVALID = 0,
83
84 SVGA3D_X8R8G8B8 = 1,
85 SVGA3D_A8R8G8B8 = 2,
86
87 SVGA3D_R5G6B5 = 3,
88 SVGA3D_X1R5G5B5 = 4,
89 SVGA3D_A1R5G5B5 = 5,
90 SVGA3D_A4R4G4B4 = 6,
91
92 SVGA3D_Z_D32 = 7,
93 SVGA3D_Z_D16 = 8,
94 SVGA3D_Z_D24S8 = 9,
95 SVGA3D_Z_D15S1 = 10,
96
97 SVGA3D_LUMINANCE8 = 11,
98 SVGA3D_LUMINANCE4_ALPHA4 = 12,
99 SVGA3D_LUMINANCE16 = 13,
100 SVGA3D_LUMINANCE8_ALPHA8 = 14,
101
102 SVGA3D_DXT1 = 15,
103 SVGA3D_DXT2 = 16,
104 SVGA3D_DXT3 = 17,
105 SVGA3D_DXT4 = 18,
106 SVGA3D_DXT5 = 19,
107
108 SVGA3D_BUMPU8V8 = 20,
109 SVGA3D_BUMPL6V5U5 = 21,
110 SVGA3D_BUMPX8L8V8U8 = 22,
111 SVGA3D_BUMPL8V8U8 = 23,
112
113 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
114 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
115
116 SVGA3D_A2R10G10B10 = 26,
117
118 /* signed formats */
119 SVGA3D_V8U8 = 27,
120 SVGA3D_Q8W8V8U8 = 28,
121 SVGA3D_CxV8U8 = 29,
122
123 /* mixed formats */
124 SVGA3D_X8L8V8U8 = 30,
125 SVGA3D_A2W10V10U10 = 31,
126
127 SVGA3D_ALPHA8 = 32,
128
129 /* Single- and dual-component floating point formats */
130 SVGA3D_R_S10E5 = 33,
131 SVGA3D_R_S23E8 = 34,
132 SVGA3D_RG_S10E5 = 35,
133 SVGA3D_RG_S23E8 = 36,
134
135 /*
136 * Any surface can be used as a buffer object, but SVGA3D_BUFFER is
137 * the most efficient format to use when creating new surfaces
138 * expressly for index or vertex data.
139 */
140 SVGA3D_BUFFER = 37,
141
142 SVGA3D_Z_D24X8 = 38,
143
144 SVGA3D_V16U16 = 39,
145
146 SVGA3D_G16R16 = 40,
147 SVGA3D_A16B16G16R16 = 41,
148
149 /* Packed Video formats */
150 SVGA3D_UYVY = 42,
151 SVGA3D_YUY2 = 43,
152
153 SVGA3D_FORMAT_MAX
154 } SVGA3dSurfaceFormat;
155
156 typedef uint32 SVGA3dColor; /* a, r, g, b */
157
158 /*
159 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
160 * them so that we can query the host for what the supported surface
161 * operations are (when we're using the D3D backend, in particular),
162 * and so we can send those operations to the guest.
163 */
164 typedef enum {
165 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
166 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
167 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
168 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
169 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
170 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
171 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
172
173 /*
174 * This format can be used as a render target if the current display mode
175 * is the same depth if the alpha channel is ignored. e.g. if the device
176 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
177 * format op list entry for A8R8G8B8 should have this cap.
178 */
179 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
180
181 /*
182 * This format contains DirectDraw support (including Flip). This flag
183 * should not to be set on alpha formats.
184 */
185 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
186
187 /*
188 * The rasterizer can support some level of Direct3D support in this format
189 * and implies that the driver can create a Context in this mode (for some
190 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
191 * flag must also be set.
192 */
193 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
194
195 /*
196 * This is set for a private format when the driver has put the bpp in
197 * the structure.
198 */
199 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
200
201 /*
202 * Indicates that this format can be converted to any RGB format for which
203 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
204 */
205 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
206
207 /*
208 * Indicates that this format can be used to create offscreen plain surfaces.
209 */
210 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
211
212 /*
213 * Indicated that this format can be read as an SRGB texture (meaning that the
214 * sampler will linearize the looked up data)
215 */
216 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
217
218 /*
219 * Indicates that this format can be used in the bumpmap instructions
220 */
221 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
222
223 /*
224 * Indicates that this format can be sampled by the displacement map sampler
225 */
226 SVGA3DFORMAT_OP_DMAP = 0x00020000,
227
228 /*
229 * Indicates that this format cannot be used with texture filtering
230 */
231 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
232
233 /*
234 * Indicates that format conversions are supported to this RGB format if
235 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
236 */
237 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
238
239 /*
240 * Indicated that this format can be written as an SRGB target (meaning that the
241 * pixel pipe will DE-linearize data on output to format)
242 */
243 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
244
245 /*
246 * Indicates that this format cannot be used with alpha blending
247 */
248 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
249
250 /*
251 * Indicates that the device can auto-generated sublevels for resources
252 * of this format
253 */
254 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
255
256 /*
257 * Indicates that this format can be used by vertex texture sampler
258 */
259 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
260
261 /*
262 * Indicates that this format supports neither texture coordinate wrap
263 * modes, nor mipmapping
264 */
265 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
266 } SVGA3dFormatOp;
267
268 /*
269 * This structure is a conversion of SVGA3DFORMAT_OP_*.
270 * Entries must be located at the same position.
271 */
272 typedef union {
273 uint32 value;
274 struct {
275 uint32 texture : 1;
276 uint32 volumeTexture : 1;
277 uint32 cubeTexture : 1;
278 uint32 offscreenRenderTarget : 1;
279 uint32 sameFormatRenderTarget : 1;
280 uint32 unknown1 : 1;
281 uint32 zStencil : 1;
282 uint32 zStencilArbitraryDepth : 1;
283 uint32 sameFormatUpToAlpha : 1;
284 uint32 unknown2 : 1;
285 uint32 displayMode : 1;
286 uint32 acceleration3d : 1;
287 uint32 pixelSize : 1;
288 uint32 convertToARGB : 1;
289 uint32 offscreenPlain : 1;
290 uint32 sRGBRead : 1;
291 uint32 bumpMap : 1;
292 uint32 dmap : 1;
293 uint32 noFilter : 1;
294 uint32 memberOfGroupARGB : 1;
295 uint32 sRGBWrite : 1;
296 uint32 noAlphaBlend : 1;
297 uint32 autoGenMipMap : 1;
298 uint32 vertexTexture : 1;
299 uint32 noTexCoordWrapNorMip : 1;
300 };
301 } SVGA3dSurfaceFormatCaps;
302
303 /*
304 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
305 * must fit in a uint32.
306 */
307
308 typedef enum {
309 SVGA3D_RS_INVALID = 0,
310 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
311 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
312 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
313 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
314 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
315 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
316 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
317 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
318 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
319 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
320 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
321 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
322 SVGA3D_RS_STENCILREF = 13, /* uint32 */
323 SVGA3D_RS_STENCILMASK = 14, /* uint32 */
324 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
325 SVGA3D_RS_FOGSTART = 16, /* float */
326 SVGA3D_RS_FOGEND = 17, /* float */
327 SVGA3D_RS_FOGDENSITY = 18, /* float */
328 SVGA3D_RS_POINTSIZE = 19, /* float */
329 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
330 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
331 SVGA3D_RS_POINTSCALE_A = 22, /* float */
332 SVGA3D_RS_POINTSCALE_B = 23, /* float */
333 SVGA3D_RS_POINTSCALE_C = 24, /* float */
334 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
335 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
336 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
337 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
338 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
339 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
340 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
341 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
342 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
343 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
344 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
345 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
346 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
347 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
348 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
349 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
350 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
351 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
352 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
353 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
354 SVGA3D_RS_ZBIAS = 45, /* float */
355 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
356 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
357 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
358 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
359 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
360 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
361 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
362 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
363 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
364 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
365 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
366 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
367 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
368 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
369 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
370 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
371 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
372 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
373 SVGA3D_RS_DEPTHBIAS = 64, /* float */
374
375
376 /*
377 * Output Gamma Level
378 *
379 * Output gamma effects the gamma curve of colors that are output from the
380 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
381 * value is <= 0.0, gamma correction is ignored and linear color space is
382 * used.
383 */
384
385 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
386 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
387 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
388 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
389 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
390 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
391 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
392 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
393 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
394 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
395 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
396 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
397 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
398 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
399 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
400 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
401 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
402 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
403 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
404 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
405 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
406 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
407 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
408 SVGA3D_RS_TWEENFACTOR = 88, /* float */
409 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
410 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
411 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
412 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
413 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
414 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
415 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
416 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
417 SVGA3D_RS_MAX
418 } SVGA3dRenderStateName;
419
420 typedef enum {
421 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
422 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
423 SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
424 } SVGA3dVertexMaterial;
425
426 typedef enum {
427 SVGA3D_FILLMODE_INVALID = 0,
428 SVGA3D_FILLMODE_POINT = 1,
429 SVGA3D_FILLMODE_LINE = 2,
430 SVGA3D_FILLMODE_FILL = 3,
431 SVGA3D_FILLMODE_MAX
432 } SVGA3dFillModeType;
433
434
435 typedef
436 union {
437 struct {
438 uint16 mode; /* SVGA3dFillModeType */
439 uint16 face; /* SVGA3dFace */
440 };
441 uint32 uintValue;
442 } SVGA3dFillMode;
443
444 typedef enum {
445 SVGA3D_SHADEMODE_INVALID = 0,
446 SVGA3D_SHADEMODE_FLAT = 1,
447 SVGA3D_SHADEMODE_SMOOTH = 2,
448 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
449 SVGA3D_SHADEMODE_MAX
450 } SVGA3dShadeMode;
451
452 typedef
453 union {
454 struct {
455 uint16 repeat;
456 uint16 pattern;
457 };
458 uint32 uintValue;
459 } SVGA3dLinePattern;
460
461 typedef enum {
462 SVGA3D_BLENDOP_INVALID = 0,
463 SVGA3D_BLENDOP_ZERO = 1,
464 SVGA3D_BLENDOP_ONE = 2,
465 SVGA3D_BLENDOP_SRCCOLOR = 3,
466 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
467 SVGA3D_BLENDOP_SRCALPHA = 5,
468 SVGA3D_BLENDOP_INVSRCALPHA = 6,
469 SVGA3D_BLENDOP_DESTALPHA = 7,
470 SVGA3D_BLENDOP_INVDESTALPHA = 8,
471 SVGA3D_BLENDOP_DESTCOLOR = 9,
472 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
473 SVGA3D_BLENDOP_SRCALPHASAT = 11,
474 SVGA3D_BLENDOP_BLENDFACTOR = 12,
475 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
476 SVGA3D_BLENDOP_MAX
477 } SVGA3dBlendOp;
478
479 typedef enum {
480 SVGA3D_BLENDEQ_INVALID = 0,
481 SVGA3D_BLENDEQ_ADD = 1,
482 SVGA3D_BLENDEQ_SUBTRACT = 2,
483 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
484 SVGA3D_BLENDEQ_MINIMUM = 4,
485 SVGA3D_BLENDEQ_MAXIMUM = 5,
486 SVGA3D_BLENDEQ_MAX
487 } SVGA3dBlendEquation;
488
489 typedef enum {
490 SVGA3D_FRONTWINDING_INVALID = 0,
491 SVGA3D_FRONTWINDING_CW = 1,
492 SVGA3D_FRONTWINDING_CCW = 2,
493 SVGA3D_FRONTWINDING_MAX
494 } SVGA3dFrontWinding;
495
496 typedef enum {
497 SVGA3D_FACE_INVALID = 0,
498 SVGA3D_FACE_NONE = 1,
499 SVGA3D_FACE_FRONT = 2,
500 SVGA3D_FACE_BACK = 3,
501 SVGA3D_FACE_FRONT_BACK = 4,
502 SVGA3D_FACE_MAX
503 } SVGA3dFace;
504
505 /*
506 * The order and the values should not be changed
507 */
508
509 typedef enum {
510 SVGA3D_CMP_INVALID = 0,
511 SVGA3D_CMP_NEVER = 1,
512 SVGA3D_CMP_LESS = 2,
513 SVGA3D_CMP_EQUAL = 3,
514 SVGA3D_CMP_LESSEQUAL = 4,
515 SVGA3D_CMP_GREATER = 5,
516 SVGA3D_CMP_NOTEQUAL = 6,
517 SVGA3D_CMP_GREATEREQUAL = 7,
518 SVGA3D_CMP_ALWAYS = 8,
519 SVGA3D_CMP_MAX
520 } SVGA3dCmpFunc;
521
522 /*
523 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
524 * the fog factor to be specified in the alpha component of the specular
525 * (a.k.a. secondary) vertex color.
526 */
527 typedef enum {
528 SVGA3D_FOGFUNC_INVALID = 0,
529 SVGA3D_FOGFUNC_EXP = 1,
530 SVGA3D_FOGFUNC_EXP2 = 2,
531 SVGA3D_FOGFUNC_LINEAR = 3,
532 SVGA3D_FOGFUNC_PER_VERTEX = 4
533 } SVGA3dFogFunction;
534
535 /*
536 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
537 * or per-pixel basis.
538 */
539 typedef enum {
540 SVGA3D_FOGTYPE_INVALID = 0,
541 SVGA3D_FOGTYPE_VERTEX = 1,
542 SVGA3D_FOGTYPE_PIXEL = 2,
543 SVGA3D_FOGTYPE_MAX = 3
544 } SVGA3dFogType;
545
546 /*
547 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
548 * computed using the eye Z value of each pixel (or vertex), whereas range-
549 * based fog is computed using the actual distance (range) to the eye.
550 */
551 typedef enum {
552 SVGA3D_FOGBASE_INVALID = 0,
553 SVGA3D_FOGBASE_DEPTHBASED = 1,
554 SVGA3D_FOGBASE_RANGEBASED = 2,
555 SVGA3D_FOGBASE_MAX = 3
556 } SVGA3dFogBase;
557
558 typedef enum {
559 SVGA3D_STENCILOP_INVALID = 0,
560 SVGA3D_STENCILOP_KEEP = 1,
561 SVGA3D_STENCILOP_ZERO = 2,
562 SVGA3D_STENCILOP_REPLACE = 3,
563 SVGA3D_STENCILOP_INCRSAT = 4,
564 SVGA3D_STENCILOP_DECRSAT = 5,
565 SVGA3D_STENCILOP_INVERT = 6,
566 SVGA3D_STENCILOP_INCR = 7,
567 SVGA3D_STENCILOP_DECR = 8,
568 SVGA3D_STENCILOP_MAX
569 } SVGA3dStencilOp;
570
571 typedef enum {
572 SVGA3D_CLIPPLANE_0 = (1 << 0),
573 SVGA3D_CLIPPLANE_1 = (1 << 1),
574 SVGA3D_CLIPPLANE_2 = (1 << 2),
575 SVGA3D_CLIPPLANE_3 = (1 << 3),
576 SVGA3D_CLIPPLANE_4 = (1 << 4),
577 SVGA3D_CLIPPLANE_5 = (1 << 5),
578 } SVGA3dClipPlanes;
579
580 typedef enum {
581 SVGA3D_CLEAR_COLOR = 0x1,
582 SVGA3D_CLEAR_DEPTH = 0x2,
583 SVGA3D_CLEAR_STENCIL = 0x4
584 } SVGA3dClearFlag;
585
586 typedef enum {
587 SVGA3D_RT_DEPTH = 0,
588 SVGA3D_RT_STENCIL = 1,
589 SVGA3D_RT_COLOR0 = 2,
590 SVGA3D_RT_COLOR1 = 3,
591 SVGA3D_RT_COLOR2 = 4,
592 SVGA3D_RT_COLOR3 = 5,
593 SVGA3D_RT_COLOR4 = 6,
594 SVGA3D_RT_COLOR5 = 7,
595 SVGA3D_RT_COLOR6 = 8,
596 SVGA3D_RT_COLOR7 = 9,
597 SVGA3D_RT_MAX,
598 SVGA3D_RT_INVALID = ((uint32)-1),
599 } SVGA3dRenderTargetType;
600
601 #define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
602
603 typedef
604 union {
605 struct {
606 uint32 red : 1;
607 uint32 green : 1;
608 uint32 blue : 1;
609 uint32 alpha : 1;
610 };
611 uint32 uintValue;
612 } SVGA3dColorMask;
613
614 typedef enum {
615 SVGA3D_VBLEND_DISABLE = 0,
616 SVGA3D_VBLEND_1WEIGHT = 1,
617 SVGA3D_VBLEND_2WEIGHT = 2,
618 SVGA3D_VBLEND_3WEIGHT = 3,
619 } SVGA3dVertexBlendFlags;
620
621 typedef enum {
622 SVGA3D_WRAPCOORD_0 = 1 << 0,
623 SVGA3D_WRAPCOORD_1 = 1 << 1,
624 SVGA3D_WRAPCOORD_2 = 1 << 2,
625 SVGA3D_WRAPCOORD_3 = 1 << 3,
626 SVGA3D_WRAPCOORD_ALL = 0xF,
627 } SVGA3dWrapFlags;
628
629 /*
630 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
631 * must fit in a uint32.
632 */
633
634 typedef enum {
635 SVGA3D_TS_INVALID = 0,
636 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
637 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
638 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
639 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
640 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
641 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
642 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
643 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
644 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
645 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
646 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
647 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
648 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
649 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
650 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
651 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
652 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
653 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
654 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
655 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
656 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
657 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
658 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
659 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
660
661
662 /*
663 * Sampler Gamma Level
664 *
665 * Sampler gamma effects the color of samples taken from the sampler. A
666 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
667 * gamma value is ignored and a linear space is used.
668 */
669
670 SVGA3D_TS_GAMMA = 25, /* float */
671 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
672 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
673 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
674 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
675 SVGA3D_TS_MAX
676 } SVGA3dTextureStateName;
677
678 typedef enum {
679 SVGA3D_TC_INVALID = 0,
680 SVGA3D_TC_DISABLE = 1,
681 SVGA3D_TC_SELECTARG1 = 2,
682 SVGA3D_TC_SELECTARG2 = 3,
683 SVGA3D_TC_MODULATE = 4,
684 SVGA3D_TC_ADD = 5,
685 SVGA3D_TC_ADDSIGNED = 6,
686 SVGA3D_TC_SUBTRACT = 7,
687 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
688 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
689 SVGA3D_TC_BLENDCURRENTALPHA = 10,
690 SVGA3D_TC_BLENDFACTORALPHA = 11,
691 SVGA3D_TC_MODULATE2X = 12,
692 SVGA3D_TC_MODULATE4X = 13,
693 SVGA3D_TC_DSDT = 14,
694 SVGA3D_TC_DOTPRODUCT3 = 15,
695 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
696 SVGA3D_TC_ADDSIGNED2X = 17,
697 SVGA3D_TC_ADDSMOOTH = 18,
698 SVGA3D_TC_PREMODULATE = 19,
699 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
700 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
701 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
702 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
703 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
704 SVGA3D_TC_MULTIPLYADD = 25,
705 SVGA3D_TC_LERP = 26,
706 SVGA3D_TC_MAX
707 } SVGA3dTextureCombiner;
708
709 #define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
710
711 typedef enum {
712 SVGA3D_TEX_ADDRESS_INVALID = 0,
713 SVGA3D_TEX_ADDRESS_WRAP = 1,
714 SVGA3D_TEX_ADDRESS_MIRROR = 2,
715 SVGA3D_TEX_ADDRESS_CLAMP = 3,
716 SVGA3D_TEX_ADDRESS_BORDER = 4,
717 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
718 SVGA3D_TEX_ADDRESS_EDGE = 6,
719 SVGA3D_TEX_ADDRESS_MAX
720 } SVGA3dTextureAddress;
721
722 /*
723 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
724 * disabled, and the rasterizer should use the magnification filter instead.
725 */
726 typedef enum {
727 SVGA3D_TEX_FILTER_NONE = 0,
728 SVGA3D_TEX_FILTER_NEAREST = 1,
729 SVGA3D_TEX_FILTER_LINEAR = 2,
730 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
731 SVGA3D_TEX_FILTER_FLATCUBIC = 4, // Deprecated, not implemented
732 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, // Deprecated, not implemented
733 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, // Not currently implemented
734 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, // Not currently implemented
735 SVGA3D_TEX_FILTER_MAX
736 } SVGA3dTextureFilter;
737
738 typedef enum {
739 SVGA3D_TEX_TRANSFORM_OFF = 0,
740 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
741 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
742 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
743 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
744 SVGA3D_TEX_PROJECTED = (1 << 15),
745 } SVGA3dTexTransformFlags;
746
747 typedef enum {
748 SVGA3D_TEXCOORD_GEN_OFF = 0,
749 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
750 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
751 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
752 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
753 SVGA3D_TEXCOORD_GEN_MAX
754 } SVGA3dTextureCoordGen;
755
756 /*
757 * Texture argument constants for texture combiner
758 */
759 typedef enum {
760 SVGA3D_TA_INVALID = 0,
761 SVGA3D_TA_CONSTANT = 1,
762 SVGA3D_TA_PREVIOUS = 2,
763 SVGA3D_TA_DIFFUSE = 3,
764 SVGA3D_TA_TEXTURE = 4,
765 SVGA3D_TA_SPECULAR = 5,
766 SVGA3D_TA_MAX
767 } SVGA3dTextureArgData;
768
769 #define SVGA3D_TM_MASK_LEN 4
770
771 /* Modifiers for texture argument constants defined above. */
772 typedef enum {
773 SVGA3D_TM_NONE = 0,
774 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
775 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
776 } SVGA3dTextureArgModifier;
777
778 #define SVGA3D_INVALID_ID ((uint32)-1)
779 #define SVGA3D_MAX_CLIP_PLANES 6
780
781 /*
782 * This is the limit to the number of fixed-function texture
783 * transforms and texture coordinates we can support. It does *not*
784 * correspond to the number of texture image units (samplers) we
785 * support!
786 */
787 #define SVGA3D_MAX_TEXTURE_COORDS 8
788
789 /*
790 * Vertex declarations
791 *
792 * Notes:
793 *
794 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
795 * draw with any POSITIONT vertex arrays, the programmable vertex
796 * pipeline will be implicitly disabled. Drawing will take place as if
797 * no vertex shader was bound.
798 */
799
800 typedef enum {
801 SVGA3D_DECLUSAGE_POSITION = 0,
802 SVGA3D_DECLUSAGE_BLENDWEIGHT, // 1
803 SVGA3D_DECLUSAGE_BLENDINDICES, // 2
804 SVGA3D_DECLUSAGE_NORMAL, // 3
805 SVGA3D_DECLUSAGE_PSIZE, // 4
806 SVGA3D_DECLUSAGE_TEXCOORD, // 5
807 SVGA3D_DECLUSAGE_TANGENT, // 6
808 SVGA3D_DECLUSAGE_BINORMAL, // 7
809 SVGA3D_DECLUSAGE_TESSFACTOR, // 8
810 SVGA3D_DECLUSAGE_POSITIONT, // 9
811 SVGA3D_DECLUSAGE_COLOR, // 10
812 SVGA3D_DECLUSAGE_FOG, // 11
813 SVGA3D_DECLUSAGE_DEPTH, // 12
814 SVGA3D_DECLUSAGE_SAMPLE, // 13
815 SVGA3D_DECLUSAGE_MAX
816 } SVGA3dDeclUsage;
817
818 typedef enum {
819 SVGA3D_DECLMETHOD_DEFAULT = 0,
820 SVGA3D_DECLMETHOD_PARTIALU,
821 SVGA3D_DECLMETHOD_PARTIALV,
822 SVGA3D_DECLMETHOD_CROSSUV, // Normal
823 SVGA3D_DECLMETHOD_UV,
824 SVGA3D_DECLMETHOD_LOOKUP, // Lookup a displacement map
825 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, // Lookup a pre-sampled displacement map
826 } SVGA3dDeclMethod;
827
828 typedef enum {
829 SVGA3D_DECLTYPE_FLOAT1 = 0,
830 SVGA3D_DECLTYPE_FLOAT2 = 1,
831 SVGA3D_DECLTYPE_FLOAT3 = 2,
832 SVGA3D_DECLTYPE_FLOAT4 = 3,
833 SVGA3D_DECLTYPE_D3DCOLOR = 4,
834 SVGA3D_DECLTYPE_UBYTE4 = 5,
835 SVGA3D_DECLTYPE_SHORT2 = 6,
836 SVGA3D_DECLTYPE_SHORT4 = 7,
837 SVGA3D_DECLTYPE_UBYTE4N = 8,
838 SVGA3D_DECLTYPE_SHORT2N = 9,
839 SVGA3D_DECLTYPE_SHORT4N = 10,
840 SVGA3D_DECLTYPE_USHORT2N = 11,
841 SVGA3D_DECLTYPE_USHORT4N = 12,
842 SVGA3D_DECLTYPE_UDEC3 = 13,
843 SVGA3D_DECLTYPE_DEC3N = 14,
844 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
845 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
846 SVGA3D_DECLTYPE_MAX,
847 } SVGA3dDeclType;
848
849 /*
850 * This structure is used for the divisor for geometry instancing;
851 * it's a direct translation of the Direct3D equivalent.
852 */
853 typedef union {
854 struct {
855 /*
856 * For index data, this number represents the number of instances to draw.
857 * For instance data, this number represents the number of
858 * instances/vertex in this stream
859 */
860 uint32 count : 30;
861
862 /*
863 * This is 1 if this is supposed to be the data that is repeated for
864 * every instance.
865 */
866 uint32 indexedData : 1;
867
868 /*
869 * This is 1 if this is supposed to be the per-instance data.
870 */
871 uint32 instanceData : 1;
872 };
873
874 uint32 value;
875 } SVGA3dVertexDivisor;
876
877 typedef enum {
878 SVGA3D_PRIMITIVE_INVALID = 0,
879 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
880 SVGA3D_PRIMITIVE_POINTLIST = 2,
881 SVGA3D_PRIMITIVE_LINELIST = 3,
882 SVGA3D_PRIMITIVE_LINESTRIP = 4,
883 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
884 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
885 SVGA3D_PRIMITIVE_MAX
886 } SVGA3dPrimitiveType;
887
888 typedef enum {
889 SVGA3D_COORDINATE_INVALID = 0,
890 SVGA3D_COORDINATE_LEFTHANDED = 1,
891 SVGA3D_COORDINATE_RIGHTHANDED = 2,
892 SVGA3D_COORDINATE_MAX
893 } SVGA3dCoordinateType;
894
895 typedef enum {
896 SVGA3D_TRANSFORM_INVALID = 0,
897 SVGA3D_TRANSFORM_WORLD = 1,
898 SVGA3D_TRANSFORM_VIEW = 2,
899 SVGA3D_TRANSFORM_PROJECTION = 3,
900 SVGA3D_TRANSFORM_TEXTURE0 = 4,
901 SVGA3D_TRANSFORM_TEXTURE1 = 5,
902 SVGA3D_TRANSFORM_TEXTURE2 = 6,
903 SVGA3D_TRANSFORM_TEXTURE3 = 7,
904 SVGA3D_TRANSFORM_TEXTURE4 = 8,
905 SVGA3D_TRANSFORM_TEXTURE5 = 9,
906 SVGA3D_TRANSFORM_TEXTURE6 = 10,
907 SVGA3D_TRANSFORM_TEXTURE7 = 11,
908 SVGA3D_TRANSFORM_WORLD1 = 12,
909 SVGA3D_TRANSFORM_WORLD2 = 13,
910 SVGA3D_TRANSFORM_WORLD3 = 14,
911 SVGA3D_TRANSFORM_MAX
912 } SVGA3dTransformType;
913
914 typedef enum {
915 SVGA3D_LIGHTTYPE_INVALID = 0,
916 SVGA3D_LIGHTTYPE_POINT = 1,
917 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
918 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
919 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
920 SVGA3D_LIGHTTYPE_MAX
921 } SVGA3dLightType;
922
923 typedef enum {
924 SVGA3D_CUBEFACE_POSX = 0,
925 SVGA3D_CUBEFACE_NEGX = 1,
926 SVGA3D_CUBEFACE_POSY = 2,
927 SVGA3D_CUBEFACE_NEGY = 3,
928 SVGA3D_CUBEFACE_POSZ = 4,
929 SVGA3D_CUBEFACE_NEGZ = 5,
930 } SVGA3dCubeFace;
931
932 typedef enum {
933 SVGA3D_SHADERTYPE_COMPILED_DX8 = 0,
934 SVGA3D_SHADERTYPE_VS = 1,
935 SVGA3D_SHADERTYPE_PS = 2,
936 SVGA3D_SHADERTYPE_MAX
937 } SVGA3dShaderType;
938
939 typedef enum {
940 SVGA3D_CONST_TYPE_FLOAT = 0,
941 SVGA3D_CONST_TYPE_INT = 1,
942 SVGA3D_CONST_TYPE_BOOL = 2,
943 } SVGA3dShaderConstType;
944
945 #define SVGA3D_MAX_SURFACE_FACES 6
946
947 typedef enum {
948 SVGA3D_STRETCH_BLT_POINT = 0,
949 SVGA3D_STRETCH_BLT_LINEAR = 1,
950 SVGA3D_STRETCH_BLT_MAX
951 } SVGA3dStretchBltMode;
952
953 typedef enum {
954 SVGA3D_QUERYTYPE_OCCLUSION = 0,
955 SVGA3D_QUERYTYPE_MAX
956 } SVGA3dQueryType;
957
958 typedef enum {
959 SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
960 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
961 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
962 SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */
963 } SVGA3dQueryState;
964
965 typedef enum {
966 SVGA3D_WRITE_HOST_VRAM = 1,
967 SVGA3D_READ_HOST_VRAM = 2,
968 } SVGA3dTransferType;
969
970 /*
971 * The maximum number vertex arrays we're guaranteed to support in
972 * SVGA_3D_CMD_DRAWPRIMITIVES.
973 */
974 #define SVGA3D_MAX_VERTEX_ARRAYS 32
975
976 /*
977 * Identifiers for commands in the command FIFO.
978 *
979 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
980 * the SVGA3D protocol and remain reserved; they should not be used in the
981 * future.
982 *
983 * IDs between 1040 and 1999 (inclusive) are available for use by the
984 * current SVGA3D protocol.
985 *
986 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
987 * and up.
988 */
989
990 #define SVGA_3D_CMD_LEGACY_BASE 1000
991 #define SVGA_3D_CMD_BASE 1040
992
993 #define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0
994 #define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
995 #define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
996 #define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
997 #define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
998 #define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
999 #define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
1000 #define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
1001 #define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
1002 #define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
1003 #define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
1004 #define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
1005 #define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
1006 #define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
1007 #define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
1008 #define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
1009 #define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
1010 #define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
1011 #define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 // Deprecated
1012 #define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
1013 #define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
1014 #define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
1015 #define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
1016 #define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
1017 #define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
1018 #define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
1019 #define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
1020 #define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
1021 #define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 // Deprecated
1022 #define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
1023 #define SVGA_3D_CMD_MAX SVGA_3D_CMD_BASE + 30
1024
1025 #define SVGA_3D_CMD_FUTURE_MAX 2000
1026
1027 /*
1028 * Common substructures used in multiple FIFO commands:
1029 */
1030
1031 typedef struct {
1032 union {
1033 struct {
1034 uint16 function; // SVGA3dFogFunction
1035 uint8 type; // SVGA3dFogType
1036 uint8 base; // SVGA3dFogBase
1037 };
1038 uint32 uintValue;
1039 };
1040 } SVGA3dFogMode;
1041
1042 /*
1043 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1044 * is a surface ID as well as face/mipmap indices.
1045 */
1046
1047 typedef
1048 struct SVGA3dSurfaceImageId {
1049 uint32 sid;
1050 uint32 face;
1051 uint32 mipmap;
1052 } SVGA3dSurfaceImageId;
1053
1054 typedef
1055 struct SVGA3dGuestImage {
1056 SVGAGuestPtr ptr;
1057
1058 /*
1059 * A note on interpretation of pitch: This value of pitch is the
1060 * number of bytes between vertically adjacent image
1061 * blocks. Normally this is the number of bytes between the first
1062 * pixel of two adjacent scanlines. With compressed textures,
1063 * however, this may represent the number of bytes between
1064 * compression blocks rather than between rows of pixels.
1065 *
1066 * XXX: Compressed textures currently must be tightly packed in guest memory.
1067 *
1068 * If the image is 1-dimensional, pitch is ignored.
1069 *
1070 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
1071 * assuming each row of blocks is tightly packed.
1072 */
1073 uint32 pitch;
1074 } SVGA3dGuestImage;
1075
1076
1077 /*
1078 * FIFO command format definitions:
1079 */
1080
1081 /*
1082 * The data size header following cmdNum for every 3d command
1083 */
1084 typedef
1085 struct {
1086 uint32 id;
1087 uint32 size;
1088 } SVGA3dCmdHeader;
1089
1090 /*
1091 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
1092 * optional mipmaps and cube faces.
1093 */
1094
1095 typedef
1096 struct {
1097 uint32 width;
1098 uint32 height;
1099 uint32 depth;
1100 } SVGA3dSize;
1101
1102 typedef enum {
1103 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
1104 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
1105 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
1106 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
1107 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
1108 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
1109 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
1110 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
1111 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
1112 } SVGA3dSurfaceFlags;
1113
1114 typedef
1115 struct {
1116 uint32 numMipLevels;
1117 } SVGA3dSurfaceFace;
1118
1119 typedef
1120 struct {
1121 uint32 sid;
1122 SVGA3dSurfaceFlags surfaceFlags;
1123 SVGA3dSurfaceFormat format;
1124 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1125 /*
1126 * Followed by an SVGA3dSize structure for each mip level in each face.
1127 *
1128 * A note on surface sizes: Sizes are always specified in pixels,
1129 * even if the true surface size is not a multiple of the minimum
1130 * block size of the surface's format. For example, a 3x3x1 DXT1
1131 * compressed texture would actually be stored as a 4x4x1 image in
1132 * memory.
1133 */
1134 } SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
1135
1136 typedef
1137 struct {
1138 uint32 sid;
1139 } SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
1140
1141 typedef
1142 struct {
1143 uint32 cid;
1144 } SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
1145
1146 typedef
1147 struct {
1148 uint32 cid;
1149 } SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
1150
1151 typedef
1152 struct {
1153 uint32 cid;
1154 SVGA3dClearFlag clearFlag;
1155 uint32 color;
1156 float depth;
1157 uint32 stencil;
1158 /* Followed by variable number of SVGA3dRect structures */
1159 } SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
1160
1161 typedef
1162 struct SVGA3dCopyRect {
1163 uint32 x;
1164 uint32 y;
1165 uint32 w;
1166 uint32 h;
1167 uint32 srcx;
1168 uint32 srcy;
1169 } SVGA3dCopyRect;
1170
1171 typedef
1172 struct SVGA3dCopyBox {
1173 uint32 x;
1174 uint32 y;
1175 uint32 z;
1176 uint32 w;
1177 uint32 h;
1178 uint32 d;
1179 uint32 srcx;
1180 uint32 srcy;
1181 uint32 srcz;
1182 } SVGA3dCopyBox;
1183
1184 typedef
1185 struct {
1186 uint32 x;
1187 uint32 y;
1188 uint32 w;
1189 uint32 h;
1190 } SVGA3dRect;
1191
1192 typedef
1193 struct {
1194 uint32 x;
1195 uint32 y;
1196 uint32 z;
1197 uint32 w;
1198 uint32 h;
1199 uint32 d;
1200 } SVGA3dBox;
1201
1202 typedef
1203 struct {
1204 uint32 x;
1205 uint32 y;
1206 uint32 z;
1207 } SVGA3dPoint;
1208
1209 typedef
1210 struct {
1211 SVGA3dLightType type;
1212 SVGA3dBool inWorldSpace;
1213 float diffuse[4];
1214 float specular[4];
1215 float ambient[4];
1216 float position[4];
1217 float direction[4];
1218 float range;
1219 float falloff;
1220 float attenuation0;
1221 float attenuation1;
1222 float attenuation2;
1223 float theta;
1224 float phi;
1225 } SVGA3dLightData;
1226
1227 typedef
1228 struct {
1229 uint32 sid;
1230 /* Followed by variable number of SVGA3dCopyRect structures */
1231 } SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
1232
1233 typedef
1234 struct {
1235 SVGA3dRenderStateName state;
1236 union {
1237 uint32 uintValue;
1238 float floatValue;
1239 };
1240 } SVGA3dRenderState;
1241
1242 typedef
1243 struct {
1244 uint32 cid;
1245 /* Followed by variable number of SVGA3dRenderState structures */
1246 } SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
1247
1248 typedef
1249 struct {
1250 uint32 cid;
1251 SVGA3dRenderTargetType type;
1252 SVGA3dSurfaceImageId target;
1253 } SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
1254
1255 typedef
1256 struct {
1257 SVGA3dSurfaceImageId src;
1258 SVGA3dSurfaceImageId dest;
1259 /* Followed by variable number of SVGA3dCopyBox structures */
1260 } SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
1261
1262 typedef
1263 struct {
1264 SVGA3dSurfaceImageId src;
1265 SVGA3dSurfaceImageId dest;
1266 SVGA3dBox boxSrc;
1267 SVGA3dBox boxDest;
1268 SVGA3dStretchBltMode mode;
1269 } SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
1270
1271 typedef
1272 struct {
1273 /*
1274 * If the discard flag is present in a surface DMA operation, the host may
1275 * discard the contents of the current mipmap level and face of the target
1276 * surface before applying the surface DMA contents.
1277 */
1278 uint32 discard : 1;
1279
1280 /*
1281 * If the unsynchronized flag is present, the host may perform this upload
1282 * without syncing to pending reads on this surface.
1283 */
1284 uint32 unsynchronized : 1;
1285
1286 /*
1287 * Guests *MUST* set the reserved bits to 0 before submitting the command
1288 * suffix as future flags may occupy these bits.
1289 */
1290 uint32 reserved : 30;
1291 } SVGA3dSurfaceDMAFlags;
1292
1293 typedef
1294 struct {
1295 SVGA3dGuestImage guest;
1296 SVGA3dSurfaceImageId host;
1297 SVGA3dTransferType transfer;
1298 /*
1299 * Followed by variable number of SVGA3dCopyBox structures. For consistency
1300 * in all clipping logic and coordinate translation, we define the
1301 * "source" in each copyBox as the guest image and the
1302 * "destination" as the host image, regardless of transfer
1303 * direction.
1304 *
1305 * For efficiency, the SVGA3D device is free to copy more data than
1306 * specified. For example, it may round copy boxes outwards such
1307 * that they lie on particular alignment boundaries.
1308 */
1309 } SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
1310
1311 /*
1312 * SVGA3dCmdSurfaceDMASuffix --
1313 *
1314 * This is a command suffix that will appear after a SurfaceDMA command in
1315 * the FIFO. It contains some extra information that hosts may use to
1316 * optimize performance or protect the guest. This suffix exists to preserve
1317 * backwards compatibility while also allowing for new functionality to be
1318 * implemented.
1319 */
1320
1321 typedef
1322 struct {
1323 uint32 suffixSize;
1324
1325 /*
1326 * The maximum offset is used to determine the maximum offset from the
1327 * guestPtr base address that will be accessed or written to during this
1328 * surfaceDMA. If the suffix is supported, the host will respect this
1329 * boundary while performing surface DMAs.
1330 *
1331 * Defaults to MAX_UINT32
1332 */
1333 uint32 maximumOffset;
1334
1335 /*
1336 * A set of flags that describes optimizations that the host may perform
1337 * while performing this surface DMA operation. The guest should never rely
1338 * on behaviour that is different when these flags are set for correctness.
1339 *
1340 * Defaults to 0
1341 */
1342 SVGA3dSurfaceDMAFlags flags;
1343 } SVGA3dCmdSurfaceDMASuffix;
1344
1345 /*
1346 * SVGA_3D_CMD_DRAW_PRIMITIVES --
1347 *
1348 * This command is the SVGA3D device's generic drawing entry point.
1349 * It can draw multiple ranges of primitives, optionally using an
1350 * index buffer, using an arbitrary collection of vertex buffers.
1351 *
1352 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
1353 * during this draw call. The declarations specify which surface
1354 * the vertex data lives in, what that vertex data is used for,
1355 * and how to interpret it.
1356 *
1357 * Each SVGA3dPrimitiveRange defines a collection of primitives
1358 * to render using the same vertex arrays. An index buffer is
1359 * optional.
1360 */
1361
1362 typedef
1363 struct {
1364 /*
1365 * A range hint is an optional specification for the range of indices
1366 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
1367 * that the entire array will be used.
1368 *
1369 * These are only hints. The SVGA3D device may use them for
1370 * performance optimization if possible, but it's also allowed to
1371 * ignore these values.
1372 */
1373 uint32 first;
1374 uint32 last;
1375 } SVGA3dArrayRangeHint;
1376
1377 typedef
1378 struct {
1379 /*
1380 * Define the origin and shape of a vertex or index array. Both
1381 * 'offset' and 'stride' are in bytes. The provided surface will be
1382 * reinterpreted as a flat array of bytes in the same format used
1383 * by surface DMA operations. To avoid unnecessary conversions, the
1384 * surface should be created with the SVGA3D_BUFFER format.
1385 *
1386 * Index 0 in the array starts 'offset' bytes into the surface.
1387 * Index 1 begins at byte 'offset + stride', etc. Array indices may
1388 * not be negative.
1389 */
1390 uint32 surfaceId;
1391 uint32 offset;
1392 uint32 stride;
1393 } SVGA3dArray;
1394
1395 typedef
1396 struct {
1397 /*
1398 * Describe a vertex array's data type, and define how it is to be
1399 * used by the fixed function pipeline or the vertex shader. It
1400 * isn't useful to have two VertexDecls with the same
1401 * VertexArrayIdentity in one draw call.
1402 */
1403 SVGA3dDeclType type;
1404 SVGA3dDeclMethod method;
1405 SVGA3dDeclUsage usage;
1406 uint32 usageIndex;
1407 } SVGA3dVertexArrayIdentity;
1408
1409 typedef
1410 struct {
1411 SVGA3dVertexArrayIdentity identity;
1412 SVGA3dArray array;
1413 SVGA3dArrayRangeHint rangeHint;
1414 } SVGA3dVertexDecl;
1415
1416 typedef
1417 struct {
1418 /*
1419 * Define a group of primitives to render, from sequential indices.
1420 *
1421 * The value of 'primitiveType' and 'primitiveCount' imply the
1422 * total number of vertices that will be rendered.
1423 */
1424 SVGA3dPrimitiveType primType;
1425 uint32 primitiveCount;
1426
1427 /*
1428 * Optional index buffer. If indexArray.surfaceId is
1429 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
1430 * without an index buffer is identical to rendering with an index
1431 * buffer containing the sequence [0, 1, 2, 3, ...].
1432 *
1433 * If an index buffer is in use, indexWidth specifies the width in
1434 * bytes of each index value. It must be less than or equal to
1435 * indexArray.stride.
1436 *
1437 * (Currently, the SVGA3D device requires index buffers to be tightly
1438 * packed. In other words, indexWidth == indexArray.stride)
1439 */
1440 SVGA3dArray indexArray;
1441 uint32 indexWidth;
1442
1443 /*
1444 * Optional index bias. This number is added to all indices from
1445 * indexArray before they are used as vertex array indices. This
1446 * can be used in multiple ways:
1447 *
1448 * - When not using an indexArray, this bias can be used to
1449 * specify where in the vertex arrays to begin rendering.
1450 *
1451 * - A positive number here is equivalent to increasing the
1452 * offset in each vertex array.
1453 *
1454 * - A negative number can be used to render using a small
1455 * vertex array and an index buffer that contains large
1456 * values. This may be used by some applications that
1457 * crop a vertex buffer without modifying their index
1458 * buffer.
1459 *
1460 * Note that rendering with a negative bias value may be slower and
1461 * use more memory than rendering with a positive or zero bias.
1462 */
1463 int32 indexBias;
1464 } SVGA3dPrimitiveRange;
1465
1466 typedef
1467 struct {
1468 uint32 cid;
1469 uint32 numVertexDecls;
1470 uint32 numRanges;
1471
1472 /*
1473 * There are two variable size arrays after the
1474 * SVGA3dCmdDrawPrimitives structure. In order,
1475 * they are:
1476 *
1477 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls'
1478 * 2. SVGA3dPrimitiveRange, quantity 'numRanges'
1479 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
1480 * the frequency divisor for this the corresponding vertex decl)
1481 */
1482 } SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
1483
1484 typedef
1485 struct {
1486 uint32 stage;
1487 SVGA3dTextureStateName name;
1488 union {
1489 uint32 value;
1490 float floatValue;
1491 };
1492 } SVGA3dTextureState;
1493
1494 typedef
1495 struct {
1496 uint32 cid;
1497 /* Followed by variable number of SVGA3dTextureState structures */
1498 } SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
1499
1500 typedef
1501 struct {
1502 uint32 cid;
1503 SVGA3dTransformType type;
1504 float matrix[16];
1505 } SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
1506
1507 typedef
1508 struct {
1509 float min;
1510 float max;
1511 } SVGA3dZRange;
1512
1513 typedef
1514 struct {
1515 uint32 cid;
1516 SVGA3dZRange zRange;
1517 } SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
1518
1519 typedef
1520 struct {
1521 float diffuse[4];
1522 float ambient[4];
1523 float specular[4];
1524 float emissive[4];
1525 float shininess;
1526 } SVGA3dMaterial;
1527
1528 typedef
1529 struct {
1530 uint32 cid;
1531 SVGA3dFace face;
1532 SVGA3dMaterial material;
1533 } SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
1534
1535 typedef
1536 struct {
1537 uint32 cid;
1538 uint32 index;
1539 SVGA3dLightData data;
1540 } SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
1541
1542 typedef
1543 struct {
1544 uint32 cid;
1545 uint32 index;
1546 uint32 enabled;
1547 } SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
1548
1549 typedef
1550 struct {
1551 uint32 cid;
1552 SVGA3dRect rect;
1553 } SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
1554
1555 typedef
1556 struct {
1557 uint32 cid;
1558 SVGA3dRect rect;
1559 } SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
1560
1561 typedef
1562 struct {
1563 uint32 cid;
1564 uint32 index;
1565 float plane[4];
1566 } SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
1567
1568 typedef
1569 struct {
1570 uint32 cid;
1571 uint32 shid;
1572 SVGA3dShaderType type;
1573 /* Followed by variable number of DWORDs for shader bycode */
1574 } SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
1575
1576 typedef
1577 struct {
1578 uint32 cid;
1579 uint32 shid;
1580 SVGA3dShaderType type;
1581 } SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
1582
1583 typedef
1584 struct {
1585 uint32 cid;
1586 uint32 reg; /* register number */
1587 SVGA3dShaderType type;
1588 SVGA3dShaderConstType ctype;
1589 uint32 values[4];
1590 } SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
1591
1592 typedef
1593 struct {
1594 uint32 cid;
1595 SVGA3dShaderType type;
1596 uint32 shid;
1597 } SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
1598
1599 typedef
1600 struct {
1601 uint32 cid;
1602 SVGA3dQueryType type;
1603 } SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1604
1605 typedef
1606 struct {
1607 uint32 cid;
1608 SVGA3dQueryType type;
1609 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1610 } SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1611
1612 typedef
1613 struct {
1614 uint32 cid; /* Same parameters passed to END_QUERY */
1615 SVGA3dQueryType type;
1616 SVGAGuestPtr guestResult;
1617 } SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1618
1619 typedef
1620 struct {
1621 uint32 totalSize; /* Set by guest before query is ended. */
1622 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1623 union { /* Set by host on exit from PENDING state */
1624 uint32 result32;
1625 };
1626 } SVGA3dQueryResult;
1627
1628 /*
1629 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1630 *
1631 * This is a blit from an SVGA3D surface to a Screen Object. Just
1632 * like GMR-to-screen blits, this blit may be directed at a
1633 * specific screen or to the virtual coordinate space.
1634 *
1635 * The blit copies from a rectangular region of an SVGA3D surface
1636 * image to a rectangular region of a screen or screens.
1637 *
1638 * This command takes an optional variable-length list of clipping
1639 * rectangles after the body of the command. If no rectangles are
1640 * specified, there is no clipping region. The entire destRect is
1641 * drawn to. If one or more rectangles are included, they describe
1642 * a clipping region. The clip rectangle coordinates are measured
1643 * relative to the top-left corner of destRect.
1644 *
1645 * This clipping region serves multiple purposes:
1646 *
1647 * - It can be used to perform an irregularly shaped blit more
1648 * efficiently than by issuing many separate blit commands.
1649 *
1650 * - It is equivalent to allowing blits with non-integer
1651 * source coordinates. You could blit just one half-pixel
1652 * of a source, for example, by specifying a larger
1653 * destination rectangle than you need, then removing
1654 * part of it using a clip rectangle.
1655 *
1656 * Availability:
1657 * SVGA_FIFO_CAP_SCREEN_OBJECT
1658 *
1659 * Limitations:
1660 *
1661 * - Currently, no backend supports blits from a mipmap or face
1662 * other than the first one.
1663 */
1664
1665 typedef
1666 struct {
1667 SVGA3dSurfaceImageId srcImage;
1668 SVGASignedRect srcRect;
1669 uint32 destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
1670 SVGASignedRect destRect; /* Supports scaling if src/rest different size */
1671 /* Clipping: zero or more SVGASignedRects follow */
1672 } SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1673
1674
1675 /*
1676 * Capability query index.
1677 *
1678 * Notes:
1679 *
1680 * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
1681 * fixed-function texture units available. Each of these units
1682 * work in both FFP and Shader modes, and they support texture
1683 * transforms and texture coordinates. The host may have additional
1684 * texture image units that are only usable with shaders.
1685 *
1686 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
1687 * return TRUE. Even on physical hardware that does not support
1688 * these formats natively, the SVGA3D device will provide an emulation
1689 * which should be invisible to the guest OS.
1690 *
1691 * In general, the SVGA3D device should support any operation on
1692 * any surface format, it just may perform some of these
1693 * operations in software depending on the capabilities of the
1694 * available physical hardware.
1695 *
1696 * XXX: In the future, we will add capabilities that describe in
1697 * detail what formats are supported in hardware for what kinds
1698 * of operations.
1699 */
1700
1701 typedef enum {
1702 SVGA3D_DEVCAP_3D = 0,
1703 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
1704 SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
1705 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
1706 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
1707 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
1708 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
1709 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
1710 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
1711 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
1712 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
1713 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
1714 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
1715 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
1716 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
1717 SVGA3D_DEVCAP_QUERY_TYPES = 15,
1718 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
1719 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
1720 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
1721 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
1722 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
1723 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
1724 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
1725 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
1726 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
1727 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
1728 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
1729 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
1730 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
1731 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
1732 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
1733 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
1734 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
1735 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
1736 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
1737 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
1738 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
1739 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
1740 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
1741 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
1742 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
1743 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
1744 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
1745 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
1746 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
1747 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
1748 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
1749 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
1750 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
1751 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
1752 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
1753 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
1754 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
1755 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
1756 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
1757 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
1758 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
1759 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
1760 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
1761 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
1762 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
1763 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
1764 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
1765
1766 /*
1767 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
1768 * render targets. This does no include the depth or stencil targets.
1769 */
1770 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
1771
1772 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
1773 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
1774 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
1775 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
1776 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
1777
1778 /*
1779 * Don't add new caps into the previous section; the values in this
1780 * enumeration must not change. You can put new values right before
1781 * SVGA3D_DEVCAP_MAX.
1782 */
1783 SVGA3D_DEVCAP_MAX /* This must be the last index. */
1784 } SVGA3dDevCapIndex;
1785
1786 typedef union {
1787 Bool b;
1788 uint32 u;
1789 int32 i;
1790 float f;
1791 } SVGA3dDevCapResult;
1792
1793 #endif /* _SVGA3D_REG_H_ */
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