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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / i2c / busses / i2c-tegra.c
blob0c6e840a627118a04be27f10e570cd36e316f1be
1 /*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
24 #include <linux/io.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h>
29 #include <linux/of_i2c.h>
30 #include <linux/module.h>
31
32 #include <asm/unaligned.h>
33
34 #include <mach/clk.h>
35
36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
37 #define BYTES_PER_FIFO_WORD 4
38
39 #define I2C_CNFG 0x000
40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
41 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43 #define I2C_STATUS 0x01C
44 #define I2C_SL_CNFG 0x020
45 #define I2C_SL_CNFG_NACK (1<<1)
46 #define I2C_SL_CNFG_NEWSL (1<<2)
47 #define I2C_SL_ADDR1 0x02c
48 #define I2C_SL_ADDR2 0x030
49 #define I2C_TX_FIFO 0x050
50 #define I2C_RX_FIFO 0x054
51 #define I2C_PACKET_TRANSFER_STATUS 0x058
52 #define I2C_FIFO_CONTROL 0x05c
53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
57 #define I2C_FIFO_STATUS 0x060
58 #define I2C_FIFO_STATUS_TX_MASK 0xF0
59 #define I2C_FIFO_STATUS_TX_SHIFT 4
60 #define I2C_FIFO_STATUS_RX_MASK 0x0F
61 #define I2C_FIFO_STATUS_RX_SHIFT 0
62 #define I2C_INT_MASK 0x064
63 #define I2C_INT_STATUS 0x068
64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
68 #define I2C_INT_NO_ACK (1<<3)
69 #define I2C_INT_ARBITRATION_LOST (1<<2)
70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
72 #define I2C_CLK_DIVISOR 0x06c
73
74 #define DVC_CTRL_REG1 0x000
75 #define DVC_CTRL_REG1_INTR_EN (1<<10)
76 #define DVC_CTRL_REG2 0x004
77 #define DVC_CTRL_REG3 0x008
78 #define DVC_CTRL_REG3_SW_PROG (1<<26)
79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80 #define DVC_STATUS 0x00c
81 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
82
83 #define I2C_ERR_NONE 0x00
84 #define I2C_ERR_NO_ACK 0x01
85 #define I2C_ERR_ARBITRATION_LOST 0x02
86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
87
88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
90 #define PACKET_HEADER0_CONT_ID_SHIFT 12
91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
92
93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94 #define I2C_HEADER_CONT_ON_NAK (1<<21)
95 #define I2C_HEADER_SEND_START_BYTE (1<<20)
96 #define I2C_HEADER_READ (1<<19)
97 #define I2C_HEADER_10BIT_ADDR (1<<18)
98 #define I2C_HEADER_IE_ENABLE (1<<17)
99 #define I2C_HEADER_REPEAT_START (1<<16)
100 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
101 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
102
103 /**
104 * struct tegra_i2c_dev - per device i2c context
105 * @dev: device reference for power management
106 * @adapter: core i2c layer adapter information
107 * @clk: clock reference for i2c controller
108 * @i2c_clk: clock reference for i2c bus
109 * @iomem: memory resource for registers
110 * @base: ioremapped registers cookie
111 * @cont_id: i2c controller id, used for for packet header
112 * @irq: irq number of transfer complete interrupt
113 * @is_dvc: identifies the DVC i2c controller, has a different register layout
114 * @msg_complete: transfer completion notifier
115 * @msg_err: error code for completed message
116 * @msg_buf: pointer to current message data
117 * @msg_buf_remaining: size of unsent data in the message buffer
118 * @msg_read: identifies read transfers
119 * @bus_clk_rate: current i2c bus clock rate
120 * @is_suspended: prevents i2c controller accesses after suspend is called
121 */
122 struct tegra_i2c_dev {
123 struct device *dev;
124 struct i2c_adapter adapter;
125 struct clk *clk;
126 struct clk *i2c_clk;
127 struct resource *iomem;
128 void __iomem *base;
129 int cont_id;
130 int irq;
131 bool irq_disabled;
132 int is_dvc;
133 struct completion msg_complete;
134 int msg_err;
135 u8 *msg_buf;
136 size_t msg_buf_remaining;
137 int msg_read;
138 unsigned long bus_clk_rate;
139 bool is_suspended;
140 };
141
142 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
143 {
144 writel(val, i2c_dev->base + reg);
145 }
146
147 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
148 {
149 return readl(i2c_dev->base + reg);
150 }
151
152 /*
153 * i2c_writel and i2c_readl will offset the register if necessary to talk
154 * to the I2C block inside the DVC block
155 */
156 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
157 unsigned long reg)
158 {
159 if (i2c_dev->is_dvc)
160 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
161 return reg;
162 }
163
164 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
165 unsigned long reg)
166 {
167 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
168 }
169
170 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
171 {
172 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
173 }
174
175 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
176 unsigned long reg, int len)
177 {
178 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
179 }
180
181 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
182 unsigned long reg, int len)
183 {
184 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
185 }
186
187 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
188 {
189 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
190 int_mask &= ~mask;
191 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
192 }
193
194 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
195 {
196 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
197 int_mask |= mask;
198 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
199 }
200
201 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
202 {
203 unsigned long timeout = jiffies + HZ;
204 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
205 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
206 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
207
208 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
209 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
210 if (time_after(jiffies, timeout)) {
211 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
212 return -ETIMEDOUT;
213 }
214 msleep(1);
215 }
216 return 0;
217 }
218
219 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
220 {
221 u32 val;
222 int rx_fifo_avail;
223 u8 *buf = i2c_dev->msg_buf;
224 size_t buf_remaining = i2c_dev->msg_buf_remaining;
225 int words_to_transfer;
226
227 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
228 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
229 I2C_FIFO_STATUS_RX_SHIFT;
230
231 /* Rounds down to not include partial word at the end of buf */
232 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
233 if (words_to_transfer > rx_fifo_avail)
234 words_to_transfer = rx_fifo_avail;
235
236 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
237
238 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
239 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
240 rx_fifo_avail -= words_to_transfer;
241
242 /*
243 * If there is a partial word at the end of buf, handle it manually to
244 * prevent overwriting past the end of buf
245 */
246 if (rx_fifo_avail > 0 && buf_remaining > 0) {
247 BUG_ON(buf_remaining > 3);
248 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
249 memcpy(buf, &val, buf_remaining);
250 buf_remaining = 0;
251 rx_fifo_avail--;
252 }
253
254 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
255 i2c_dev->msg_buf_remaining = buf_remaining;
256 i2c_dev->msg_buf = buf;
257 return 0;
258 }
259
260 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
261 {
262 u32 val;
263 int tx_fifo_avail;
264 u8 *buf = i2c_dev->msg_buf;
265 size_t buf_remaining = i2c_dev->msg_buf_remaining;
266 int words_to_transfer;
267
268 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
269 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
270 I2C_FIFO_STATUS_TX_SHIFT;
271
272 /* Rounds down to not include partial word at the end of buf */
273 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
274 if (words_to_transfer > tx_fifo_avail)
275 words_to_transfer = tx_fifo_avail;
276
277 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
278
279 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
280 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
281 tx_fifo_avail -= words_to_transfer;
282
283 /*
284 * If there is a partial word at the end of buf, handle it manually to
285 * prevent reading past the end of buf, which could cross a page
286 * boundary and fault.
287 */
288 if (tx_fifo_avail > 0 && buf_remaining > 0) {
289 BUG_ON(buf_remaining > 3);
290 memcpy(&val, buf, buf_remaining);
291 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
292 buf_remaining = 0;
293 tx_fifo_avail--;
294 }
295
296 BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
297 i2c_dev->msg_buf_remaining = buf_remaining;
298 i2c_dev->msg_buf = buf;
299 return 0;
300 }
301
302 /*
303 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
304 * block. This block is identical to the rest of the I2C blocks, except that
305 * it only supports master mode, it has registers moved around, and it needs
306 * some extra init to get it into I2C mode. The register moves are handled
307 * by i2c_readl and i2c_writel
308 */
309 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
310 {
311 u32 val = 0;
312 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
313 val |= DVC_CTRL_REG3_SW_PROG;
314 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
315 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
316
317 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
318 val |= DVC_CTRL_REG1_INTR_EN;
319 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
320 }
321
322 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
323 {
324 u32 val;
325 int err = 0;
326
327 clk_enable(i2c_dev->clk);
328
329 tegra_periph_reset_assert(i2c_dev->clk);
330 udelay(2);
331 tegra_periph_reset_deassert(i2c_dev->clk);
332
333 if (i2c_dev->is_dvc)
334 tegra_dvc_init(i2c_dev);
335
336 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
337 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
338 i2c_writel(i2c_dev, val, I2C_CNFG);
339 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
340 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
341
342 if (!i2c_dev->is_dvc) {
343 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
344 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
345 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
346 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
347 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
348
349 }
350
351 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
352 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
353 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
354
355 if (tegra_i2c_flush_fifos(i2c_dev))
356 err = -ETIMEDOUT;
357
358 clk_disable(i2c_dev->clk);
359
360 if (i2c_dev->irq_disabled) {
361 i2c_dev->irq_disabled = 0;
362 enable_irq(i2c_dev->irq);
363 }
364
365 return err;
366 }
367
368 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
369 {
370 u32 status;
371 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
372 struct tegra_i2c_dev *i2c_dev = dev_id;
373
374 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
375
376 if (status == 0) {
377 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
378 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
379 i2c_readl(i2c_dev, I2C_STATUS),
380 i2c_readl(i2c_dev, I2C_CNFG));
381 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
382
383 if (!i2c_dev->irq_disabled) {
384 disable_irq_nosync(i2c_dev->irq);
385 i2c_dev->irq_disabled = 1;
386 }
387
388 complete(&i2c_dev->msg_complete);
389 goto err;
390 }
391
392 if (unlikely(status & status_err)) {
393 if (status & I2C_INT_NO_ACK)
394 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
395 if (status & I2C_INT_ARBITRATION_LOST)
396 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
397 complete(&i2c_dev->msg_complete);
398 goto err;
399 }
400
401 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
402 if (i2c_dev->msg_buf_remaining)
403 tegra_i2c_empty_rx_fifo(i2c_dev);
404 else
405 BUG();
406 }
407
408 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
409 if (i2c_dev->msg_buf_remaining)
410 tegra_i2c_fill_tx_fifo(i2c_dev);
411 else
412 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
413 }
414
415 if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
416 !i2c_dev->msg_buf_remaining)
417 complete(&i2c_dev->msg_complete);
418
419 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
420 if (i2c_dev->is_dvc)
421 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
422 return IRQ_HANDLED;
423 err:
424 /* An error occurred, mask all interrupts */
425 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
426 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
427 I2C_INT_RX_FIFO_DATA_REQ);
428 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
429 if (i2c_dev->is_dvc)
430 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
431 return IRQ_HANDLED;
432 }
433
434 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
435 struct i2c_msg *msg, int stop)
436 {
437 u32 packet_header;
438 u32 int_mask;
439 int ret;
440
441 tegra_i2c_flush_fifos(i2c_dev);
442 i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
443
444 if (msg->len == 0)
445 return -EINVAL;
446
447 i2c_dev->msg_buf = msg->buf;
448 i2c_dev->msg_buf_remaining = msg->len;
449 i2c_dev->msg_err = I2C_ERR_NONE;
450 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
451 INIT_COMPLETION(i2c_dev->msg_complete);
452
453 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
454 PACKET_HEADER0_PROTOCOL_I2C |
455 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
456 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
457 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
458
459 packet_header = msg->len - 1;
460 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
461
462 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
463 packet_header |= I2C_HEADER_IE_ENABLE;
464 if (!stop)
465 packet_header |= I2C_HEADER_REPEAT_START;
466 if (msg->flags & I2C_M_TEN)
467 packet_header |= I2C_HEADER_10BIT_ADDR;
468 if (msg->flags & I2C_M_IGNORE_NAK)
469 packet_header |= I2C_HEADER_CONT_ON_NAK;
470 if (msg->flags & I2C_M_RD)
471 packet_header |= I2C_HEADER_READ;
472 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
473
474 if (!(msg->flags & I2C_M_RD))
475 tegra_i2c_fill_tx_fifo(i2c_dev);
476
477 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
478 if (msg->flags & I2C_M_RD)
479 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
480 else if (i2c_dev->msg_buf_remaining)
481 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
482 tegra_i2c_unmask_irq(i2c_dev, int_mask);
483 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
484 i2c_readl(i2c_dev, I2C_INT_MASK));
485
486 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
487 tegra_i2c_mask_irq(i2c_dev, int_mask);
488
489 if (WARN_ON(ret == 0)) {
490 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
491
492 tegra_i2c_init(i2c_dev);
493 return -ETIMEDOUT;
494 }
495
496 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
497 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
498
499 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
500 return 0;
501
502 tegra_i2c_init(i2c_dev);
503 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
504 if (msg->flags & I2C_M_IGNORE_NAK)
505 return 0;
506 return -EREMOTEIO;
507 }
508
509 return -EIO;
510 }
511
512 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
513 int num)
514 {
515 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
516 int i;
517 int ret = 0;
518
519 if (i2c_dev->is_suspended)
520 return -EBUSY;
521
522 clk_enable(i2c_dev->clk);
523 for (i = 0; i < num; i++) {
524 int stop = (i == (num - 1)) ? 1 : 0;
525 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
526 if (ret)
527 break;
528 }
529 clk_disable(i2c_dev->clk);
530 return ret ?: i;
531 }
532
533 static u32 tegra_i2c_func(struct i2c_adapter *adap)
534 {
535 return I2C_FUNC_I2C;
536 }
537
538 static const struct i2c_algorithm tegra_i2c_algo = {
539 .master_xfer = tegra_i2c_xfer,
540 .functionality = tegra_i2c_func,
541 };
542
543 static int tegra_i2c_probe(struct platform_device *pdev)
544 {
545 struct tegra_i2c_dev *i2c_dev;
546 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
547 struct resource *res;
548 struct resource *iomem;
549 struct clk *clk;
550 struct clk *i2c_clk;
551 const unsigned int *prop;
552 void *base;
553 int irq;
554 int ret = 0;
555
556 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557 if (!res) {
558 dev_err(&pdev->dev, "no mem resource\n");
559 return -EINVAL;
560 }
561 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
562 if (!iomem) {
563 dev_err(&pdev->dev, "I2C region already claimed\n");
564 return -EBUSY;
565 }
566
567 base = ioremap(iomem->start, resource_size(iomem));
568 if (!base) {
569 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
570 return -ENOMEM;
571 }
572
573 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
574 if (!res) {
575 dev_err(&pdev->dev, "no irq resource\n");
576 ret = -EINVAL;
577 goto err_iounmap;
578 }
579 irq = res->start;
580
581 clk = clk_get(&pdev->dev, NULL);
582 if (IS_ERR(clk)) {
583 dev_err(&pdev->dev, "missing controller clock");
584 ret = PTR_ERR(clk);
585 goto err_release_region;
586 }
587
588 i2c_clk = clk_get(&pdev->dev, "i2c");
589 if (IS_ERR(i2c_clk)) {
590 dev_err(&pdev->dev, "missing bus clock");
591 ret = PTR_ERR(i2c_clk);
592 goto err_clk_put;
593 }
594
595 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
596 if (!i2c_dev) {
597 ret = -ENOMEM;
598 goto err_i2c_clk_put;
599 }
600
601 i2c_dev->base = base;
602 i2c_dev->clk = clk;
603 i2c_dev->i2c_clk = i2c_clk;
604 i2c_dev->iomem = iomem;
605 i2c_dev->adapter.algo = &tegra_i2c_algo;
606 i2c_dev->irq = irq;
607 i2c_dev->cont_id = pdev->id;
608 i2c_dev->dev = &pdev->dev;
609
610 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
611 if (pdata) {
612 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
613
614 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
615 prop = of_get_property(i2c_dev->dev->of_node,
616 "clock-frequency", NULL);
617 if (prop)
618 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
619 }
620
621 if (pdev->id == 3)
622 i2c_dev->is_dvc = 1;
623 init_completion(&i2c_dev->msg_complete);
624
625 platform_set_drvdata(pdev, i2c_dev);
626
627 ret = tegra_i2c_init(i2c_dev);
628 if (ret) {
629 dev_err(&pdev->dev, "Failed to initialize i2c controller");
630 goto err_free;
631 }
632
633 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
634 if (ret) {
635 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
636 goto err_free;
637 }
638
639 clk_enable(i2c_dev->i2c_clk);
640
641 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
642 i2c_dev->adapter.owner = THIS_MODULE;
643 i2c_dev->adapter.class = I2C_CLASS_HWMON;
644 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
645 sizeof(i2c_dev->adapter.name));
646 i2c_dev->adapter.algo = &tegra_i2c_algo;
647 i2c_dev->adapter.dev.parent = &pdev->dev;
648 i2c_dev->adapter.nr = pdev->id;
649 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
650
651 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
652 if (ret) {
653 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
654 goto err_free_irq;
655 }
656
657 of_i2c_register_devices(&i2c_dev->adapter);
658
659 return 0;
660 err_free_irq:
661 free_irq(i2c_dev->irq, i2c_dev);
662 err_free:
663 kfree(i2c_dev);
664 err_i2c_clk_put:
665 clk_put(i2c_clk);
666 err_clk_put:
667 clk_put(clk);
668 err_release_region:
669 release_mem_region(iomem->start, resource_size(iomem));
670 err_iounmap:
671 iounmap(base);
672 return ret;
673 }
674
675 static int tegra_i2c_remove(struct platform_device *pdev)
676 {
677 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
678 i2c_del_adapter(&i2c_dev->adapter);
679 free_irq(i2c_dev->irq, i2c_dev);
680 clk_put(i2c_dev->i2c_clk);
681 clk_put(i2c_dev->clk);
682 release_mem_region(i2c_dev->iomem->start,
683 resource_size(i2c_dev->iomem));
684 iounmap(i2c_dev->base);
685 kfree(i2c_dev);
686 return 0;
687 }
688
689 #ifdef CONFIG_PM
690 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
691 {
692 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
693
694 i2c_lock_adapter(&i2c_dev->adapter);
695 i2c_dev->is_suspended = true;
696 i2c_unlock_adapter(&i2c_dev->adapter);
697
698 return 0;
699 }
700
701 static int tegra_i2c_resume(struct platform_device *pdev)
702 {
703 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
704 int ret;
705
706 i2c_lock_adapter(&i2c_dev->adapter);
707
708 ret = tegra_i2c_init(i2c_dev);
709
710 if (ret) {
711 i2c_unlock_adapter(&i2c_dev->adapter);
712 return ret;
713 }
714
715 i2c_dev->is_suspended = false;
716
717 i2c_unlock_adapter(&i2c_dev->adapter);
718
719 return 0;
720 }
721 #endif
722
723 static struct platform_driver tegra_i2c_driver = {
724 .probe = tegra_i2c_probe,
725 .remove = tegra_i2c_remove,
726 #ifdef CONFIG_PM
727 .suspend = tegra_i2c_suspend,
728 .resume = tegra_i2c_resume,
729 #endif
730 .driver = {
731 .name = "tegra-i2c",
732 .owner = THIS_MODULE,
733 },
734 };
735
736 static int __init tegra_i2c_init_driver(void)
737 {
738 return platform_driver_register(&tegra_i2c_driver);
739 }
740
741 static void __exit tegra_i2c_exit_driver(void)
742 {
743 platform_driver_unregister(&tegra_i2c_driver);
744 }
745
746 subsys_initcall(tegra_i2c_init_driver);
747 module_exit(tegra_i2c_exit_driver);
748
749 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
750 MODULE_AUTHOR("Colin Cross");
751 MODULE_LICENSE("GPL v2");
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