drivers/media/rc/nuvoton-cir.h

   1 /*
   2  * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
   3  *
   4  * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
   5  * Copyright (C) 2009 Nuvoton PS Team
   6  *
   7  * Special thanks to Nuvoton for providing hardware, spec sheets and
   8  * sample code upon which portions of this driver are based. Indirect
   9  * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
  10  * modeled after.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of the
  15  * License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
  18  * WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  25  * USA
  26  */
  27
  28 #include <linux/spinlock.h>
  29 #include <linux/ioctl.h>
  30
  31 /* platform driver name to register */
  32 #define NVT_DRIVER_NAME "nuvoton-cir"
  33
  34 /* debugging module parameter */
  35 static int debug;
  36
  37
  38 #define nvt_pr(level, text, ...) \
  39         printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  40
  41 #define nvt_dbg(text, ...) \
  42         if (debug) \
  43                 printk(KERN_DEBUG \
  44                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  45
  46 #define nvt_dbg_verbose(text, ...) \
  47         if (debug > 1) \
  48                 printk(KERN_DEBUG \
  49                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  50
  51 #define nvt_dbg_wake(text, ...) \
  52         if (debug > 2) \
  53                 printk(KERN_DEBUG \
  54                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  55
  56
  57 /*
  58  * Original lirc driver said min value of 76, and recommended value of 256
  59  * for the buffer length, but then used 2048. Never mind that the size of the
  60  * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
  61  * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
  62  * and I don't have TX-capable hardware to test/debug on...
  63  */
  64 #define TX_BUF_LEN 256
  65 #define RX_BUF_LEN 32
  66
  67 struct nvt_dev {
  68         struct pnp_dev *pdev;
  69         struct rc_dev *rdev;
  70         struct ir_raw_event rawir;
  71
  72         spinlock_t nvt_lock;
  73
  74         /* for rx */
  75         u8 buf[RX_BUF_LEN];
  76         unsigned int pkts;
  77
  78         struct {
  79                 spinlock_t lock;
  80                 u8 buf[TX_BUF_LEN];
  81                 unsigned int buf_count;
  82                 unsigned int cur_buf_num;
  83                 wait_queue_head_t queue;
  84                 u8 tx_state;
  85         } tx;
  86
  87         /* EFER Config register index/data pair */
  88         u8 cr_efir;
  89         u8 cr_efdr;
  90
  91         /* hardware I/O settings */
  92         unsigned long cir_addr;
  93         unsigned long cir_wake_addr;
  94         int cir_irq;
  95         int cir_wake_irq;
  96
  97         /* hardware id */
  98         u8 chip_major;
  99         u8 chip_minor;
 100
 101         /* hardware features */
 102         bool hw_learning_capable;
 103         bool hw_tx_capable;
 104
 105         /* rx settings */
 106         bool learning_enabled;
 107         bool carrier_detect_enabled;
 108
 109         /* track cir wake state */
 110         u8 wake_state;
 111         /* for study */
 112         u8 study_state;
 113         /* carrier period = 1 / frequency */
 114         u32 carrier;
 115 };
 116
 117 /* study states */
 118 #define ST_STUDY_NONE      0x0
 119 #define ST_STUDY_START     0x1
 120 #define ST_STUDY_CARRIER   0x2
 121 #define ST_STUDY_ALL_RECV  0x4
 122
 123 /* wake states */
 124 #define ST_WAKE_NONE    0x0
 125 #define ST_WAKE_START   0x1
 126 #define ST_WAKE_FINISH  0x2
 127
 128 /* receive states */
 129 #define ST_RX_WAIT_7F           0x1
 130 #define ST_RX_WAIT_HEAD         0x2
 131 #define ST_RX_WAIT_SILENT_END   0x4
 132
 133 /* send states */
 134 #define ST_TX_NONE      0x0
 135 #define ST_TX_REQUEST   0x2
 136 #define ST_TX_REPLY     0x4
 137
 138 /* buffer packet constants */
 139 #define BUF_PULSE_BIT   0x80
 140 #define BUF_LEN_MASK    0x7f
 141 #define BUF_REPEAT_BYTE 0x70
 142 #define BUF_REPEAT_MASK 0xf0
 143
 144 /* CIR settings */
 145
 146 /* total length of CIR and CIR WAKE */
 147 #define CIR_IOREG_LENGTH        0x0f
 148
 149 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */
 150 #define CIR_RX_LIMIT_COUNT      0x7d0
 151
 152 /* CIR Regs */
 153 #define CIR_IRCON       0x00
 154 #define CIR_IRSTS       0x01
 155 #define CIR_IREN        0x02
 156 #define CIR_RXFCONT     0x03
 157 #define CIR_CP          0x04
 158 #define CIR_CC          0x05
 159 #define CIR_SLCH        0x06
 160 #define CIR_SLCL        0x07
 161 #define CIR_FIFOCON     0x08
 162 #define CIR_IRFIFOSTS   0x09
 163 #define CIR_SRXFIFO     0x0a
 164 #define CIR_TXFCONT     0x0b
 165 #define CIR_STXFIFO     0x0c
 166 #define CIR_FCCH        0x0d
 167 #define CIR_FCCL        0x0e
 168 #define CIR_IRFSM       0x0f
 169
 170 /* CIR IRCON settings */
 171 #define CIR_IRCON_RECV   0x80
 172 #define CIR_IRCON_WIREN  0x40
 173 #define CIR_IRCON_TXEN   0x20
 174 #define CIR_IRCON_RXEN   0x10
 175 #define CIR_IRCON_WRXINV 0x08
 176 #define CIR_IRCON_RXINV  0x04
 177
 178 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1   0x00
 179 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25  0x01
 180 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50  0x02
 181 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
 182
 183 /* FIXME: make this a runtime option */
 184 /* select sample period as 50us */
 185 #define CIR_IRCON_SAMPLE_PERIOD_SEL     CIR_IRCON_SAMPLE_PERIOD_SEL_50
 186
 187 /* CIR IRSTS settings */
 188 #define CIR_IRSTS_RDR   0x80
 189 #define CIR_IRSTS_RTR   0x40
 190 #define CIR_IRSTS_PE    0x20
 191 #define CIR_IRSTS_RFO   0x10
 192 #define CIR_IRSTS_TE    0x08
 193 #define CIR_IRSTS_TTR   0x04
 194 #define CIR_IRSTS_TFU   0x02
 195 #define CIR_IRSTS_GH    0x01
 196
 197 /* CIR IREN settings */
 198 #define CIR_IREN_RDR    0x80
 199 #define CIR_IREN_RTR    0x40
 200 #define CIR_IREN_PE     0x20
 201 #define CIR_IREN_RFO    0x10
 202 #define CIR_IREN_TE     0x08
 203 #define CIR_IREN_TTR    0x04
 204 #define CIR_IREN_TFU    0x02
 205 #define CIR_IREN_GH     0x01
 206
 207 /* CIR FIFOCON settings */
 208 #define CIR_FIFOCON_TXFIFOCLR           0x80
 209
 210 #define CIR_FIFOCON_TX_TRIGGER_LEV_31   0x00
 211 #define CIR_FIFOCON_TX_TRIGGER_LEV_24   0x10
 212 #define CIR_FIFOCON_TX_TRIGGER_LEV_16   0x20
 213 #define CIR_FIFOCON_TX_TRIGGER_LEV_8    0x30
 214
 215 /* FIXME: make this a runtime option */
 216 /* select TX trigger level as 16 */
 217 #define CIR_FIFOCON_TX_TRIGGER_LEV      CIR_FIFOCON_TX_TRIGGER_LEV_16
 218
 219 #define CIR_FIFOCON_RXFIFOCLR           0x08
 220
 221 #define CIR_FIFOCON_RX_TRIGGER_LEV_1    0x00
 222 #define CIR_FIFOCON_RX_TRIGGER_LEV_8    0x01
 223 #define CIR_FIFOCON_RX_TRIGGER_LEV_16   0x02
 224 #define CIR_FIFOCON_RX_TRIGGER_LEV_24   0x03
 225
 226 /* FIXME: make this a runtime option */
 227 /* select RX trigger level as 24 */
 228 #define CIR_FIFOCON_RX_TRIGGER_LEV      CIR_FIFOCON_RX_TRIGGER_LEV_24
 229
 230 /* CIR IRFIFOSTS settings */
 231 #define CIR_IRFIFOSTS_IR_PENDING        0x80
 232 #define CIR_IRFIFOSTS_RX_GS             0x40
 233 #define CIR_IRFIFOSTS_RX_FTA            0x20
 234 #define CIR_IRFIFOSTS_RX_EMPTY          0x10
 235 #define CIR_IRFIFOSTS_RX_FULL           0x08
 236 #define CIR_IRFIFOSTS_TX_FTA            0x04
 237 #define CIR_IRFIFOSTS_TX_EMPTY          0x02
 238 #define CIR_IRFIFOSTS_TX_FULL           0x01
 239
 240
 241 /* CIR WAKE UP Regs */
 242 #define CIR_WAKE_IRCON                  0x00
 243 #define CIR_WAKE_IRSTS                  0x01
 244 #define CIR_WAKE_IREN                   0x02
 245 #define CIR_WAKE_FIFO_CMP_DEEP          0x03
 246 #define CIR_WAKE_FIFO_CMP_TOL           0x04
 247 #define CIR_WAKE_FIFO_COUNT             0x05
 248 #define CIR_WAKE_SLCH                   0x06
 249 #define CIR_WAKE_SLCL                   0x07
 250 #define CIR_WAKE_FIFOCON                0x08
 251 #define CIR_WAKE_SRXFSTS                0x09
 252 #define CIR_WAKE_SAMPLE_RX_FIFO         0x0a
 253 #define CIR_WAKE_WR_FIFO_DATA           0x0b
 254 #define CIR_WAKE_RD_FIFO_ONLY           0x0c
 255 #define CIR_WAKE_RD_FIFO_ONLY_IDX       0x0d
 256 #define CIR_WAKE_FIFO_IGNORE            0x0e
 257 #define CIR_WAKE_IRFSM                  0x0f
 258
 259 /* CIR WAKE UP IRCON settings */
 260 #define CIR_WAKE_IRCON_DEC_RST          0x80
 261 #define CIR_WAKE_IRCON_MODE1            0x40
 262 #define CIR_WAKE_IRCON_MODE0            0x20
 263 #define CIR_WAKE_IRCON_RXEN             0x10
 264 #define CIR_WAKE_IRCON_R                0x08
 265 #define CIR_WAKE_IRCON_RXINV            0x04
 266
 267 /* FIXME/jarod: make this a runtime option */
 268 /* select a same sample period like cir register */
 269 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL        CIR_IRCON_SAMPLE_PERIOD_SEL_50
 270
 271 /* CIR WAKE IRSTS Bits */
 272 #define CIR_WAKE_IRSTS_RDR              0x80
 273 #define CIR_WAKE_IRSTS_RTR              0x40
 274 #define CIR_WAKE_IRSTS_PE               0x20
 275 #define CIR_WAKE_IRSTS_RFO              0x10
 276 #define CIR_WAKE_IRSTS_GH               0x08
 277 #define CIR_WAKE_IRSTS_IR_PENDING       0x01
 278
 279 /* CIR WAKE UP IREN Bits */
 280 #define CIR_WAKE_IREN_RDR               0x80
 281 #define CIR_WAKE_IREN_RTR               0x40
 282 #define CIR_WAKE_IREN_PE                0x20
 283 #define CIR_WAKE_IREN_RFO               0x10
 284 #define CIR_WAKE_IREN_TE                0x08
 285 #define CIR_WAKE_IREN_TTR               0x04
 286 #define CIR_WAKE_IREN_TFU               0x02
 287 #define CIR_WAKE_IREN_GH                0x01
 288
 289 /* CIR WAKE FIFOCON settings */
 290 #define CIR_WAKE_FIFOCON_RXFIFOCLR      0x08
 291
 292 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67      0x00
 293 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66      0x01
 294 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65      0x02
 295 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64      0x03
 296
 297 /* FIXME: make this a runtime option */
 298 /* select WAKE UP RX trigger level as 67 */
 299 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
 300
 301 /* CIR WAKE SRXFSTS settings */
 302 #define CIR_WAKE_IRFIFOSTS_RX_GS        0x80
 303 #define CIR_WAKE_IRFIFOSTS_RX_FTA       0x40
 304 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY     0x20
 305 #define CIR_WAKE_IRFIFOSTS_RX_FULL      0x10
 306
 307 /*
 308  * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
 309  * the system comparing only 65 bytes (fails with this set to 67)
 310  */
 311 #define CIR_WAKE_FIFO_CMP_BYTES         65
 312 /* CIR Wake byte comparison tolerance */
 313 #define CIR_WAKE_CMP_TOLERANCE          5
 314
 315 /*
 316  * Extended Function Enable Registers:
 317  *  Extended Function Index Register
 318  *  Extended Function Data Register
 319  */
 320 #define CR_EFIR                 0x2e
 321 #define CR_EFDR                 0x2f
 322
 323 /* Possible alternate EFER values, depends on how the chip is wired */
 324 #define CR_EFIR2                0x4e
 325 #define CR_EFDR2                0x4f
 326
 327 /* Extended Function Mode enable/disable magic values */
 328 #define EFER_EFM_ENABLE         0x87
 329 #define EFER_EFM_DISABLE        0xaa
 330
 331 /* Chip IDs found in CR_CHIP_ID_{HI,LO} */
 332 #define CHIP_ID_HIGH_667        0xa5
 333 #define CHIP_ID_HIGH_677B       0xb4
 334 #define CHIP_ID_HIGH_677C       0xc3
 335 #define CHIP_ID_LOW_667         0x13
 336 #define CHIP_ID_LOW_677B2       0x72
 337 #define CHIP_ID_LOW_677B3       0x73
 338 #define CHIP_ID_LOW_677C        0x33
 339
 340 /* Config regs we need to care about */
 341 #define CR_SOFTWARE_RESET       0x02
 342 #define CR_LOGICAL_DEV_SEL      0x07
 343 #define CR_CHIP_ID_HI           0x20
 344 #define CR_CHIP_ID_LO           0x21
 345 #define CR_DEV_POWER_DOWN       0x22 /* bit 2 is CIR power, default power on */
 346 #define CR_OUTPUT_PIN_SEL       0x27
 347 #define CR_MULTIFUNC_PIN_SEL    0x2c
 348 #define CR_LOGICAL_DEV_EN       0x30 /* valid for all logical devices */
 349 /* next three regs valid for both the CIR and CIR_WAKE logical devices */
 350 #define CR_CIR_BASE_ADDR_HI     0x60
 351 #define CR_CIR_BASE_ADDR_LO     0x61
 352 #define CR_CIR_IRQ_RSRC         0x70
 353 /* next three regs valid only for ACPI logical dev */
 354 #define CR_ACPI_CIR_WAKE        0xe0
 355 #define CR_ACPI_IRQ_EVENTS      0xf6
 356 #define CR_ACPI_IRQ_EVENTS2     0xf7
 357
 358 /* Logical devices that we need to care about */
 359 #define LOGICAL_DEV_LPT         0x01
 360 #define LOGICAL_DEV_CIR         0x06
 361 #define LOGICAL_DEV_ACPI        0x0a
 362 #define LOGICAL_DEV_CIR_WAKE    0x0e
 363
 364 #define LOGICAL_DEV_DISABLE     0x00
 365 #define LOGICAL_DEV_ENABLE      0x01
 366
 367 #define CIR_WAKE_ENABLE_BIT     0x08
 368 #define CIR_INTR_MOUSE_IRQ_BIT  0x80
 369 #define PME_INTR_CIR_PASS_BIT   0x08
 370
 371 /* w83677hg CIR pin config */
 372 #define OUTPUT_PIN_SEL_MASK     0xbc
 373 #define OUTPUT_ENABLE_CIR       0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
 374 #define OUTPUT_ENABLE_CIRWB     0x40 /* enable wide-band sensor */
 375
 376 /* w83667hg CIR pin config */
 377 #define MULTIFUNC_PIN_SEL_MASK  0x1f
 378 #define MULTIFUNC_ENABLE_CIR    0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
 379 #define MULTIFUNC_ENABLE_CIRWB  0x20 /* enable wide-band sensor */
 380
 381 /* MCE CIR signal length, related on sample period */
 382
 383 /* MCE CIR controller signal length: about 43ms
 384  * 43ms / 50us (sample period) * 0.85 (inaccuracy)
 385  */
 386 #define CONTROLLER_BUF_LEN_MIN 830
 387
 388 /* MCE CIR keyboard signal length: about 26ms
 389  * 26ms / 50us (sample period) * 0.85 (inaccuracy)
 390  */
 391 #define KEYBOARD_BUF_LEN_MAX 650
 392 #define KEYBOARD_BUF_LEN_MIN 610
 393
 394 /* MCE CIR mouse signal length: about 24ms
 395  * 24ms / 50us (sample period) * 0.85 (inaccuracy)
 396  */
 397 #define MOUSE_BUF_LEN_MIN 565
 398
 399 #define CIR_SAMPLE_PERIOD 50
 400 #define CIR_SAMPLE_LOW_INACCURACY 0.85
 401
 402 /* MAX silence time that driver will sent to lirc */
 403 #define MAX_SILENCE_TIME 60000
 404
 405 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
 406 #define SAMPLE_PERIOD 100
 407
 408 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
 409 #define SAMPLE_PERIOD 50
 410
 411 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
 412 #define SAMPLE_PERIOD 25
 413
 414 #else
 415 #define SAMPLE_PERIOD 1
 416 #endif
 417
 418 /* as VISTA MCE definition, valid carrier value */
 419 #define MAX_CARRIER 60000
 420 #define MIN_CARRIER 30000