3 * Support for a cx23417 mpeg encoder via cx23885 host port.
5 * (c) 2004 Jelle Foks <jelle@foks.us>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
8 * - CX23885/7/8 support
10 * Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/cx2341x.h>
40 #include "cx23885-ioctl.h"
42 #define CX23885_FIRM_IMAGE_SIZE 376836
43 #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
45 static unsigned int mpegbufs
= 32;
46 module_param(mpegbufs
, int, 0644);
47 MODULE_PARM_DESC(mpegbufs
, "number of mpeg buffers, range 2-32");
48 static unsigned int mpeglines
= 32;
49 module_param(mpeglines
, int, 0644);
50 MODULE_PARM_DESC(mpeglines
, "number of lines in an MPEG buffer, range 2-32");
51 static unsigned int mpeglinesize
= 512;
52 module_param(mpeglinesize
, int, 0644);
53 MODULE_PARM_DESC(mpeglinesize
,
54 "number of bytes in each line of an MPEG buffer, range 512-1024");
56 static unsigned int v4l_debug
;
57 module_param(v4l_debug
, int, 0644);
58 MODULE_PARM_DESC(v4l_debug
, "enable V4L debug messages");
60 #define dprintk(level, fmt, arg...)\
61 do { if (v4l_debug >= level) \
62 printk(KERN_DEBUG "%s: " fmt, \
63 (dev) ? dev->name : "cx23885[?]", ## arg); \
66 static struct cx23885_tvnorm cx23885_tvnorms
[] = {
69 .id
= V4L2_STD_NTSC_M
,
72 .id
= V4L2_STD_NTSC_M_JP
,
75 .id
= V4L2_STD_PAL_BG
,
78 .id
= V4L2_STD_PAL_DK
,
90 .id
= V4L2_STD_PAL_Nc
,
93 .id
= V4L2_STD_PAL_60
,
96 .id
= V4L2_STD_SECAM_L
,
99 .id
= V4L2_STD_SECAM_DK
,
103 /* ------------------------------------------------------------------ */
104 enum cx23885_capture_type
{
105 CX23885_MPEG_CAPTURE
,
107 CX23885_RAW_PASSTHRU_CAPTURE
109 enum cx23885_capture_bits
{
110 CX23885_RAW_BITS_NONE
= 0x00,
111 CX23885_RAW_BITS_YUV_CAPTURE
= 0x01,
112 CX23885_RAW_BITS_PCM_CAPTURE
= 0x02,
113 CX23885_RAW_BITS_VBI_CAPTURE
= 0x04,
114 CX23885_RAW_BITS_PASSTHRU_CAPTURE
= 0x08,
115 CX23885_RAW_BITS_TO_HOST_CAPTURE
= 0x10
117 enum cx23885_capture_end
{
118 CX23885_END_AT_GOP
, /* stop at the end of gop, generate irq */
119 CX23885_END_NOW
, /* stop immediately, no irq */
121 enum cx23885_framerate
{
122 CX23885_FRAMERATE_NTSC_30
, /* NTSC: 30fps */
123 CX23885_FRAMERATE_PAL_25
/* PAL: 25fps */
125 enum cx23885_stream_port
{
126 CX23885_OUTPUT_PORT_MEMORY
,
127 CX23885_OUTPUT_PORT_STREAMING
,
128 CX23885_OUTPUT_PORT_SERIAL
130 enum cx23885_data_xfer_status
{
131 CX23885_MORE_BUFFERS_FOLLOW
,
134 enum cx23885_picture_mask
{
135 CX23885_PICTURE_MASK_NONE
,
136 CX23885_PICTURE_MASK_I_FRAMES
,
137 CX23885_PICTURE_MASK_I_P_FRAMES
= 0x3,
138 CX23885_PICTURE_MASK_ALL_FRAMES
= 0x7,
140 enum cx23885_vbi_mode_bits
{
141 CX23885_VBI_BITS_SLICED
,
142 CX23885_VBI_BITS_RAW
,
144 enum cx23885_vbi_insertion_bits
{
145 CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA
,
146 CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS
= 0x1 << 1,
147 CX23885_VBI_BITS_SEPARATE_STREAM
= 0x2 << 1,
148 CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA
= 0x4 << 1,
149 CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA
= 0x5 << 1,
151 enum cx23885_dma_unit
{
155 enum cx23885_dma_transfer_status_bits
{
156 CX23885_DMA_TRANSFER_BITS_DONE
= 0x01,
157 CX23885_DMA_TRANSFER_BITS_ERROR
= 0x04,
158 CX23885_DMA_TRANSFER_BITS_LL_ERROR
= 0x10,
161 CX23885_PAUSE_ENCODING
,
162 CX23885_RESUME_ENCODING
,
164 enum cx23885_copyright
{
165 CX23885_COPYRIGHT_OFF
,
166 CX23885_COPYRIGHT_ON
,
168 enum cx23885_notification_type
{
169 CX23885_NOTIFICATION_REFRESH
,
171 enum cx23885_notification_status
{
172 CX23885_NOTIFICATION_OFF
,
173 CX23885_NOTIFICATION_ON
,
175 enum cx23885_notification_mailbox
{
176 CX23885_NOTIFICATION_NO_MAILBOX
= -1,
178 enum cx23885_field1_lines
{
179 CX23885_FIELD1_SAA7114
= 0x00EF, /* 239 */
180 CX23885_FIELD1_SAA7115
= 0x00F0, /* 240 */
181 CX23885_FIELD1_MICRONAS
= 0x0105, /* 261 */
183 enum cx23885_field2_lines
{
184 CX23885_FIELD2_SAA7114
= 0x00EF, /* 239 */
185 CX23885_FIELD2_SAA7115
= 0x00F0, /* 240 */
186 CX23885_FIELD2_MICRONAS
= 0x0106, /* 262 */
188 enum cx23885_custom_data_type
{
189 CX23885_CUSTOM_EXTENSION_USR_DATA
,
190 CX23885_CUSTOM_PRIVATE_PACKET
,
196 enum cx23885_mute_video_mask
{
197 CX23885_MUTE_VIDEO_V_MASK
= 0x0000FF00,
198 CX23885_MUTE_VIDEO_U_MASK
= 0x00FF0000,
199 CX23885_MUTE_VIDEO_Y_MASK
= 0xFF000000,
201 enum cx23885_mute_video_shift
{
202 CX23885_MUTE_VIDEO_V_SHIFT
= 8,
203 CX23885_MUTE_VIDEO_U_SHIFT
= 16,
204 CX23885_MUTE_VIDEO_Y_SHIFT
= 24,
207 /* defines below are from ivtv-driver.h */
208 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
210 /* Firmware API commands */
211 #define IVTV_API_STD_TIMEOUT 500
214 /* IVTV_REG_OFFSET */
215 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
216 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
217 #define IVTV_REG_SPU (0x9050)
218 #define IVTV_REG_HW_BLOCKS (0x9054)
219 #define IVTV_REG_VPU (0x9058)
220 #define IVTV_REG_APU (0xA064)
222 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
227 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
228 +-------+-------+-------+-------+-------+-------+-------+-------+
229 | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
230 +-------+-------+-------+-------+-------+-------+-------+-------+
231 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
232 +-------+-------+-------+-------+-------+-------+-------+-------+
233 |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
234 +-------+-------+-------+-------+-------+-------+-------+-------+
236 #define MC417_MIWR 0x8000
237 #define MC417_MIRD 0x4000
238 #define MC417_MICS 0x2000
239 #define MC417_MIRDY 0x1000
240 #define MC417_MIADDR 0x0F00
241 #define MC417_MIDATA 0x00FF
243 /* MIADDR* nibble definitions */
244 #define MCI_MEMORY_DATA_BYTE0 0x000
245 #define MCI_MEMORY_DATA_BYTE1 0x100
246 #define MCI_MEMORY_DATA_BYTE2 0x200
247 #define MCI_MEMORY_DATA_BYTE3 0x300
248 #define MCI_MEMORY_ADDRESS_BYTE2 0x400
249 #define MCI_MEMORY_ADDRESS_BYTE1 0x500
250 #define MCI_MEMORY_ADDRESS_BYTE0 0x600
251 #define MCI_REGISTER_DATA_BYTE0 0x800
252 #define MCI_REGISTER_DATA_BYTE1 0x900
253 #define MCI_REGISTER_DATA_BYTE2 0xA00
254 #define MCI_REGISTER_DATA_BYTE3 0xB00
255 #define MCI_REGISTER_ADDRESS_BYTE0 0xC00
256 #define MCI_REGISTER_ADDRESS_BYTE1 0xD00
257 #define MCI_REGISTER_MODE 0xE00
259 /* Read and write modes */
260 #define MCI_MODE_REGISTER_READ 0
261 #define MCI_MODE_REGISTER_WRITE 1
262 #define MCI_MODE_MEMORY_READ 0
263 #define MCI_MODE_MEMORY_WRITE 0x40
265 /*** Bit definitions for MC417_CTL register ****
266 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
267 +--------+-------------+--------+--------------+------------+
268 |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
269 +--------+-------------+--------+--------------+------------+
271 #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
272 #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
273 #define MC417_UART_GPIO_EN 0x00000001
275 /* Values for speed control */
276 #define MC417_SPD_CTL_SLOW 0x1
277 #define MC417_SPD_CTL_MEDIUM 0x0
278 #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
280 /* Values for GPIO select */
281 #define MC417_GPIO_SEL_GPIO3 0x3
282 #define MC417_GPIO_SEL_GPIO2 0x2
283 #define MC417_GPIO_SEL_GPIO1 0x1
284 #define MC417_GPIO_SEL_GPIO0 0x0
286 void cx23885_mc417_init(struct cx23885_dev
*dev
)
290 dprintk(2, "%s()\n", __func__
);
292 /* Configure MC417_CTL register to defaults. */
293 regval
= MC417_SPD_CTL(MC417_SPD_CTL_FAST
) |
294 MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3
) |
296 cx_write(MC417_CTL
, regval
);
298 /* Configure MC417_OEN to defaults. */
299 regval
= MC417_MIRDY
;
300 cx_write(MC417_OEN
, regval
);
302 /* Configure MC417_RWD to defaults. */
303 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
;
304 cx_write(MC417_RWD
, regval
);
307 static int mc417_wait_ready(struct cx23885_dev
*dev
)
310 unsigned long timeout
= jiffies
+ msecs_to_jiffies(1);
313 mi_ready
= cx_read(MC417_RWD
) & MC417_MIRDY
;
316 if (time_after(jiffies
, timeout
))
322 int mc417_register_write(struct cx23885_dev
*dev
, u16 address
, u32 value
)
326 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
329 cx_write(MC417_OEN
, MC417_MIRDY
);
331 /* Write data byte 0 */
332 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE0
|
333 (value
& 0x000000FF);
334 cx_write(MC417_RWD
, regval
);
336 /* Transition CS/WR to effect write transaction across bus. */
337 regval
|= MC417_MICS
| MC417_MIWR
;
338 cx_write(MC417_RWD
, regval
);
340 /* Write data byte 1 */
341 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE1
|
342 ((value
>> 8) & 0x000000FF);
343 cx_write(MC417_RWD
, regval
);
344 regval
|= MC417_MICS
| MC417_MIWR
;
345 cx_write(MC417_RWD
, regval
);
347 /* Write data byte 2 */
348 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE2
|
349 ((value
>> 16) & 0x000000FF);
350 cx_write(MC417_RWD
, regval
);
351 regval
|= MC417_MICS
| MC417_MIWR
;
352 cx_write(MC417_RWD
, regval
);
354 /* Write data byte 3 */
355 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE3
|
356 ((value
>> 24) & 0x000000FF);
357 cx_write(MC417_RWD
, regval
);
358 regval
|= MC417_MICS
| MC417_MIWR
;
359 cx_write(MC417_RWD
, regval
);
361 /* Write address byte 0 */
362 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_ADDRESS_BYTE0
|
364 cx_write(MC417_RWD
, regval
);
365 regval
|= MC417_MICS
| MC417_MIWR
;
366 cx_write(MC417_RWD
, regval
);
368 /* Write address byte 1 */
369 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_ADDRESS_BYTE1
|
370 ((address
>> 8) & 0xFF);
371 cx_write(MC417_RWD
, regval
);
372 regval
|= MC417_MICS
| MC417_MIWR
;
373 cx_write(MC417_RWD
, regval
);
375 /* Indicate that this is a write. */
376 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_MODE
|
377 MCI_MODE_REGISTER_WRITE
;
378 cx_write(MC417_RWD
, regval
);
379 regval
|= MC417_MICS
| MC417_MIWR
;
380 cx_write(MC417_RWD
, regval
);
382 /* Wait for the trans to complete (MC417_MIRDY asserted). */
383 return mc417_wait_ready(dev
);
386 int mc417_register_read(struct cx23885_dev
*dev
, u16 address
, u32
*value
)
393 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
396 cx_write(MC417_OEN
, MC417_MIRDY
);
398 /* Write address byte 0 */
399 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_ADDRESS_BYTE0
|
400 ((address
& 0x00FF));
401 cx_write(MC417_RWD
, regval
);
402 regval
|= MC417_MICS
| MC417_MIWR
;
403 cx_write(MC417_RWD
, regval
);
405 /* Write address byte 1 */
406 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_ADDRESS_BYTE1
|
407 ((address
>> 8) & 0xFF);
408 cx_write(MC417_RWD
, regval
);
409 regval
|= MC417_MICS
| MC417_MIWR
;
410 cx_write(MC417_RWD
, regval
);
412 /* Indicate that this is a register read. */
413 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_MODE
|
414 MCI_MODE_REGISTER_READ
;
415 cx_write(MC417_RWD
, regval
);
416 regval
|= MC417_MICS
| MC417_MIWR
;
417 cx_write(MC417_RWD
, regval
);
419 /* Wait for the trans to complete (MC417_MIRDY asserted). */
420 retval
= mc417_wait_ready(dev
);
422 /* switch the DAT0-7 GPIO[10:3] to input mode */
423 cx_write(MC417_OEN
, MC417_MIRDY
| MC417_MIDATA
);
425 /* Read data byte 0 */
426 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE0
;
427 cx_write(MC417_RWD
, regval
);
429 /* Transition RD to effect read transaction across bus.
430 * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
431 * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
434 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE0
;
435 cx_write(MC417_RWD
, regval
);
438 tempval
= cx_read(MC417_RWD
);
439 dataval
= tempval
& 0x000000FF;
441 /* Bring CS and RD high. */
442 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
443 cx_write(MC417_RWD
, regval
);
445 /* Read data byte 1 */
446 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE1
;
447 cx_write(MC417_RWD
, regval
);
448 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE1
;
449 cx_write(MC417_RWD
, regval
);
450 tempval
= cx_read(MC417_RWD
);
451 dataval
|= ((tempval
& 0x000000FF) << 8);
452 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
453 cx_write(MC417_RWD
, regval
);
455 /* Read data byte 2 */
456 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE2
;
457 cx_write(MC417_RWD
, regval
);
458 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE2
;
459 cx_write(MC417_RWD
, regval
);
460 tempval
= cx_read(MC417_RWD
);
461 dataval
|= ((tempval
& 0x000000FF) << 16);
462 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
463 cx_write(MC417_RWD
, regval
);
465 /* Read data byte 3 */
466 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE3
;
467 cx_write(MC417_RWD
, regval
);
468 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_REGISTER_DATA_BYTE3
;
469 cx_write(MC417_RWD
, regval
);
470 tempval
= cx_read(MC417_RWD
);
471 dataval
|= ((tempval
& 0x000000FF) << 24);
472 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
473 cx_write(MC417_RWD
, regval
);
480 int mc417_memory_write(struct cx23885_dev
*dev
, u32 address
, u32 value
)
484 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
487 cx_write(MC417_OEN
, MC417_MIRDY
);
489 /* Write data byte 0 */
490 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE0
|
491 (value
& 0x000000FF);
492 cx_write(MC417_RWD
, regval
);
494 /* Transition CS/WR to effect write transaction across bus. */
495 regval
|= MC417_MICS
| MC417_MIWR
;
496 cx_write(MC417_RWD
, regval
);
498 /* Write data byte 1 */
499 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE1
|
500 ((value
>> 8) & 0x000000FF);
501 cx_write(MC417_RWD
, regval
);
502 regval
|= MC417_MICS
| MC417_MIWR
;
503 cx_write(MC417_RWD
, regval
);
505 /* Write data byte 2 */
506 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE2
|
507 ((value
>> 16) & 0x000000FF);
508 cx_write(MC417_RWD
, regval
);
509 regval
|= MC417_MICS
| MC417_MIWR
;
510 cx_write(MC417_RWD
, regval
);
512 /* Write data byte 3 */
513 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE3
|
514 ((value
>> 24) & 0x000000FF);
515 cx_write(MC417_RWD
, regval
);
516 regval
|= MC417_MICS
| MC417_MIWR
;
517 cx_write(MC417_RWD
, regval
);
519 /* Write address byte 2 */
520 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_ADDRESS_BYTE2
|
521 MCI_MODE_MEMORY_WRITE
| ((address
>> 16) & 0x3F);
522 cx_write(MC417_RWD
, regval
);
523 regval
|= MC417_MICS
| MC417_MIWR
;
524 cx_write(MC417_RWD
, regval
);
526 /* Write address byte 1 */
527 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_ADDRESS_BYTE1
|
528 ((address
>> 8) & 0xFF);
529 cx_write(MC417_RWD
, regval
);
530 regval
|= MC417_MICS
| MC417_MIWR
;
531 cx_write(MC417_RWD
, regval
);
533 /* Write address byte 0 */
534 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_ADDRESS_BYTE0
|
536 cx_write(MC417_RWD
, regval
);
537 regval
|= MC417_MICS
| MC417_MIWR
;
538 cx_write(MC417_RWD
, regval
);
540 /* Wait for the trans to complete (MC417_MIRDY asserted). */
541 return mc417_wait_ready(dev
);
544 int mc417_memory_read(struct cx23885_dev
*dev
, u32 address
, u32
*value
)
551 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
554 cx_write(MC417_OEN
, MC417_MIRDY
);
556 /* Write address byte 2 */
557 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_ADDRESS_BYTE2
|
558 MCI_MODE_MEMORY_READ
| ((address
>> 16) & 0x3F);
559 cx_write(MC417_RWD
, regval
);
560 regval
|= MC417_MICS
| MC417_MIWR
;
561 cx_write(MC417_RWD
, regval
);
563 /* Write address byte 1 */
564 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_ADDRESS_BYTE1
|
565 ((address
>> 8) & 0xFF);
566 cx_write(MC417_RWD
, regval
);
567 regval
|= MC417_MICS
| MC417_MIWR
;
568 cx_write(MC417_RWD
, regval
);
570 /* Write address byte 0 */
571 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_ADDRESS_BYTE0
|
573 cx_write(MC417_RWD
, regval
);
574 regval
|= MC417_MICS
| MC417_MIWR
;
575 cx_write(MC417_RWD
, regval
);
577 /* Wait for the trans to complete (MC417_MIRDY asserted). */
578 retval
= mc417_wait_ready(dev
);
580 /* switch the DAT0-7 GPIO[10:3] to input mode */
581 cx_write(MC417_OEN
, MC417_MIRDY
| MC417_MIDATA
);
583 /* Read data byte 3 */
584 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE3
;
585 cx_write(MC417_RWD
, regval
);
587 /* Transition RD to effect read transaction across bus. */
588 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE3
;
589 cx_write(MC417_RWD
, regval
);
592 tempval
= cx_read(MC417_RWD
);
593 dataval
= ((tempval
& 0x000000FF) << 24);
595 /* Bring CS and RD high. */
596 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
597 cx_write(MC417_RWD
, regval
);
599 /* Read data byte 2 */
600 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE2
;
601 cx_write(MC417_RWD
, regval
);
602 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE2
;
603 cx_write(MC417_RWD
, regval
);
604 tempval
= cx_read(MC417_RWD
);
605 dataval
|= ((tempval
& 0x000000FF) << 16);
606 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
607 cx_write(MC417_RWD
, regval
);
609 /* Read data byte 1 */
610 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE1
;
611 cx_write(MC417_RWD
, regval
);
612 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE1
;
613 cx_write(MC417_RWD
, regval
);
614 tempval
= cx_read(MC417_RWD
);
615 dataval
|= ((tempval
& 0x000000FF) << 8);
616 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
617 cx_write(MC417_RWD
, regval
);
619 /* Read data byte 0 */
620 regval
= MC417_MIRD
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE0
;
621 cx_write(MC417_RWD
, regval
);
622 regval
= MC417_MIWR
| MC417_MIRDY
| MCI_MEMORY_DATA_BYTE0
;
623 cx_write(MC417_RWD
, regval
);
624 tempval
= cx_read(MC417_RWD
);
625 dataval
|= (tempval
& 0x000000FF);
626 regval
= MC417_MIWR
| MC417_MIRD
| MC417_MICS
| MC417_MIRDY
;
627 cx_write(MC417_RWD
, regval
);
634 void mc417_gpio_set(struct cx23885_dev
*dev
, u32 mask
)
638 /* Set the gpio value */
639 mc417_register_read(dev
, 0x900C, &val
);
640 val
|= (mask
& 0x000ffff);
641 mc417_register_write(dev
, 0x900C, val
);
644 void mc417_gpio_clear(struct cx23885_dev
*dev
, u32 mask
)
648 /* Clear the gpio value */
649 mc417_register_read(dev
, 0x900C, &val
);
650 val
&= ~(mask
& 0x0000ffff);
651 mc417_register_write(dev
, 0x900C, val
);
654 void mc417_gpio_enable(struct cx23885_dev
*dev
, u32 mask
, int asoutput
)
658 /* Enable GPIO direction bits */
659 mc417_register_read(dev
, 0x9020, &val
);
661 val
|= (mask
& 0x0000ffff);
663 val
&= ~(mask
& 0x0000ffff);
665 mc417_register_write(dev
, 0x9020, val
);
667 /* ------------------------------------------------------------------ */
669 /* MPEG encoder API */
670 static char *cmd_to_str(int cmd
)
673 case CX2341X_ENC_PING_FW
:
675 case CX2341X_ENC_START_CAPTURE
:
676 return "START_CAPTURE";
677 case CX2341X_ENC_STOP_CAPTURE
:
678 return "STOP_CAPTURE";
679 case CX2341X_ENC_SET_AUDIO_ID
:
680 return "SET_AUDIO_ID";
681 case CX2341X_ENC_SET_VIDEO_ID
:
682 return "SET_VIDEO_ID";
683 case CX2341X_ENC_SET_PCR_ID
:
685 case CX2341X_ENC_SET_FRAME_RATE
:
686 return "SET_FRAME_RATE";
687 case CX2341X_ENC_SET_FRAME_SIZE
:
688 return "SET_FRAME_SIZE";
689 case CX2341X_ENC_SET_BIT_RATE
:
690 return "SET_BIT_RATE";
691 case CX2341X_ENC_SET_GOP_PROPERTIES
:
692 return "SET_GOP_PROPERTIES";
693 case CX2341X_ENC_SET_ASPECT_RATIO
:
694 return "SET_ASPECT_RATIO";
695 case CX2341X_ENC_SET_DNR_FILTER_MODE
:
696 return "SET_DNR_FILTER_MODE";
697 case CX2341X_ENC_SET_DNR_FILTER_PROPS
:
698 return "SET_DNR_FILTER_PROPS";
699 case CX2341X_ENC_SET_CORING_LEVELS
:
700 return "SET_CORING_LEVELS";
701 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE
:
702 return "SET_SPATIAL_FILTER_TYPE";
703 case CX2341X_ENC_SET_VBI_LINE
:
704 return "SET_VBI_LINE";
705 case CX2341X_ENC_SET_STREAM_TYPE
:
706 return "SET_STREAM_TYPE";
707 case CX2341X_ENC_SET_OUTPUT_PORT
:
708 return "SET_OUTPUT_PORT";
709 case CX2341X_ENC_SET_AUDIO_PROPERTIES
:
710 return "SET_AUDIO_PROPERTIES";
711 case CX2341X_ENC_HALT_FW
:
713 case CX2341X_ENC_GET_VERSION
:
714 return "GET_VERSION";
715 case CX2341X_ENC_SET_GOP_CLOSURE
:
716 return "SET_GOP_CLOSURE";
717 case CX2341X_ENC_GET_SEQ_END
:
718 return "GET_SEQ_END";
719 case CX2341X_ENC_SET_PGM_INDEX_INFO
:
720 return "SET_PGM_INDEX_INFO";
721 case CX2341X_ENC_SET_VBI_CONFIG
:
722 return "SET_VBI_CONFIG";
723 case CX2341X_ENC_SET_DMA_BLOCK_SIZE
:
724 return "SET_DMA_BLOCK_SIZE";
725 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10
:
726 return "GET_PREV_DMA_INFO_MB_10";
727 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
:
728 return "GET_PREV_DMA_INFO_MB_9";
729 case CX2341X_ENC_SCHED_DMA_TO_HOST
:
730 return "SCHED_DMA_TO_HOST";
731 case CX2341X_ENC_INITIALIZE_INPUT
:
732 return "INITIALIZE_INPUT";
733 case CX2341X_ENC_SET_FRAME_DROP_RATE
:
734 return "SET_FRAME_DROP_RATE";
735 case CX2341X_ENC_PAUSE_ENCODER
:
736 return "PAUSE_ENCODER";
737 case CX2341X_ENC_REFRESH_INPUT
:
738 return "REFRESH_INPUT";
739 case CX2341X_ENC_SET_COPYRIGHT
:
740 return "SET_COPYRIGHT";
741 case CX2341X_ENC_SET_EVENT_NOTIFICATION
:
742 return "SET_EVENT_NOTIFICATION";
743 case CX2341X_ENC_SET_NUM_VSYNC_LINES
:
744 return "SET_NUM_VSYNC_LINES";
745 case CX2341X_ENC_SET_PLACEHOLDER
:
746 return "SET_PLACEHOLDER";
747 case CX2341X_ENC_MUTE_VIDEO
:
749 case CX2341X_ENC_MUTE_AUDIO
:
751 case CX2341X_ENC_MISC
:
758 static int cx23885_mbox_func(void *priv
,
762 u32 data
[CX2341X_MBOX_MAX_DATA
])
764 struct cx23885_dev
*dev
= priv
;
765 unsigned long timeout
;
766 u32 value
, flag
, retval
= 0;
769 dprintk(3, "%s: command(0x%X) = %s\n", __func__
, command
,
770 cmd_to_str(command
));
772 /* this may not be 100% safe if we can't read any memory location
773 without side effects */
774 mc417_memory_read(dev
, dev
->cx23417_mailbox
- 4, &value
);
775 if (value
!= 0x12345678) {
777 "Firmware and/or mailbox pointer not initialized "
778 "or corrupted, signature = 0x%x, cmd = %s\n", value
,
779 cmd_to_str(command
));
783 /* This read looks at 32 bits, but flag is only 8 bits.
784 * Seems we also bail if CMD or TIMEOUT bytes are set???
786 mc417_memory_read(dev
, dev
->cx23417_mailbox
, &flag
);
788 printk(KERN_ERR
"ERROR: Mailbox appears to be in use "
789 "(%x), cmd = %s\n", flag
, cmd_to_str(command
));
793 flag
|= 1; /* tell 'em we're working on it */
794 mc417_memory_write(dev
, dev
->cx23417_mailbox
, flag
);
796 /* write command + args + fill remaining with zeros */
798 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 1, command
);
799 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 3,
800 IVTV_API_STD_TIMEOUT
); /* timeout */
801 for (i
= 0; i
< in
; i
++) {
802 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 4 + i
, data
[i
]);
803 dprintk(3, "API Input %d = %d\n", i
, data
[i
]);
805 for (; i
< CX2341X_MBOX_MAX_DATA
; i
++)
806 mc417_memory_write(dev
, dev
->cx23417_mailbox
+ 4 + i
, 0);
808 flag
|= 3; /* tell 'em we're done writing */
809 mc417_memory_write(dev
, dev
->cx23417_mailbox
, flag
);
811 /* wait for firmware to handle the API command */
812 timeout
= jiffies
+ msecs_to_jiffies(10);
814 mc417_memory_read(dev
, dev
->cx23417_mailbox
, &flag
);
817 if (time_after(jiffies
, timeout
)) {
818 printk(KERN_ERR
"ERROR: API Mailbox timeout\n");
824 /* read output values */
825 for (i
= 0; i
< out
; i
++) {
826 mc417_memory_read(dev
, dev
->cx23417_mailbox
+ 4 + i
, data
+ i
);
827 dprintk(3, "API Output %d = %d\n", i
, data
[i
]);
830 mc417_memory_read(dev
, dev
->cx23417_mailbox
+ 2, &retval
);
831 dprintk(3, "API result = %d\n", retval
);
834 mc417_memory_write(dev
, dev
->cx23417_mailbox
, flag
);
839 /* We don't need to call the API often, so using just one
840 * mailbox will probably suffice
842 static int cx23885_api_cmd(struct cx23885_dev
*dev
,
848 u32 data
[CX2341X_MBOX_MAX_DATA
];
852 dprintk(3, "%s() cmds = 0x%08x\n", __func__
, command
);
854 va_start(vargs
, outputcnt
);
855 for (i
= 0; i
< inputcnt
; i
++)
856 data
[i
] = va_arg(vargs
, int);
858 err
= cx23885_mbox_func(dev
, command
, inputcnt
, outputcnt
, data
);
859 for (i
= 0; i
< outputcnt
; i
++) {
860 int *vptr
= va_arg(vargs
, int *);
868 static int cx23885_find_mailbox(struct cx23885_dev
*dev
)
871 0x12345678, 0x34567812, 0x56781234, 0x78123456
873 int signaturecnt
= 0;
877 dprintk(2, "%s()\n", __func__
);
879 for (i
= 0; i
< CX23885_FIRM_IMAGE_SIZE
; i
++) {
880 mc417_memory_read(dev
, i
, &value
);
881 if (value
== signature
[signaturecnt
])
885 if (4 == signaturecnt
) {
886 dprintk(1, "Mailbox signature found at 0x%x\n", i
+1);
890 printk(KERN_ERR
"Mailbox signature values not found!\n");
894 static int cx23885_load_firmware(struct cx23885_dev
*dev
)
896 static const unsigned char magic
[8] = {
897 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
899 const struct firmware
*firmware
;
906 dprintk(2, "%s()\n", __func__
);
908 /* Save GPIO settings before reset of APU */
909 retval
|= mc417_memory_read(dev
, 0x9020, &gpio_output
);
910 retval
|= mc417_memory_read(dev
, 0x900C, &value
);
912 retval
= mc417_register_write(dev
,
913 IVTV_REG_VPU
, 0xFFFFFFED);
914 retval
|= mc417_register_write(dev
,
915 IVTV_REG_HW_BLOCKS
, IVTV_CMD_HW_BLOCKS_RST
);
916 retval
|= mc417_register_write(dev
,
917 IVTV_REG_ENC_SDRAM_REFRESH
, 0x80000800);
918 retval
|= mc417_register_write(dev
,
919 IVTV_REG_ENC_SDRAM_PRECHARGE
, 0x1A);
920 retval
|= mc417_register_write(dev
,
924 printk(KERN_ERR
"%s: Error with mc417_register_write\n",
929 retval
= request_firmware(&firmware
, CX23885_FIRM_IMAGE_NAME
,
934 "ERROR: Hotplug firmware request failed (%s).\n",
935 CX23885_FIRM_IMAGE_NAME
);
936 printk(KERN_ERR
"Please fix your hotplug setup, the board will "
937 "not work without firmware loaded!\n");
941 if (firmware
->size
!= CX23885_FIRM_IMAGE_SIZE
) {
942 printk(KERN_ERR
"ERROR: Firmware size mismatch "
943 "(have %zd, expected %d)\n",
944 firmware
->size
, CX23885_FIRM_IMAGE_SIZE
);
945 release_firmware(firmware
);
949 if (0 != memcmp(firmware
->data
, magic
, 8)) {
951 "ERROR: Firmware magic mismatch, wrong file?\n");
952 release_firmware(firmware
);
956 /* transfer to the chip */
957 dprintk(2, "Loading firmware ...\n");
958 dataptr
= (u32
*)firmware
->data
;
959 for (i
= 0; i
< (firmware
->size
>> 2); i
++) {
962 if (mc417_memory_write(dev
, i
, value
) != 0) {
963 printk(KERN_ERR
"ERROR: Loading firmware failed!\n");
964 release_firmware(firmware
);
970 /* read back to verify with the checksum */
971 dprintk(1, "Verifying firmware ...\n");
972 for (i
--; i
>= 0; i
--) {
973 if (mc417_memory_read(dev
, i
, &value
) != 0) {
974 printk(KERN_ERR
"ERROR: Reading firmware failed!\n");
975 release_firmware(firmware
);
982 "ERROR: Firmware load failed (checksum mismatch).\n");
983 release_firmware(firmware
);
986 release_firmware(firmware
);
987 dprintk(1, "Firmware upload successful.\n");
989 retval
|= mc417_register_write(dev
, IVTV_REG_HW_BLOCKS
,
990 IVTV_CMD_HW_BLOCKS_RST
);
992 /* F/W power up disturbs the GPIOs, restore state */
993 retval
|= mc417_register_write(dev
, 0x9020, gpio_output
);
994 retval
|= mc417_register_write(dev
, 0x900C, value
);
996 retval
|= mc417_register_read(dev
, IVTV_REG_VPU
, &value
);
997 retval
|= mc417_register_write(dev
, IVTV_REG_VPU
, value
& 0xFFFFFFE8);
1000 printk(KERN_ERR
"%s: Error with mc417_register_write\n",
1005 void cx23885_417_check_encoder(struct cx23885_dev
*dev
)
1010 cx23885_api_cmd(dev
, CX2341X_ENC_GET_SEQ_END
, 0, 2, &status
, &seq
);
1011 dprintk(1, "%s() status = %d, seq = %d\n", __func__
, status
, seq
);
1014 static void cx23885_codec_settings(struct cx23885_dev
*dev
)
1016 dprintk(1, "%s()\n", __func__
);
1018 /* assign frame size */
1019 cx23885_api_cmd(dev
, CX2341X_ENC_SET_FRAME_SIZE
, 2, 0,
1020 dev
->ts1
.height
, dev
->ts1
.width
);
1022 dev
->mpeg_params
.width
= dev
->ts1
.width
;
1023 dev
->mpeg_params
.height
= dev
->ts1
.height
;
1024 dev
->mpeg_params
.is_50hz
=
1025 (dev
->encodernorm
.id
& V4L2_STD_625_50
) != 0;
1027 cx2341x_update(dev
, cx23885_mbox_func
, NULL
, &dev
->mpeg_params
);
1029 cx23885_api_cmd(dev
, CX2341X_ENC_MISC
, 2, 0, 3, 1);
1030 cx23885_api_cmd(dev
, CX2341X_ENC_MISC
, 2, 0, 4, 1);
1033 static int cx23885_initialize_codec(struct cx23885_dev
*dev
)
1039 dprintk(1, "%s()\n", __func__
);
1041 retval
= cx23885_api_cmd(dev
, CX2341X_ENC_PING_FW
, 0, 0); /* ping */
1043 dprintk(2, "%s() PING OK\n", __func__
);
1044 retval
= cx23885_load_firmware(dev
);
1046 printk(KERN_ERR
"%s() f/w load failed\n", __func__
);
1049 retval
= cx23885_find_mailbox(dev
);
1051 printk(KERN_ERR
"%s() mailbox < 0, error\n",
1055 dev
->cx23417_mailbox
= retval
;
1056 retval
= cx23885_api_cmd(dev
, CX2341X_ENC_PING_FW
, 0, 0);
1059 "ERROR: cx23417 firmware ping failed!\n");
1062 retval
= cx23885_api_cmd(dev
, CX2341X_ENC_GET_VERSION
, 0, 1,
1065 printk(KERN_ERR
"ERROR: cx23417 firmware get encoder :"
1066 "version failed!\n");
1069 dprintk(1, "cx23417 firmware version is 0x%08x\n", version
);
1073 cx23885_codec_settings(dev
);
1076 cx23885_api_cmd(dev
, CX2341X_ENC_SET_NUM_VSYNC_LINES
, 2, 0,
1077 CX23885_FIELD1_SAA7115
, CX23885_FIELD2_SAA7115
);
1078 cx23885_api_cmd(dev
, CX2341X_ENC_SET_PLACEHOLDER
, 12, 0,
1079 CX23885_CUSTOM_EXTENSION_USR_DATA
, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1082 /* Setup to capture VBI */
1083 data
[0] = 0x0001BD00;
1084 data
[1] = 1; /* frames per interrupt */
1085 data
[2] = 4; /* total bufs */
1086 data
[3] = 0x91559155; /* start codes */
1087 data
[4] = 0x206080C0; /* stop codes */
1088 data
[5] = 6; /* lines */
1089 data
[6] = 64; /* BPL */
1091 cx23885_api_cmd(dev
, CX2341X_ENC_SET_VBI_CONFIG
, 7, 0, data
[0], data
[1],
1092 data
[2], data
[3], data
[4], data
[5], data
[6]);
1094 for (i
= 2; i
<= 24; i
++) {
1097 valid
= ((i
>= 19) && (i
<= 21));
1098 cx23885_api_cmd(dev
, CX2341X_ENC_SET_VBI_LINE
, 5, 0, i
,
1100 cx23885_api_cmd(dev
, CX2341X_ENC_SET_VBI_LINE
, 5, 0,
1101 i
| 0x80000000, valid
, 0, 0, 0);
1104 cx23885_api_cmd(dev
, CX2341X_ENC_MUTE_AUDIO
, 1, 0, CX23885_UNMUTE
);
1107 /* initialize the video input */
1108 cx23885_api_cmd(dev
, CX2341X_ENC_INITIALIZE_INPUT
, 0, 0);
1111 /* Enable VIP style pixel invalidation so we work with scaled mode */
1112 mc417_memory_write(dev
, 2120, 0x00000080);
1114 /* start capturing to the host interface */
1115 cx23885_api_cmd(dev
, CX2341X_ENC_START_CAPTURE
, 2, 0,
1116 CX23885_MPEG_CAPTURE
, CX23885_RAW_BITS_NONE
);
1122 /* ------------------------------------------------------------------ */
1124 static int bb_buf_setup(struct videobuf_queue
*q
,
1125 unsigned int *count
, unsigned int *size
)
1127 struct cx23885_fh
*fh
= q
->priv_data
;
1129 fh
->dev
->ts1
.ts_packet_size
= mpeglinesize
;
1130 fh
->dev
->ts1
.ts_packet_count
= mpeglines
;
1132 *size
= fh
->dev
->ts1
.ts_packet_size
* fh
->dev
->ts1
.ts_packet_count
;
1138 static int bb_buf_prepare(struct videobuf_queue
*q
,
1139 struct videobuf_buffer
*vb
, enum v4l2_field field
)
1141 struct cx23885_fh
*fh
= q
->priv_data
;
1142 return cx23885_buf_prepare(q
, &fh
->dev
->ts1
,
1143 (struct cx23885_buffer
*)vb
,
1147 static void bb_buf_queue(struct videobuf_queue
*q
,
1148 struct videobuf_buffer
*vb
)
1150 struct cx23885_fh
*fh
= q
->priv_data
;
1151 cx23885_buf_queue(&fh
->dev
->ts1
, (struct cx23885_buffer
*)vb
);
1154 static void bb_buf_release(struct videobuf_queue
*q
,
1155 struct videobuf_buffer
*vb
)
1157 cx23885_free_buffer(q
, (struct cx23885_buffer
*)vb
);
1160 static struct videobuf_queue_ops cx23885_qops
= {
1161 .buf_setup
= bb_buf_setup
,
1162 .buf_prepare
= bb_buf_prepare
,
1163 .buf_queue
= bb_buf_queue
,
1164 .buf_release
= bb_buf_release
,
1167 /* ------------------------------------------------------------------ */
1169 static const u32
*ctrl_classes
[] = {
1174 static int cx23885_queryctrl(struct cx23885_dev
*dev
,
1175 struct v4l2_queryctrl
*qctrl
)
1177 qctrl
->id
= v4l2_ctrl_next(ctrl_classes
, qctrl
->id
);
1181 /* MPEG V4L2 controls */
1182 if (cx2341x_ctrl_query(&dev
->mpeg_params
, qctrl
))
1183 qctrl
->flags
|= V4L2_CTRL_FLAG_DISABLED
;
1188 static int cx23885_querymenu(struct cx23885_dev
*dev
,
1189 struct v4l2_querymenu
*qmenu
)
1191 struct v4l2_queryctrl qctrl
;
1193 qctrl
.id
= qmenu
->id
;
1194 cx23885_queryctrl(dev
, &qctrl
);
1195 return v4l2_ctrl_query_menu(qmenu
, &qctrl
,
1196 cx2341x_ctrl_get_menu(&dev
->mpeg_params
, qmenu
->id
));
1199 static int vidioc_s_std(struct file
*file
, void *priv
, v4l2_std_id
*id
)
1201 struct cx23885_fh
*fh
= file
->private_data
;
1202 struct cx23885_dev
*dev
= fh
->dev
;
1205 for (i
= 0; i
< ARRAY_SIZE(cx23885_tvnorms
); i
++)
1206 if (*id
& cx23885_tvnorms
[i
].id
)
1208 if (i
== ARRAY_SIZE(cx23885_tvnorms
))
1210 dev
->encodernorm
= cx23885_tvnorms
[i
];
1214 static int vidioc_enum_input(struct file
*file
, void *priv
,
1215 struct v4l2_input
*i
)
1217 struct cx23885_fh
*fh
= file
->private_data
;
1218 struct cx23885_dev
*dev
= fh
->dev
;
1219 struct cx23885_input
*input
;
1225 input
= &cx23885_boards
[dev
->board
].input
[i
->index
];
1227 if (input
->type
== 0)
1231 * strcpy(i->name, input->name); */
1232 strcpy(i
->name
, "unset");
1234 if (input
->type
== CX23885_VMUX_TELEVISION
||
1235 input
->type
== CX23885_VMUX_CABLE
)
1236 i
->type
= V4L2_INPUT_TYPE_TUNER
;
1238 i
->type
= V4L2_INPUT_TYPE_CAMERA
;
1240 for (n
= 0; n
< ARRAY_SIZE(cx23885_tvnorms
); n
++)
1241 i
->std
|= cx23885_tvnorms
[n
].id
;
1245 static int vidioc_g_input(struct file
*file
, void *priv
, unsigned int *i
)
1247 struct cx23885_fh
*fh
= file
->private_data
;
1248 struct cx23885_dev
*dev
= fh
->dev
;
1254 static int vidioc_s_input(struct file
*file
, void *priv
, unsigned int i
)
1262 static int vidioc_g_tuner(struct file
*file
, void *priv
,
1263 struct v4l2_tuner
*t
)
1265 struct cx23885_fh
*fh
= file
->private_data
;
1266 struct cx23885_dev
*dev
= fh
->dev
;
1268 if (UNSET
== dev
->tuner_type
)
1272 strcpy(t
->name
, "Television");
1273 call_all(dev
, tuner
, g_tuner
, t
);
1275 dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t
->type
);
1280 static int vidioc_s_tuner(struct file
*file
, void *priv
,
1281 struct v4l2_tuner
*t
)
1283 struct cx23885_fh
*fh
= file
->private_data
;
1284 struct cx23885_dev
*dev
= fh
->dev
;
1286 if (UNSET
== dev
->tuner_type
)
1289 /* Update the A/V core */
1290 call_all(dev
, tuner
, s_tuner
, t
);
1295 static int vidioc_g_frequency(struct file
*file
, void *priv
,
1296 struct v4l2_frequency
*f
)
1298 struct cx23885_fh
*fh
= file
->private_data
;
1299 struct cx23885_dev
*dev
= fh
->dev
;
1301 if (UNSET
== dev
->tuner_type
)
1303 f
->type
= V4L2_TUNER_ANALOG_TV
;
1304 f
->frequency
= dev
->freq
;
1306 call_all(dev
, tuner
, g_frequency
, f
);
1311 static int vidioc_s_frequency(struct file
*file
, void *priv
,
1312 struct v4l2_frequency
*f
)
1314 struct cx23885_fh
*fh
= file
->private_data
;
1315 struct cx23885_dev
*dev
= fh
->dev
;
1317 cx23885_api_cmd(fh
->dev
, CX2341X_ENC_STOP_CAPTURE
, 3, 0,
1318 CX23885_END_NOW
, CX23885_MPEG_CAPTURE
,
1319 CX23885_RAW_BITS_NONE
);
1321 dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1323 dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1325 if (UNSET
== dev
->tuner_type
)
1329 if (f
->type
!= V4L2_TUNER_ANALOG_TV
)
1331 dev
->freq
= f
->frequency
;
1333 call_all(dev
, tuner
, s_frequency
, f
);
1335 cx23885_initialize_codec(dev
);
1340 static int vidioc_s_ctrl(struct file
*file
, void *priv
,
1341 struct v4l2_control
*ctl
)
1343 struct cx23885_fh
*fh
= file
->private_data
;
1344 struct cx23885_dev
*dev
= fh
->dev
;
1346 /* Update the A/V core */
1347 call_all(dev
, core
, s_ctrl
, ctl
);
1351 static int vidioc_querycap(struct file
*file
, void *priv
,
1352 struct v4l2_capability
*cap
)
1354 struct cx23885_fh
*fh
= file
->private_data
;
1355 struct cx23885_dev
*dev
= fh
->dev
;
1356 struct cx23885_tsport
*tsport
= &dev
->ts1
;
1358 strlcpy(cap
->driver
, dev
->name
, sizeof(cap
->driver
));
1359 strlcpy(cap
->card
, cx23885_boards
[tsport
->dev
->board
].name
,
1361 sprintf(cap
->bus_info
, "PCI:%s", pci_name(dev
->pci
));
1363 V4L2_CAP_VIDEO_CAPTURE
|
1364 V4L2_CAP_READWRITE
|
1365 V4L2_CAP_STREAMING
|
1367 if (UNSET
!= dev
->tuner_type
)
1368 cap
->capabilities
|= V4L2_CAP_TUNER
;
1373 static int vidioc_enum_fmt_vid_cap(struct file
*file
, void *priv
,
1374 struct v4l2_fmtdesc
*f
)
1379 strlcpy(f
->description
, "MPEG", sizeof(f
->description
));
1380 f
->pixelformat
= V4L2_PIX_FMT_MPEG
;
1385 static int vidioc_g_fmt_vid_cap(struct file
*file
, void *priv
,
1386 struct v4l2_format
*f
)
1388 struct cx23885_fh
*fh
= file
->private_data
;
1389 struct cx23885_dev
*dev
= fh
->dev
;
1391 f
->fmt
.pix
.pixelformat
= V4L2_PIX_FMT_MPEG
;
1392 f
->fmt
.pix
.bytesperline
= 0;
1393 f
->fmt
.pix
.sizeimage
=
1394 dev
->ts1
.ts_packet_size
* dev
->ts1
.ts_packet_count
;
1395 f
->fmt
.pix
.colorspace
= 0;
1396 f
->fmt
.pix
.width
= dev
->ts1
.width
;
1397 f
->fmt
.pix
.height
= dev
->ts1
.height
;
1398 f
->fmt
.pix
.field
= fh
->mpegq
.field
;
1399 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1400 dev
->ts1
.width
, dev
->ts1
.height
, fh
->mpegq
.field
);
1404 static int vidioc_try_fmt_vid_cap(struct file
*file
, void *priv
,
1405 struct v4l2_format
*f
)
1407 struct cx23885_fh
*fh
= file
->private_data
;
1408 struct cx23885_dev
*dev
= fh
->dev
;
1410 f
->fmt
.pix
.pixelformat
= V4L2_PIX_FMT_MPEG
;
1411 f
->fmt
.pix
.bytesperline
= 0;
1412 f
->fmt
.pix
.sizeimage
=
1413 dev
->ts1
.ts_packet_size
* dev
->ts1
.ts_packet_count
;
1414 f
->fmt
.pix
.colorspace
= 0;
1415 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1416 dev
->ts1
.width
, dev
->ts1
.height
, fh
->mpegq
.field
);
1420 static int vidioc_s_fmt_vid_cap(struct file
*file
, void *priv
,
1421 struct v4l2_format
*f
)
1423 struct cx23885_fh
*fh
= file
->private_data
;
1424 struct cx23885_dev
*dev
= fh
->dev
;
1426 f
->fmt
.pix
.pixelformat
= V4L2_PIX_FMT_MPEG
;
1427 f
->fmt
.pix
.bytesperline
= 0;
1428 f
->fmt
.pix
.sizeimage
=
1429 dev
->ts1
.ts_packet_size
* dev
->ts1
.ts_packet_count
;
1430 f
->fmt
.pix
.colorspace
= 0;
1431 dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1432 f
->fmt
.pix
.width
, f
->fmt
.pix
.height
, f
->fmt
.pix
.field
);
1436 static int vidioc_reqbufs(struct file
*file
, void *priv
,
1437 struct v4l2_requestbuffers
*p
)
1439 struct cx23885_fh
*fh
= file
->private_data
;
1441 return videobuf_reqbufs(&fh
->mpegq
, p
);
1444 static int vidioc_querybuf(struct file
*file
, void *priv
,
1445 struct v4l2_buffer
*p
)
1447 struct cx23885_fh
*fh
= file
->private_data
;
1449 return videobuf_querybuf(&fh
->mpegq
, p
);
1452 static int vidioc_qbuf(struct file
*file
, void *priv
,
1453 struct v4l2_buffer
*p
)
1455 struct cx23885_fh
*fh
= file
->private_data
;
1457 return videobuf_qbuf(&fh
->mpegq
, p
);
1460 static int vidioc_dqbuf(struct file
*file
, void *priv
, struct v4l2_buffer
*b
)
1462 struct cx23885_fh
*fh
= priv
;
1464 return videobuf_dqbuf(&fh
->mpegq
, b
, file
->f_flags
& O_NONBLOCK
);
1468 static int vidioc_streamon(struct file
*file
, void *priv
,
1469 enum v4l2_buf_type i
)
1471 struct cx23885_fh
*fh
= file
->private_data
;
1473 return videobuf_streamon(&fh
->mpegq
);
1476 static int vidioc_streamoff(struct file
*file
, void *priv
, enum v4l2_buf_type i
)
1478 struct cx23885_fh
*fh
= file
->private_data
;
1480 return videobuf_streamoff(&fh
->mpegq
);
1483 static int vidioc_g_ext_ctrls(struct file
*file
, void *priv
,
1484 struct v4l2_ext_controls
*f
)
1486 struct cx23885_fh
*fh
= priv
;
1487 struct cx23885_dev
*dev
= fh
->dev
;
1489 if (f
->ctrl_class
!= V4L2_CTRL_CLASS_MPEG
)
1491 return cx2341x_ext_ctrls(&dev
->mpeg_params
, 0, f
, VIDIOC_G_EXT_CTRLS
);
1494 static int vidioc_s_ext_ctrls(struct file
*file
, void *priv
,
1495 struct v4l2_ext_controls
*f
)
1497 struct cx23885_fh
*fh
= priv
;
1498 struct cx23885_dev
*dev
= fh
->dev
;
1499 struct cx2341x_mpeg_params p
;
1502 if (f
->ctrl_class
!= V4L2_CTRL_CLASS_MPEG
)
1505 p
= dev
->mpeg_params
;
1506 err
= cx2341x_ext_ctrls(&p
, 0, f
, VIDIOC_S_EXT_CTRLS
);
1509 err
= cx2341x_update(dev
, cx23885_mbox_func
,
1510 &dev
->mpeg_params
, &p
);
1511 dev
->mpeg_params
= p
;
1516 static int vidioc_try_ext_ctrls(struct file
*file
, void *priv
,
1517 struct v4l2_ext_controls
*f
)
1519 struct cx23885_fh
*fh
= priv
;
1520 struct cx23885_dev
*dev
= fh
->dev
;
1521 struct cx2341x_mpeg_params p
;
1524 if (f
->ctrl_class
!= V4L2_CTRL_CLASS_MPEG
)
1527 p
= dev
->mpeg_params
;
1528 err
= cx2341x_ext_ctrls(&p
, 0, f
, VIDIOC_TRY_EXT_CTRLS
);
1532 static int vidioc_log_status(struct file
*file
, void *priv
)
1534 struct cx23885_fh
*fh
= priv
;
1535 struct cx23885_dev
*dev
= fh
->dev
;
1538 snprintf(name
, sizeof(name
), "%s/2", dev
->name
);
1540 "%s/2: ============ START LOG STATUS ============\n",
1542 call_all(dev
, core
, log_status
);
1543 cx2341x_log_status(&dev
->mpeg_params
, name
);
1545 "%s/2: ============= END LOG STATUS =============\n",
1550 static int vidioc_querymenu(struct file
*file
, void *priv
,
1551 struct v4l2_querymenu
*a
)
1553 struct cx23885_fh
*fh
= priv
;
1554 struct cx23885_dev
*dev
= fh
->dev
;
1556 return cx23885_querymenu(dev
, a
);
1559 static int vidioc_queryctrl(struct file
*file
, void *priv
,
1560 struct v4l2_queryctrl
*c
)
1562 struct cx23885_fh
*fh
= priv
;
1563 struct cx23885_dev
*dev
= fh
->dev
;
1565 return cx23885_queryctrl(dev
, c
);
1568 static int mpeg_open(struct file
*file
)
1570 struct cx23885_dev
*dev
= video_drvdata(file
);
1571 struct cx23885_fh
*fh
;
1573 dprintk(2, "%s()\n", __func__
);
1575 /* allocate + initialize per filehandle data */
1576 fh
= kzalloc(sizeof(*fh
), GFP_KERNEL
);
1580 file
->private_data
= fh
;
1583 videobuf_queue_sg_init(&fh
->mpegq
, &cx23885_qops
,
1584 &dev
->pci
->dev
, &dev
->ts1
.slock
,
1585 V4L2_BUF_TYPE_VIDEO_CAPTURE
,
1586 V4L2_FIELD_INTERLACED
,
1587 sizeof(struct cx23885_buffer
),
1592 static int mpeg_release(struct file
*file
)
1594 struct cx23885_fh
*fh
= file
->private_data
;
1595 struct cx23885_dev
*dev
= fh
->dev
;
1597 dprintk(2, "%s()\n", __func__
);
1599 /* FIXME: Review this crap */
1600 /* Shut device down on last close */
1601 if (atomic_cmpxchg(&fh
->v4l_reading
, 1, 0) == 1) {
1602 if (atomic_dec_return(&dev
->v4l_reader_count
) == 0) {
1603 /* stop mpeg capture */
1604 cx23885_api_cmd(fh
->dev
, CX2341X_ENC_STOP_CAPTURE
, 3, 0,
1605 CX23885_END_NOW
, CX23885_MPEG_CAPTURE
,
1606 CX23885_RAW_BITS_NONE
);
1609 cx23885_417_check_encoder(dev
);
1611 cx23885_cancel_buffers(&fh
->dev
->ts1
);
1615 if (fh
->mpegq
.streaming
)
1616 videobuf_streamoff(&fh
->mpegq
);
1617 if (fh
->mpegq
.reading
)
1618 videobuf_read_stop(&fh
->mpegq
);
1620 videobuf_mmap_free(&fh
->mpegq
);
1621 file
->private_data
= NULL
;
1627 static ssize_t
mpeg_read(struct file
*file
, char __user
*data
,
1628 size_t count
, loff_t
*ppos
)
1630 struct cx23885_fh
*fh
= file
->private_data
;
1631 struct cx23885_dev
*dev
= fh
->dev
;
1633 dprintk(2, "%s()\n", __func__
);
1635 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1636 /* Start mpeg encoder on first read. */
1637 if (atomic_cmpxchg(&fh
->v4l_reading
, 0, 1) == 0) {
1638 if (atomic_inc_return(&dev
->v4l_reader_count
) == 1) {
1639 if (cx23885_initialize_codec(dev
) < 0)
1644 return videobuf_read_stream(&fh
->mpegq
, data
, count
, ppos
, 0,
1645 file
->f_flags
& O_NONBLOCK
);
1648 static unsigned int mpeg_poll(struct file
*file
,
1649 struct poll_table_struct
*wait
)
1651 struct cx23885_fh
*fh
= file
->private_data
;
1652 struct cx23885_dev
*dev
= fh
->dev
;
1654 dprintk(2, "%s\n", __func__
);
1656 return videobuf_poll_stream(file
, &fh
->mpegq
, wait
);
1659 static int mpeg_mmap(struct file
*file
, struct vm_area_struct
*vma
)
1661 struct cx23885_fh
*fh
= file
->private_data
;
1662 struct cx23885_dev
*dev
= fh
->dev
;
1664 dprintk(2, "%s()\n", __func__
);
1666 return videobuf_mmap_mapper(&fh
->mpegq
, vma
);
1669 static struct v4l2_file_operations mpeg_fops
= {
1670 .owner
= THIS_MODULE
,
1672 .release
= mpeg_release
,
1676 .ioctl
= video_ioctl2
,
1679 static const struct v4l2_ioctl_ops mpeg_ioctl_ops
= {
1680 .vidioc_s_std
= vidioc_s_std
,
1681 .vidioc_enum_input
= vidioc_enum_input
,
1682 .vidioc_g_input
= vidioc_g_input
,
1683 .vidioc_s_input
= vidioc_s_input
,
1684 .vidioc_g_tuner
= vidioc_g_tuner
,
1685 .vidioc_s_tuner
= vidioc_s_tuner
,
1686 .vidioc_g_frequency
= vidioc_g_frequency
,
1687 .vidioc_s_frequency
= vidioc_s_frequency
,
1688 .vidioc_s_ctrl
= vidioc_s_ctrl
,
1689 .vidioc_querycap
= vidioc_querycap
,
1690 .vidioc_enum_fmt_vid_cap
= vidioc_enum_fmt_vid_cap
,
1691 .vidioc_g_fmt_vid_cap
= vidioc_g_fmt_vid_cap
,
1692 .vidioc_try_fmt_vid_cap
= vidioc_try_fmt_vid_cap
,
1693 .vidioc_s_fmt_vid_cap
= vidioc_s_fmt_vid_cap
,
1694 .vidioc_reqbufs
= vidioc_reqbufs
,
1695 .vidioc_querybuf
= vidioc_querybuf
,
1696 .vidioc_qbuf
= vidioc_qbuf
,
1697 .vidioc_dqbuf
= vidioc_dqbuf
,
1698 .vidioc_streamon
= vidioc_streamon
,
1699 .vidioc_streamoff
= vidioc_streamoff
,
1700 .vidioc_g_ext_ctrls
= vidioc_g_ext_ctrls
,
1701 .vidioc_s_ext_ctrls
= vidioc_s_ext_ctrls
,
1702 .vidioc_try_ext_ctrls
= vidioc_try_ext_ctrls
,
1703 .vidioc_log_status
= vidioc_log_status
,
1704 .vidioc_querymenu
= vidioc_querymenu
,
1705 .vidioc_queryctrl
= vidioc_queryctrl
,
1706 .vidioc_g_chip_ident
= cx23885_g_chip_ident
,
1707 #ifdef CONFIG_VIDEO_ADV_DEBUG
1708 .vidioc_g_register
= cx23885_g_register
,
1709 .vidioc_s_register
= cx23885_s_register
,
1713 static struct video_device cx23885_mpeg_template
= {
1716 .ioctl_ops
= &mpeg_ioctl_ops
,
1717 .tvnorms
= CX23885_NORMS
,
1718 .current_norm
= V4L2_STD_NTSC_M
,
1721 void cx23885_417_unregister(struct cx23885_dev
*dev
)
1723 dprintk(1, "%s()\n", __func__
);
1725 if (dev
->v4l_device
) {
1726 if (video_is_registered(dev
->v4l_device
))
1727 video_unregister_device(dev
->v4l_device
);
1729 video_device_release(dev
->v4l_device
);
1730 dev
->v4l_device
= NULL
;
1734 static struct video_device
*cx23885_video_dev_alloc(
1735 struct cx23885_tsport
*tsport
,
1736 struct pci_dev
*pci
,
1737 struct video_device
*template,
1740 struct video_device
*vfd
;
1741 struct cx23885_dev
*dev
= tsport
->dev
;
1743 dprintk(1, "%s()\n", __func__
);
1745 vfd
= video_device_alloc();
1749 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s %s (%s)", dev
->name
,
1750 type
, cx23885_boards
[tsport
->dev
->board
].name
);
1751 vfd
->parent
= &pci
->dev
;
1752 vfd
->release
= video_device_release
;
1756 int cx23885_417_register(struct cx23885_dev
*dev
)
1758 /* FIXME: Port1 hardcoded here */
1760 struct cx23885_tsport
*tsport
= &dev
->ts1
;
1762 dprintk(1, "%s()\n", __func__
);
1764 if (cx23885_boards
[dev
->board
].portb
!= CX23885_MPEG_ENCODER
)
1767 /* Set default TV standard */
1768 dev
->encodernorm
= cx23885_tvnorms
[0];
1770 if (dev
->encodernorm
.id
& V4L2_STD_525_60
)
1771 tsport
->height
= 480;
1773 tsport
->height
= 576;
1775 tsport
->width
= 720;
1776 cx2341x_fill_defaults(&dev
->mpeg_params
);
1778 dev
->mpeg_params
.port
= CX2341X_PORT_SERIAL
;
1780 /* Allocate and initialize V4L video device */
1781 dev
->v4l_device
= cx23885_video_dev_alloc(tsport
,
1782 dev
->pci
, &cx23885_mpeg_template
, "mpeg");
1783 video_set_drvdata(dev
->v4l_device
, dev
);
1784 err
= video_register_device(dev
->v4l_device
,
1785 VFL_TYPE_GRABBER
, -1);
1787 printk(KERN_INFO
"%s: can't register mpeg device\n", dev
->name
);
1791 printk(KERN_INFO
"%s: registered device %s [mpeg]\n",
1792 dev
->name
, video_device_node_name(dev
->v4l_device
));