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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / media / video / ov6650.c
blob2e1680631f0fe4913f204bd07da42cc4e7031e43
1 /*
2 * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32
33 #include <media/soc_camera.h>
34 #include <media/v4l2-chip-ident.h>
35
36
37 /* Register definitions */
38 #define REG_GAIN 0x00 /* range 00 - 3F */
39 #define REG_BLUE 0x01
40 #define REG_RED 0x02
41 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
42 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
43
44 #define REG_BRT 0x06
45
46 #define REG_PIDH 0x0a
47 #define REG_PIDL 0x0b
48
49 #define REG_AECH 0x10
50 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
51 /* [7:6] Input system clock (MHz)*/
52 /* 00=8, 01=12, 10=16, 11=24 */
53 /* [5:0]: Internal Clock Pre-Scaler */
54 #define REG_COMA 0x12 /* [7] Reset */
55 #define REG_COMB 0x13
56 #define REG_COMC 0x14
57 #define REG_COMD 0x15
58 #define REG_COML 0x16
59 #define REG_HSTRT 0x17
60 #define REG_HSTOP 0x18
61 #define REG_VSTRT 0x19
62 #define REG_VSTOP 0x1a
63 #define REG_PSHFT 0x1b
64 #define REG_MIDH 0x1c
65 #define REG_MIDL 0x1d
66 #define REG_HSYNS 0x1e
67 #define REG_HSYNE 0x1f
68 #define REG_COME 0x20
69 #define REG_YOFF 0x21
70 #define REG_UOFF 0x22
71 #define REG_VOFF 0x23
72 #define REG_AEW 0x24
73 #define REG_AEB 0x25
74 #define REG_COMF 0x26
75 #define REG_COMG 0x27
76 #define REG_COMH 0x28
77 #define REG_COMI 0x29
78
79 #define REG_FRARL 0x2b
80 #define REG_COMJ 0x2c
81 #define REG_COMK 0x2d
82 #define REG_AVGY 0x2e
83 #define REG_REF0 0x2f
84 #define REG_REF1 0x30
85 #define REG_REF2 0x31
86 #define REG_FRAJH 0x32
87 #define REG_FRAJL 0x33
88 #define REG_FACT 0x34
89 #define REG_L1AEC 0x35
90 #define REG_AVGU 0x36
91 #define REG_AVGV 0x37
92
93 #define REG_SPCB 0x60
94 #define REG_SPCC 0x61
95 #define REG_GAM1 0x62
96 #define REG_GAM2 0x63
97 #define REG_GAM3 0x64
98 #define REG_SPCD 0x65
99
100 #define REG_SPCE 0x68
101 #define REG_ADCL 0x69
102
103 #define REG_RMCO 0x6c
104 #define REG_GMCO 0x6d
105 #define REG_BMCO 0x6e
106
107
108 /* Register bits, values, etc. */
109 #define OV6650_PIDH 0x66 /* high byte of product ID number */
110 #define OV6650_PIDL 0x50 /* low byte of product ID number */
111 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
112 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
113
114 #define DEF_GAIN 0x00
115 #define DEF_BLUE 0x80
116 #define DEF_RED 0x80
117
118 #define SAT_SHIFT 4
119 #define SAT_MASK (0xf << SAT_SHIFT)
120 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
121
122 #define HUE_EN BIT(5)
123 #define HUE_MASK 0x1f
124 #define DEF_HUE 0x10
125 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
126
127 #define DEF_AECH 0x4D
128
129 #define CLKRC_6MHz 0x00
130 #define CLKRC_12MHz 0x40
131 #define CLKRC_16MHz 0x80
132 #define CLKRC_24MHz 0xc0
133 #define CLKRC_DIV_MASK 0x3f
134 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
135
136 #define COMA_RESET BIT(7)
137 #define COMA_QCIF BIT(5)
138 #define COMA_RAW_RGB BIT(4)
139 #define COMA_RGB BIT(3)
140 #define COMA_BW BIT(2)
141 #define COMA_WORD_SWAP BIT(1)
142 #define COMA_BYTE_SWAP BIT(0)
143 #define DEF_COMA 0x00
144
145 #define COMB_FLIP_V BIT(7)
146 #define COMB_FLIP_H BIT(5)
147 #define COMB_BAND_FILTER BIT(4)
148 #define COMB_AWB BIT(2)
149 #define COMB_AGC BIT(1)
150 #define COMB_AEC BIT(0)
151 #define DEF_COMB 0x5f
152
153 #define COML_ONE_CHANNEL BIT(7)
154
155 #define DEF_HSTRT 0x24
156 #define DEF_HSTOP 0xd4
157 #define DEF_VSTRT 0x04
158 #define DEF_VSTOP 0x94
159
160 #define COMF_HREF_LOW BIT(4)
161
162 #define COMJ_PCLK_RISING BIT(4)
163 #define COMJ_VSYNC_HIGH BIT(0)
164
165 /* supported resolutions */
166 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
167 #define W_CIF (W_QCIF << 1)
168 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
169 #define H_CIF (H_QCIF << 1)
170
171 #define FRAME_RATE_MAX 30
172
173
174 struct ov6650_reg {
175 u8 reg;
176 u8 val;
177 };
178
179 struct ov6650 {
180 struct v4l2_subdev subdev;
181
182 int gain;
183 int blue;
184 int red;
185 int saturation;
186 int hue;
187 int brightness;
188 int exposure;
189 int gamma;
190 int aec;
191 bool vflip;
192 bool hflip;
193 bool awb;
194 bool agc;
195 bool half_scale; /* scale down output by 2 */
196 struct v4l2_rect rect; /* sensor cropping window */
197 unsigned long pclk_limit; /* from host */
198 unsigned long pclk_max; /* from resolution and format */
199 struct v4l2_fract tpf; /* as requested with s_parm */
200 enum v4l2_mbus_pixelcode code;
201 enum v4l2_colorspace colorspace;
202 };
203
204
205 static enum v4l2_mbus_pixelcode ov6650_codes[] = {
206 V4L2_MBUS_FMT_YUYV8_2X8,
207 V4L2_MBUS_FMT_UYVY8_2X8,
208 V4L2_MBUS_FMT_YVYU8_2X8,
209 V4L2_MBUS_FMT_VYUY8_2X8,
210 V4L2_MBUS_FMT_SBGGR8_1X8,
211 V4L2_MBUS_FMT_Y8_1X8,
212 };
213
214 static const struct v4l2_queryctrl ov6650_controls[] = {
215 {
216 .id = V4L2_CID_AUTOGAIN,
217 .type = V4L2_CTRL_TYPE_BOOLEAN,
218 .name = "AGC",
219 .minimum = 0,
220 .maximum = 1,
221 .step = 1,
222 .default_value = 1,
223 },
224 {
225 .id = V4L2_CID_GAIN,
226 .type = V4L2_CTRL_TYPE_INTEGER,
227 .name = "Gain",
228 .minimum = 0,
229 .maximum = 0x3f,
230 .step = 1,
231 .default_value = DEF_GAIN,
232 },
233 {
234 .id = V4L2_CID_AUTO_WHITE_BALANCE,
235 .type = V4L2_CTRL_TYPE_BOOLEAN,
236 .name = "AWB",
237 .minimum = 0,
238 .maximum = 1,
239 .step = 1,
240 .default_value = 1,
241 },
242 {
243 .id = V4L2_CID_BLUE_BALANCE,
244 .type = V4L2_CTRL_TYPE_INTEGER,
245 .name = "Blue",
246 .minimum = 0,
247 .maximum = 0xff,
248 .step = 1,
249 .default_value = DEF_BLUE,
250 },
251 {
252 .id = V4L2_CID_RED_BALANCE,
253 .type = V4L2_CTRL_TYPE_INTEGER,
254 .name = "Red",
255 .minimum = 0,
256 .maximum = 0xff,
257 .step = 1,
258 .default_value = DEF_RED,
259 },
260 {
261 .id = V4L2_CID_SATURATION,
262 .type = V4L2_CTRL_TYPE_INTEGER,
263 .name = "Saturation",
264 .minimum = 0,
265 .maximum = 0xf,
266 .step = 1,
267 .default_value = 0x8,
268 },
269 {
270 .id = V4L2_CID_HUE,
271 .type = V4L2_CTRL_TYPE_INTEGER,
272 .name = "Hue",
273 .minimum = 0,
274 .maximum = HUE_MASK,
275 .step = 1,
276 .default_value = DEF_HUE,
277 },
278 {
279 .id = V4L2_CID_BRIGHTNESS,
280 .type = V4L2_CTRL_TYPE_INTEGER,
281 .name = "Brightness",
282 .minimum = 0,
283 .maximum = 0xff,
284 .step = 1,
285 .default_value = 0x80,
286 },
287 {
288 .id = V4L2_CID_EXPOSURE_AUTO,
289 .type = V4L2_CTRL_TYPE_INTEGER,
290 .name = "AEC",
291 .minimum = 0,
292 .maximum = 3,
293 .step = 1,
294 .default_value = 0,
295 },
296 {
297 .id = V4L2_CID_EXPOSURE,
298 .type = V4L2_CTRL_TYPE_INTEGER,
299 .name = "Exposure",
300 .minimum = 0,
301 .maximum = 0xff,
302 .step = 1,
303 .default_value = DEF_AECH,
304 },
305 {
306 .id = V4L2_CID_GAMMA,
307 .type = V4L2_CTRL_TYPE_INTEGER,
308 .name = "Gamma",
309 .minimum = 0,
310 .maximum = 0xff,
311 .step = 1,
312 .default_value = 0x12,
313 },
314 {
315 .id = V4L2_CID_VFLIP,
316 .type = V4L2_CTRL_TYPE_BOOLEAN,
317 .name = "Flip Vertically",
318 .minimum = 0,
319 .maximum = 1,
320 .step = 1,
321 .default_value = 0,
322 },
323 {
324 .id = V4L2_CID_HFLIP,
325 .type = V4L2_CTRL_TYPE_BOOLEAN,
326 .name = "Flip Horizontally",
327 .minimum = 0,
328 .maximum = 1,
329 .step = 1,
330 .default_value = 0,
331 },
332 };
333
334 /* read a register */
335 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
336 {
337 int ret;
338 u8 data = reg;
339 struct i2c_msg msg = {
340 .addr = client->addr,
341 .flags = 0,
342 .len = 1,
343 .buf = &data,
344 };
345
346 ret = i2c_transfer(client->adapter, &msg, 1);
347 if (ret < 0)
348 goto err;
349
350 msg.flags = I2C_M_RD;
351 ret = i2c_transfer(client->adapter, &msg, 1);
352 if (ret < 0)
353 goto err;
354
355 *val = data;
356 return 0;
357
358 err:
359 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
360 return ret;
361 }
362
363 /* write a register */
364 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
365 {
366 int ret;
367 unsigned char data[2] = { reg, val };
368 struct i2c_msg msg = {
369 .addr = client->addr,
370 .flags = 0,
371 .len = 2,
372 .buf = data,
373 };
374
375 ret = i2c_transfer(client->adapter, &msg, 1);
376 udelay(100);
377
378 if (ret < 0) {
379 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
380 return ret;
381 }
382 return 0;
383 }
384
385
386 /* Read a register, alter its bits, write it back */
387 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
388 {
389 u8 val;
390 int ret;
391
392 ret = ov6650_reg_read(client, reg, &val);
393 if (ret) {
394 dev_err(&client->dev,
395 "[Read]-Modify-Write of register 0x%02x failed!\n",
396 reg);
397 return ret;
398 }
399
400 val &= ~mask;
401 val |= set;
402
403 ret = ov6650_reg_write(client, reg, val);
404 if (ret)
405 dev_err(&client->dev,
406 "Read-Modify-[Write] of register 0x%02x failed!\n",
407 reg);
408
409 return ret;
410 }
411
412 static struct ov6650 *to_ov6650(const struct i2c_client *client)
413 {
414 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
415 }
416
417 /* Start/Stop streaming from the device */
418 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
419 {
420 return 0;
421 }
422
423 /* Alter bus settings on camera side */
424 static int ov6650_set_bus_param(struct soc_camera_device *icd,
425 unsigned long flags)
426 {
427 struct soc_camera_link *icl = to_soc_camera_link(icd);
428 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
429 int ret;
430
431 flags = soc_camera_apply_sensor_flags(icl, flags);
432
433 if (flags & SOCAM_PCLK_SAMPLE_RISING)
434 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
435 else
436 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
437 if (ret)
438 return ret;
439
440 if (flags & SOCAM_HSYNC_ACTIVE_LOW)
441 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
442 else
443 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
444 if (ret)
445 return ret;
446
447 if (flags & SOCAM_VSYNC_ACTIVE_HIGH)
448 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
449 else
450 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
451
452 return ret;
453 }
454
455 /* Request bus settings on camera side */
456 static unsigned long ov6650_query_bus_param(struct soc_camera_device *icd)
457 {
458 struct soc_camera_link *icl = to_soc_camera_link(icd);
459
460 unsigned long flags = SOCAM_MASTER |
461 SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING |
462 SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_LOW |
463 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_LOW |
464 SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8;
465
466 return soc_camera_apply_sensor_flags(icl, flags);
467 }
468
469 /* Get status of additional camera capabilities */
470 static int ov6650_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
471 {
472 struct i2c_client *client = v4l2_get_subdevdata(sd);
473 struct ov6650 *priv = to_ov6650(client);
474 uint8_t reg;
475 int ret = 0;
476
477 switch (ctrl->id) {
478 case V4L2_CID_AUTOGAIN:
479 ctrl->value = priv->agc;
480 break;
481 case V4L2_CID_GAIN:
482 if (priv->agc) {
483 ret = ov6650_reg_read(client, REG_GAIN, &reg);
484 ctrl->value = reg;
485 } else {
486 ctrl->value = priv->gain;
487 }
488 break;
489 case V4L2_CID_AUTO_WHITE_BALANCE:
490 ctrl->value = priv->awb;
491 break;
492 case V4L2_CID_BLUE_BALANCE:
493 if (priv->awb) {
494 ret = ov6650_reg_read(client, REG_BLUE, &reg);
495 ctrl->value = reg;
496 } else {
497 ctrl->value = priv->blue;
498 }
499 break;
500 case V4L2_CID_RED_BALANCE:
501 if (priv->awb) {
502 ret = ov6650_reg_read(client, REG_RED, &reg);
503 ctrl->value = reg;
504 } else {
505 ctrl->value = priv->red;
506 }
507 break;
508 case V4L2_CID_SATURATION:
509 ctrl->value = priv->saturation;
510 break;
511 case V4L2_CID_HUE:
512 ctrl->value = priv->hue;
513 break;
514 case V4L2_CID_BRIGHTNESS:
515 ctrl->value = priv->brightness;
516 break;
517 case V4L2_CID_EXPOSURE_AUTO:
518 ctrl->value = priv->aec;
519 break;
520 case V4L2_CID_EXPOSURE:
521 if (priv->aec) {
522 ret = ov6650_reg_read(client, REG_AECH, &reg);
523 ctrl->value = reg;
524 } else {
525 ctrl->value = priv->exposure;
526 }
527 break;
528 case V4L2_CID_GAMMA:
529 ctrl->value = priv->gamma;
530 break;
531 case V4L2_CID_VFLIP:
532 ctrl->value = priv->vflip;
533 break;
534 case V4L2_CID_HFLIP:
535 ctrl->value = priv->hflip;
536 break;
537 }
538 return ret;
539 }
540
541 /* Set status of additional camera capabilities */
542 static int ov6650_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
543 {
544 struct i2c_client *client = v4l2_get_subdevdata(sd);
545 struct ov6650 *priv = to_ov6650(client);
546 int ret = 0;
547
548 switch (ctrl->id) {
549 case V4L2_CID_AUTOGAIN:
550 ret = ov6650_reg_rmw(client, REG_COMB,
551 ctrl->value ? COMB_AGC : 0, COMB_AGC);
552 if (!ret)
553 priv->agc = ctrl->value;
554 break;
555 case V4L2_CID_GAIN:
556 ret = ov6650_reg_write(client, REG_GAIN, ctrl->value);
557 if (!ret)
558 priv->gain = ctrl->value;
559 break;
560 case V4L2_CID_AUTO_WHITE_BALANCE:
561 ret = ov6650_reg_rmw(client, REG_COMB,
562 ctrl->value ? COMB_AWB : 0, COMB_AWB);
563 if (!ret)
564 priv->awb = ctrl->value;
565 break;
566 case V4L2_CID_BLUE_BALANCE:
567 ret = ov6650_reg_write(client, REG_BLUE, ctrl->value);
568 if (!ret)
569 priv->blue = ctrl->value;
570 break;
571 case V4L2_CID_RED_BALANCE:
572 ret = ov6650_reg_write(client, REG_RED, ctrl->value);
573 if (!ret)
574 priv->red = ctrl->value;
575 break;
576 case V4L2_CID_SATURATION:
577 ret = ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->value),
578 SAT_MASK);
579 if (!ret)
580 priv->saturation = ctrl->value;
581 break;
582 case V4L2_CID_HUE:
583 ret = ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->value),
584 HUE_MASK);
585 if (!ret)
586 priv->hue = ctrl->value;
587 break;
588 case V4L2_CID_BRIGHTNESS:
589 ret = ov6650_reg_write(client, REG_BRT, ctrl->value);
590 if (!ret)
591 priv->brightness = ctrl->value;
592 break;
593 case V4L2_CID_EXPOSURE_AUTO:
594 switch (ctrl->value) {
595 case V4L2_EXPOSURE_AUTO:
596 ret = ov6650_reg_rmw(client, REG_COMB, COMB_AEC, 0);
597 break;
598 default:
599 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_AEC);
600 break;
601 }
602 if (!ret)
603 priv->aec = ctrl->value;
604 break;
605 case V4L2_CID_EXPOSURE:
606 ret = ov6650_reg_write(client, REG_AECH, ctrl->value);
607 if (!ret)
608 priv->exposure = ctrl->value;
609 break;
610 case V4L2_CID_GAMMA:
611 ret = ov6650_reg_write(client, REG_GAM1, ctrl->value);
612 if (!ret)
613 priv->gamma = ctrl->value;
614 break;
615 case V4L2_CID_VFLIP:
616 ret = ov6650_reg_rmw(client, REG_COMB,
617 ctrl->value ? COMB_FLIP_V : 0, COMB_FLIP_V);
618 if (!ret)
619 priv->vflip = ctrl->value;
620 break;
621 case V4L2_CID_HFLIP:
622 ret = ov6650_reg_rmw(client, REG_COMB,
623 ctrl->value ? COMB_FLIP_H : 0, COMB_FLIP_H);
624 if (!ret)
625 priv->hflip = ctrl->value;
626 break;
627 }
628
629 return ret;
630 }
631
632 /* Get chip identification */
633 static int ov6650_g_chip_ident(struct v4l2_subdev *sd,
634 struct v4l2_dbg_chip_ident *id)
635 {
636 id->ident = V4L2_IDENT_OV6650;
637 id->revision = 0;
638
639 return 0;
640 }
641
642 #ifdef CONFIG_VIDEO_ADV_DEBUG
643 static int ov6650_get_register(struct v4l2_subdev *sd,
644 struct v4l2_dbg_register *reg)
645 {
646 struct i2c_client *client = v4l2_get_subdevdata(sd);
647 int ret;
648 u8 val;
649
650 if (reg->reg & ~0xff)
651 return -EINVAL;
652
653 reg->size = 1;
654
655 ret = ov6650_reg_read(client, reg->reg, &val);
656 if (!ret)
657 reg->val = (__u64)val;
658
659 return ret;
660 }
661
662 static int ov6650_set_register(struct v4l2_subdev *sd,
663 struct v4l2_dbg_register *reg)
664 {
665 struct i2c_client *client = v4l2_get_subdevdata(sd);
666
667 if (reg->reg & ~0xff || reg->val & ~0xff)
668 return -EINVAL;
669
670 return ov6650_reg_write(client, reg->reg, reg->val);
671 }
672 #endif
673
674 static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
675 {
676 struct i2c_client *client = v4l2_get_subdevdata(sd);
677 struct ov6650 *priv = to_ov6650(client);
678
679 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
680 a->c = priv->rect;
681
682 return 0;
683 }
684
685 static int ov6650_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
686 {
687 struct i2c_client *client = v4l2_get_subdevdata(sd);
688 struct ov6650 *priv = to_ov6650(client);
689 struct v4l2_rect *rect = &a->c;
690 int ret;
691
692 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
693 return -EINVAL;
694
695 rect->left = ALIGN(rect->left, 2);
696 rect->width = ALIGN(rect->width, 2);
697 rect->top = ALIGN(rect->top, 2);
698 rect->height = ALIGN(rect->height, 2);
699 soc_camera_limit_side(&rect->left, &rect->width,
700 DEF_HSTRT << 1, 2, W_CIF);
701 soc_camera_limit_side(&rect->top, &rect->height,
702 DEF_VSTRT << 1, 2, H_CIF);
703
704 ret = ov6650_reg_write(client, REG_HSTRT, rect->left >> 1);
705 if (!ret) {
706 priv->rect.left = rect->left;
707 ret = ov6650_reg_write(client, REG_HSTOP,
708 (rect->left + rect->width) >> 1);
709 }
710 if (!ret) {
711 priv->rect.width = rect->width;
712 ret = ov6650_reg_write(client, REG_VSTRT, rect->top >> 1);
713 }
714 if (!ret) {
715 priv->rect.top = rect->top;
716 ret = ov6650_reg_write(client, REG_VSTOP,
717 (rect->top + rect->height) >> 1);
718 }
719 if (!ret)
720 priv->rect.height = rect->height;
721
722 return ret;
723 }
724
725 static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
726 {
727 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
728 return -EINVAL;
729
730 a->bounds.left = DEF_HSTRT << 1;
731 a->bounds.top = DEF_VSTRT << 1;
732 a->bounds.width = W_CIF;
733 a->bounds.height = H_CIF;
734 a->defrect = a->bounds;
735 a->pixelaspect.numerator = 1;
736 a->pixelaspect.denominator = 1;
737
738 return 0;
739 }
740
741 static int ov6650_g_fmt(struct v4l2_subdev *sd,
742 struct v4l2_mbus_framefmt *mf)
743 {
744 struct i2c_client *client = v4l2_get_subdevdata(sd);
745 struct ov6650 *priv = to_ov6650(client);
746
747 mf->width = priv->rect.width >> priv->half_scale;
748 mf->height = priv->rect.height >> priv->half_scale;
749 mf->code = priv->code;
750 mf->colorspace = priv->colorspace;
751 mf->field = V4L2_FIELD_NONE;
752
753 return 0;
754 }
755
756 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
757 {
758 return width > rect->width >> 1 || height > rect->height >> 1;
759 }
760
761 static u8 to_clkrc(struct v4l2_fract *timeperframe,
762 unsigned long pclk_limit, unsigned long pclk_max)
763 {
764 unsigned long pclk;
765
766 if (timeperframe->numerator && timeperframe->denominator)
767 pclk = pclk_max * timeperframe->denominator /
768 (FRAME_RATE_MAX * timeperframe->numerator);
769 else
770 pclk = pclk_max;
771
772 if (pclk_limit && pclk_limit < pclk)
773 pclk = pclk_limit;
774
775 return (pclk_max - 1) / pclk;
776 }
777
778 /* set the format we will capture in */
779 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
780 {
781 struct i2c_client *client = v4l2_get_subdevdata(sd);
782 struct soc_camera_device *icd = client->dev.platform_data;
783 struct soc_camera_sense *sense = icd->sense;
784 struct ov6650 *priv = to_ov6650(client);
785 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
786 struct v4l2_crop a = {
787 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
788 .c = {
789 .left = priv->rect.left + (priv->rect.width >> 1) -
790 (mf->width >> (1 - half_scale)),
791 .top = priv->rect.top + (priv->rect.height >> 1) -
792 (mf->height >> (1 - half_scale)),
793 .width = mf->width << half_scale,
794 .height = mf->height << half_scale,
795 },
796 };
797 enum v4l2_mbus_pixelcode code = mf->code;
798 unsigned long mclk, pclk;
799 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
800 int ret;
801
802 /* select color matrix configuration for given color encoding */
803 switch (code) {
804 case V4L2_MBUS_FMT_Y8_1X8:
805 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
806 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
807 coma_set |= COMA_BW;
808 break;
809 case V4L2_MBUS_FMT_YUYV8_2X8:
810 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
811 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
812 coma_set |= COMA_WORD_SWAP;
813 break;
814 case V4L2_MBUS_FMT_YVYU8_2X8:
815 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
816 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
817 COMA_BYTE_SWAP;
818 break;
819 case V4L2_MBUS_FMT_UYVY8_2X8:
820 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
821 if (half_scale) {
822 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
823 coma_set |= COMA_BYTE_SWAP;
824 } else {
825 coma_mask |= COMA_RGB | COMA_BW;
826 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
827 }
828 break;
829 case V4L2_MBUS_FMT_VYUY8_2X8:
830 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
831 if (half_scale) {
832 coma_mask |= COMA_RGB | COMA_BW;
833 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
834 } else {
835 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
836 coma_set |= COMA_BYTE_SWAP;
837 }
838 break;
839 case V4L2_MBUS_FMT_SBGGR8_1X8:
840 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
841 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
842 coma_set |= COMA_RAW_RGB | COMA_RGB;
843 break;
844 default:
845 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
846 return -EINVAL;
847 }
848 priv->code = code;
849
850 if (code == V4L2_MBUS_FMT_Y8_1X8 ||
851 code == V4L2_MBUS_FMT_SBGGR8_1X8) {
852 coml_mask = COML_ONE_CHANNEL;
853 coml_set = 0;
854 priv->pclk_max = 4000000;
855 } else {
856 coml_mask = 0;
857 coml_set = COML_ONE_CHANNEL;
858 priv->pclk_max = 8000000;
859 }
860
861 if (code == V4L2_MBUS_FMT_SBGGR8_1X8)
862 priv->colorspace = V4L2_COLORSPACE_SRGB;
863 else if (code != 0)
864 priv->colorspace = V4L2_COLORSPACE_JPEG;
865
866 if (half_scale) {
867 dev_dbg(&client->dev, "max resolution: QCIF\n");
868 coma_set |= COMA_QCIF;
869 priv->pclk_max /= 2;
870 } else {
871 dev_dbg(&client->dev, "max resolution: CIF\n");
872 coma_mask |= COMA_QCIF;
873 }
874 priv->half_scale = half_scale;
875
876 if (sense) {
877 if (sense->master_clock == 8000000) {
878 dev_dbg(&client->dev, "8MHz input clock\n");
879 clkrc = CLKRC_6MHz;
880 } else if (sense->master_clock == 12000000) {
881 dev_dbg(&client->dev, "12MHz input clock\n");
882 clkrc = CLKRC_12MHz;
883 } else if (sense->master_clock == 16000000) {
884 dev_dbg(&client->dev, "16MHz input clock\n");
885 clkrc = CLKRC_16MHz;
886 } else if (sense->master_clock == 24000000) {
887 dev_dbg(&client->dev, "24MHz input clock\n");
888 clkrc = CLKRC_24MHz;
889 } else {
890 dev_err(&client->dev,
891 "unspported input clock, check platform data\n");
892 return -EINVAL;
893 }
894 mclk = sense->master_clock;
895 priv->pclk_limit = sense->pixel_clock_max;
896 } else {
897 clkrc = CLKRC_24MHz;
898 mclk = 24000000;
899 priv->pclk_limit = 0;
900 dev_dbg(&client->dev, "using default 24MHz input clock\n");
901 }
902
903 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
904
905 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
906 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
907 mclk / pclk, 10 * mclk % pclk / pclk);
908
909 ret = ov6650_s_crop(sd, &a);
910 if (!ret)
911 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
912 if (!ret)
913 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
914 if (!ret)
915 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
916
917 if (!ret) {
918 mf->colorspace = priv->colorspace;
919 mf->width = priv->rect.width >> half_scale;
920 mf->height = priv->rect.height >> half_scale;
921 }
922
923 return ret;
924 }
925
926 static int ov6650_try_fmt(struct v4l2_subdev *sd,
927 struct v4l2_mbus_framefmt *mf)
928 {
929 struct i2c_client *client = v4l2_get_subdevdata(sd);
930 struct ov6650 *priv = to_ov6650(client);
931
932 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
933 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
934 &mf->height, 2, H_CIF, 1, 0);
935
936 mf->field = V4L2_FIELD_NONE;
937
938 switch (mf->code) {
939 case V4L2_MBUS_FMT_Y10_1X10:
940 mf->code = V4L2_MBUS_FMT_Y8_1X8;
941 case V4L2_MBUS_FMT_Y8_1X8:
942 case V4L2_MBUS_FMT_YVYU8_2X8:
943 case V4L2_MBUS_FMT_YUYV8_2X8:
944 case V4L2_MBUS_FMT_VYUY8_2X8:
945 case V4L2_MBUS_FMT_UYVY8_2X8:
946 mf->colorspace = V4L2_COLORSPACE_JPEG;
947 break;
948 default:
949 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
950 case V4L2_MBUS_FMT_SBGGR8_1X8:
951 mf->colorspace = V4L2_COLORSPACE_SRGB;
952 break;
953 }
954
955 return 0;
956 }
957
958 static int ov6650_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
959 enum v4l2_mbus_pixelcode *code)
960 {
961 if (index >= ARRAY_SIZE(ov6650_codes))
962 return -EINVAL;
963
964 *code = ov6650_codes[index];
965 return 0;
966 }
967
968 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
969 {
970 struct i2c_client *client = v4l2_get_subdevdata(sd);
971 struct ov6650 *priv = to_ov6650(client);
972 struct v4l2_captureparm *cp = &parms->parm.capture;
973
974 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
975 return -EINVAL;
976
977 memset(cp, 0, sizeof(*cp));
978 cp->capability = V4L2_CAP_TIMEPERFRAME;
979 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
980 priv->pclk_limit, priv->pclk_max));
981 cp->timeperframe.denominator = FRAME_RATE_MAX;
982
983 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
984 cp->timeperframe.numerator, cp->timeperframe.denominator);
985
986 return 0;
987 }
988
989 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
990 {
991 struct i2c_client *client = v4l2_get_subdevdata(sd);
992 struct ov6650 *priv = to_ov6650(client);
993 struct v4l2_captureparm *cp = &parms->parm.capture;
994 struct v4l2_fract *tpf = &cp->timeperframe;
995 int div, ret;
996 u8 clkrc;
997
998 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
999 return -EINVAL;
1000
1001 if (cp->extendedmode != 0)
1002 return -EINVAL;
1003
1004 if (tpf->numerator == 0 || tpf->denominator == 0)
1005 div = 1; /* Reset to full rate */
1006 else
1007 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
1008
1009 if (div == 0)
1010 div = 1;
1011 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
1012 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
1013
1014 /*
1015 * Keep result to be used as tpf limit
1016 * for subseqent clock divider calculations
1017 */
1018 priv->tpf.numerator = div;
1019 priv->tpf.denominator = FRAME_RATE_MAX;
1020
1021 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
1022
1023 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
1024 if (!ret) {
1025 tpf->numerator = GET_CLKRC_DIV(clkrc);
1026 tpf->denominator = FRAME_RATE_MAX;
1027 }
1028
1029 return ret;
1030 }
1031
1032 /* Soft reset the camera. This has nothing to do with the RESET pin! */
1033 static int ov6650_reset(struct i2c_client *client)
1034 {
1035 int ret;
1036
1037 dev_dbg(&client->dev, "reset\n");
1038
1039 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
1040 if (ret)
1041 dev_err(&client->dev,
1042 "An error occurred while entering soft reset!\n");
1043
1044 return ret;
1045 }
1046
1047 /* program default register values */
1048 static int ov6650_prog_dflt(struct i2c_client *client)
1049 {
1050 int ret;
1051
1052 dev_dbg(&client->dev, "initializing\n");
1053
1054 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
1055 if (!ret)
1056 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
1057
1058 return ret;
1059 }
1060
1061 static int ov6650_video_probe(struct soc_camera_device *icd,
1062 struct i2c_client *client)
1063 {
1064 u8 pidh, pidl, midh, midl;
1065 int ret = 0;
1066
1067 /*
1068 * check and show product ID and manufacturer ID
1069 */
1070 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
1071 if (!ret)
1072 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
1073 if (!ret)
1074 ret = ov6650_reg_read(client, REG_MIDH, &midh);
1075 if (!ret)
1076 ret = ov6650_reg_read(client, REG_MIDL, &midl);
1077
1078 if (ret)
1079 return ret;
1080
1081 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
1082 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
1083 pidh, pidl);
1084 return -ENODEV;
1085 }
1086
1087 dev_info(&client->dev,
1088 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
1089 pidh, pidl, midh, midl);
1090
1091 ret = ov6650_reset(client);
1092 if (!ret)
1093 ret = ov6650_prog_dflt(client);
1094
1095 return ret;
1096 }
1097
1098 static struct soc_camera_ops ov6650_ops = {
1099 .set_bus_param = ov6650_set_bus_param,
1100 .query_bus_param = ov6650_query_bus_param,
1101 .controls = ov6650_controls,
1102 .num_controls = ARRAY_SIZE(ov6650_controls),
1103 };
1104
1105 static struct v4l2_subdev_core_ops ov6650_core_ops = {
1106 .g_ctrl = ov6650_g_ctrl,
1107 .s_ctrl = ov6650_s_ctrl,
1108 .g_chip_ident = ov6650_g_chip_ident,
1109 #ifdef CONFIG_VIDEO_ADV_DEBUG
1110 .g_register = ov6650_get_register,
1111 .s_register = ov6650_set_register,
1112 #endif
1113 };
1114
1115 static struct v4l2_subdev_video_ops ov6650_video_ops = {
1116 .s_stream = ov6650_s_stream,
1117 .g_mbus_fmt = ov6650_g_fmt,
1118 .s_mbus_fmt = ov6650_s_fmt,
1119 .try_mbus_fmt = ov6650_try_fmt,
1120 .enum_mbus_fmt = ov6650_enum_fmt,
1121 .cropcap = ov6650_cropcap,
1122 .g_crop = ov6650_g_crop,
1123 .s_crop = ov6650_s_crop,
1124 .g_parm = ov6650_g_parm,
1125 .s_parm = ov6650_s_parm,
1126 };
1127
1128 static struct v4l2_subdev_ops ov6650_subdev_ops = {
1129 .core = &ov6650_core_ops,
1130 .video = &ov6650_video_ops,
1131 };
1132
1133 /*
1134 * i2c_driver function
1135 */
1136 static int ov6650_probe(struct i2c_client *client,
1137 const struct i2c_device_id *did)
1138 {
1139 struct ov6650 *priv;
1140 struct soc_camera_device *icd = client->dev.platform_data;
1141 struct soc_camera_link *icl;
1142 int ret;
1143
1144 if (!icd) {
1145 dev_err(&client->dev, "Missing soc-camera data!\n");
1146 return -EINVAL;
1147 }
1148
1149 icl = to_soc_camera_link(icd);
1150 if (!icl) {
1151 dev_err(&client->dev, "Missing platform_data for driver\n");
1152 return -EINVAL;
1153 }
1154
1155 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1156 if (!priv) {
1157 dev_err(&client->dev,
1158 "Failed to allocate memory for private data!\n");
1159 return -ENOMEM;
1160 }
1161
1162 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
1163
1164 icd->ops = &ov6650_ops;
1165
1166 priv->rect.left = DEF_HSTRT << 1;
1167 priv->rect.top = DEF_VSTRT << 1;
1168 priv->rect.width = W_CIF;
1169 priv->rect.height = H_CIF;
1170 priv->half_scale = false;
1171 priv->code = V4L2_MBUS_FMT_YUYV8_2X8;
1172 priv->colorspace = V4L2_COLORSPACE_JPEG;
1173
1174 ret = ov6650_video_probe(icd, client);
1175
1176 if (ret) {
1177 icd->ops = NULL;
1178 kfree(priv);
1179 }
1180
1181 return ret;
1182 }
1183
1184 static int ov6650_remove(struct i2c_client *client)
1185 {
1186 struct ov6650 *priv = to_ov6650(client);
1187
1188 kfree(priv);
1189 return 0;
1190 }
1191
1192 static const struct i2c_device_id ov6650_id[] = {
1193 { "ov6650", 0 },
1194 { }
1195 };
1196 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1197
1198 static struct i2c_driver ov6650_i2c_driver = {
1199 .driver = {
1200 .name = "ov6650",
1201 },
1202 .probe = ov6650_probe,
1203 .remove = ov6650_remove,
1204 .id_table = ov6650_id,
1205 };
1206
1207 static int __init ov6650_module_init(void)
1208 {
1209 return i2c_add_driver(&ov6650_i2c_driver);
1210 }
1211
1212 static void __exit ov6650_module_exit(void)
1213 {
1214 i2c_del_driver(&ov6650_i2c_driver);
1215 }
1216
1217 module_init(ov6650_module_init);
1218 module_exit(ov6650_module_exit);
1219
1220 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1221 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1222 MODULE_LICENSE("GPL v2");
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