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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / mmc / host / sh_mmcif.c
blobd9391e427d0eaf258d95dc3cc37e93f23c378395
1 /*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/mmc/card.h>
25 #include <linux/mmc/core.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/sdio.h>
29 #include <linux/mmc/sh_mmcif.h>
30 #include <linux/pagemap.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/spinlock.h>
34 #include <linux/module.h>
35
36 #define DRIVER_NAME "sh_mmcif"
37 #define DRIVER_VERSION "2010-04-28"
38
39 /* CE_CMD_SET */
40 #define CMD_MASK 0x3f000000
41 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
42 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
43 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
44 #define CMD_SET_RBSY (1 << 21) /* R1b */
45 #define CMD_SET_CCSEN (1 << 20)
46 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
47 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
48 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
49 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
50 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
51 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
52 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
53 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
54 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
55 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
56 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
57 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
58 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
59 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
60 #define CMD_SET_CCSH (1 << 5)
61 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
62 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
63 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
64
65 /* CE_CMD_CTRL */
66 #define CMD_CTRL_BREAK (1 << 0)
67
68 /* CE_BLOCK_SET */
69 #define BLOCK_SIZE_MASK 0x0000ffff
70
71 /* CE_INT */
72 #define INT_CCSDE (1 << 29)
73 #define INT_CMD12DRE (1 << 26)
74 #define INT_CMD12RBE (1 << 25)
75 #define INT_CMD12CRE (1 << 24)
76 #define INT_DTRANE (1 << 23)
77 #define INT_BUFRE (1 << 22)
78 #define INT_BUFWEN (1 << 21)
79 #define INT_BUFREN (1 << 20)
80 #define INT_CCSRCV (1 << 19)
81 #define INT_RBSYE (1 << 17)
82 #define INT_CRSPE (1 << 16)
83 #define INT_CMDVIO (1 << 15)
84 #define INT_BUFVIO (1 << 14)
85 #define INT_WDATERR (1 << 11)
86 #define INT_RDATERR (1 << 10)
87 #define INT_RIDXERR (1 << 9)
88 #define INT_RSPERR (1 << 8)
89 #define INT_CCSTO (1 << 5)
90 #define INT_CRCSTO (1 << 4)
91 #define INT_WDATTO (1 << 3)
92 #define INT_RDATTO (1 << 2)
93 #define INT_RBSYTO (1 << 1)
94 #define INT_RSPTO (1 << 0)
95 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
96 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
97 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
98 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
99
100 /* CE_INT_MASK */
101 #define MASK_ALL 0x00000000
102 #define MASK_MCCSDE (1 << 29)
103 #define MASK_MCMD12DRE (1 << 26)
104 #define MASK_MCMD12RBE (1 << 25)
105 #define MASK_MCMD12CRE (1 << 24)
106 #define MASK_MDTRANE (1 << 23)
107 #define MASK_MBUFRE (1 << 22)
108 #define MASK_MBUFWEN (1 << 21)
109 #define MASK_MBUFREN (1 << 20)
110 #define MASK_MCCSRCV (1 << 19)
111 #define MASK_MRBSYE (1 << 17)
112 #define MASK_MCRSPE (1 << 16)
113 #define MASK_MCMDVIO (1 << 15)
114 #define MASK_MBUFVIO (1 << 14)
115 #define MASK_MWDATERR (1 << 11)
116 #define MASK_MRDATERR (1 << 10)
117 #define MASK_MRIDXERR (1 << 9)
118 #define MASK_MRSPERR (1 << 8)
119 #define MASK_MCCSTO (1 << 5)
120 #define MASK_MCRCSTO (1 << 4)
121 #define MASK_MWDATTO (1 << 3)
122 #define MASK_MRDATTO (1 << 2)
123 #define MASK_MRBSYTO (1 << 1)
124 #define MASK_MRSPTO (1 << 0)
125
126 /* CE_HOST_STS1 */
127 #define STS1_CMDSEQ (1 << 31)
128
129 /* CE_HOST_STS2 */
130 #define STS2_CRCSTE (1 << 31)
131 #define STS2_CRC16E (1 << 30)
132 #define STS2_AC12CRCE (1 << 29)
133 #define STS2_RSPCRC7E (1 << 28)
134 #define STS2_CRCSTEBE (1 << 27)
135 #define STS2_RDATEBE (1 << 26)
136 #define STS2_AC12REBE (1 << 25)
137 #define STS2_RSPEBE (1 << 24)
138 #define STS2_AC12IDXE (1 << 23)
139 #define STS2_RSPIDXE (1 << 22)
140 #define STS2_CCSTO (1 << 15)
141 #define STS2_RDATTO (1 << 14)
142 #define STS2_DATBSYTO (1 << 13)
143 #define STS2_CRCSTTO (1 << 12)
144 #define STS2_AC12BSYTO (1 << 11)
145 #define STS2_RSPBSYTO (1 << 10)
146 #define STS2_AC12RSPTO (1 << 9)
147 #define STS2_RSPTO (1 << 8)
148 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
149 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
150 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
151 STS2_DATBSYTO | STS2_CRCSTTO | \
152 STS2_AC12BSYTO | STS2_RSPBSYTO | \
153 STS2_AC12RSPTO | STS2_RSPTO)
154
155 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
156 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
157 #define CLKDEV_INIT 400000 /* 400 KHz */
158
159 enum mmcif_state {
160 STATE_IDLE,
161 STATE_REQUEST,
162 STATE_IOS,
163 };
164
165 struct sh_mmcif_host {
166 struct mmc_host *mmc;
167 struct mmc_data *data;
168 struct platform_device *pd;
169 struct clk *hclk;
170 unsigned int clk;
171 int bus_width;
172 bool sd_error;
173 long timeout;
174 void __iomem *addr;
175 struct completion intr_wait;
176 enum mmcif_state state;
177 spinlock_t lock;
178 bool power;
179 bool card_present;
180
181 /* DMA support */
182 struct dma_chan *chan_rx;
183 struct dma_chan *chan_tx;
184 struct completion dma_complete;
185 bool dma_active;
186 };
187
188 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
189 unsigned int reg, u32 val)
190 {
191 writel(val | readl(host->addr + reg), host->addr + reg);
192 }
193
194 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
195 unsigned int reg, u32 val)
196 {
197 writel(~val & readl(host->addr + reg), host->addr + reg);
198 }
199
200 static void mmcif_dma_complete(void *arg)
201 {
202 struct sh_mmcif_host *host = arg;
203 dev_dbg(&host->pd->dev, "Command completed\n");
204
205 if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
206 dev_name(&host->pd->dev)))
207 return;
208
209 if (host->data->flags & MMC_DATA_READ)
210 dma_unmap_sg(host->chan_rx->device->dev,
211 host->data->sg, host->data->sg_len,
212 DMA_FROM_DEVICE);
213 else
214 dma_unmap_sg(host->chan_tx->device->dev,
215 host->data->sg, host->data->sg_len,
216 DMA_TO_DEVICE);
217
218 complete(&host->dma_complete);
219 }
220
221 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
222 {
223 struct scatterlist *sg = host->data->sg;
224 struct dma_async_tx_descriptor *desc = NULL;
225 struct dma_chan *chan = host->chan_rx;
226 dma_cookie_t cookie = -EINVAL;
227 int ret;
228
229 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
230 DMA_FROM_DEVICE);
231 if (ret > 0) {
232 host->dma_active = true;
233 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
234 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
235 }
236
237 if (desc) {
238 desc->callback = mmcif_dma_complete;
239 desc->callback_param = host;
240 cookie = dmaengine_submit(desc);
241 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
242 dma_async_issue_pending(chan);
243 }
244 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
245 __func__, host->data->sg_len, ret, cookie);
246
247 if (!desc) {
248 /* DMA failed, fall back to PIO */
249 if (ret >= 0)
250 ret = -EIO;
251 host->chan_rx = NULL;
252 host->dma_active = false;
253 dma_release_channel(chan);
254 /* Free the Tx channel too */
255 chan = host->chan_tx;
256 if (chan) {
257 host->chan_tx = NULL;
258 dma_release_channel(chan);
259 }
260 dev_warn(&host->pd->dev,
261 "DMA failed: %d, falling back to PIO\n", ret);
262 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
263 }
264
265 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
266 desc, cookie, host->data->sg_len);
267 }
268
269 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
270 {
271 struct scatterlist *sg = host->data->sg;
272 struct dma_async_tx_descriptor *desc = NULL;
273 struct dma_chan *chan = host->chan_tx;
274 dma_cookie_t cookie = -EINVAL;
275 int ret;
276
277 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
278 DMA_TO_DEVICE);
279 if (ret > 0) {
280 host->dma_active = true;
281 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
282 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
283 }
284
285 if (desc) {
286 desc->callback = mmcif_dma_complete;
287 desc->callback_param = host;
288 cookie = dmaengine_submit(desc);
289 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
290 dma_async_issue_pending(chan);
291 }
292 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
293 __func__, host->data->sg_len, ret, cookie);
294
295 if (!desc) {
296 /* DMA failed, fall back to PIO */
297 if (ret >= 0)
298 ret = -EIO;
299 host->chan_tx = NULL;
300 host->dma_active = false;
301 dma_release_channel(chan);
302 /* Free the Rx channel too */
303 chan = host->chan_rx;
304 if (chan) {
305 host->chan_rx = NULL;
306 dma_release_channel(chan);
307 }
308 dev_warn(&host->pd->dev,
309 "DMA failed: %d, falling back to PIO\n", ret);
310 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
311 }
312
313 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
314 desc, cookie);
315 }
316
317 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
318 {
319 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
320 chan->private = arg;
321 return true;
322 }
323
324 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
325 struct sh_mmcif_plat_data *pdata)
326 {
327 host->dma_active = false;
328
329 /* We can only either use DMA for both Tx and Rx or not use it at all */
330 if (pdata->dma) {
331 dma_cap_mask_t mask;
332
333 dma_cap_zero(mask);
334 dma_cap_set(DMA_SLAVE, mask);
335
336 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter,
337 &pdata->dma->chan_priv_tx);
338 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
339 host->chan_tx);
340
341 if (!host->chan_tx)
342 return;
343
344 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter,
345 &pdata->dma->chan_priv_rx);
346 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
347 host->chan_rx);
348
349 if (!host->chan_rx) {
350 dma_release_channel(host->chan_tx);
351 host->chan_tx = NULL;
352 return;
353 }
354
355 init_completion(&host->dma_complete);
356 }
357 }
358
359 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
360 {
361 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
362 /* Descriptors are freed automatically */
363 if (host->chan_tx) {
364 struct dma_chan *chan = host->chan_tx;
365 host->chan_tx = NULL;
366 dma_release_channel(chan);
367 }
368 if (host->chan_rx) {
369 struct dma_chan *chan = host->chan_rx;
370 host->chan_rx = NULL;
371 dma_release_channel(chan);
372 }
373
374 host->dma_active = false;
375 }
376
377 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
378 {
379 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
380
381 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
382 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
383
384 if (!clk)
385 return;
386 if (p->sup_pclk && clk == host->clk)
387 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
388 else
389 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
390 (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
391
392 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
393 }
394
395 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
396 {
397 u32 tmp;
398
399 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
400
401 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
402 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
403 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
404 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
405 /* byte swap on */
406 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
407 }
408
409 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
410 {
411 u32 state1, state2;
412 int ret, timeout = 10000000;
413
414 host->sd_error = false;
415
416 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
417 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
418 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
419 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
420
421 if (state1 & STS1_CMDSEQ) {
422 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
423 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
424 while (1) {
425 timeout--;
426 if (timeout < 0) {
427 dev_err(&host->pd->dev,
428 "Forceed end of command sequence timeout err\n");
429 return -EIO;
430 }
431 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
432 & STS1_CMDSEQ))
433 break;
434 mdelay(1);
435 }
436 sh_mmcif_sync_reset(host);
437 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
438 return -EIO;
439 }
440
441 if (state2 & STS2_CRC_ERR) {
442 dev_dbg(&host->pd->dev, ": Happened CRC error\n");
443 ret = -EIO;
444 } else if (state2 & STS2_TIMEOUT_ERR) {
445 dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
446 ret = -ETIMEDOUT;
447 } else {
448 dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
449 ret = -EIO;
450 }
451 return ret;
452 }
453
454 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
455 struct mmc_request *mrq)
456 {
457 struct mmc_data *data = mrq->data;
458 long time;
459 u32 blocksize, i, *p = sg_virt(data->sg);
460
461 /* buf read enable */
462 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
463 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
464 host->timeout);
465 if (time <= 0 || host->sd_error)
466 return sh_mmcif_error_manage(host);
467
468 blocksize = (BLOCK_SIZE_MASK &
469 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
470 for (i = 0; i < blocksize / 4; i++)
471 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
472
473 /* buffer read end */
474 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
475 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
476 host->timeout);
477 if (time <= 0 || host->sd_error)
478 return sh_mmcif_error_manage(host);
479
480 return 0;
481 }
482
483 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
484 struct mmc_request *mrq)
485 {
486 struct mmc_data *data = mrq->data;
487 long time;
488 u32 blocksize, i, j, sec, *p;
489
490 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
491 MMCIF_CE_BLOCK_SET);
492 for (j = 0; j < data->sg_len; j++) {
493 p = sg_virt(data->sg);
494 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
495 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
496 /* buf read enable */
497 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
498 host->timeout);
499
500 if (time <= 0 || host->sd_error)
501 return sh_mmcif_error_manage(host);
502
503 for (i = 0; i < blocksize / 4; i++)
504 *p++ = sh_mmcif_readl(host->addr,
505 MMCIF_CE_DATA);
506 }
507 if (j < data->sg_len - 1)
508 data->sg++;
509 }
510 return 0;
511 }
512
513 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
514 struct mmc_request *mrq)
515 {
516 struct mmc_data *data = mrq->data;
517 long time;
518 u32 blocksize, i, *p = sg_virt(data->sg);
519
520 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
521
522 /* buf write enable */
523 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
524 host->timeout);
525 if (time <= 0 || host->sd_error)
526 return sh_mmcif_error_manage(host);
527
528 blocksize = (BLOCK_SIZE_MASK &
529 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
530 for (i = 0; i < blocksize / 4; i++)
531 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
532
533 /* buffer write end */
534 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
535
536 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
537 host->timeout);
538 if (time <= 0 || host->sd_error)
539 return sh_mmcif_error_manage(host);
540
541 return 0;
542 }
543
544 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
545 struct mmc_request *mrq)
546 {
547 struct mmc_data *data = mrq->data;
548 long time;
549 u32 i, sec, j, blocksize, *p;
550
551 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
552 MMCIF_CE_BLOCK_SET);
553
554 for (j = 0; j < data->sg_len; j++) {
555 p = sg_virt(data->sg);
556 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
557 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
558 /* buf write enable*/
559 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
560 host->timeout);
561
562 if (time <= 0 || host->sd_error)
563 return sh_mmcif_error_manage(host);
564
565 for (i = 0; i < blocksize / 4; i++)
566 sh_mmcif_writel(host->addr,
567 MMCIF_CE_DATA, *p++);
568 }
569 if (j < data->sg_len - 1)
570 data->sg++;
571 }
572 return 0;
573 }
574
575 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
576 struct mmc_command *cmd)
577 {
578 if (cmd->flags & MMC_RSP_136) {
579 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
580 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
581 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
582 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
583 } else
584 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
585 }
586
587 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
588 struct mmc_command *cmd)
589 {
590 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
591 }
592
593 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
594 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
595 {
596 u32 tmp = 0;
597
598 /* Response Type check */
599 switch (mmc_resp_type(cmd)) {
600 case MMC_RSP_NONE:
601 tmp |= CMD_SET_RTYP_NO;
602 break;
603 case MMC_RSP_R1:
604 case MMC_RSP_R1B:
605 case MMC_RSP_R3:
606 tmp |= CMD_SET_RTYP_6B;
607 break;
608 case MMC_RSP_R2:
609 tmp |= CMD_SET_RTYP_17B;
610 break;
611 default:
612 dev_err(&host->pd->dev, "Unsupported response type.\n");
613 break;
614 }
615 switch (opc) {
616 /* RBSY */
617 case MMC_SWITCH:
618 case MMC_STOP_TRANSMISSION:
619 case MMC_SET_WRITE_PROT:
620 case MMC_CLR_WRITE_PROT:
621 case MMC_ERASE:
622 case MMC_GEN_CMD:
623 tmp |= CMD_SET_RBSY;
624 break;
625 }
626 /* WDAT / DATW */
627 if (host->data) {
628 tmp |= CMD_SET_WDAT;
629 switch (host->bus_width) {
630 case MMC_BUS_WIDTH_1:
631 tmp |= CMD_SET_DATW_1;
632 break;
633 case MMC_BUS_WIDTH_4:
634 tmp |= CMD_SET_DATW_4;
635 break;
636 case MMC_BUS_WIDTH_8:
637 tmp |= CMD_SET_DATW_8;
638 break;
639 default:
640 dev_err(&host->pd->dev, "Unsupported bus width.\n");
641 break;
642 }
643 }
644 /* DWEN */
645 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
646 tmp |= CMD_SET_DWEN;
647 /* CMLTE/CMD12EN */
648 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
649 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
650 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
651 mrq->data->blocks << 16);
652 }
653 /* RIDXC[1:0] check bits */
654 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
655 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
656 tmp |= CMD_SET_RIDXC_BITS;
657 /* RCRC7C[1:0] check bits */
658 if (opc == MMC_SEND_OP_COND)
659 tmp |= CMD_SET_CRC7C_BITS;
660 /* RCRC7C[1:0] internal CRC7 */
661 if (opc == MMC_ALL_SEND_CID ||
662 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
663 tmp |= CMD_SET_CRC7C_INTERNAL;
664
665 return opc = ((opc << 24) | tmp);
666 }
667
668 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
669 struct mmc_request *mrq, u32 opc)
670 {
671 int ret;
672
673 switch (opc) {
674 case MMC_READ_MULTIPLE_BLOCK:
675 ret = sh_mmcif_multi_read(host, mrq);
676 break;
677 case MMC_WRITE_MULTIPLE_BLOCK:
678 ret = sh_mmcif_multi_write(host, mrq);
679 break;
680 case MMC_WRITE_BLOCK:
681 ret = sh_mmcif_single_write(host, mrq);
682 break;
683 case MMC_READ_SINGLE_BLOCK:
684 case MMC_SEND_EXT_CSD:
685 ret = sh_mmcif_single_read(host, mrq);
686 break;
687 default:
688 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
689 ret = -EINVAL;
690 break;
691 }
692 return ret;
693 }
694
695 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
696 struct mmc_request *mrq, struct mmc_command *cmd)
697 {
698 long time;
699 int ret = 0, mask = 0;
700 u32 opc = cmd->opcode;
701
702 switch (opc) {
703 /* respons busy check */
704 case MMC_SWITCH:
705 case MMC_STOP_TRANSMISSION:
706 case MMC_SET_WRITE_PROT:
707 case MMC_CLR_WRITE_PROT:
708 case MMC_ERASE:
709 case MMC_GEN_CMD:
710 mask = MASK_MRBSYE;
711 break;
712 default:
713 mask = MASK_MCRSPE;
714 break;
715 }
716 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
717 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
718 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
719 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
720
721 if (host->data) {
722 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
723 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
724 mrq->data->blksz);
725 }
726 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
727
728 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
729 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
730 /* set arg */
731 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
732 /* set cmd */
733 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
734
735 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
736 host->timeout);
737 if (time <= 0) {
738 cmd->error = sh_mmcif_error_manage(host);
739 return;
740 }
741 if (host->sd_error) {
742 switch (cmd->opcode) {
743 case MMC_ALL_SEND_CID:
744 case MMC_SELECT_CARD:
745 case MMC_APP_CMD:
746 cmd->error = -ETIMEDOUT;
747 break;
748 default:
749 dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
750 cmd->opcode);
751 cmd->error = sh_mmcif_error_manage(host);
752 break;
753 }
754 host->sd_error = false;
755 return;
756 }
757 if (!(cmd->flags & MMC_RSP_PRESENT)) {
758 cmd->error = 0;
759 return;
760 }
761 sh_mmcif_get_response(host, cmd);
762 if (host->data) {
763 if (!host->dma_active) {
764 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
765 } else {
766 long time =
767 wait_for_completion_interruptible_timeout(&host->dma_complete,
768 host->timeout);
769 if (!time)
770 ret = -ETIMEDOUT;
771 else if (time < 0)
772 ret = time;
773 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
774 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
775 host->dma_active = false;
776 }
777 if (ret < 0)
778 mrq->data->bytes_xfered = 0;
779 else
780 mrq->data->bytes_xfered =
781 mrq->data->blocks * mrq->data->blksz;
782 }
783 cmd->error = ret;
784 }
785
786 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
787 struct mmc_request *mrq, struct mmc_command *cmd)
788 {
789 long time;
790
791 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
792 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
793 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
794 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
795 else {
796 dev_err(&host->pd->dev, "unsupported stop cmd\n");
797 cmd->error = sh_mmcif_error_manage(host);
798 return;
799 }
800
801 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
802 host->timeout);
803 if (time <= 0 || host->sd_error) {
804 cmd->error = sh_mmcif_error_manage(host);
805 return;
806 }
807 sh_mmcif_get_cmd12response(host, cmd);
808 cmd->error = 0;
809 }
810
811 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
812 {
813 struct sh_mmcif_host *host = mmc_priv(mmc);
814 unsigned long flags;
815
816 spin_lock_irqsave(&host->lock, flags);
817 if (host->state != STATE_IDLE) {
818 spin_unlock_irqrestore(&host->lock, flags);
819 mrq->cmd->error = -EAGAIN;
820 mmc_request_done(mmc, mrq);
821 return;
822 }
823
824 host->state = STATE_REQUEST;
825 spin_unlock_irqrestore(&host->lock, flags);
826
827 switch (mrq->cmd->opcode) {
828 /* MMCIF does not support SD/SDIO command */
829 case SD_IO_SEND_OP_COND:
830 case MMC_APP_CMD:
831 host->state = STATE_IDLE;
832 mrq->cmd->error = -ETIMEDOUT;
833 mmc_request_done(mmc, mrq);
834 return;
835 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
836 if (!mrq->data) {
837 /* send_if_cond cmd (not support) */
838 host->state = STATE_IDLE;
839 mrq->cmd->error = -ETIMEDOUT;
840 mmc_request_done(mmc, mrq);
841 return;
842 }
843 break;
844 default:
845 break;
846 }
847 host->data = mrq->data;
848 if (mrq->data) {
849 if (mrq->data->flags & MMC_DATA_READ) {
850 if (host->chan_rx)
851 sh_mmcif_start_dma_rx(host);
852 } else {
853 if (host->chan_tx)
854 sh_mmcif_start_dma_tx(host);
855 }
856 }
857 sh_mmcif_start_cmd(host, mrq, mrq->cmd);
858 host->data = NULL;
859
860 if (!mrq->cmd->error && mrq->stop)
861 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
862 host->state = STATE_IDLE;
863 mmc_request_done(mmc, mrq);
864 }
865
866 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
867 {
868 struct sh_mmcif_host *host = mmc_priv(mmc);
869 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
870 unsigned long flags;
871
872 spin_lock_irqsave(&host->lock, flags);
873 if (host->state != STATE_IDLE) {
874 spin_unlock_irqrestore(&host->lock, flags);
875 return;
876 }
877
878 host->state = STATE_IOS;
879 spin_unlock_irqrestore(&host->lock, flags);
880
881 if (ios->power_mode == MMC_POWER_UP) {
882 if (!host->card_present) {
883 /* See if we also get DMA */
884 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
885 host->card_present = true;
886 }
887 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
888 /* clock stop */
889 sh_mmcif_clock_control(host, 0);
890 if (ios->power_mode == MMC_POWER_OFF) {
891 if (host->card_present) {
892 sh_mmcif_release_dma(host);
893 host->card_present = false;
894 }
895 }
896 if (host->power) {
897 pm_runtime_put(&host->pd->dev);
898 host->power = false;
899 if (p->down_pwr)
900 p->down_pwr(host->pd);
901 }
902 host->state = STATE_IDLE;
903 return;
904 }
905
906 if (ios->clock) {
907 if (!host->power) {
908 if (p->set_pwr)
909 p->set_pwr(host->pd, ios->power_mode);
910 pm_runtime_get_sync(&host->pd->dev);
911 host->power = true;
912 sh_mmcif_sync_reset(host);
913 }
914 sh_mmcif_clock_control(host, ios->clock);
915 }
916
917 host->bus_width = ios->bus_width;
918 host->state = STATE_IDLE;
919 }
920
921 static int sh_mmcif_get_cd(struct mmc_host *mmc)
922 {
923 struct sh_mmcif_host *host = mmc_priv(mmc);
924 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
925
926 if (!p->get_cd)
927 return -ENOSYS;
928 else
929 return p->get_cd(host->pd);
930 }
931
932 static struct mmc_host_ops sh_mmcif_ops = {
933 .request = sh_mmcif_request,
934 .set_ios = sh_mmcif_set_ios,
935 .get_cd = sh_mmcif_get_cd,
936 };
937
938 static void sh_mmcif_detect(struct mmc_host *mmc)
939 {
940 mmc_detect_change(mmc, 0);
941 }
942
943 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
944 {
945 struct sh_mmcif_host *host = dev_id;
946 u32 state;
947 int err = 0;
948
949 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
950
951 if (state & INT_RBSYE) {
952 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
953 ~(INT_RBSYE | INT_CRSPE));
954 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
955 } else if (state & INT_CRSPE) {
956 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
957 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
958 } else if (state & INT_BUFREN) {
959 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
960 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
961 } else if (state & INT_BUFWEN) {
962 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
963 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
964 } else if (state & INT_CMD12DRE) {
965 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
966 ~(INT_CMD12DRE | INT_CMD12RBE |
967 INT_CMD12CRE | INT_BUFRE));
968 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
969 } else if (state & INT_BUFRE) {
970 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
971 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
972 } else if (state & INT_DTRANE) {
973 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
974 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
975 } else if (state & INT_CMD12RBE) {
976 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
977 ~(INT_CMD12RBE | INT_CMD12CRE));
978 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
979 } else if (state & INT_ERR_STS) {
980 /* err interrupts */
981 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
982 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
983 err = 1;
984 } else {
985 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
986 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
987 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
988 err = 1;
989 }
990 if (err) {
991 host->sd_error = true;
992 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
993 }
994 if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
995 complete(&host->intr_wait);
996 else
997 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
998
999 return IRQ_HANDLED;
1000 }
1001
1002 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1003 {
1004 int ret = 0, irq[2];
1005 struct mmc_host *mmc;
1006 struct sh_mmcif_host *host;
1007 struct sh_mmcif_plat_data *pd;
1008 struct resource *res;
1009 void __iomem *reg;
1010 char clk_name[8];
1011
1012 irq[0] = platform_get_irq(pdev, 0);
1013 irq[1] = platform_get_irq(pdev, 1);
1014 if (irq[0] < 0 || irq[1] < 0) {
1015 dev_err(&pdev->dev, "Get irq error\n");
1016 return -ENXIO;
1017 }
1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1019 if (!res) {
1020 dev_err(&pdev->dev, "platform_get_resource error.\n");
1021 return -ENXIO;
1022 }
1023 reg = ioremap(res->start, resource_size(res));
1024 if (!reg) {
1025 dev_err(&pdev->dev, "ioremap error.\n");
1026 return -ENOMEM;
1027 }
1028 pd = pdev->dev.platform_data;
1029 if (!pd) {
1030 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1031 ret = -ENXIO;
1032 goto clean_up;
1033 }
1034 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1035 if (!mmc) {
1036 ret = -ENOMEM;
1037 goto clean_up;
1038 }
1039 host = mmc_priv(mmc);
1040 host->mmc = mmc;
1041 host->addr = reg;
1042 host->timeout = 1000;
1043
1044 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1045 host->hclk = clk_get(&pdev->dev, clk_name);
1046 if (IS_ERR(host->hclk)) {
1047 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1048 ret = PTR_ERR(host->hclk);
1049 goto clean_up1;
1050 }
1051 clk_enable(host->hclk);
1052 host->clk = clk_get_rate(host->hclk);
1053 host->pd = pdev;
1054
1055 init_completion(&host->intr_wait);
1056 spin_lock_init(&host->lock);
1057
1058 mmc->ops = &sh_mmcif_ops;
1059 mmc->f_max = host->clk;
1060 /* close to 400KHz */
1061 if (mmc->f_max < 51200000)
1062 mmc->f_min = mmc->f_max / 128;
1063 else if (mmc->f_max < 102400000)
1064 mmc->f_min = mmc->f_max / 256;
1065 else
1066 mmc->f_min = mmc->f_max / 512;
1067 if (pd->ocr)
1068 mmc->ocr_avail = pd->ocr;
1069 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1070 if (pd->caps)
1071 mmc->caps |= pd->caps;
1072 mmc->max_segs = 32;
1073 mmc->max_blk_size = 512;
1074 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1075 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1076 mmc->max_seg_size = mmc->max_req_size;
1077
1078 sh_mmcif_sync_reset(host);
1079 platform_set_drvdata(pdev, host);
1080
1081 pm_runtime_enable(&pdev->dev);
1082 host->power = false;
1083
1084 ret = pm_runtime_resume(&pdev->dev);
1085 if (ret < 0)
1086 goto clean_up2;
1087
1088 mmc_add_host(mmc);
1089
1090 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1091
1092 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1093 if (ret) {
1094 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1095 goto clean_up3;
1096 }
1097 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1098 if (ret) {
1099 free_irq(irq[0], host);
1100 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1101 goto clean_up3;
1102 }
1103
1104 sh_mmcif_detect(host->mmc);
1105
1106 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1107 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1108 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1109 return ret;
1110
1111 clean_up3:
1112 mmc_remove_host(mmc);
1113 pm_runtime_suspend(&pdev->dev);
1114 clean_up2:
1115 pm_runtime_disable(&pdev->dev);
1116 clk_disable(host->hclk);
1117 clean_up1:
1118 mmc_free_host(mmc);
1119 clean_up:
1120 if (reg)
1121 iounmap(reg);
1122 return ret;
1123 }
1124
1125 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1126 {
1127 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1128 int irq[2];
1129
1130 pm_runtime_get_sync(&pdev->dev);
1131
1132 mmc_remove_host(host->mmc);
1133 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1134
1135 if (host->addr)
1136 iounmap(host->addr);
1137
1138 irq[0] = platform_get_irq(pdev, 0);
1139 irq[1] = platform_get_irq(pdev, 1);
1140
1141 free_irq(irq[0], host);
1142 free_irq(irq[1], host);
1143
1144 platform_set_drvdata(pdev, NULL);
1145
1146 clk_disable(host->hclk);
1147 mmc_free_host(host->mmc);
1148 pm_runtime_put_sync(&pdev->dev);
1149 pm_runtime_disable(&pdev->dev);
1150
1151 return 0;
1152 }
1153
1154 #ifdef CONFIG_PM
1155 static int sh_mmcif_suspend(struct device *dev)
1156 {
1157 struct platform_device *pdev = to_platform_device(dev);
1158 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1159 int ret = mmc_suspend_host(host->mmc);
1160
1161 if (!ret) {
1162 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1163 clk_disable(host->hclk);
1164 }
1165
1166 return ret;
1167 }
1168
1169 static int sh_mmcif_resume(struct device *dev)
1170 {
1171 struct platform_device *pdev = to_platform_device(dev);
1172 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1173
1174 clk_enable(host->hclk);
1175
1176 return mmc_resume_host(host->mmc);
1177 }
1178 #else
1179 #define sh_mmcif_suspend NULL
1180 #define sh_mmcif_resume NULL
1181 #endif /* CONFIG_PM */
1182
1183 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1184 .suspend = sh_mmcif_suspend,
1185 .resume = sh_mmcif_resume,
1186 };
1187
1188 static struct platform_driver sh_mmcif_driver = {
1189 .probe = sh_mmcif_probe,
1190 .remove = sh_mmcif_remove,
1191 .driver = {
1192 .name = DRIVER_NAME,
1193 .pm = &sh_mmcif_dev_pm_ops,
1194 },
1195 };
1196
1197 static int __init sh_mmcif_init(void)
1198 {
1199 return platform_driver_register(&sh_mmcif_driver);
1200 }
1201
1202 static void __exit sh_mmcif_exit(void)
1203 {
1204 platform_driver_unregister(&sh_mmcif_driver);
1205 }
1206
1207 module_init(sh_mmcif_init);
1208 module_exit(sh_mmcif_exit);
1209
1210
1211 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1212 MODULE_LICENSE("GPL");
1213 MODULE_ALIAS("platform:" DRIVER_NAME);
1214 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
linux-next