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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / mtd / nand / nand_base.c
blobd2ee68a14d911b0038c4b4b15eb98567a9d8ed79
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <linux/io.h>
50 #include <linux/mtd/partitions.h>
51
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61 };
62
63 static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69 };
70
71 static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80 };
81
82 static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94 };
95
96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102 /*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106 DEFINE_LED_TRIGGER(nand_led_trigger);
107
108 static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110 {
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__);
123 ret = -EINVAL;
124 }
125
126 /* Do not allow past end of device */
127 if (ofs + len > mtd->size) {
128 pr_debug("%s: past end of device\n", __func__);
129 ret = -EINVAL;
130 }
131
132 return ret;
133 }
134
135 /**
136 * nand_release_device - [GENERIC] release chip
137 * @mtd: MTD device structure
138 *
139 * Deselect, release chip lock and wake up anyone waiting on the device.
140 */
141 static void nand_release_device(struct mtd_info *mtd)
142 {
143 struct nand_chip *chip = mtd->priv;
144
145 /* De-select the NAND device */
146 chip->select_chip(mtd, -1);
147
148 /* Release the controller and the chip */
149 spin_lock(&chip->controller->lock);
150 chip->controller->active = NULL;
151 chip->state = FL_READY;
152 wake_up(&chip->controller->wq);
153 spin_unlock(&chip->controller->lock);
154 }
155
156 /**
157 * nand_read_byte - [DEFAULT] read one byte from the chip
158 * @mtd: MTD device structure
159 *
160 * Default read function for 8bit buswidth
161 */
162 static uint8_t nand_read_byte(struct mtd_info *mtd)
163 {
164 struct nand_chip *chip = mtd->priv;
165 return readb(chip->IO_ADDR_R);
166 }
167
168 /**
169 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
170 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
171 * @mtd: MTD device structure
172 *
173 * Default read function for 16bit buswidth with endianness conversion.
174 *
175 */
176 static uint8_t nand_read_byte16(struct mtd_info *mtd)
177 {
178 struct nand_chip *chip = mtd->priv;
179 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
180 }
181
182 /**
183 * nand_read_word - [DEFAULT] read one word from the chip
184 * @mtd: MTD device structure
185 *
186 * Default read function for 16bit buswidth without endianness conversion.
187 */
188 static u16 nand_read_word(struct mtd_info *mtd)
189 {
190 struct nand_chip *chip = mtd->priv;
191 return readw(chip->IO_ADDR_R);
192 }
193
194 /**
195 * nand_select_chip - [DEFAULT] control CE line
196 * @mtd: MTD device structure
197 * @chipnr: chipnumber to select, -1 for deselect
198 *
199 * Default select function for 1 chip devices.
200 */
201 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
202 {
203 struct nand_chip *chip = mtd->priv;
204
205 switch (chipnr) {
206 case -1:
207 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
208 break;
209 case 0:
210 break;
211
212 default:
213 BUG();
214 }
215 }
216
217 /**
218 * nand_write_buf - [DEFAULT] write buffer to chip
219 * @mtd: MTD device structure
220 * @buf: data buffer
221 * @len: number of bytes to write
222 *
223 * Default write function for 8bit buswidth.
224 */
225 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
226 {
227 int i;
228 struct nand_chip *chip = mtd->priv;
229
230 for (i = 0; i < len; i++)
231 writeb(buf[i], chip->IO_ADDR_W);
232 }
233
234 /**
235 * nand_read_buf - [DEFAULT] read chip data into buffer
236 * @mtd: MTD device structure
237 * @buf: buffer to store date
238 * @len: number of bytes to read
239 *
240 * Default read function for 8bit buswidth.
241 */
242 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
243 {
244 int i;
245 struct nand_chip *chip = mtd->priv;
246
247 for (i = 0; i < len; i++)
248 buf[i] = readb(chip->IO_ADDR_R);
249 }
250
251 /**
252 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
253 * @mtd: MTD device structure
254 * @buf: buffer containing the data to compare
255 * @len: number of bytes to compare
256 *
257 * Default verify function for 8bit buswidth.
258 */
259 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
260 {
261 int i;
262 struct nand_chip *chip = mtd->priv;
263
264 for (i = 0; i < len; i++)
265 if (buf[i] != readb(chip->IO_ADDR_R))
266 return -EFAULT;
267 return 0;
268 }
269
270 /**
271 * nand_write_buf16 - [DEFAULT] write buffer to chip
272 * @mtd: MTD device structure
273 * @buf: data buffer
274 * @len: number of bytes to write
275 *
276 * Default write function for 16bit buswidth.
277 */
278 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
279 {
280 int i;
281 struct nand_chip *chip = mtd->priv;
282 u16 *p = (u16 *) buf;
283 len >>= 1;
284
285 for (i = 0; i < len; i++)
286 writew(p[i], chip->IO_ADDR_W);
287
288 }
289
290 /**
291 * nand_read_buf16 - [DEFAULT] read chip data into buffer
292 * @mtd: MTD device structure
293 * @buf: buffer to store date
294 * @len: number of bytes to read
295 *
296 * Default read function for 16bit buswidth.
297 */
298 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
299 {
300 int i;
301 struct nand_chip *chip = mtd->priv;
302 u16 *p = (u16 *) buf;
303 len >>= 1;
304
305 for (i = 0; i < len; i++)
306 p[i] = readw(chip->IO_ADDR_R);
307 }
308
309 /**
310 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
311 * @mtd: MTD device structure
312 * @buf: buffer containing the data to compare
313 * @len: number of bytes to compare
314 *
315 * Default verify function for 16bit buswidth.
316 */
317 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
318 {
319 int i;
320 struct nand_chip *chip = mtd->priv;
321 u16 *p = (u16 *) buf;
322 len >>= 1;
323
324 for (i = 0; i < len; i++)
325 if (p[i] != readw(chip->IO_ADDR_R))
326 return -EFAULT;
327
328 return 0;
329 }
330
331 /**
332 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
333 * @mtd: MTD device structure
334 * @ofs: offset from device start
335 * @getchip: 0, if the chip is already selected
336 *
337 * Check, if the block is bad.
338 */
339 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340 {
341 int page, chipnr, res = 0;
342 struct nand_chip *chip = mtd->priv;
343 u16 bad;
344
345 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
346 ofs += mtd->erasesize - mtd->writesize;
347
348 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
349
350 if (getchip) {
351 chipnr = (int)(ofs >> chip->chip_shift);
352
353 nand_get_device(chip, mtd, FL_READING);
354
355 /* Select the NAND device */
356 chip->select_chip(mtd, chipnr);
357 }
358
359 if (chip->options & NAND_BUSWIDTH_16) {
360 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
361 page);
362 bad = cpu_to_le16(chip->read_word(mtd));
363 if (chip->badblockpos & 0x1)
364 bad >>= 8;
365 else
366 bad &= 0xFF;
367 } else {
368 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
369 bad = chip->read_byte(mtd);
370 }
371
372 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF;
374 else
375 res = hweight8(bad) < chip->badblockbits;
376
377 if (getchip)
378 nand_release_device(mtd);
379
380 return res;
381 }
382
383 /**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
385 * @mtd: MTD device structure
386 * @ofs: offset from device start
387 *
388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver.
390 */
391 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
392 {
393 struct nand_chip *chip = mtd->priv;
394 uint8_t buf[2] = { 0, 0 };
395 int block, ret, i = 0;
396
397 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
398 ofs += mtd->erasesize - mtd->writesize;
399
400 /* Get block number */
401 block = (int)(ofs >> chip->bbt_erase_shift);
402 if (chip->bbt)
403 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
404
405 /* Do we have a flash based bad block table? */
406 if (chip->bbt_options & NAND_BBT_USE_FLASH)
407 ret = nand_update_bbt(mtd, ofs);
408 else {
409 nand_get_device(chip, mtd, FL_WRITING);
410
411 /*
412 * Write to first two pages if necessary. If we write to more
413 * than one location, the first error encountered quits the
414 * procedure. We write two bytes per location, so we dont have
415 * to mess with 16 bit access.
416 */
417 do {
418 chip->ops.len = chip->ops.ooblen = 2;
419 chip->ops.datbuf = NULL;
420 chip->ops.oobbuf = buf;
421 chip->ops.ooboffs = chip->badblockpos & ~0x01;
422
423 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
424
425 i++;
426 ofs += mtd->writesize;
427 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
428 i < 2);
429
430 nand_release_device(mtd);
431 }
432 if (!ret)
433 mtd->ecc_stats.badblocks++;
434
435 return ret;
436 }
437
438 /**
439 * nand_check_wp - [GENERIC] check if the chip is write protected
440 * @mtd: MTD device structure
441 *
442 * Check, if the device is write protected. The function expects, that the
443 * device is already selected.
444 */
445 static int nand_check_wp(struct mtd_info *mtd)
446 {
447 struct nand_chip *chip = mtd->priv;
448
449 /* Broken xD cards report WP despite being writable */
450 if (chip->options & NAND_BROKEN_XD)
451 return 0;
452
453 /* Check the WP bit */
454 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
455 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
456 }
457
458 /**
459 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
460 * @mtd: MTD device structure
461 * @ofs: offset from device start
462 * @getchip: 0, if the chip is already selected
463 * @allowbbt: 1, if its allowed to access the bbt area
464 *
465 * Check, if the block is bad. Either by reading the bad block table or
466 * calling of the scan function.
467 */
468 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
469 int allowbbt)
470 {
471 struct nand_chip *chip = mtd->priv;
472
473 if (!chip->bbt)
474 return chip->block_bad(mtd, ofs, getchip);
475
476 /* Return info from the table */
477 return nand_isbad_bbt(mtd, ofs, allowbbt);
478 }
479
480 /**
481 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
482 * @mtd: MTD device structure
483 * @timeo: Timeout
484 *
485 * Helper function for nand_wait_ready used when needing to wait in interrupt
486 * context.
487 */
488 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
489 {
490 struct nand_chip *chip = mtd->priv;
491 int i;
492
493 /* Wait for the device to get ready */
494 for (i = 0; i < timeo; i++) {
495 if (chip->dev_ready(mtd))
496 break;
497 touch_softlockup_watchdog();
498 mdelay(1);
499 }
500 }
501
502 /* Wait for the ready pin, after a command. The timeout is caught later. */
503 void nand_wait_ready(struct mtd_info *mtd)
504 {
505 struct nand_chip *chip = mtd->priv;
506 unsigned long timeo = jiffies + 2;
507
508 /* 400ms timeout */
509 if (in_interrupt() || oops_in_progress)
510 return panic_nand_wait_ready(mtd, 400);
511
512 led_trigger_event(nand_led_trigger, LED_FULL);
513 /* Wait until command is processed or timeout occurs */
514 do {
515 if (chip->dev_ready(mtd))
516 break;
517 touch_softlockup_watchdog();
518 } while (time_before(jiffies, timeo));
519 led_trigger_event(nand_led_trigger, LED_OFF);
520 }
521 EXPORT_SYMBOL_GPL(nand_wait_ready);
522
523 /**
524 * nand_command - [DEFAULT] Send command to NAND device
525 * @mtd: MTD device structure
526 * @command: the command to be sent
527 * @column: the column address for this command, -1 if none
528 * @page_addr: the page address for this command, -1 if none
529 *
530 * Send command to NAND device. This function is used for small page devices
531 * (256/512 Bytes per page).
532 */
533 static void nand_command(struct mtd_info *mtd, unsigned int command,
534 int column, int page_addr)
535 {
536 register struct nand_chip *chip = mtd->priv;
537 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
538
539 /* Write out the command to the device */
540 if (command == NAND_CMD_SEQIN) {
541 int readcmd;
542
543 if (column >= mtd->writesize) {
544 /* OOB area */
545 column -= mtd->writesize;
546 readcmd = NAND_CMD_READOOB;
547 } else if (column < 256) {
548 /* First 256 bytes --> READ0 */
549 readcmd = NAND_CMD_READ0;
550 } else {
551 column -= 256;
552 readcmd = NAND_CMD_READ1;
553 }
554 chip->cmd_ctrl(mtd, readcmd, ctrl);
555 ctrl &= ~NAND_CTRL_CHANGE;
556 }
557 chip->cmd_ctrl(mtd, command, ctrl);
558
559 /* Address cycle, when necessary */
560 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
561 /* Serially input address */
562 if (column != -1) {
563 /* Adjust columns for 16 bit buswidth */
564 if (chip->options & NAND_BUSWIDTH_16)
565 column >>= 1;
566 chip->cmd_ctrl(mtd, column, ctrl);
567 ctrl &= ~NAND_CTRL_CHANGE;
568 }
569 if (page_addr != -1) {
570 chip->cmd_ctrl(mtd, page_addr, ctrl);
571 ctrl &= ~NAND_CTRL_CHANGE;
572 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
573 /* One more address cycle for devices > 32MiB */
574 if (chip->chipsize > (32 << 20))
575 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
576 }
577 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
578
579 /*
580 * Program and erase have their own busy handlers status and sequential
581 * in needs no delay
582 */
583 switch (command) {
584
585 case NAND_CMD_PAGEPROG:
586 case NAND_CMD_ERASE1:
587 case NAND_CMD_ERASE2:
588 case NAND_CMD_SEQIN:
589 case NAND_CMD_STATUS:
590 return;
591
592 case NAND_CMD_RESET:
593 if (chip->dev_ready)
594 break;
595 udelay(chip->chip_delay);
596 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
597 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
598 chip->cmd_ctrl(mtd,
599 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
600 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
601 ;
602 return;
603
604 /* This applies to read commands */
605 default:
606 /*
607 * If we don't have access to the busy pin, we apply the given
608 * command delay
609 */
610 if (!chip->dev_ready) {
611 udelay(chip->chip_delay);
612 return;
613 }
614 }
615 /*
616 * Apply this short delay always to ensure that we do wait tWB in
617 * any case on any machine.
618 */
619 ndelay(100);
620
621 nand_wait_ready(mtd);
622 }
623
624 /**
625 * nand_command_lp - [DEFAULT] Send command to NAND large page device
626 * @mtd: MTD device structure
627 * @command: the command to be sent
628 * @column: the column address for this command, -1 if none
629 * @page_addr: the page address for this command, -1 if none
630 *
631 * Send command to NAND device. This is the version for the new large page
632 * devices. We don't have the separate regions as we have in the small page
633 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
634 */
635 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
636 int column, int page_addr)
637 {
638 register struct nand_chip *chip = mtd->priv;
639
640 /* Emulate NAND_CMD_READOOB */
641 if (command == NAND_CMD_READOOB) {
642 column += mtd->writesize;
643 command = NAND_CMD_READ0;
644 }
645
646 /* Command latch cycle */
647 chip->cmd_ctrl(mtd, command & 0xff,
648 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
649
650 if (column != -1 || page_addr != -1) {
651 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
652
653 /* Serially input address */
654 if (column != -1) {
655 /* Adjust columns for 16 bit buswidth */
656 if (chip->options & NAND_BUSWIDTH_16)
657 column >>= 1;
658 chip->cmd_ctrl(mtd, column, ctrl);
659 ctrl &= ~NAND_CTRL_CHANGE;
660 chip->cmd_ctrl(mtd, column >> 8, ctrl);
661 }
662 if (page_addr != -1) {
663 chip->cmd_ctrl(mtd, page_addr, ctrl);
664 chip->cmd_ctrl(mtd, page_addr >> 8,
665 NAND_NCE | NAND_ALE);
666 /* One more address cycle for devices > 128MiB */
667 if (chip->chipsize > (128 << 20))
668 chip->cmd_ctrl(mtd, page_addr >> 16,
669 NAND_NCE | NAND_ALE);
670 }
671 }
672 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
673
674 /*
675 * Program and erase have their own busy handlers status, sequential
676 * in, and deplete1 need no delay.
677 */
678 switch (command) {
679
680 case NAND_CMD_CACHEDPROG:
681 case NAND_CMD_PAGEPROG:
682 case NAND_CMD_ERASE1:
683 case NAND_CMD_ERASE2:
684 case NAND_CMD_SEQIN:
685 case NAND_CMD_RNDIN:
686 case NAND_CMD_STATUS:
687 case NAND_CMD_DEPLETE1:
688 return;
689
690 case NAND_CMD_STATUS_ERROR:
691 case NAND_CMD_STATUS_ERROR0:
692 case NAND_CMD_STATUS_ERROR1:
693 case NAND_CMD_STATUS_ERROR2:
694 case NAND_CMD_STATUS_ERROR3:
695 /* Read error status commands require only a short delay */
696 udelay(chip->chip_delay);
697 return;
698
699 case NAND_CMD_RESET:
700 if (chip->dev_ready)
701 break;
702 udelay(chip->chip_delay);
703 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
704 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
705 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
706 NAND_NCE | NAND_CTRL_CHANGE);
707 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
708 ;
709 return;
710
711 case NAND_CMD_RNDOUT:
712 /* No ready / busy check necessary */
713 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 return;
718
719 case NAND_CMD_READ0:
720 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
721 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
722 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
723 NAND_NCE | NAND_CTRL_CHANGE);
724
725 /* This applies to read commands */
726 default:
727 /*
728 * If we don't have access to the busy pin, we apply the given
729 * command delay.
730 */
731 if (!chip->dev_ready) {
732 udelay(chip->chip_delay);
733 return;
734 }
735 }
736
737 /*
738 * Apply this short delay always to ensure that we do wait tWB in
739 * any case on any machine.
740 */
741 ndelay(100);
742
743 nand_wait_ready(mtd);
744 }
745
746 /**
747 * panic_nand_get_device - [GENERIC] Get chip for selected access
748 * @chip: the nand chip descriptor
749 * @mtd: MTD device structure
750 * @new_state: the state which is requested
751 *
752 * Used when in panic, no locks are taken.
753 */
754 static void panic_nand_get_device(struct nand_chip *chip,
755 struct mtd_info *mtd, int new_state)
756 {
757 /* Hardware controller shared among independent devices */
758 chip->controller->active = chip;
759 chip->state = new_state;
760 }
761
762 /**
763 * nand_get_device - [GENERIC] Get chip for selected access
764 * @chip: the nand chip descriptor
765 * @mtd: MTD device structure
766 * @new_state: the state which is requested
767 *
768 * Get the device and lock it for exclusive access
769 */
770 static int
771 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
772 {
773 spinlock_t *lock = &chip->controller->lock;
774 wait_queue_head_t *wq = &chip->controller->wq;
775 DECLARE_WAITQUEUE(wait, current);
776 retry:
777 spin_lock(lock);
778
779 /* Hardware controller shared among independent devices */
780 if (!chip->controller->active)
781 chip->controller->active = chip;
782
783 if (chip->controller->active == chip && chip->state == FL_READY) {
784 chip->state = new_state;
785 spin_unlock(lock);
786 return 0;
787 }
788 if (new_state == FL_PM_SUSPENDED) {
789 if (chip->controller->active->state == FL_PM_SUSPENDED) {
790 chip->state = FL_PM_SUSPENDED;
791 spin_unlock(lock);
792 return 0;
793 }
794 }
795 set_current_state(TASK_UNINTERRUPTIBLE);
796 add_wait_queue(wq, &wait);
797 spin_unlock(lock);
798 schedule();
799 remove_wait_queue(wq, &wait);
800 goto retry;
801 }
802
803 /**
804 * panic_nand_wait - [GENERIC] wait until the command is done
805 * @mtd: MTD device structure
806 * @chip: NAND chip structure
807 * @timeo: timeout
808 *
809 * Wait for command done. This is a helper function for nand_wait used when
810 * we are in interrupt context. May happen when in panic and trying to write
811 * an oops through mtdoops.
812 */
813 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
814 unsigned long timeo)
815 {
816 int i;
817 for (i = 0; i < timeo; i++) {
818 if (chip->dev_ready) {
819 if (chip->dev_ready(mtd))
820 break;
821 } else {
822 if (chip->read_byte(mtd) & NAND_STATUS_READY)
823 break;
824 }
825 mdelay(1);
826 }
827 }
828
829 /**
830 * nand_wait - [DEFAULT] wait until the command is done
831 * @mtd: MTD device structure
832 * @chip: NAND chip structure
833 *
834 * Wait for command done. This applies to erase and program only. Erase can
835 * take up to 400ms and program up to 20ms according to general NAND and
836 * SmartMedia specs.
837 */
838 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
839 {
840
841 unsigned long timeo = jiffies;
842 int status, state = chip->state;
843
844 if (state == FL_ERASING)
845 timeo += (HZ * 400) / 1000;
846 else
847 timeo += (HZ * 20) / 1000;
848
849 led_trigger_event(nand_led_trigger, LED_FULL);
850
851 /*
852 * Apply this short delay always to ensure that we do wait tWB in any
853 * case on any machine.
854 */
855 ndelay(100);
856
857 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
858 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
859 else
860 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
861
862 if (in_interrupt() || oops_in_progress)
863 panic_nand_wait(mtd, chip, timeo);
864 else {
865 while (time_before(jiffies, timeo)) {
866 if (chip->dev_ready) {
867 if (chip->dev_ready(mtd))
868 break;
869 } else {
870 if (chip->read_byte(mtd) & NAND_STATUS_READY)
871 break;
872 }
873 cond_resched();
874 }
875 }
876 led_trigger_event(nand_led_trigger, LED_OFF);
877
878 status = (int)chip->read_byte(mtd);
879 return status;
880 }
881
882 /**
883 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
884 * @mtd: mtd info
885 * @ofs: offset to start unlock from
886 * @len: length to unlock
887 * @invert: when = 0, unlock the range of blocks within the lower and
888 * upper boundary address
889 * when = 1, unlock the range of blocks outside the boundaries
890 * of the lower and upper boundary address
891 *
892 * Returs unlock status.
893 */
894 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
895 uint64_t len, int invert)
896 {
897 int ret = 0;
898 int status, page;
899 struct nand_chip *chip = mtd->priv;
900
901 /* Submit address of first page to unlock */
902 page = ofs >> chip->page_shift;
903 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
904
905 /* Submit address of last page to unlock */
906 page = (ofs + len) >> chip->page_shift;
907 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
908 (page | invert) & chip->pagemask);
909
910 /* Call wait ready function */
911 status = chip->waitfunc(mtd, chip);
912 /* See if device thinks it succeeded */
913 if (status & 0x01) {
914 pr_debug("%s: error status = 0x%08x\n",
915 __func__, status);
916 ret = -EIO;
917 }
918
919 return ret;
920 }
921
922 /**
923 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
924 * @mtd: mtd info
925 * @ofs: offset to start unlock from
926 * @len: length to unlock
927 *
928 * Returns unlock status.
929 */
930 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
931 {
932 int ret = 0;
933 int chipnr;
934 struct nand_chip *chip = mtd->priv;
935
936 pr_debug("%s: start = 0x%012llx, len = %llu\n",
937 __func__, (unsigned long long)ofs, len);
938
939 if (check_offs_len(mtd, ofs, len))
940 ret = -EINVAL;
941
942 /* Align to last block address if size addresses end of the device */
943 if (ofs + len == mtd->size)
944 len -= mtd->erasesize;
945
946 nand_get_device(chip, mtd, FL_UNLOCKING);
947
948 /* Shift to get chip number */
949 chipnr = ofs >> chip->chip_shift;
950
951 chip->select_chip(mtd, chipnr);
952
953 /* Check, if it is write protected */
954 if (nand_check_wp(mtd)) {
955 pr_debug("%s: device is write protected!\n",
956 __func__);
957 ret = -EIO;
958 goto out;
959 }
960
961 ret = __nand_unlock(mtd, ofs, len, 0);
962
963 out:
964 nand_release_device(mtd);
965
966 return ret;
967 }
968 EXPORT_SYMBOL(nand_unlock);
969
970 /**
971 * nand_lock - [REPLACEABLE] locks all blocks present in the device
972 * @mtd: mtd info
973 * @ofs: offset to start unlock from
974 * @len: length to unlock
975 *
976 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
977 * have this feature, but it allows only to lock all blocks, not for specified
978 * range for block. Implementing 'lock' feature by making use of 'unlock', for
979 * now.
980 *
981 * Returns lock status.
982 */
983 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
984 {
985 int ret = 0;
986 int chipnr, status, page;
987 struct nand_chip *chip = mtd->priv;
988
989 pr_debug("%s: start = 0x%012llx, len = %llu\n",
990 __func__, (unsigned long long)ofs, len);
991
992 if (check_offs_len(mtd, ofs, len))
993 ret = -EINVAL;
994
995 nand_get_device(chip, mtd, FL_LOCKING);
996
997 /* Shift to get chip number */
998 chipnr = ofs >> chip->chip_shift;
999
1000 chip->select_chip(mtd, chipnr);
1001
1002 /* Check, if it is write protected */
1003 if (nand_check_wp(mtd)) {
1004 pr_debug("%s: device is write protected!\n",
1005 __func__);
1006 status = MTD_ERASE_FAILED;
1007 ret = -EIO;
1008 goto out;
1009 }
1010
1011 /* Submit address of first page to lock */
1012 page = ofs >> chip->page_shift;
1013 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1014
1015 /* Call wait ready function */
1016 status = chip->waitfunc(mtd, chip);
1017 /* See if device thinks it succeeded */
1018 if (status & 0x01) {
1019 pr_debug("%s: error status = 0x%08x\n",
1020 __func__, status);
1021 ret = -EIO;
1022 goto out;
1023 }
1024
1025 ret = __nand_unlock(mtd, ofs, len, 0x1);
1026
1027 out:
1028 nand_release_device(mtd);
1029
1030 return ret;
1031 }
1032 EXPORT_SYMBOL(nand_lock);
1033
1034 /**
1035 * nand_read_page_raw - [INTERN] read raw page data without ecc
1036 * @mtd: mtd info structure
1037 * @chip: nand chip info structure
1038 * @buf: buffer to store read data
1039 * @page: page number to read
1040 *
1041 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1042 */
1043 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1044 uint8_t *buf, int page)
1045 {
1046 chip->read_buf(mtd, buf, mtd->writesize);
1047 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1048 return 0;
1049 }
1050
1051 /**
1052 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1053 * @mtd: mtd info structure
1054 * @chip: nand chip info structure
1055 * @buf: buffer to store read data
1056 * @page: page number to read
1057 *
1058 * We need a special oob layout and handling even when OOB isn't used.
1059 */
1060 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1061 struct nand_chip *chip,
1062 uint8_t *buf, int page)
1063 {
1064 int eccsize = chip->ecc.size;
1065 int eccbytes = chip->ecc.bytes;
1066 uint8_t *oob = chip->oob_poi;
1067 int steps, size;
1068
1069 for (steps = chip->ecc.steps; steps > 0; steps--) {
1070 chip->read_buf(mtd, buf, eccsize);
1071 buf += eccsize;
1072
1073 if (chip->ecc.prepad) {
1074 chip->read_buf(mtd, oob, chip->ecc.prepad);
1075 oob += chip->ecc.prepad;
1076 }
1077
1078 chip->read_buf(mtd, oob, eccbytes);
1079 oob += eccbytes;
1080
1081 if (chip->ecc.postpad) {
1082 chip->read_buf(mtd, oob, chip->ecc.postpad);
1083 oob += chip->ecc.postpad;
1084 }
1085 }
1086
1087 size = mtd->oobsize - (oob - chip->oob_poi);
1088 if (size)
1089 chip->read_buf(mtd, oob, size);
1090
1091 return 0;
1092 }
1093
1094 /**
1095 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1096 * @mtd: mtd info structure
1097 * @chip: nand chip info structure
1098 * @buf: buffer to store read data
1099 * @page: page number to read
1100 */
1101 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1102 uint8_t *buf, int page)
1103 {
1104 int i, eccsize = chip->ecc.size;
1105 int eccbytes = chip->ecc.bytes;
1106 int eccsteps = chip->ecc.steps;
1107 uint8_t *p = buf;
1108 uint8_t *ecc_calc = chip->buffers->ecccalc;
1109 uint8_t *ecc_code = chip->buffers->ecccode;
1110 uint32_t *eccpos = chip->ecc.layout->eccpos;
1111
1112 chip->ecc.read_page_raw(mtd, chip, buf, page);
1113
1114 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1115 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1116
1117 for (i = 0; i < chip->ecc.total; i++)
1118 ecc_code[i] = chip->oob_poi[eccpos[i]];
1119
1120 eccsteps = chip->ecc.steps;
1121 p = buf;
1122
1123 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1124 int stat;
1125
1126 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1127 if (stat < 0)
1128 mtd->ecc_stats.failed++;
1129 else
1130 mtd->ecc_stats.corrected += stat;
1131 }
1132 return 0;
1133 }
1134
1135 /**
1136 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1137 * @mtd: mtd info structure
1138 * @chip: nand chip info structure
1139 * @data_offs: offset of requested data within the page
1140 * @readlen: data length
1141 * @bufpoi: buffer to store read data
1142 */
1143 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1144 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1145 {
1146 int start_step, end_step, num_steps;
1147 uint32_t *eccpos = chip->ecc.layout->eccpos;
1148 uint8_t *p;
1149 int data_col_addr, i, gaps = 0;
1150 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1151 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1152 int index = 0;
1153
1154 /* Column address within the page aligned to ECC size (256bytes) */
1155 start_step = data_offs / chip->ecc.size;
1156 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1157 num_steps = end_step - start_step + 1;
1158
1159 /* Data size aligned to ECC ecc.size */
1160 datafrag_len = num_steps * chip->ecc.size;
1161 eccfrag_len = num_steps * chip->ecc.bytes;
1162
1163 data_col_addr = start_step * chip->ecc.size;
1164 /* If we read not a page aligned data */
1165 if (data_col_addr != 0)
1166 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1167
1168 p = bufpoi + data_col_addr;
1169 chip->read_buf(mtd, p, datafrag_len);
1170
1171 /* Calculate ECC */
1172 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1173 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1174
1175 /*
1176 * The performance is faster if we position offsets according to
1177 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1178 */
1179 for (i = 0; i < eccfrag_len - 1; i++) {
1180 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1181 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1182 gaps = 1;
1183 break;
1184 }
1185 }
1186 if (gaps) {
1187 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1188 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1189 } else {
1190 /*
1191 * Send the command to read the particular ECC bytes take care
1192 * about buswidth alignment in read_buf.
1193 */
1194 index = start_step * chip->ecc.bytes;
1195
1196 aligned_pos = eccpos[index] & ~(busw - 1);
1197 aligned_len = eccfrag_len;
1198 if (eccpos[index] & (busw - 1))
1199 aligned_len++;
1200 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1201 aligned_len++;
1202
1203 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1204 mtd->writesize + aligned_pos, -1);
1205 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1206 }
1207
1208 for (i = 0; i < eccfrag_len; i++)
1209 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1210
1211 p = bufpoi + data_col_addr;
1212 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1213 int stat;
1214
1215 stat = chip->ecc.correct(mtd, p,
1216 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1217 if (stat < 0)
1218 mtd->ecc_stats.failed++;
1219 else
1220 mtd->ecc_stats.corrected += stat;
1221 }
1222 return 0;
1223 }
1224
1225 /**
1226 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1227 * @mtd: mtd info structure
1228 * @chip: nand chip info structure
1229 * @buf: buffer to store read data
1230 * @page: page number to read
1231 *
1232 * Not for syndrome calculating ECC controllers which need a special oob layout.
1233 */
1234 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1235 uint8_t *buf, int page)
1236 {
1237 int i, eccsize = chip->ecc.size;
1238 int eccbytes = chip->ecc.bytes;
1239 int eccsteps = chip->ecc.steps;
1240 uint8_t *p = buf;
1241 uint8_t *ecc_calc = chip->buffers->ecccalc;
1242 uint8_t *ecc_code = chip->buffers->ecccode;
1243 uint32_t *eccpos = chip->ecc.layout->eccpos;
1244
1245 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1246 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1247 chip->read_buf(mtd, p, eccsize);
1248 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1249 }
1250 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1251
1252 for (i = 0; i < chip->ecc.total; i++)
1253 ecc_code[i] = chip->oob_poi[eccpos[i]];
1254
1255 eccsteps = chip->ecc.steps;
1256 p = buf;
1257
1258 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1259 int stat;
1260
1261 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1262 if (stat < 0)
1263 mtd->ecc_stats.failed++;
1264 else
1265 mtd->ecc_stats.corrected += stat;
1266 }
1267 return 0;
1268 }
1269
1270 /**
1271 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1272 * @mtd: mtd info structure
1273 * @chip: nand chip info structure
1274 * @buf: buffer to store read data
1275 * @page: page number to read
1276 *
1277 * Hardware ECC for large page chips, require OOB to be read first. For this
1278 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1279 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1280 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1281 * the data area, by overwriting the NAND manufacturer bad block markings.
1282 */
1283 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1284 struct nand_chip *chip, uint8_t *buf, int page)
1285 {
1286 int i, eccsize = chip->ecc.size;
1287 int eccbytes = chip->ecc.bytes;
1288 int eccsteps = chip->ecc.steps;
1289 uint8_t *p = buf;
1290 uint8_t *ecc_code = chip->buffers->ecccode;
1291 uint32_t *eccpos = chip->ecc.layout->eccpos;
1292 uint8_t *ecc_calc = chip->buffers->ecccalc;
1293
1294 /* Read the OOB area first */
1295 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1296 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1297 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1298
1299 for (i = 0; i < chip->ecc.total; i++)
1300 ecc_code[i] = chip->oob_poi[eccpos[i]];
1301
1302 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1303 int stat;
1304
1305 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1306 chip->read_buf(mtd, p, eccsize);
1307 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1308
1309 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1310 if (stat < 0)
1311 mtd->ecc_stats.failed++;
1312 else
1313 mtd->ecc_stats.corrected += stat;
1314 }
1315 return 0;
1316 }
1317
1318 /**
1319 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1320 * @mtd: mtd info structure
1321 * @chip: nand chip info structure
1322 * @buf: buffer to store read data
1323 * @page: page number to read
1324 *
1325 * The hw generator calculates the error syndrome automatically. Therefore we
1326 * need a special oob layout and handling.
1327 */
1328 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1329 uint8_t *buf, int page)
1330 {
1331 int i, eccsize = chip->ecc.size;
1332 int eccbytes = chip->ecc.bytes;
1333 int eccsteps = chip->ecc.steps;
1334 uint8_t *p = buf;
1335 uint8_t *oob = chip->oob_poi;
1336
1337 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1338 int stat;
1339
1340 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1341 chip->read_buf(mtd, p, eccsize);
1342
1343 if (chip->ecc.prepad) {
1344 chip->read_buf(mtd, oob, chip->ecc.prepad);
1345 oob += chip->ecc.prepad;
1346 }
1347
1348 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1349 chip->read_buf(mtd, oob, eccbytes);
1350 stat = chip->ecc.correct(mtd, p, oob, NULL);
1351
1352 if (stat < 0)
1353 mtd->ecc_stats.failed++;
1354 else
1355 mtd->ecc_stats.corrected += stat;
1356
1357 oob += eccbytes;
1358
1359 if (chip->ecc.postpad) {
1360 chip->read_buf(mtd, oob, chip->ecc.postpad);
1361 oob += chip->ecc.postpad;
1362 }
1363 }
1364
1365 /* Calculate remaining oob bytes */
1366 i = mtd->oobsize - (oob - chip->oob_poi);
1367 if (i)
1368 chip->read_buf(mtd, oob, i);
1369
1370 return 0;
1371 }
1372
1373 /**
1374 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1375 * @chip: nand chip structure
1376 * @oob: oob destination address
1377 * @ops: oob ops structure
1378 * @len: size of oob to transfer
1379 */
1380 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1381 struct mtd_oob_ops *ops, size_t len)
1382 {
1383 switch (ops->mode) {
1384
1385 case MTD_OOB_PLACE:
1386 case MTD_OOB_RAW:
1387 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1388 return oob + len;
1389
1390 case MTD_OOB_AUTO: {
1391 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1392 uint32_t boffs = 0, roffs = ops->ooboffs;
1393 size_t bytes = 0;
1394
1395 for (; free->length && len; free++, len -= bytes) {
1396 /* Read request not from offset 0? */
1397 if (unlikely(roffs)) {
1398 if (roffs >= free->length) {
1399 roffs -= free->length;
1400 continue;
1401 }
1402 boffs = free->offset + roffs;
1403 bytes = min_t(size_t, len,
1404 (free->length - roffs));
1405 roffs = 0;
1406 } else {
1407 bytes = min_t(size_t, len, free->length);
1408 boffs = free->offset;
1409 }
1410 memcpy(oob, chip->oob_poi + boffs, bytes);
1411 oob += bytes;
1412 }
1413 return oob;
1414 }
1415 default:
1416 BUG();
1417 }
1418 return NULL;
1419 }
1420
1421 /**
1422 * nand_do_read_ops - [INTERN] Read data with ECC
1423 * @mtd: MTD device structure
1424 * @from: offset to read from
1425 * @ops: oob ops structure
1426 *
1427 * Internal function. Called with chip held.
1428 */
1429 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1430 struct mtd_oob_ops *ops)
1431 {
1432 int chipnr, page, realpage, col, bytes, aligned;
1433 struct nand_chip *chip = mtd->priv;
1434 struct mtd_ecc_stats stats;
1435 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1436 int sndcmd = 1;
1437 int ret = 0;
1438 uint32_t readlen = ops->len;
1439 uint32_t oobreadlen = ops->ooblen;
1440 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1441 mtd->oobavail : mtd->oobsize;
1442
1443 uint8_t *bufpoi, *oob, *buf;
1444
1445 stats = mtd->ecc_stats;
1446
1447 chipnr = (int)(from >> chip->chip_shift);
1448 chip->select_chip(mtd, chipnr);
1449
1450 realpage = (int)(from >> chip->page_shift);
1451 page = realpage & chip->pagemask;
1452
1453 col = (int)(from & (mtd->writesize - 1));
1454
1455 buf = ops->datbuf;
1456 oob = ops->oobbuf;
1457
1458 while (1) {
1459 bytes = min(mtd->writesize - col, readlen);
1460 aligned = (bytes == mtd->writesize);
1461
1462 /* Is the current page in the buffer? */
1463 if (realpage != chip->pagebuf || oob) {
1464 bufpoi = aligned ? buf : chip->buffers->databuf;
1465
1466 if (likely(sndcmd)) {
1467 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1468 sndcmd = 0;
1469 }
1470
1471 /* Now read the page into the buffer */
1472 if (unlikely(ops->mode == MTD_OOB_RAW))
1473 ret = chip->ecc.read_page_raw(mtd, chip,
1474 bufpoi, page);
1475 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1476 ret = chip->ecc.read_subpage(mtd, chip,
1477 col, bytes, bufpoi);
1478 else
1479 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1480 page);
1481 if (ret < 0)
1482 break;
1483
1484 /* Transfer not aligned data */
1485 if (!aligned) {
1486 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1487 !(mtd->ecc_stats.failed - stats.failed))
1488 chip->pagebuf = realpage;
1489 memcpy(buf, chip->buffers->databuf + col, bytes);
1490 }
1491
1492 buf += bytes;
1493
1494 if (unlikely(oob)) {
1495
1496 int toread = min(oobreadlen, max_oobsize);
1497
1498 if (toread) {
1499 oob = nand_transfer_oob(chip,
1500 oob, ops, toread);
1501 oobreadlen -= toread;
1502 }
1503 }
1504
1505 if (!(chip->options & NAND_NO_READRDY)) {
1506 /*
1507 * Apply delay or wait for ready/busy pin. Do
1508 * this before the AUTOINCR check, so no
1509 * problems arise if a chip which does auto
1510 * increment is marked as NOAUTOINCR by the
1511 * board driver.
1512 */
1513 if (!chip->dev_ready)
1514 udelay(chip->chip_delay);
1515 else
1516 nand_wait_ready(mtd);
1517 }
1518 } else {
1519 memcpy(buf, chip->buffers->databuf + col, bytes);
1520 buf += bytes;
1521 }
1522
1523 readlen -= bytes;
1524
1525 if (!readlen)
1526 break;
1527
1528 /* For subsequent reads align to page boundary */
1529 col = 0;
1530 /* Increment page address */
1531 realpage++;
1532
1533 page = realpage & chip->pagemask;
1534 /* Check, if we cross a chip boundary */
1535 if (!page) {
1536 chipnr++;
1537 chip->select_chip(mtd, -1);
1538 chip->select_chip(mtd, chipnr);
1539 }
1540
1541 /*
1542 * Check, if the chip supports auto page increment or if we
1543 * have hit a block boundary.
1544 */
1545 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1546 sndcmd = 1;
1547 }
1548
1549 ops->retlen = ops->len - (size_t) readlen;
1550 if (oob)
1551 ops->oobretlen = ops->ooblen - oobreadlen;
1552
1553 if (ret)
1554 return ret;
1555
1556 if (mtd->ecc_stats.failed - stats.failed)
1557 return -EBADMSG;
1558
1559 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1560 }
1561
1562 /**
1563 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1564 * @mtd: MTD device structure
1565 * @from: offset to read from
1566 * @len: number of bytes to read
1567 * @retlen: pointer to variable to store the number of read bytes
1568 * @buf: the databuffer to put data
1569 *
1570 * Get hold of the chip and call nand_do_read.
1571 */
1572 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1573 size_t *retlen, uint8_t *buf)
1574 {
1575 struct nand_chip *chip = mtd->priv;
1576 int ret;
1577
1578 /* Do not allow reads past end of device */
1579 if ((from + len) > mtd->size)
1580 return -EINVAL;
1581 if (!len)
1582 return 0;
1583
1584 nand_get_device(chip, mtd, FL_READING);
1585
1586 chip->ops.len = len;
1587 chip->ops.datbuf = buf;
1588 chip->ops.oobbuf = NULL;
1589
1590 ret = nand_do_read_ops(mtd, from, &chip->ops);
1591
1592 *retlen = chip->ops.retlen;
1593
1594 nand_release_device(mtd);
1595
1596 return ret;
1597 }
1598
1599 /**
1600 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1601 * @mtd: mtd info structure
1602 * @chip: nand chip info structure
1603 * @page: page number to read
1604 * @sndcmd: flag whether to issue read command or not
1605 */
1606 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1607 int page, int sndcmd)
1608 {
1609 if (sndcmd) {
1610 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1611 sndcmd = 0;
1612 }
1613 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1614 return sndcmd;
1615 }
1616
1617 /**
1618 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1619 * with syndromes
1620 * @mtd: mtd info structure
1621 * @chip: nand chip info structure
1622 * @page: page number to read
1623 * @sndcmd: flag whether to issue read command or not
1624 */
1625 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1626 int page, int sndcmd)
1627 {
1628 uint8_t *buf = chip->oob_poi;
1629 int length = mtd->oobsize;
1630 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1631 int eccsize = chip->ecc.size;
1632 uint8_t *bufpoi = buf;
1633 int i, toread, sndrnd = 0, pos;
1634
1635 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1636 for (i = 0; i < chip->ecc.steps; i++) {
1637 if (sndrnd) {
1638 pos = eccsize + i * (eccsize + chunk);
1639 if (mtd->writesize > 512)
1640 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1641 else
1642 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1643 } else
1644 sndrnd = 1;
1645 toread = min_t(int, length, chunk);
1646 chip->read_buf(mtd, bufpoi, toread);
1647 bufpoi += toread;
1648 length -= toread;
1649 }
1650 if (length > 0)
1651 chip->read_buf(mtd, bufpoi, length);
1652
1653 return 1;
1654 }
1655
1656 /**
1657 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1658 * @mtd: mtd info structure
1659 * @chip: nand chip info structure
1660 * @page: page number to write
1661 */
1662 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1663 int page)
1664 {
1665 int status = 0;
1666 const uint8_t *buf = chip->oob_poi;
1667 int length = mtd->oobsize;
1668
1669 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1670 chip->write_buf(mtd, buf, length);
1671 /* Send command to program the OOB data */
1672 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1673
1674 status = chip->waitfunc(mtd, chip);
1675
1676 return status & NAND_STATUS_FAIL ? -EIO : 0;
1677 }
1678
1679 /**
1680 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1681 * with syndrome - only for large page flash
1682 * @mtd: mtd info structure
1683 * @chip: nand chip info structure
1684 * @page: page number to write
1685 */
1686 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1687 struct nand_chip *chip, int page)
1688 {
1689 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1690 int eccsize = chip->ecc.size, length = mtd->oobsize;
1691 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1692 const uint8_t *bufpoi = chip->oob_poi;
1693
1694 /*
1695 * data-ecc-data-ecc ... ecc-oob
1696 * or
1697 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1698 */
1699 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1700 pos = steps * (eccsize + chunk);
1701 steps = 0;
1702 } else
1703 pos = eccsize;
1704
1705 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1706 for (i = 0; i < steps; i++) {
1707 if (sndcmd) {
1708 if (mtd->writesize <= 512) {
1709 uint32_t fill = 0xFFFFFFFF;
1710
1711 len = eccsize;
1712 while (len > 0) {
1713 int num = min_t(int, len, 4);
1714 chip->write_buf(mtd, (uint8_t *)&fill,
1715 num);
1716 len -= num;
1717 }
1718 } else {
1719 pos = eccsize + i * (eccsize + chunk);
1720 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1721 }
1722 } else
1723 sndcmd = 1;
1724 len = min_t(int, length, chunk);
1725 chip->write_buf(mtd, bufpoi, len);
1726 bufpoi += len;
1727 length -= len;
1728 }
1729 if (length > 0)
1730 chip->write_buf(mtd, bufpoi, length);
1731
1732 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1733 status = chip->waitfunc(mtd, chip);
1734
1735 return status & NAND_STATUS_FAIL ? -EIO : 0;
1736 }
1737
1738 /**
1739 * nand_do_read_oob - [INTERN] NAND read out-of-band
1740 * @mtd: MTD device structure
1741 * @from: offset to read from
1742 * @ops: oob operations description structure
1743 *
1744 * NAND read out-of-band data from the spare area.
1745 */
1746 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1747 struct mtd_oob_ops *ops)
1748 {
1749 int page, realpage, chipnr, sndcmd = 1;
1750 struct nand_chip *chip = mtd->priv;
1751 struct mtd_ecc_stats stats;
1752 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1753 int readlen = ops->ooblen;
1754 int len;
1755 uint8_t *buf = ops->oobbuf;
1756
1757 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1758 __func__, (unsigned long long)from, readlen);
1759
1760 stats = mtd->ecc_stats;
1761
1762 if (ops->mode == MTD_OOB_AUTO)
1763 len = chip->ecc.layout->oobavail;
1764 else
1765 len = mtd->oobsize;
1766
1767 if (unlikely(ops->ooboffs >= len)) {
1768 pr_debug("%s: attempt to start read outside oob\n",
1769 __func__);
1770 return -EINVAL;
1771 }
1772
1773 /* Do not allow reads past end of device */
1774 if (unlikely(from >= mtd->size ||
1775 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1776 (from >> chip->page_shift)) * len)) {
1777 pr_debug("%s: attempt to read beyond end of device\n",
1778 __func__);
1779 return -EINVAL;
1780 }
1781
1782 chipnr = (int)(from >> chip->chip_shift);
1783 chip->select_chip(mtd, chipnr);
1784
1785 /* Shift to get page */
1786 realpage = (int)(from >> chip->page_shift);
1787 page = realpage & chip->pagemask;
1788
1789 while (1) {
1790 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1791
1792 len = min(len, readlen);
1793 buf = nand_transfer_oob(chip, buf, ops, len);
1794
1795 if (!(chip->options & NAND_NO_READRDY)) {
1796 /*
1797 * Apply delay or wait for ready/busy pin. Do this
1798 * before the AUTOINCR check, so no problems arise if a
1799 * chip which does auto increment is marked as
1800 * NOAUTOINCR by the board driver.
1801 */
1802 if (!chip->dev_ready)
1803 udelay(chip->chip_delay);
1804 else
1805 nand_wait_ready(mtd);
1806 }
1807
1808 readlen -= len;
1809 if (!readlen)
1810 break;
1811
1812 /* Increment page address */
1813 realpage++;
1814
1815 page = realpage & chip->pagemask;
1816 /* Check, if we cross a chip boundary */
1817 if (!page) {
1818 chipnr++;
1819 chip->select_chip(mtd, -1);
1820 chip->select_chip(mtd, chipnr);
1821 }
1822
1823 /*
1824 * Check, if the chip supports auto page increment or if we
1825 * have hit a block boundary.
1826 */
1827 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1828 sndcmd = 1;
1829 }
1830
1831 ops->oobretlen = ops->ooblen;
1832
1833 if (mtd->ecc_stats.failed - stats.failed)
1834 return -EBADMSG;
1835
1836 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1837 }
1838
1839 /**
1840 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1841 * @mtd: MTD device structure
1842 * @from: offset to read from
1843 * @ops: oob operation description structure
1844 *
1845 * NAND read data and/or out-of-band data.
1846 */
1847 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1848 struct mtd_oob_ops *ops)
1849 {
1850 struct nand_chip *chip = mtd->priv;
1851 int ret = -ENOTSUPP;
1852
1853 ops->retlen = 0;
1854
1855 /* Do not allow reads past end of device */
1856 if (ops->datbuf && (from + ops->len) > mtd->size) {
1857 pr_debug("%s: attempt to read beyond end of device\n",
1858 __func__);
1859 return -EINVAL;
1860 }
1861
1862 nand_get_device(chip, mtd, FL_READING);
1863
1864 switch (ops->mode) {
1865 case MTD_OOB_PLACE:
1866 case MTD_OOB_AUTO:
1867 case MTD_OOB_RAW:
1868 break;
1869
1870 default:
1871 goto out;
1872 }
1873
1874 if (!ops->datbuf)
1875 ret = nand_do_read_oob(mtd, from, ops);
1876 else
1877 ret = nand_do_read_ops(mtd, from, ops);
1878
1879 out:
1880 nand_release_device(mtd);
1881 return ret;
1882 }
1883
1884
1885 /**
1886 * nand_write_page_raw - [INTERN] raw page write function
1887 * @mtd: mtd info structure
1888 * @chip: nand chip info structure
1889 * @buf: data buffer
1890 *
1891 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1892 */
1893 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1894 const uint8_t *buf)
1895 {
1896 chip->write_buf(mtd, buf, mtd->writesize);
1897 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1898 }
1899
1900 /**
1901 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1902 * @mtd: mtd info structure
1903 * @chip: nand chip info structure
1904 * @buf: data buffer
1905 *
1906 * We need a special oob layout and handling even when ECC isn't checked.
1907 */
1908 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1909 struct nand_chip *chip,
1910 const uint8_t *buf)
1911 {
1912 int eccsize = chip->ecc.size;
1913 int eccbytes = chip->ecc.bytes;
1914 uint8_t *oob = chip->oob_poi;
1915 int steps, size;
1916
1917 for (steps = chip->ecc.steps; steps > 0; steps--) {
1918 chip->write_buf(mtd, buf, eccsize);
1919 buf += eccsize;
1920
1921 if (chip->ecc.prepad) {
1922 chip->write_buf(mtd, oob, chip->ecc.prepad);
1923 oob += chip->ecc.prepad;
1924 }
1925
1926 chip->read_buf(mtd, oob, eccbytes);
1927 oob += eccbytes;
1928
1929 if (chip->ecc.postpad) {
1930 chip->write_buf(mtd, oob, chip->ecc.postpad);
1931 oob += chip->ecc.postpad;
1932 }
1933 }
1934
1935 size = mtd->oobsize - (oob - chip->oob_poi);
1936 if (size)
1937 chip->write_buf(mtd, oob, size);
1938 }
1939 /**
1940 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1941 * @mtd: mtd info structure
1942 * @chip: nand chip info structure
1943 * @buf: data buffer
1944 */
1945 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1946 const uint8_t *buf)
1947 {
1948 int i, eccsize = chip->ecc.size;
1949 int eccbytes = chip->ecc.bytes;
1950 int eccsteps = chip->ecc.steps;
1951 uint8_t *ecc_calc = chip->buffers->ecccalc;
1952 const uint8_t *p = buf;
1953 uint32_t *eccpos = chip->ecc.layout->eccpos;
1954
1955 /* Software ECC calculation */
1956 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1957 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1958
1959 for (i = 0; i < chip->ecc.total; i++)
1960 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1961
1962 chip->ecc.write_page_raw(mtd, chip, buf);
1963 }
1964
1965 /**
1966 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1967 * @mtd: mtd info structure
1968 * @chip: nand chip info structure
1969 * @buf: data buffer
1970 */
1971 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1972 const uint8_t *buf)
1973 {
1974 int i, eccsize = chip->ecc.size;
1975 int eccbytes = chip->ecc.bytes;
1976 int eccsteps = chip->ecc.steps;
1977 uint8_t *ecc_calc = chip->buffers->ecccalc;
1978 const uint8_t *p = buf;
1979 uint32_t *eccpos = chip->ecc.layout->eccpos;
1980
1981 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1982 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1983 chip->write_buf(mtd, p, eccsize);
1984 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1985 }
1986
1987 for (i = 0; i < chip->ecc.total; i++)
1988 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1989
1990 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1991 }
1992
1993 /**
1994 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1995 * @mtd: mtd info structure
1996 * @chip: nand chip info structure
1997 * @buf: data buffer
1998 *
1999 * The hw generator calculates the error syndrome automatically. Therefore we
2000 * need a special oob layout and handling.
2001 */
2002 static void nand_write_page_syndrome(struct mtd_info *mtd,
2003 struct nand_chip *chip, const uint8_t *buf)
2004 {
2005 int i, eccsize = chip->ecc.size;
2006 int eccbytes = chip->ecc.bytes;
2007 int eccsteps = chip->ecc.steps;
2008 const uint8_t *p = buf;
2009 uint8_t *oob = chip->oob_poi;
2010
2011 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2012
2013 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2014 chip->write_buf(mtd, p, eccsize);
2015
2016 if (chip->ecc.prepad) {
2017 chip->write_buf(mtd, oob, chip->ecc.prepad);
2018 oob += chip->ecc.prepad;
2019 }
2020
2021 chip->ecc.calculate(mtd, p, oob);
2022 chip->write_buf(mtd, oob, eccbytes);
2023 oob += eccbytes;
2024
2025 if (chip->ecc.postpad) {
2026 chip->write_buf(mtd, oob, chip->ecc.postpad);
2027 oob += chip->ecc.postpad;
2028 }
2029 }
2030
2031 /* Calculate remaining oob bytes */
2032 i = mtd->oobsize - (oob - chip->oob_poi);
2033 if (i)
2034 chip->write_buf(mtd, oob, i);
2035 }
2036
2037 /**
2038 * nand_write_page - [REPLACEABLE] write one page
2039 * @mtd: MTD device structure
2040 * @chip: NAND chip descriptor
2041 * @buf: the data to write
2042 * @page: page number to write
2043 * @cached: cached programming
2044 * @raw: use _raw version of write_page
2045 */
2046 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2047 const uint8_t *buf, int page, int cached, int raw)
2048 {
2049 int status;
2050
2051 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2052
2053 if (unlikely(raw))
2054 chip->ecc.write_page_raw(mtd, chip, buf);
2055 else
2056 chip->ecc.write_page(mtd, chip, buf);
2057
2058 /*
2059 * Cached progamming disabled for now. Not sure if it's worth the
2060 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2061 */
2062 cached = 0;
2063
2064 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2065
2066 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2067 status = chip->waitfunc(mtd, chip);
2068 /*
2069 * See if operation failed and additional status checks are
2070 * available.
2071 */
2072 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2073 status = chip->errstat(mtd, chip, FL_WRITING, status,
2074 page);
2075
2076 if (status & NAND_STATUS_FAIL)
2077 return -EIO;
2078 } else {
2079 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2080 status = chip->waitfunc(mtd, chip);
2081 }
2082
2083 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2084 /* Send command to read back the data */
2085 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2086
2087 if (chip->verify_buf(mtd, buf, mtd->writesize))
2088 return -EIO;
2089 #endif
2090 return 0;
2091 }
2092
2093 /**
2094 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2095 * @mtd: MTD device structure
2096 * @oob: oob data buffer
2097 * @len: oob data write length
2098 * @ops: oob ops structure
2099 */
2100 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2101 struct mtd_oob_ops *ops)
2102 {
2103 struct nand_chip *chip = mtd->priv;
2104
2105 /*
2106 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2107 * data from a previous OOB read.
2108 */
2109 memset(chip->oob_poi, 0xff, mtd->oobsize);
2110
2111 switch (ops->mode) {
2112
2113 case MTD_OOB_PLACE:
2114 case MTD_OOB_RAW:
2115 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2116 return oob + len;
2117
2118 case MTD_OOB_AUTO: {
2119 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2120 uint32_t boffs = 0, woffs = ops->ooboffs;
2121 size_t bytes = 0;
2122
2123 for (; free->length && len; free++, len -= bytes) {
2124 /* Write request not from offset 0? */
2125 if (unlikely(woffs)) {
2126 if (woffs >= free->length) {
2127 woffs -= free->length;
2128 continue;
2129 }
2130 boffs = free->offset + woffs;
2131 bytes = min_t(size_t, len,
2132 (free->length - woffs));
2133 woffs = 0;
2134 } else {
2135 bytes = min_t(size_t, len, free->length);
2136 boffs = free->offset;
2137 }
2138 memcpy(chip->oob_poi + boffs, oob, bytes);
2139 oob += bytes;
2140 }
2141 return oob;
2142 }
2143 default:
2144 BUG();
2145 }
2146 return NULL;
2147 }
2148
2149 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2150
2151 /**
2152 * nand_do_write_ops - [INTERN] NAND write with ECC
2153 * @mtd: MTD device structure
2154 * @to: offset to write to
2155 * @ops: oob operations description structure
2156 *
2157 * NAND write with ECC.
2158 */
2159 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2160 struct mtd_oob_ops *ops)
2161 {
2162 int chipnr, realpage, page, blockmask, column;
2163 struct nand_chip *chip = mtd->priv;
2164 uint32_t writelen = ops->len;
2165
2166 uint32_t oobwritelen = ops->ooblen;
2167 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2168 mtd->oobavail : mtd->oobsize;
2169
2170 uint8_t *oob = ops->oobbuf;
2171 uint8_t *buf = ops->datbuf;
2172 int ret, subpage;
2173
2174 ops->retlen = 0;
2175 if (!writelen)
2176 return 0;
2177
2178 /* Reject writes, which are not page aligned */
2179 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2180 pr_notice("%s: attempt to write non page aligned data\n",
2181 __func__);
2182 return -EINVAL;
2183 }
2184
2185 column = to & (mtd->writesize - 1);
2186 subpage = column || (writelen & (mtd->writesize - 1));
2187
2188 if (subpage && oob)
2189 return -EINVAL;
2190
2191 chipnr = (int)(to >> chip->chip_shift);
2192 chip->select_chip(mtd, chipnr);
2193
2194 /* Check, if it is write protected */
2195 if (nand_check_wp(mtd))
2196 return -EIO;
2197
2198 realpage = (int)(to >> chip->page_shift);
2199 page = realpage & chip->pagemask;
2200 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2201
2202 /* Invalidate the page cache, when we write to the cached page */
2203 if (to <= (chip->pagebuf << chip->page_shift) &&
2204 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2205 chip->pagebuf = -1;
2206
2207 /* Don't allow multipage oob writes with offset */
2208 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2209 return -EINVAL;
2210
2211 while (1) {
2212 int bytes = mtd->writesize;
2213 int cached = writelen > bytes && page != blockmask;
2214 uint8_t *wbuf = buf;
2215
2216 /* Partial page write? */
2217 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2218 cached = 0;
2219 bytes = min_t(int, bytes - column, (int) writelen);
2220 chip->pagebuf = -1;
2221 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2222 memcpy(&chip->buffers->databuf[column], buf, bytes);
2223 wbuf = chip->buffers->databuf;
2224 }
2225
2226 if (unlikely(oob)) {
2227 size_t len = min(oobwritelen, oobmaxlen);
2228 oob = nand_fill_oob(mtd, oob, len, ops);
2229 oobwritelen -= len;
2230 }
2231
2232 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2233 (ops->mode == MTD_OOB_RAW));
2234 if (ret)
2235 break;
2236
2237 writelen -= bytes;
2238 if (!writelen)
2239 break;
2240
2241 column = 0;
2242 buf += bytes;
2243 realpage++;
2244
2245 page = realpage & chip->pagemask;
2246 /* Check, if we cross a chip boundary */
2247 if (!page) {
2248 chipnr++;
2249 chip->select_chip(mtd, -1);
2250 chip->select_chip(mtd, chipnr);
2251 }
2252 }
2253
2254 ops->retlen = ops->len - writelen;
2255 if (unlikely(oob))
2256 ops->oobretlen = ops->ooblen;
2257 return ret;
2258 }
2259
2260 /**
2261 * panic_nand_write - [MTD Interface] NAND write with ECC
2262 * @mtd: MTD device structure
2263 * @to: offset to write to
2264 * @len: number of bytes to write
2265 * @retlen: pointer to variable to store the number of written bytes
2266 * @buf: the data to write
2267 *
2268 * NAND write with ECC. Used when performing writes in interrupt context, this
2269 * may for example be called by mtdoops when writing an oops while in panic.
2270 */
2271 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2272 size_t *retlen, const uint8_t *buf)
2273 {
2274 struct nand_chip *chip = mtd->priv;
2275 int ret;
2276
2277 /* Do not allow reads past end of device */
2278 if ((to + len) > mtd->size)
2279 return -EINVAL;
2280 if (!len)
2281 return 0;
2282
2283 /* Wait for the device to get ready */
2284 panic_nand_wait(mtd, chip, 400);
2285
2286 /* Grab the device */
2287 panic_nand_get_device(chip, mtd, FL_WRITING);
2288
2289 chip->ops.len = len;
2290 chip->ops.datbuf = (uint8_t *)buf;
2291 chip->ops.oobbuf = NULL;
2292
2293 ret = nand_do_write_ops(mtd, to, &chip->ops);
2294
2295 *retlen = chip->ops.retlen;
2296 return ret;
2297 }
2298
2299 /**
2300 * nand_write - [MTD Interface] NAND write with ECC
2301 * @mtd: MTD device structure
2302 * @to: offset to write to
2303 * @len: number of bytes to write
2304 * @retlen: pointer to variable to store the number of written bytes
2305 * @buf: the data to write
2306 *
2307 * NAND write with ECC.
2308 */
2309 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2310 size_t *retlen, const uint8_t *buf)
2311 {
2312 struct nand_chip *chip = mtd->priv;
2313 int ret;
2314
2315 /* Do not allow reads past end of device */
2316 if ((to + len) > mtd->size)
2317 return -EINVAL;
2318 if (!len)
2319 return 0;
2320
2321 nand_get_device(chip, mtd, FL_WRITING);
2322
2323 chip->ops.len = len;
2324 chip->ops.datbuf = (uint8_t *)buf;
2325 chip->ops.oobbuf = NULL;
2326
2327 ret = nand_do_write_ops(mtd, to, &chip->ops);
2328
2329 *retlen = chip->ops.retlen;
2330
2331 nand_release_device(mtd);
2332
2333 return ret;
2334 }
2335
2336 /**
2337 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2338 * @mtd: MTD device structure
2339 * @to: offset to write to
2340 * @ops: oob operation description structure
2341 *
2342 * NAND write out-of-band.
2343 */
2344 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2345 struct mtd_oob_ops *ops)
2346 {
2347 int chipnr, page, status, len;
2348 struct nand_chip *chip = mtd->priv;
2349
2350 pr_debug("%s: to = 0x%08x, len = %i\n",
2351 __func__, (unsigned int)to, (int)ops->ooblen);
2352
2353 if (ops->mode == MTD_OOB_AUTO)
2354 len = chip->ecc.layout->oobavail;
2355 else
2356 len = mtd->oobsize;
2357
2358 /* Do not allow write past end of page */
2359 if ((ops->ooboffs + ops->ooblen) > len) {
2360 pr_debug("%s: attempt to write past end of page\n",
2361 __func__);
2362 return -EINVAL;
2363 }
2364
2365 if (unlikely(ops->ooboffs >= len)) {
2366 pr_debug("%s: attempt to start write outside oob\n",
2367 __func__);
2368 return -EINVAL;
2369 }
2370
2371 /* Do not allow write past end of device */
2372 if (unlikely(to >= mtd->size ||
2373 ops->ooboffs + ops->ooblen >
2374 ((mtd->size >> chip->page_shift) -
2375 (to >> chip->page_shift)) * len)) {
2376 pr_debug("%s: attempt to write beyond end of device\n",
2377 __func__);
2378 return -EINVAL;
2379 }
2380
2381 chipnr = (int)(to >> chip->chip_shift);
2382 chip->select_chip(mtd, chipnr);
2383
2384 /* Shift to get page */
2385 page = (int)(to >> chip->page_shift);
2386
2387 /*
2388 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2389 * of my DiskOnChip 2000 test units) will clear the whole data page too
2390 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2391 * it in the doc2000 driver in August 1999. dwmw2.
2392 */
2393 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2394
2395 /* Check, if it is write protected */
2396 if (nand_check_wp(mtd))
2397 return -EROFS;
2398
2399 /* Invalidate the page cache, if we write to the cached page */
2400 if (page == chip->pagebuf)
2401 chip->pagebuf = -1;
2402
2403 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2404 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2405
2406 if (status)
2407 return status;
2408
2409 ops->oobretlen = ops->ooblen;
2410
2411 return 0;
2412 }
2413
2414 /**
2415 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2416 * @mtd: MTD device structure
2417 * @to: offset to write to
2418 * @ops: oob operation description structure
2419 */
2420 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2421 struct mtd_oob_ops *ops)
2422 {
2423 struct nand_chip *chip = mtd->priv;
2424 int ret = -ENOTSUPP;
2425
2426 ops->retlen = 0;
2427
2428 /* Do not allow writes past end of device */
2429 if (ops->datbuf && (to + ops->len) > mtd->size) {
2430 pr_debug("%s: attempt to write beyond end of device\n",
2431 __func__);
2432 return -EINVAL;
2433 }
2434
2435 nand_get_device(chip, mtd, FL_WRITING);
2436
2437 switch (ops->mode) {
2438 case MTD_OOB_PLACE:
2439 case MTD_OOB_AUTO:
2440 case MTD_OOB_RAW:
2441 break;
2442
2443 default:
2444 goto out;
2445 }
2446
2447 if (!ops->datbuf)
2448 ret = nand_do_write_oob(mtd, to, ops);
2449 else
2450 ret = nand_do_write_ops(mtd, to, ops);
2451
2452 out:
2453 nand_release_device(mtd);
2454 return ret;
2455 }
2456
2457 /**
2458 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2459 * @mtd: MTD device structure
2460 * @page: the page address of the block which will be erased
2461 *
2462 * Standard erase command for NAND chips.
2463 */
2464 static void single_erase_cmd(struct mtd_info *mtd, int page)
2465 {
2466 struct nand_chip *chip = mtd->priv;
2467 /* Send commands to erase a block */
2468 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2469 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2470 }
2471
2472 /**
2473 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2474 * @mtd: MTD device structure
2475 * @page: the page address of the block which will be erased
2476 *
2477 * AND multi block erase command function. Erase 4 consecutive blocks.
2478 */
2479 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2480 {
2481 struct nand_chip *chip = mtd->priv;
2482 /* Send commands to erase a block */
2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2486 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2487 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2488 }
2489
2490 /**
2491 * nand_erase - [MTD Interface] erase block(s)
2492 * @mtd: MTD device structure
2493 * @instr: erase instruction
2494 *
2495 * Erase one ore more blocks.
2496 */
2497 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2498 {
2499 return nand_erase_nand(mtd, instr, 0);
2500 }
2501
2502 #define BBT_PAGE_MASK 0xffffff3f
2503 /**
2504 * nand_erase_nand - [INTERN] erase block(s)
2505 * @mtd: MTD device structure
2506 * @instr: erase instruction
2507 * @allowbbt: allow erasing the bbt area
2508 *
2509 * Erase one ore more blocks.
2510 */
2511 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2512 int allowbbt)
2513 {
2514 int page, status, pages_per_block, ret, chipnr;
2515 struct nand_chip *chip = mtd->priv;
2516 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2517 unsigned int bbt_masked_page = 0xffffffff;
2518 loff_t len;
2519
2520 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2521 __func__, (unsigned long long)instr->addr,
2522 (unsigned long long)instr->len);
2523
2524 if (check_offs_len(mtd, instr->addr, instr->len))
2525 return -EINVAL;
2526
2527 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2528
2529 /* Grab the lock and see if the device is available */
2530 nand_get_device(chip, mtd, FL_ERASING);
2531
2532 /* Shift to get first page */
2533 page = (int)(instr->addr >> chip->page_shift);
2534 chipnr = (int)(instr->addr >> chip->chip_shift);
2535
2536 /* Calculate pages in each block */
2537 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2538
2539 /* Select the NAND device */
2540 chip->select_chip(mtd, chipnr);
2541
2542 /* Check, if it is write protected */
2543 if (nand_check_wp(mtd)) {
2544 pr_debug("%s: device is write protected!\n",
2545 __func__);
2546 instr->state = MTD_ERASE_FAILED;
2547 goto erase_exit;
2548 }
2549
2550 /*
2551 * If BBT requires refresh, set the BBT page mask to see if the BBT
2552 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2553 * can not be matched. This is also done when the bbt is actually
2554 * erased to avoid recursive updates.
2555 */
2556 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2557 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2558
2559 /* Loop through the pages */
2560 len = instr->len;
2561
2562 instr->state = MTD_ERASING;
2563
2564 while (len) {
2565 /* Heck if we have a bad block, we do not erase bad blocks! */
2566 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2567 chip->page_shift, 0, allowbbt)) {
2568 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2569 __func__, page);
2570 instr->state = MTD_ERASE_FAILED;
2571 goto erase_exit;
2572 }
2573
2574 /*
2575 * Invalidate the page cache, if we erase the block which
2576 * contains the current cached page.
2577 */
2578 if (page <= chip->pagebuf && chip->pagebuf <
2579 (page + pages_per_block))
2580 chip->pagebuf = -1;
2581
2582 chip->erase_cmd(mtd, page & chip->pagemask);
2583
2584 status = chip->waitfunc(mtd, chip);
2585
2586 /*
2587 * See if operation failed and additional status checks are
2588 * available
2589 */
2590 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2591 status = chip->errstat(mtd, chip, FL_ERASING,
2592 status, page);
2593
2594 /* See if block erase succeeded */
2595 if (status & NAND_STATUS_FAIL) {
2596 pr_debug("%s: failed erase, page 0x%08x\n",
2597 __func__, page);
2598 instr->state = MTD_ERASE_FAILED;
2599 instr->fail_addr =
2600 ((loff_t)page << chip->page_shift);
2601 goto erase_exit;
2602 }
2603
2604 /*
2605 * If BBT requires refresh, set the BBT rewrite flag to the
2606 * page being erased.
2607 */
2608 if (bbt_masked_page != 0xffffffff &&
2609 (page & BBT_PAGE_MASK) == bbt_masked_page)
2610 rewrite_bbt[chipnr] =
2611 ((loff_t)page << chip->page_shift);
2612
2613 /* Increment page address and decrement length */
2614 len -= (1 << chip->phys_erase_shift);
2615 page += pages_per_block;
2616
2617 /* Check, if we cross a chip boundary */
2618 if (len && !(page & chip->pagemask)) {
2619 chipnr++;
2620 chip->select_chip(mtd, -1);
2621 chip->select_chip(mtd, chipnr);
2622
2623 /*
2624 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2625 * page mask to see if this BBT should be rewritten.
2626 */
2627 if (bbt_masked_page != 0xffffffff &&
2628 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2629 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2630 BBT_PAGE_MASK;
2631 }
2632 }
2633 instr->state = MTD_ERASE_DONE;
2634
2635 erase_exit:
2636
2637 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2638
2639 /* Deselect and wake up anyone waiting on the device */
2640 nand_release_device(mtd);
2641
2642 /* Do call back function */
2643 if (!ret)
2644 mtd_erase_callback(instr);
2645
2646 /*
2647 * If BBT requires refresh and erase was successful, rewrite any
2648 * selected bad block tables.
2649 */
2650 if (bbt_masked_page == 0xffffffff || ret)
2651 return ret;
2652
2653 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2654 if (!rewrite_bbt[chipnr])
2655 continue;
2656 /* Update the BBT for chip */
2657 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2658 __func__, chipnr, rewrite_bbt[chipnr],
2659 chip->bbt_td->pages[chipnr]);
2660 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2661 }
2662
2663 /* Return more or less happy */
2664 return ret;
2665 }
2666
2667 /**
2668 * nand_sync - [MTD Interface] sync
2669 * @mtd: MTD device structure
2670 *
2671 * Sync is actually a wait for chip ready function.
2672 */
2673 static void nand_sync(struct mtd_info *mtd)
2674 {
2675 struct nand_chip *chip = mtd->priv;
2676
2677 pr_debug("%s: called\n", __func__);
2678
2679 /* Grab the lock and see if the device is available */
2680 nand_get_device(chip, mtd, FL_SYNCING);
2681 /* Release it and go back */
2682 nand_release_device(mtd);
2683 }
2684
2685 /**
2686 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2687 * @mtd: MTD device structure
2688 * @offs: offset relative to mtd start
2689 */
2690 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2691 {
2692 /* Check for invalid offset */
2693 if (offs > mtd->size)
2694 return -EINVAL;
2695
2696 return nand_block_checkbad(mtd, offs, 1, 0);
2697 }
2698
2699 /**
2700 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2701 * @mtd: MTD device structure
2702 * @ofs: offset relative to mtd start
2703 */
2704 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2705 {
2706 struct nand_chip *chip = mtd->priv;
2707 int ret;
2708
2709 ret = nand_block_isbad(mtd, ofs);
2710 if (ret) {
2711 /* If it was bad already, return success and do nothing */
2712 if (ret > 0)
2713 return 0;
2714 return ret;
2715 }
2716
2717 return chip->block_markbad(mtd, ofs);
2718 }
2719
2720 /**
2721 * nand_suspend - [MTD Interface] Suspend the NAND flash
2722 * @mtd: MTD device structure
2723 */
2724 static int nand_suspend(struct mtd_info *mtd)
2725 {
2726 struct nand_chip *chip = mtd->priv;
2727
2728 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2729 }
2730
2731 /**
2732 * nand_resume - [MTD Interface] Resume the NAND flash
2733 * @mtd: MTD device structure
2734 */
2735 static void nand_resume(struct mtd_info *mtd)
2736 {
2737 struct nand_chip *chip = mtd->priv;
2738
2739 if (chip->state == FL_PM_SUSPENDED)
2740 nand_release_device(mtd);
2741 else
2742 pr_err("%s called for a chip which is not in suspended state\n",
2743 __func__);
2744 }
2745
2746 /* Set default functions */
2747 static void nand_set_defaults(struct nand_chip *chip, int busw)
2748 {
2749 /* check for proper chip_delay setup, set 20us if not */
2750 if (!chip->chip_delay)
2751 chip->chip_delay = 20;
2752
2753 /* check, if a user supplied command function given */
2754 if (chip->cmdfunc == NULL)
2755 chip->cmdfunc = nand_command;
2756
2757 /* check, if a user supplied wait function given */
2758 if (chip->waitfunc == NULL)
2759 chip->waitfunc = nand_wait;
2760
2761 if (!chip->select_chip)
2762 chip->select_chip = nand_select_chip;
2763 if (!chip->read_byte)
2764 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2765 if (!chip->read_word)
2766 chip->read_word = nand_read_word;
2767 if (!chip->block_bad)
2768 chip->block_bad = nand_block_bad;
2769 if (!chip->block_markbad)
2770 chip->block_markbad = nand_default_block_markbad;
2771 if (!chip->write_buf)
2772 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2773 if (!chip->read_buf)
2774 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2775 if (!chip->verify_buf)
2776 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2777 if (!chip->scan_bbt)
2778 chip->scan_bbt = nand_default_bbt;
2779
2780 if (!chip->controller) {
2781 chip->controller = &chip->hwcontrol;
2782 spin_lock_init(&chip->controller->lock);
2783 init_waitqueue_head(&chip->controller->wq);
2784 }
2785
2786 }
2787
2788 /* Sanitize ONFI strings so we can safely print them */
2789 static void sanitize_string(uint8_t *s, size_t len)
2790 {
2791 ssize_t i;
2792
2793 /* Null terminate */
2794 s[len - 1] = 0;
2795
2796 /* Remove non printable chars */
2797 for (i = 0; i < len - 1; i++) {
2798 if (s[i] < ' ' || s[i] > 127)
2799 s[i] = '?';
2800 }
2801
2802 /* Remove trailing spaces */
2803 strim(s);
2804 }
2805
2806 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2807 {
2808 int i;
2809 while (len--) {
2810 crc ^= *p++ << 8;
2811 for (i = 0; i < 8; i++)
2812 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2813 }
2814
2815 return crc;
2816 }
2817
2818 /*
2819 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2820 */
2821 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2822 int *busw)
2823 {
2824 struct nand_onfi_params *p = &chip->onfi_params;
2825 int i;
2826 int val;
2827
2828 /* Try ONFI for unknown chip or LP */
2829 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2830 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2831 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2832 return 0;
2833
2834 pr_info("ONFI flash detected\n");
2835 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2836 for (i = 0; i < 3; i++) {
2837 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2838 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2839 le16_to_cpu(p->crc)) {
2840 pr_info("ONFI param page %d valid\n", i);
2841 break;
2842 }
2843 }
2844
2845 if (i == 3)
2846 return 0;
2847
2848 /* Check version */
2849 val = le16_to_cpu(p->revision);
2850 if (val & (1 << 5))
2851 chip->onfi_version = 23;
2852 else if (val & (1 << 4))
2853 chip->onfi_version = 22;
2854 else if (val & (1 << 3))
2855 chip->onfi_version = 21;
2856 else if (val & (1 << 2))
2857 chip->onfi_version = 20;
2858 else if (val & (1 << 1))
2859 chip->onfi_version = 10;
2860 else
2861 chip->onfi_version = 0;
2862
2863 if (!chip->onfi_version) {
2864 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2865 return 0;
2866 }
2867
2868 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2869 sanitize_string(p->model, sizeof(p->model));
2870 if (!mtd->name)
2871 mtd->name = p->model;
2872 mtd->writesize = le32_to_cpu(p->byte_per_page);
2873 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2874 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2875 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2876 *busw = 0;
2877 if (le16_to_cpu(p->features) & 1)
2878 *busw = NAND_BUSWIDTH_16;
2879
2880 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2881 chip->options |= (NAND_NO_READRDY |
2882 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2883
2884 return 1;
2885 }
2886
2887 /*
2888 * Get the flash and manufacturer id and lookup if the type is supported.
2889 */
2890 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2891 struct nand_chip *chip,
2892 int busw,
2893 int *maf_id, int *dev_id,
2894 struct nand_flash_dev *type)
2895 {
2896 int i, maf_idx;
2897 u8 id_data[8];
2898 int ret;
2899
2900 /* Select the device */
2901 chip->select_chip(mtd, 0);
2902
2903 /*
2904 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2905 * after power-up.
2906 */
2907 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2908
2909 /* Send the command for reading device ID */
2910 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2911
2912 /* Read manufacturer and device IDs */
2913 *maf_id = chip->read_byte(mtd);
2914 *dev_id = chip->read_byte(mtd);
2915
2916 /*
2917 * Try again to make sure, as some systems the bus-hold or other
2918 * interface concerns can cause random data which looks like a
2919 * possibly credible NAND flash to appear. If the two results do
2920 * not match, ignore the device completely.
2921 */
2922
2923 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2924
2925 for (i = 0; i < 2; i++)
2926 id_data[i] = chip->read_byte(mtd);
2927
2928 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2929 pr_info("%s: second ID read did not match "
2930 "%02x,%02x against %02x,%02x\n", __func__,
2931 *maf_id, *dev_id, id_data[0], id_data[1]);
2932 return ERR_PTR(-ENODEV);
2933 }
2934
2935 if (!type)
2936 type = nand_flash_ids;
2937
2938 for (; type->name != NULL; type++)
2939 if (*dev_id == type->id)
2940 break;
2941
2942 chip->onfi_version = 0;
2943 if (!type->name || !type->pagesize) {
2944 /* Check is chip is ONFI compliant */
2945 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2946 if (ret)
2947 goto ident_done;
2948 }
2949
2950 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2951
2952 /* Read entire ID string */
2953
2954 for (i = 0; i < 8; i++)
2955 id_data[i] = chip->read_byte(mtd);
2956
2957 if (!type->name)
2958 return ERR_PTR(-ENODEV);
2959
2960 if (!mtd->name)
2961 mtd->name = type->name;
2962
2963 chip->chipsize = (uint64_t)type->chipsize << 20;
2964
2965 if (!type->pagesize && chip->init_size) {
2966 /* Set the pagesize, oobsize, erasesize by the driver */
2967 busw = chip->init_size(mtd, chip, id_data);
2968 } else if (!type->pagesize) {
2969 int extid;
2970 /* The 3rd id byte holds MLC / multichip data */
2971 chip->cellinfo = id_data[2];
2972 /* The 4th id byte is the important one */
2973 extid = id_data[3];
2974
2975 /*
2976 * Field definitions are in the following datasheets:
2977 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2978 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2979 *
2980 * Check for wraparound + Samsung ID + nonzero 6th byte
2981 * to decide what to do.
2982 */
2983 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2984 id_data[0] == NAND_MFR_SAMSUNG &&
2985 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2986 id_data[5] != 0x00) {
2987 /* Calc pagesize */
2988 mtd->writesize = 2048 << (extid & 0x03);
2989 extid >>= 2;
2990 /* Calc oobsize */
2991 switch (extid & 0x03) {
2992 case 1:
2993 mtd->oobsize = 128;
2994 break;
2995 case 2:
2996 mtd->oobsize = 218;
2997 break;
2998 case 3:
2999 mtd->oobsize = 400;
3000 break;
3001 default:
3002 mtd->oobsize = 436;
3003 break;
3004 }
3005 extid >>= 2;
3006 /* Calc blocksize */
3007 mtd->erasesize = (128 * 1024) <<
3008 (((extid >> 1) & 0x04) | (extid & 0x03));
3009 busw = 0;
3010 } else {
3011 /* Calc pagesize */
3012 mtd->writesize = 1024 << (extid & 0x03);
3013 extid >>= 2;
3014 /* Calc oobsize */
3015 mtd->oobsize = (8 << (extid & 0x01)) *
3016 (mtd->writesize >> 9);
3017 extid >>= 2;
3018 /* Calc blocksize. Blocksize is multiples of 64KiB */
3019 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3020 extid >>= 2;
3021 /* Get buswidth information */
3022 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3023 }
3024 } else {
3025 /*
3026 * Old devices have chip data hardcoded in the device id table.
3027 */
3028 mtd->erasesize = type->erasesize;
3029 mtd->writesize = type->pagesize;
3030 mtd->oobsize = mtd->writesize / 32;
3031 busw = type->options & NAND_BUSWIDTH_16;
3032
3033 /*
3034 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3035 * some Spansion chips have erasesize that conflicts with size
3036 * listed in nand_ids table.
3037 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3038 */
3039 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3040 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3041 id_data[7] == 0x00 && mtd->writesize == 512) {
3042 mtd->erasesize = 128 * 1024;
3043 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3044 }
3045 }
3046 /* Get chip options, preserve non chip based options */
3047 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3048 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3049
3050 /*
3051 * Check if chip is not a Samsung device. Do not clear the
3052 * options for chips which do not have an extended id.
3053 */
3054 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3055 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3056 ident_done:
3057
3058 /*
3059 * Set chip as a default. Board drivers can override it, if necessary.
3060 */
3061 chip->options |= NAND_NO_AUTOINCR;
3062
3063 /* Try to identify manufacturer */
3064 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3065 if (nand_manuf_ids[maf_idx].id == *maf_id)
3066 break;
3067 }
3068
3069 /*
3070 * Check, if buswidth is correct. Hardware drivers should set
3071 * chip correct!
3072 */
3073 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3074 pr_info("NAND device: Manufacturer ID:"
3075 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3076 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3077 pr_warn("NAND bus width %d instead %d bit\n",
3078 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3079 busw ? 16 : 8);
3080 return ERR_PTR(-EINVAL);
3081 }
3082
3083 /* Calculate the address shift from the page size */
3084 chip->page_shift = ffs(mtd->writesize) - 1;
3085 /* Convert chipsize to number of pages per chip -1 */
3086 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3087
3088 chip->bbt_erase_shift = chip->phys_erase_shift =
3089 ffs(mtd->erasesize) - 1;
3090 if (chip->chipsize & 0xffffffff)
3091 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3092 else {
3093 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3094 chip->chip_shift += 32 - 1;
3095 }
3096
3097 chip->badblockbits = 8;
3098
3099 /* Set the bad block position */
3100 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3101 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3102 else
3103 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3104
3105 /*
3106 * Bad block marker is stored in the last page of each block
3107 * on Samsung and Hynix MLC devices; stored in first two pages
3108 * of each block on Micron devices with 2KiB pages and on
3109 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3110 * only the first page.
3111 */
3112 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3113 (*maf_id == NAND_MFR_SAMSUNG ||
3114 *maf_id == NAND_MFR_HYNIX))
3115 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3116 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3117 (*maf_id == NAND_MFR_SAMSUNG ||
3118 *maf_id == NAND_MFR_HYNIX ||
3119 *maf_id == NAND_MFR_TOSHIBA ||
3120 *maf_id == NAND_MFR_AMD)) ||
3121 (mtd->writesize == 2048 &&
3122 *maf_id == NAND_MFR_MICRON))
3123 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3124
3125 /* Check for AND chips with 4 page planes */
3126 if (chip->options & NAND_4PAGE_ARRAY)
3127 chip->erase_cmd = multi_erase_cmd;
3128 else
3129 chip->erase_cmd = single_erase_cmd;
3130
3131 /* Do not replace user supplied command function! */
3132 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3133 chip->cmdfunc = nand_command_lp;
3134
3135 pr_info("NAND device: Manufacturer ID:"
3136 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3137 nand_manuf_ids[maf_idx].name,
3138 chip->onfi_version ? chip->onfi_params.model : type->name);
3139
3140 return type;
3141 }
3142
3143 /**
3144 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3145 * @mtd: MTD device structure
3146 * @maxchips: number of chips to scan for
3147 * @table: alternative NAND ID table
3148 *
3149 * This is the first phase of the normal nand_scan() function. It reads the
3150 * flash ID and sets up MTD fields accordingly.
3151 *
3152 * The mtd->owner field must be set to the module of the caller.
3153 */
3154 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3155 struct nand_flash_dev *table)
3156 {
3157 int i, busw, nand_maf_id, nand_dev_id;
3158 struct nand_chip *chip = mtd->priv;
3159 struct nand_flash_dev *type;
3160
3161 /* Get buswidth to select the correct functions */
3162 busw = chip->options & NAND_BUSWIDTH_16;
3163 /* Set the default functions */
3164 nand_set_defaults(chip, busw);
3165
3166 /* Read the flash type */
3167 type = nand_get_flash_type(mtd, chip, busw,
3168 &nand_maf_id, &nand_dev_id, table);
3169
3170 if (IS_ERR(type)) {
3171 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3172 pr_warn("No NAND device found\n");
3173 chip->select_chip(mtd, -1);
3174 return PTR_ERR(type);
3175 }
3176
3177 /* Check for a chip array */
3178 for (i = 1; i < maxchips; i++) {
3179 chip->select_chip(mtd, i);
3180 /* See comment in nand_get_flash_type for reset */
3181 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3182 /* Send the command for reading device ID */
3183 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3184 /* Read manufacturer and device IDs */
3185 if (nand_maf_id != chip->read_byte(mtd) ||
3186 nand_dev_id != chip->read_byte(mtd))
3187 break;
3188 }
3189 if (i > 1)
3190 pr_info("%d NAND chips detected\n", i);
3191
3192 /* Store the number of chips and calc total size for mtd */
3193 chip->numchips = i;
3194 mtd->size = i * chip->chipsize;
3195
3196 return 0;
3197 }
3198 EXPORT_SYMBOL(nand_scan_ident);
3199
3200
3201 /**
3202 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3203 * @mtd: MTD device structure
3204 *
3205 * This is the second phase of the normal nand_scan() function. It fills out
3206 * all the uninitialized function pointers with the defaults and scans for a
3207 * bad block table if appropriate.
3208 */
3209 int nand_scan_tail(struct mtd_info *mtd)
3210 {
3211 int i;
3212 struct nand_chip *chip = mtd->priv;
3213
3214 if (!(chip->options & NAND_OWN_BUFFERS))
3215 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3216 if (!chip->buffers)
3217 return -ENOMEM;
3218
3219 /* Set the internal oob buffer location, just after the page data */
3220 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3221
3222 /*
3223 * If no default placement scheme is given, select an appropriate one.
3224 */
3225 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3226 switch (mtd->oobsize) {
3227 case 8:
3228 chip->ecc.layout = &nand_oob_8;
3229 break;
3230 case 16:
3231 chip->ecc.layout = &nand_oob_16;
3232 break;
3233 case 64:
3234 chip->ecc.layout = &nand_oob_64;
3235 break;
3236 case 128:
3237 chip->ecc.layout = &nand_oob_128;
3238 break;
3239 default:
3240 pr_warn("No oob scheme defined for oobsize %d\n",
3241 mtd->oobsize);
3242 BUG();
3243 }
3244 }
3245
3246 if (!chip->write_page)
3247 chip->write_page = nand_write_page;
3248
3249 /*
3250 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3251 * selected and we have 256 byte pagesize fallback to software ECC
3252 */
3253
3254 switch (chip->ecc.mode) {
3255 case NAND_ECC_HW_OOB_FIRST:
3256 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3257 if (!chip->ecc.calculate || !chip->ecc.correct ||
3258 !chip->ecc.hwctl) {
3259 pr_warn("No ECC functions supplied; "
3260 "hardware ECC not possible\n");
3261 BUG();
3262 }
3263 if (!chip->ecc.read_page)
3264 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3265
3266 case NAND_ECC_HW:
3267 /* Use standard hwecc read page function? */
3268 if (!chip->ecc.read_page)
3269 chip->ecc.read_page = nand_read_page_hwecc;
3270 if (!chip->ecc.write_page)
3271 chip->ecc.write_page = nand_write_page_hwecc;
3272 if (!chip->ecc.read_page_raw)
3273 chip->ecc.read_page_raw = nand_read_page_raw;
3274 if (!chip->ecc.write_page_raw)
3275 chip->ecc.write_page_raw = nand_write_page_raw;
3276 if (!chip->ecc.read_oob)
3277 chip->ecc.read_oob = nand_read_oob_std;
3278 if (!chip->ecc.write_oob)
3279 chip->ecc.write_oob = nand_write_oob_std;
3280
3281 case NAND_ECC_HW_SYNDROME:
3282 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3283 !chip->ecc.hwctl) &&
3284 (!chip->ecc.read_page ||
3285 chip->ecc.read_page == nand_read_page_hwecc ||
3286 !chip->ecc.write_page ||
3287 chip->ecc.write_page == nand_write_page_hwecc)) {
3288 pr_warn("No ECC functions supplied; "
3289 "hardware ECC not possible\n");
3290 BUG();
3291 }
3292 /* Use standard syndrome read/write page function? */
3293 if (!chip->ecc.read_page)
3294 chip->ecc.read_page = nand_read_page_syndrome;
3295 if (!chip->ecc.write_page)
3296 chip->ecc.write_page = nand_write_page_syndrome;
3297 if (!chip->ecc.read_page_raw)
3298 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3299 if (!chip->ecc.write_page_raw)
3300 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3301 if (!chip->ecc.read_oob)
3302 chip->ecc.read_oob = nand_read_oob_syndrome;
3303 if (!chip->ecc.write_oob)
3304 chip->ecc.write_oob = nand_write_oob_syndrome;
3305
3306 if (mtd->writesize >= chip->ecc.size)
3307 break;
3308 pr_warn("%d byte HW ECC not possible on "
3309 "%d byte page size, fallback to SW ECC\n",
3310 chip->ecc.size, mtd->writesize);
3311 chip->ecc.mode = NAND_ECC_SOFT;
3312
3313 case NAND_ECC_SOFT:
3314 chip->ecc.calculate = nand_calculate_ecc;
3315 chip->ecc.correct = nand_correct_data;
3316 chip->ecc.read_page = nand_read_page_swecc;
3317 chip->ecc.read_subpage = nand_read_subpage;
3318 chip->ecc.write_page = nand_write_page_swecc;
3319 chip->ecc.read_page_raw = nand_read_page_raw;
3320 chip->ecc.write_page_raw = nand_write_page_raw;
3321 chip->ecc.read_oob = nand_read_oob_std;
3322 chip->ecc.write_oob = nand_write_oob_std;
3323 if (!chip->ecc.size)
3324 chip->ecc.size = 256;
3325 chip->ecc.bytes = 3;
3326 break;
3327
3328 case NAND_ECC_SOFT_BCH:
3329 if (!mtd_nand_has_bch()) {
3330 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3331 BUG();
3332 }
3333 chip->ecc.calculate = nand_bch_calculate_ecc;
3334 chip->ecc.correct = nand_bch_correct_data;
3335 chip->ecc.read_page = nand_read_page_swecc;
3336 chip->ecc.read_subpage = nand_read_subpage;
3337 chip->ecc.write_page = nand_write_page_swecc;
3338 chip->ecc.read_page_raw = nand_read_page_raw;
3339 chip->ecc.write_page_raw = nand_write_page_raw;
3340 chip->ecc.read_oob = nand_read_oob_std;
3341 chip->ecc.write_oob = nand_write_oob_std;
3342 /*
3343 * Board driver should supply ecc.size and ecc.bytes values to
3344 * select how many bits are correctable; see nand_bch_init()
3345 * for details. Otherwise, default to 4 bits for large page
3346 * devices.
3347 */
3348 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3349 chip->ecc.size = 512;
3350 chip->ecc.bytes = 7;
3351 }
3352 chip->ecc.priv = nand_bch_init(mtd,
3353 chip->ecc.size,
3354 chip->ecc.bytes,
3355 &chip->ecc.layout);
3356 if (!chip->ecc.priv) {
3357 pr_warn("BCH ECC initialization failed!\n");
3358 BUG();
3359 }
3360 break;
3361
3362 case NAND_ECC_NONE:
3363 pr_warn("NAND_ECC_NONE selected by board driver. "
3364 "This is not recommended!\n");
3365 chip->ecc.read_page = nand_read_page_raw;
3366 chip->ecc.write_page = nand_write_page_raw;
3367 chip->ecc.read_oob = nand_read_oob_std;
3368 chip->ecc.read_page_raw = nand_read_page_raw;
3369 chip->ecc.write_page_raw = nand_write_page_raw;
3370 chip->ecc.write_oob = nand_write_oob_std;
3371 chip->ecc.size = mtd->writesize;
3372 chip->ecc.bytes = 0;
3373 break;
3374
3375 default:
3376 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3377 BUG();
3378 }
3379
3380 /*
3381 * The number of bytes available for a client to place data into
3382 * the out of band area.
3383 */
3384 chip->ecc.layout->oobavail = 0;
3385 for (i = 0; chip->ecc.layout->oobfree[i].length
3386 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3387 chip->ecc.layout->oobavail +=
3388 chip->ecc.layout->oobfree[i].length;
3389 mtd->oobavail = chip->ecc.layout->oobavail;
3390
3391 /*
3392 * Set the number of read / write steps for one page depending on ECC
3393 * mode.
3394 */
3395 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3396 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3397 pr_warn("Invalid ECC parameters\n");
3398 BUG();
3399 }
3400 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3401
3402 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3403 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3404 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3405 switch (chip->ecc.steps) {
3406 case 2:
3407 mtd->subpage_sft = 1;
3408 break;
3409 case 4:
3410 case 8:
3411 case 16:
3412 mtd->subpage_sft = 2;
3413 break;
3414 }
3415 }
3416 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3417
3418 /* Initialize state */
3419 chip->state = FL_READY;
3420
3421 /* De-select the device */
3422 chip->select_chip(mtd, -1);
3423
3424 /* Invalidate the pagebuffer reference */
3425 chip->pagebuf = -1;
3426
3427 /* Fill in remaining MTD driver data */
3428 mtd->type = MTD_NANDFLASH;
3429 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3430 MTD_CAP_NANDFLASH;
3431 mtd->erase = nand_erase;
3432 mtd->point = NULL;
3433 mtd->unpoint = NULL;
3434 mtd->read = nand_read;
3435 mtd->write = nand_write;
3436 mtd->panic_write = panic_nand_write;
3437 mtd->read_oob = nand_read_oob;
3438 mtd->write_oob = nand_write_oob;
3439 mtd->sync = nand_sync;
3440 mtd->lock = NULL;
3441 mtd->unlock = NULL;
3442 mtd->suspend = nand_suspend;
3443 mtd->resume = nand_resume;
3444 mtd->block_isbad = nand_block_isbad;
3445 mtd->block_markbad = nand_block_markbad;
3446 mtd->writebufsize = mtd->writesize;
3447
3448 /* propagate ecc.layout to mtd_info */
3449 mtd->ecclayout = chip->ecc.layout;
3450
3451 /* Check, if we should skip the bad block table scan */
3452 if (chip->options & NAND_SKIP_BBTSCAN)
3453 return 0;
3454
3455 /* Build bad block table */
3456 return chip->scan_bbt(mtd);
3457 }
3458 EXPORT_SYMBOL(nand_scan_tail);
3459
3460 /*
3461 * is_module_text_address() isn't exported, and it's mostly a pointless
3462 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3463 * to call us from in-kernel code if the core NAND support is modular.
3464 */
3465 #ifdef MODULE
3466 #define caller_is_module() (1)
3467 #else
3468 #define caller_is_module() \
3469 is_module_text_address((unsigned long)__builtin_return_address(0))
3470 #endif
3471
3472 /**
3473 * nand_scan - [NAND Interface] Scan for the NAND device
3474 * @mtd: MTD device structure
3475 * @maxchips: number of chips to scan for
3476 *
3477 * This fills out all the uninitialized function pointers with the defaults.
3478 * The flash ID is read and the mtd/chip structures are filled with the
3479 * appropriate values. The mtd->owner field must be set to the module of the
3480 * caller.
3481 */
3482 int nand_scan(struct mtd_info *mtd, int maxchips)
3483 {
3484 int ret;
3485
3486 /* Many callers got this wrong, so check for it for a while... */
3487 if (!mtd->owner && caller_is_module()) {
3488 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3489 BUG();
3490 }
3491
3492 ret = nand_scan_ident(mtd, maxchips, NULL);
3493 if (!ret)
3494 ret = nand_scan_tail(mtd);
3495 return ret;
3496 }
3497 EXPORT_SYMBOL(nand_scan);
3498
3499 /**
3500 * nand_release - [NAND Interface] Free resources held by the NAND device
3501 * @mtd: MTD device structure
3502 */
3503 void nand_release(struct mtd_info *mtd)
3504 {
3505 struct nand_chip *chip = mtd->priv;
3506
3507 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3508 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3509
3510 mtd_device_unregister(mtd);
3511
3512 /* Free bad block table memory */
3513 kfree(chip->bbt);
3514 if (!(chip->options & NAND_OWN_BUFFERS))
3515 kfree(chip->buffers);
3516 }
3517 EXPORT_SYMBOL_GPL(nand_release);
3518
3519 static int __init nand_base_init(void)
3520 {
3521 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3522 return 0;
3523 }
3524
3525 static void __exit nand_base_exit(void)
3526 {
3527 led_trigger_unregister_simple(nand_led_trigger);
3528 }
3529
3530 module_init(nand_base_init);
3531 module_exit(nand_base_exit);
3532
3533 MODULE_LICENSE("GPL");
3534 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3535 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3536 MODULE_DESCRIPTION("Generic NAND flash driver code");
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