drivers/net/ethernet/amd/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 115
 116 #define DRV_NAME        "nmclan_cs"
 117 #define DRV_VERSION     "0.16"
 118
 119
 120 /* ----------------------------------------------------------------------------
 121 Conditional Compilation Options
 122 ---------------------------------------------------------------------------- */
 123
 124 #define MULTI_TX                        0
 125 #define RESET_ON_TIMEOUT                1
 126 #define TX_INTERRUPTABLE                1
 127 #define RESET_XILINX                    0
 128
 129 /* ----------------------------------------------------------------------------
 130 Include Files
 131 ---------------------------------------------------------------------------- */
 132
 133 #include <linux/module.h>
 134 #include <linux/kernel.h>
 135 #include <linux/init.h>
 136 #include <linux/ptrace.h>
 137 #include <linux/slab.h>
 138 #include <linux/string.h>
 139 #include <linux/timer.h>
 140 #include <linux/interrupt.h>
 141 #include <linux/in.h>
 142 #include <linux/delay.h>
 143 #include <linux/ethtool.h>
 144 #include <linux/netdevice.h>
 145 #include <linux/etherdevice.h>
 146 #include <linux/skbuff.h>
 147 #include <linux/if_arp.h>
 148 #include <linux/ioport.h>
 149 #include <linux/bitops.h>
 150
 151 #include <pcmcia/cisreg.h>
 152 #include <pcmcia/cistpl.h>
 153 #include <pcmcia/ds.h>
 154
 155 #include <asm/uaccess.h>
 156 #include <asm/io.h>
 157 #include <asm/system.h>
 158
 159 /* ----------------------------------------------------------------------------
 160 Defines
 161 ---------------------------------------------------------------------------- */
 162
 163 #define ETHER_ADDR_LEN                  ETH_ALEN
 164                                         /* 6 bytes in an Ethernet Address */
 165 #define MACE_LADRF_LEN                  8
 166                                         /* 8 bytes in Logical Address Filter */
 167
 168 /* Loop Control Defines */
 169 #define MACE_MAX_IR_ITERATIONS          10
 170 #define MACE_MAX_RX_ITERATIONS          12
 171         /*
 172         TBD: Dean brought this up, and I assumed the hardware would
 173         handle it:
 174
 175         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 176         non-zero when the isr exits.  We may not get another interrupt
 177         to process the remaining packets for some time.
 178         */
 179
 180 /*
 181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 182 which manages the interface between the MACE and the PCMCIA bus.  It
 183 also includes buffer management for the 32K x 8 SRAM to control up to
 184 four transmit and 12 receive frames at a time.
 185 */
 186 #define AM2150_MAX_TX_FRAMES            4
 187 #define AM2150_MAX_RX_FRAMES            12
 188
 189 /* Am2150 Ethernet Card I/O Mapping */
 190 #define AM2150_RCV                      0x00
 191 #define AM2150_XMT                      0x04
 192 #define AM2150_XMT_SKIP                 0x09
 193 #define AM2150_RCV_NEXT                 0x0A
 194 #define AM2150_RCV_FRAME_COUNT          0x0B
 195 #define AM2150_MACE_BANK                0x0C
 196 #define AM2150_MACE_BASE                0x10
 197
 198 /* MACE Registers */
 199 #define MACE_RCVFIFO                    0
 200 #define MACE_XMTFIFO                    1
 201 #define MACE_XMTFC                      2
 202 #define MACE_XMTFS                      3
 203 #define MACE_XMTRC                      4
 204 #define MACE_RCVFC                      5
 205 #define MACE_RCVFS                      6
 206 #define MACE_FIFOFC                     7
 207 #define MACE_IR                         8
 208 #define MACE_IMR                        9
 209 #define MACE_PR                         10
 210 #define MACE_BIUCC                      11
 211 #define MACE_FIFOCC                     12
 212 #define MACE_MACCC                      13
 213 #define MACE_PLSCC                      14
 214 #define MACE_PHYCC                      15
 215 #define MACE_CHIPIDL                    16
 216 #define MACE_CHIPIDH                    17
 217 #define MACE_IAC                        18
 218 /* Reserved */
 219 #define MACE_LADRF                      20
 220 #define MACE_PADR                       21
 221 /* Reserved */
 222 /* Reserved */
 223 #define MACE_MPC                        24
 224 /* Reserved */
 225 #define MACE_RNTPC                      26
 226 #define MACE_RCVCC                      27
 227 /* Reserved */
 228 #define MACE_UTR                        29
 229 #define MACE_RTR1                       30
 230 #define MACE_RTR2                       31
 231
 232 /* MACE Bit Masks */
 233 #define MACE_XMTRC_EXDEF                0x80
 234 #define MACE_XMTRC_XMTRC                0x0F
 235
 236 #define MACE_XMTFS_XMTSV                0x80
 237 #define MACE_XMTFS_UFLO                 0x40
 238 #define MACE_XMTFS_LCOL                 0x20
 239 #define MACE_XMTFS_MORE                 0x10
 240 #define MACE_XMTFS_ONE                  0x08
 241 #define MACE_XMTFS_DEFER                0x04
 242 #define MACE_XMTFS_LCAR                 0x02
 243 #define MACE_XMTFS_RTRY                 0x01
 244
 245 #define MACE_RCVFS_RCVSTS               0xF000
 246 #define MACE_RCVFS_OFLO                 0x8000
 247 #define MACE_RCVFS_CLSN                 0x4000
 248 #define MACE_RCVFS_FRAM                 0x2000
 249 #define MACE_RCVFS_FCS                  0x1000
 250
 251 #define MACE_FIFOFC_RCVFC               0xF0
 252 #define MACE_FIFOFC_XMTFC               0x0F
 253
 254 #define MACE_IR_JAB                     0x80
 255 #define MACE_IR_BABL                    0x40
 256 #define MACE_IR_CERR                    0x20
 257 #define MACE_IR_RCVCCO                  0x10
 258 #define MACE_IR_RNTPCO                  0x08
 259 #define MACE_IR_MPCO                    0x04
 260 #define MACE_IR_RCVINT                  0x02
 261 #define MACE_IR_XMTINT                  0x01
 262
 263 #define MACE_MACCC_PROM                 0x80
 264 #define MACE_MACCC_DXMT2PD              0x40
 265 #define MACE_MACCC_EMBA                 0x20
 266 #define MACE_MACCC_RESERVED             0x10
 267 #define MACE_MACCC_DRCVPA               0x08
 268 #define MACE_MACCC_DRCVBC               0x04
 269 #define MACE_MACCC_ENXMT                0x02
 270 #define MACE_MACCC_ENRCV                0x01
 271
 272 #define MACE_PHYCC_LNKFL                0x80
 273 #define MACE_PHYCC_DLNKTST              0x40
 274 #define MACE_PHYCC_REVPOL               0x20
 275 #define MACE_PHYCC_DAPC                 0x10
 276 #define MACE_PHYCC_LRT                  0x08
 277 #define MACE_PHYCC_ASEL                 0x04
 278 #define MACE_PHYCC_RWAKE                0x02
 279 #define MACE_PHYCC_AWAKE                0x01
 280
 281 #define MACE_IAC_ADDRCHG                0x80
 282 #define MACE_IAC_PHYADDR                0x04
 283 #define MACE_IAC_LOGADDR                0x02
 284
 285 #define MACE_UTR_RTRE                   0x80
 286 #define MACE_UTR_RTRD                   0x40
 287 #define MACE_UTR_RPA                    0x20
 288 #define MACE_UTR_FCOLL                  0x10
 289 #define MACE_UTR_RCVFCSE                0x08
 290 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 291 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 292 #define MACE_UTR_LOOP_EXTERNAL          0x02
 293 #define MACE_UTR_LOOP_NONE              0x00
 294 #define MACE_UTR_RESERVED               0x01
 295
 296 /* Switch MACE register bank (only 0 and 1 are valid) */
 297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 298
 299 #define MACE_IMR_DEFAULT \
 300   (0xFF - \
 301     ( \
 302       MACE_IR_CERR | \
 303       MACE_IR_RCVCCO | \
 304       MACE_IR_RNTPCO | \
 305       MACE_IR_MPCO | \
 306       MACE_IR_RCVINT | \
 307       MACE_IR_XMTINT \
 308     ) \
 309   )
 310 #undef MACE_IMR_DEFAULT
 311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 312
 313 #define TX_TIMEOUT              ((400*HZ)/1000)
 314
 315 /* ----------------------------------------------------------------------------
 316 Type Definitions
 317 ---------------------------------------------------------------------------- */
 318
 319 typedef struct _mace_statistics {
 320     /* MACE_XMTFS */
 321     int xmtsv;
 322     int uflo;
 323     int lcol;
 324     int more;
 325     int one;
 326     int defer;
 327     int lcar;
 328     int rtry;
 329
 330     /* MACE_XMTRC */
 331     int exdef;
 332     int xmtrc;
 333
 334     /* RFS1--Receive Status (RCVSTS) */
 335     int oflo;
 336     int clsn;
 337     int fram;
 338     int fcs;
 339
 340     /* RFS2--Runt Packet Count (RNTPC) */
 341     int rfs_rntpc;
 342
 343     /* RFS3--Receive Collision Count (RCVCC) */
 344     int rfs_rcvcc;
 345
 346     /* MACE_IR */
 347     int jab;
 348     int babl;
 349     int cerr;
 350     int rcvcco;
 351     int rntpco;
 352     int mpco;
 353
 354     /* MACE_MPC */
 355     int mpc;
 356
 357     /* MACE_RNTPC */
 358     int rntpc;
 359
 360     /* MACE_RCVCC */
 361     int rcvcc;
 362 } mace_statistics;
 363
 364 typedef struct _mace_private {
 365         struct pcmcia_device    *p_dev;
 366     struct net_device_stats linux_stats; /* Linux statistics counters */
 367     mace_statistics mace_stats; /* MACE chip statistics counters */
 368
 369     /* restore_multicast_list() state variables */
 370     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 371     int multicast_num_addrs;
 372
 373     char tx_free_frames; /* Number of free transmit frame buffers */
 374     char tx_irq_disabled; /* MACE TX interrupt disabled */
 375
 376     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 377 } mace_private;
 378
 379 /* ----------------------------------------------------------------------------
 380 Private Global Variables
 381 ---------------------------------------------------------------------------- */
 382
 383 static const char *if_names[]={
 384     "Auto", "10baseT", "BNC",
 385 };
 386
 387 /* ----------------------------------------------------------------------------
 388 Parameters
 389         These are the parameters that can be set during loading with
 390         'insmod'.
 391 ---------------------------------------------------------------------------- */
 392
 393 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 394 MODULE_LICENSE("GPL");
 395
 396 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
 397
 398 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 399 INT_MODULE_PARM(if_port, 0);
 400
 401
 402 /* ----------------------------------------------------------------------------
 403 Function Prototypes
 404 ---------------------------------------------------------------------------- */
 405
 406 static int nmclan_config(struct pcmcia_device *link);
 407 static void nmclan_release(struct pcmcia_device *link);
 408
 409 static void nmclan_reset(struct net_device *dev);
 410 static int mace_config(struct net_device *dev, struct ifmap *map);
 411 static int mace_open(struct net_device *dev);
 412 static int mace_close(struct net_device *dev);
 413 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
 414                                          struct net_device *dev);
 415 static void mace_tx_timeout(struct net_device *dev);
 416 static irqreturn_t mace_interrupt(int irq, void *dev_id);
 417 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 418 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 419 static void restore_multicast_list(struct net_device *dev);
 420 static void set_multicast_list(struct net_device *dev);
 421 static const struct ethtool_ops netdev_ethtool_ops;
 422
 423
 424 static void nmclan_detach(struct pcmcia_device *p_dev);
 425
 426 static const struct net_device_ops mace_netdev_ops = {
 427         .ndo_open               = mace_open,
 428         .ndo_stop               = mace_close,
 429         .ndo_start_xmit         = mace_start_xmit,
 430         .ndo_tx_timeout         = mace_tx_timeout,
 431         .ndo_set_config         = mace_config,
 432         .ndo_get_stats          = mace_get_stats,
 433         .ndo_set_rx_mode        = set_multicast_list,
 434         .ndo_change_mtu         = eth_change_mtu,
 435         .ndo_set_mac_address    = eth_mac_addr,
 436         .ndo_validate_addr      = eth_validate_addr,
 437 };
 438
 439 static int nmclan_probe(struct pcmcia_device *link)
 440 {
 441     mace_private *lp;
 442     struct net_device *dev;
 443
 444     dev_dbg(&link->dev, "nmclan_attach()\n");
 445
 446     /* Create new ethernet device */
 447     dev = alloc_etherdev(sizeof(mace_private));
 448     if (!dev)
 449             return -ENOMEM;
 450     lp = netdev_priv(dev);
 451     lp->p_dev = link;
 452     link->priv = dev;
 453
 454     spin_lock_init(&lp->bank_lock);
 455     link->resource[0]->end = 32;
 456     link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
 457     link->config_flags |= CONF_ENABLE_IRQ;
 458     link->config_index = 1;
 459     link->config_regs = PRESENT_OPTION;
 460
 461     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 462
 463     dev->netdev_ops = &mace_netdev_ops;
 464     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 465     dev->watchdog_timeo = TX_TIMEOUT;
 466
 467     return nmclan_config(link);
 468 } /* nmclan_attach */
 469
 470 static void nmclan_detach(struct pcmcia_device *link)
 471 {
 472     struct net_device *dev = link->priv;
 473
 474     dev_dbg(&link->dev, "nmclan_detach\n");
 475
 476     unregister_netdev(dev);
 477
 478     nmclan_release(link);
 479
 480     free_netdev(dev);
 481 } /* nmclan_detach */
 482
 483 /* ----------------------------------------------------------------------------
 484 mace_read
 485         Reads a MACE register.  This is bank independent; however, the
 486         caller must ensure that this call is not interruptable.  We are
 487         assuming that during normal operation, the MACE is always in
 488         bank 0.
 489 ---------------------------------------------------------------------------- */
 490 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
 491 {
 492   int data = 0xFF;
 493   unsigned long flags;
 494
 495   switch (reg >> 4) {
 496     case 0: /* register 0-15 */
 497       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 498       break;
 499     case 1: /* register 16-31 */
 500       spin_lock_irqsave(&lp->bank_lock, flags);
 501       MACEBANK(1);
 502       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 503       MACEBANK(0);
 504       spin_unlock_irqrestore(&lp->bank_lock, flags);
 505       break;
 506   }
 507   return data & 0xFF;
 508 } /* mace_read */
 509
 510 /* ----------------------------------------------------------------------------
 511 mace_write
 512         Writes to a MACE register.  This is bank independent; however,
 513         the caller must ensure that this call is not interruptable.  We
 514         are assuming that during normal operation, the MACE is always in
 515         bank 0.
 516 ---------------------------------------------------------------------------- */
 517 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
 518                        int data)
 519 {
 520   unsigned long flags;
 521
 522   switch (reg >> 4) {
 523     case 0: /* register 0-15 */
 524       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 525       break;
 526     case 1: /* register 16-31 */
 527       spin_lock_irqsave(&lp->bank_lock, flags);
 528       MACEBANK(1);
 529       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 530       MACEBANK(0);
 531       spin_unlock_irqrestore(&lp->bank_lock, flags);
 532       break;
 533   }
 534 } /* mace_write */
 535
 536 /* ----------------------------------------------------------------------------
 537 mace_init
 538         Resets the MACE chip.
 539 ---------------------------------------------------------------------------- */
 540 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
 541 {
 542   int i;
 543   int ct = 0;
 544
 545   /* MACE Software reset */
 546   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 547   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 548     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 549     if(++ct > 500)
 550     {
 551         pr_err("reset failed, card removed?\n");
 552         return -1;
 553     }
 554     udelay(1);
 555   }
 556   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 557
 558   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 559   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 560
 561   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 562   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 563
 564   /*
 565    * Bit 2-1 PORTSEL[1-0] Port Select.
 566    * 00 AUI/10Base-2
 567    * 01 10Base-T
 568    * 10 DAI Port (reserved in Am2150)
 569    * 11 GPSI
 570    * For this card, only the first two are valid.
 571    * So, PLSCC should be set to
 572    * 0x00 for 10Base-2
 573    * 0x02 for 10Base-T
 574    * Or just set ASEL in PHYCC below!
 575    */
 576   switch (if_port) {
 577     case 1:
 578       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 579       break;
 580     case 2:
 581       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 582       break;
 583     default:
 584       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 585       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 586          and the MACE device will automatically select the operating media
 587          interface port. */
 588       break;
 589   }
 590
 591   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 592   /* Poll ADDRCHG bit */
 593   ct = 0;
 594   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 595   {
 596         if(++ ct > 500)
 597         {
 598                 pr_err("ADDRCHG timeout, card removed?\n");
 599                 return -1;
 600         }
 601   }
 602   /* Set PADR register */
 603   for (i = 0; i < ETHER_ADDR_LEN; i++)
 604     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 605
 606   /* MAC Configuration Control Register should be written last */
 607   /* Let set_multicast_list set this. */
 608   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 609   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 610   return 0;
 611 } /* mace_init */
 612
 613 static int nmclan_config(struct pcmcia_device *link)
 614 {
 615   struct net_device *dev = link->priv;
 616   mace_private *lp = netdev_priv(dev);
 617   u8 *buf;
 618   size_t len;
 619   int i, ret;
 620   unsigned int ioaddr;
 621
 622   dev_dbg(&link->dev, "nmclan_config\n");
 623
 624   link->io_lines = 5;
 625   ret = pcmcia_request_io(link);
 626   if (ret)
 627           goto failed;
 628   ret = pcmcia_request_exclusive_irq(link, mace_interrupt);
 629   if (ret)
 630           goto failed;
 631   ret = pcmcia_enable_device(link);
 632   if (ret)
 633           goto failed;
 634
 635   dev->irq = link->irq;
 636   dev->base_addr = link->resource[0]->start;
 637
 638   ioaddr = dev->base_addr;
 639
 640   /* Read the ethernet address from the CIS. */
 641   len = pcmcia_get_tuple(link, 0x80, &buf);
 642   if (!buf || len < ETHER_ADDR_LEN) {
 643           kfree(buf);
 644           goto failed;
 645   }
 646   memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
 647   kfree(buf);
 648
 649   /* Verify configuration by reading the MACE ID. */
 650   {
 651     char sig[2];
 652
 653     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 654     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 655     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 656       dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
 657             sig[0], sig[1]);
 658     } else {
 659       pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
 660                 sig[0], sig[1]);
 661       return -ENODEV;
 662     }
 663   }
 664
 665   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 666         goto failed;
 667
 668   /* The if_port symbol can be set when the module is loaded */
 669   if (if_port <= 2)
 670     dev->if_port = if_port;
 671   else
 672     pr_notice("invalid if_port requested\n");
 673
 674   SET_NETDEV_DEV(dev, &link->dev);
 675
 676   i = register_netdev(dev);
 677   if (i != 0) {
 678     pr_notice("register_netdev() failed\n");
 679     goto failed;
 680   }
 681
 682   netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
 683               dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
 684   return 0;
 685
 686 failed:
 687         nmclan_release(link);
 688         return -ENODEV;
 689 } /* nmclan_config */
 690
 691 static void nmclan_release(struct pcmcia_device *link)
 692 {
 693         dev_dbg(&link->dev, "nmclan_release\n");
 694         pcmcia_disable_device(link);
 695 }
 696
 697 static int nmclan_suspend(struct pcmcia_device *link)
 698 {
 699         struct net_device *dev = link->priv;
 700
 701         if (link->open)
 702                 netif_device_detach(dev);
 703
 704         return 0;
 705 }
 706
 707 static int nmclan_resume(struct pcmcia_device *link)
 708 {
 709         struct net_device *dev = link->priv;
 710
 711         if (link->open) {
 712                 nmclan_reset(dev);
 713                 netif_device_attach(dev);
 714         }
 715
 716         return 0;
 717 }
 718
 719
 720 /* ----------------------------------------------------------------------------
 721 nmclan_reset
 722         Reset and restore all of the Xilinx and MACE registers.
 723 ---------------------------------------------------------------------------- */
 724 static void nmclan_reset(struct net_device *dev)
 725 {
 726   mace_private *lp = netdev_priv(dev);
 727
 728 #if RESET_XILINX
 729   struct pcmcia_device *link = &lp->link;
 730   u8 OrigCorValue;
 731
 732   /* Save original COR value */
 733   pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
 734
 735   /* Reset Xilinx */
 736   dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
 737         OrigCorValue);
 738   pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
 739   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 740
 741   /* Restore original COR configuration index */
 742   pcmcia_write_config_byte(link, CISREG_COR,
 743                           (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
 744   /* Xilinx is now completely reset along with the MACE chip. */
 745   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 746
 747 #endif /* #if RESET_XILINX */
 748
 749   /* Xilinx is now completely reset along with the MACE chip. */
 750   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 751
 752   /* Reinitialize the MACE chip for operation. */
 753   mace_init(lp, dev->base_addr, dev->dev_addr);
 754   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 755
 756   /* Restore the multicast list and enable TX and RX. */
 757   restore_multicast_list(dev);
 758 } /* nmclan_reset */
 759
 760 /* ----------------------------------------------------------------------------
 761 mace_config
 762         [Someone tell me what this is supposed to do?  Is if_port a defined
 763         standard?  If so, there should be defines to indicate 1=10Base-T,
 764         2=10Base-2, etc. including limited automatic detection.]
 765 ---------------------------------------------------------------------------- */
 766 static int mace_config(struct net_device *dev, struct ifmap *map)
 767 {
 768   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 769     if (map->port <= 2) {
 770       dev->if_port = map->port;
 771       netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
 772     } else
 773       return -EINVAL;
 774   }
 775   return 0;
 776 } /* mace_config */
 777
 778 /* ----------------------------------------------------------------------------
 779 mace_open
 780         Open device driver.
 781 ---------------------------------------------------------------------------- */
 782 static int mace_open(struct net_device *dev)
 783 {
 784   unsigned int ioaddr = dev->base_addr;
 785   mace_private *lp = netdev_priv(dev);
 786   struct pcmcia_device *link = lp->p_dev;
 787
 788   if (!pcmcia_dev_present(link))
 789     return -ENODEV;
 790
 791   link->open++;
 792
 793   MACEBANK(0);
 794
 795   netif_start_queue(dev);
 796   nmclan_reset(dev);
 797
 798   return 0; /* Always succeed */
 799 } /* mace_open */
 800
 801 /* ----------------------------------------------------------------------------
 802 mace_close
 803         Closes device driver.
 804 ---------------------------------------------------------------------------- */
 805 static int mace_close(struct net_device *dev)
 806 {
 807   unsigned int ioaddr = dev->base_addr;
 808   mace_private *lp = netdev_priv(dev);
 809   struct pcmcia_device *link = lp->p_dev;
 810
 811   dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
 812
 813   /* Mask off all interrupts from the MACE chip. */
 814   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 815
 816   link->open--;
 817   netif_stop_queue(dev);
 818
 819   return 0;
 820 } /* mace_close */
 821
 822 static void netdev_get_drvinfo(struct net_device *dev,
 823                                struct ethtool_drvinfo *info)
 824 {
 825         strcpy(info->driver, DRV_NAME);
 826         strcpy(info->version, DRV_VERSION);
 827         sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
 828 }
 829
 830 static const struct ethtool_ops netdev_ethtool_ops = {
 831         .get_drvinfo            = netdev_get_drvinfo,
 832 };
 833
 834 /* ----------------------------------------------------------------------------
 835 mace_start_xmit
 836         This routine begins the packet transmit function.  When completed,
 837         it will generate a transmit interrupt.
 838
 839         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
 840         returns 0, the "packet is now solely the responsibility of the
 841         driver."  If _start_xmit returns non-zero, the "transmission
 842         failed, put skb back into a list."
 843 ---------------------------------------------------------------------------- */
 844
 845 static void mace_tx_timeout(struct net_device *dev)
 846 {
 847   mace_private *lp = netdev_priv(dev);
 848   struct pcmcia_device *link = lp->p_dev;
 849
 850   netdev_notice(dev, "transmit timed out -- ");
 851 #if RESET_ON_TIMEOUT
 852   pr_cont("resetting card\n");
 853   pcmcia_reset_card(link->socket);
 854 #else /* #if RESET_ON_TIMEOUT */
 855   pr_cont("NOT resetting card\n");
 856 #endif /* #if RESET_ON_TIMEOUT */
 857   dev->trans_start = jiffies; /* prevent tx timeout */
 858   netif_wake_queue(dev);
 859 }
 860
 861 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
 862                                          struct net_device *dev)
 863 {
 864   mace_private *lp = netdev_priv(dev);
 865   unsigned int ioaddr = dev->base_addr;
 866
 867   netif_stop_queue(dev);
 868
 869   pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
 870         dev->name, (long)skb->len);
 871
 872 #if (!TX_INTERRUPTABLE)
 873   /* Disable MACE TX interrupts. */
 874   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
 875     ioaddr + AM2150_MACE_BASE + MACE_IMR);
 876   lp->tx_irq_disabled=1;
 877 #endif /* #if (!TX_INTERRUPTABLE) */
 878
 879   {
 880     /* This block must not be interrupted by another transmit request!
 881        mace_tx_timeout will take care of timer-based retransmissions from
 882        the upper layers.  The interrupt handler is guaranteed never to
 883        service a transmit interrupt while we are in here.
 884     */
 885
 886     lp->linux_stats.tx_bytes += skb->len;
 887     lp->tx_free_frames--;
 888
 889     /* WARNING: Write the _exact_ number of bytes written in the header! */
 890     /* Put out the word header [must be an outw()] . . . */
 891     outw(skb->len, ioaddr + AM2150_XMT);
 892     /* . . . and the packet [may be any combination of outw() and outb()] */
 893     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
 894     if (skb->len & 1) {
 895       /* Odd byte transfer */
 896       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
 897     }
 898
 899 #if MULTI_TX
 900     if (lp->tx_free_frames > 0)
 901       netif_start_queue(dev);
 902 #endif /* #if MULTI_TX */
 903   }
 904
 905 #if (!TX_INTERRUPTABLE)
 906   /* Re-enable MACE TX interrupts. */
 907   lp->tx_irq_disabled=0;
 908   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 909 #endif /* #if (!TX_INTERRUPTABLE) */
 910
 911   dev_kfree_skb(skb);
 912
 913   return NETDEV_TX_OK;
 914 } /* mace_start_xmit */
 915
 916 /* ----------------------------------------------------------------------------
 917 mace_interrupt
 918         The interrupt handler.
 919 ---------------------------------------------------------------------------- */
 920 static irqreturn_t mace_interrupt(int irq, void *dev_id)
 921 {
 922   struct net_device *dev = (struct net_device *) dev_id;
 923   mace_private *lp = netdev_priv(dev);
 924   unsigned int ioaddr;
 925   int status;
 926   int IntrCnt = MACE_MAX_IR_ITERATIONS;
 927
 928   if (dev == NULL) {
 929     pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
 930           irq);
 931     return IRQ_NONE;
 932   }
 933
 934   ioaddr = dev->base_addr;
 935
 936   if (lp->tx_irq_disabled) {
 937     const char *msg;
 938     if (lp->tx_irq_disabled)
 939       msg = "Interrupt with tx_irq_disabled";
 940     else
 941       msg = "Re-entering the interrupt handler";
 942     netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
 943                   msg,
 944                   inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
 945                   inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
 946     /* WARNING: MACE_IR has been read! */
 947     return IRQ_NONE;
 948   }
 949
 950   if (!netif_device_present(dev)) {
 951     netdev_dbg(dev, "interrupt from dead card\n");
 952     return IRQ_NONE;
 953   }
 954
 955   do {
 956     /* WARNING: MACE_IR is a READ/CLEAR port! */
 957     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
 958
 959     pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
 960
 961     if (status & MACE_IR_RCVINT) {
 962       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
 963     }
 964
 965     if (status & MACE_IR_XMTINT) {
 966       unsigned char fifofc;
 967       unsigned char xmtrc;
 968       unsigned char xmtfs;
 969
 970       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
 971       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
 972         lp->linux_stats.tx_errors++;
 973         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
 974       }
 975
 976       /* Transmit Retry Count (XMTRC, reg 4) */
 977       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
 978       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
 979       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
 980
 981       if (
 982         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
 983         MACE_XMTFS_XMTSV /* Transmit Status Valid */
 984       ) {
 985         lp->mace_stats.xmtsv++;
 986
 987         if (xmtfs & ~MACE_XMTFS_XMTSV) {
 988           if (xmtfs & MACE_XMTFS_UFLO) {
 989             /* Underflow.  Indicates that the Transmit FIFO emptied before
 990                the end of frame was reached. */
 991             lp->mace_stats.uflo++;
 992           }
 993           if (xmtfs & MACE_XMTFS_LCOL) {
 994             /* Late Collision */
 995             lp->mace_stats.lcol++;
 996           }
 997           if (xmtfs & MACE_XMTFS_MORE) {
 998             /* MORE than one retry was needed */
 999             lp->mace_stats.more++;
1000           }
1001           if (xmtfs & MACE_XMTFS_ONE) {
1002             /* Exactly ONE retry occurred */
1003             lp->mace_stats.one++;
1004           }
1005           if (xmtfs & MACE_XMTFS_DEFER) {
1006             /* Transmission was defered */
1007             lp->mace_stats.defer++;
1008           }
1009           if (xmtfs & MACE_XMTFS_LCAR) {
1010             /* Loss of carrier */
1011             lp->mace_stats.lcar++;
1012           }
1013           if (xmtfs & MACE_XMTFS_RTRY) {
1014             /* Retry error: transmit aborted after 16 attempts */
1015             lp->mace_stats.rtry++;
1016           }
1017         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1018
1019       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1020
1021       lp->linux_stats.tx_packets++;
1022       lp->tx_free_frames++;
1023       netif_wake_queue(dev);
1024     } /* if (status & MACE_IR_XMTINT) */
1025
1026     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1027       if (status & MACE_IR_JAB) {
1028         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1029         lp->mace_stats.jab++;
1030       }
1031       if (status & MACE_IR_BABL) {
1032         /* Babble Error.  >1518 bytes transmitted. */
1033         lp->mace_stats.babl++;
1034       }
1035       if (status & MACE_IR_CERR) {
1036         /* Collision Error.  CERR indicates the absence of the
1037            Signal Quality Error Test message after a packet
1038            transmission. */
1039         lp->mace_stats.cerr++;
1040       }
1041       if (status & MACE_IR_RCVCCO) {
1042         /* Receive Collision Count Overflow; */
1043         lp->mace_stats.rcvcco++;
1044       }
1045       if (status & MACE_IR_RNTPCO) {
1046         /* Runt Packet Count Overflow */
1047         lp->mace_stats.rntpco++;
1048       }
1049       if (status & MACE_IR_MPCO) {
1050         /* Missed Packet Count Overflow */
1051         lp->mace_stats.mpco++;
1052       }
1053     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1054
1055   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1056
1057   return IRQ_HANDLED;
1058 } /* mace_interrupt */
1059
1060 /* ----------------------------------------------------------------------------
1061 mace_rx
1062         Receives packets.
1063 ---------------------------------------------------------------------------- */
1064 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1065 {
1066   mace_private *lp = netdev_priv(dev);
1067   unsigned int ioaddr = dev->base_addr;
1068   unsigned char rx_framecnt;
1069   unsigned short rx_status;
1070
1071   while (
1072     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1073     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1074     (RxCnt--)
1075   ) {
1076     rx_status = inw(ioaddr + AM2150_RCV);
1077
1078     pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1079           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1080
1081     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1082       lp->linux_stats.rx_errors++;
1083       if (rx_status & MACE_RCVFS_OFLO) {
1084         lp->mace_stats.oflo++;
1085       }
1086       if (rx_status & MACE_RCVFS_CLSN) {
1087         lp->mace_stats.clsn++;
1088       }
1089       if (rx_status & MACE_RCVFS_FRAM) {
1090         lp->mace_stats.fram++;
1091       }
1092       if (rx_status & MACE_RCVFS_FCS) {
1093         lp->mace_stats.fcs++;
1094       }
1095     } else {
1096       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1097         /* Auto Strip is off, always subtract 4 */
1098       struct sk_buff *skb;
1099
1100       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1101         /* runt packet count */
1102       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1103         /* rcv collision count */
1104
1105       pr_debug("    receiving packet size 0x%X rx_status"
1106             " 0x%X.\n", pkt_len, rx_status);
1107
1108       skb = dev_alloc_skb(pkt_len+2);
1109
1110       if (skb != NULL) {
1111         skb_reserve(skb, 2);
1112         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1113         if (pkt_len & 1)
1114             *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1115         skb->protocol = eth_type_trans(skb, dev);
1116
1117         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1118
1119         lp->linux_stats.rx_packets++;
1120         lp->linux_stats.rx_bytes += pkt_len;
1121         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1122         continue;
1123       } else {
1124         pr_debug("%s: couldn't allocate a sk_buff of size"
1125               " %d.\n", dev->name, pkt_len);
1126         lp->linux_stats.rx_dropped++;
1127       }
1128     }
1129     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1130   } /* while */
1131
1132   return 0;
1133 } /* mace_rx */
1134
1135 /* ----------------------------------------------------------------------------
1136 pr_linux_stats
1137 ---------------------------------------------------------------------------- */
1138 static void pr_linux_stats(struct net_device_stats *pstats)
1139 {
1140   pr_debug("pr_linux_stats\n");
1141   pr_debug(" rx_packets=%-7ld        tx_packets=%ld\n",
1142         (long)pstats->rx_packets, (long)pstats->tx_packets);
1143   pr_debug(" rx_errors=%-7ld         tx_errors=%ld\n",
1144         (long)pstats->rx_errors, (long)pstats->tx_errors);
1145   pr_debug(" rx_dropped=%-7ld        tx_dropped=%ld\n",
1146         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1147   pr_debug(" multicast=%-7ld         collisions=%ld\n",
1148         (long)pstats->multicast, (long)pstats->collisions);
1149
1150   pr_debug(" rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1151         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1152   pr_debug(" rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1153         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1154   pr_debug(" rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1155         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1156
1157   pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1158         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1159   pr_debug(" tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1160         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1161   pr_debug(" tx_window_errors=%ld\n",
1162         (long)pstats->tx_window_errors);
1163 } /* pr_linux_stats */
1164
1165 /* ----------------------------------------------------------------------------
1166 pr_mace_stats
1167 ---------------------------------------------------------------------------- */
1168 static void pr_mace_stats(mace_statistics *pstats)
1169 {
1170   pr_debug("pr_mace_stats\n");
1171
1172   pr_debug(" xmtsv=%-7d             uflo=%d\n",
1173         pstats->xmtsv, pstats->uflo);
1174   pr_debug(" lcol=%-7d              more=%d\n",
1175         pstats->lcol, pstats->more);
1176   pr_debug(" one=%-7d               defer=%d\n",
1177         pstats->one, pstats->defer);
1178   pr_debug(" lcar=%-7d              rtry=%d\n",
1179         pstats->lcar, pstats->rtry);
1180
1181   /* MACE_XMTRC */
1182   pr_debug(" exdef=%-7d             xmtrc=%d\n",
1183         pstats->exdef, pstats->xmtrc);
1184
1185   /* RFS1--Receive Status (RCVSTS) */
1186   pr_debug(" oflo=%-7d              clsn=%d\n",
1187         pstats->oflo, pstats->clsn);
1188   pr_debug(" fram=%-7d              fcs=%d\n",
1189         pstats->fram, pstats->fcs);
1190
1191   /* RFS2--Runt Packet Count (RNTPC) */
1192   /* RFS3--Receive Collision Count (RCVCC) */
1193   pr_debug(" rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1194         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1195
1196   /* MACE_IR */
1197   pr_debug(" jab=%-7d               babl=%d\n",
1198         pstats->jab, pstats->babl);
1199   pr_debug(" cerr=%-7d              rcvcco=%d\n",
1200         pstats->cerr, pstats->rcvcco);
1201   pr_debug(" rntpco=%-7d            mpco=%d\n",
1202         pstats->rntpco, pstats->mpco);
1203
1204   /* MACE_MPC */
1205   pr_debug(" mpc=%d\n", pstats->mpc);
1206
1207   /* MACE_RNTPC */
1208   pr_debug(" rntpc=%d\n", pstats->rntpc);
1209
1210   /* MACE_RCVCC */
1211   pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1212
1213 } /* pr_mace_stats */
1214
1215 /* ----------------------------------------------------------------------------
1216 update_stats
1217         Update statistics.  We change to register window 1, so this
1218         should be run single-threaded if the device is active. This is
1219         expected to be a rare operation, and it's simpler for the rest
1220         of the driver to assume that window 0 is always valid rather
1221         than use a special window-state variable.
1222
1223         oflo & uflo should _never_ occur since it would mean the Xilinx
1224         was not able to transfer data between the MACE FIFO and the
1225         card's SRAM fast enough.  If this happens, something is
1226         seriously wrong with the hardware.
1227 ---------------------------------------------------------------------------- */
1228 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1229 {
1230   mace_private *lp = netdev_priv(dev);
1231
1232   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1233   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1234   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1235   /* At this point, mace_stats is fully updated for this call.
1236      We may now update the linux_stats. */
1237
1238   /* The MACE has no equivalent for linux_stats field which are commented
1239      out. */
1240
1241   /* lp->linux_stats.multicast; */
1242   lp->linux_stats.collisions =
1243     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1244     /* Collision: The MACE may retry sending a packet 15 times
1245        before giving up.  The retry count is in XMTRC.
1246        Does each retry constitute a collision?
1247        If so, why doesn't the RCVCC record these collisions? */
1248
1249   /* detailed rx_errors: */
1250   lp->linux_stats.rx_length_errors =
1251     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1252   /* lp->linux_stats.rx_over_errors */
1253   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1254   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1255   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1256   lp->linux_stats.rx_missed_errors =
1257     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1258
1259   /* detailed tx_errors */
1260   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1261   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1262     /* LCAR usually results from bad cabling. */
1263   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1264   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1265   /* lp->linux_stats.tx_window_errors; */
1266 } /* update_stats */
1267
1268 /* ----------------------------------------------------------------------------
1269 mace_get_stats
1270         Gathers ethernet statistics from the MACE chip.
1271 ---------------------------------------------------------------------------- */
1272 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1273 {
1274   mace_private *lp = netdev_priv(dev);
1275
1276   update_stats(dev->base_addr, dev);
1277
1278   pr_debug("%s: updating the statistics.\n", dev->name);
1279   pr_linux_stats(&lp->linux_stats);
1280   pr_mace_stats(&lp->mace_stats);
1281
1282   return &lp->linux_stats;
1283 } /* net_device_stats */
1284
1285 /* ----------------------------------------------------------------------------
1286 updateCRC
1287         Modified from Am79C90 data sheet.
1288 ---------------------------------------------------------------------------- */
1289
1290 #ifdef BROKEN_MULTICAST
1291
1292 static void updateCRC(int *CRC, int bit)
1293 {
1294   static const int poly[]={
1295     1,1,1,0, 1,1,0,1,
1296     1,0,1,1, 1,0,0,0,
1297     1,0,0,0, 0,0,1,1,
1298     0,0,1,0, 0,0,0,0
1299   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1300         CRC generator polynomial. */
1301
1302   int j;
1303
1304   /* shift CRC and control bit (CRC[32]) */
1305   for (j = 32; j > 0; j--)
1306     CRC[j] = CRC[j-1];
1307   CRC[0] = 0;
1308
1309   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1310   if (bit ^ CRC[32])
1311     for (j = 0; j < 32; j++)
1312       CRC[j] ^= poly[j];
1313 } /* updateCRC */
1314
1315 /* ----------------------------------------------------------------------------
1316 BuildLAF
1317         Build logical address filter.
1318         Modified from Am79C90 data sheet.
1319
1320 Input
1321         ladrf: logical address filter (contents initialized to 0)
1322         adr: ethernet address
1323 ---------------------------------------------------------------------------- */
1324 static void BuildLAF(int *ladrf, int *adr)
1325 {
1326   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1327
1328   int i, byte; /* temporary array indices */
1329   int hashcode; /* the output object */
1330
1331   CRC[32]=0;
1332
1333   for (byte = 0; byte < 6; byte++)
1334     for (i = 0; i < 8; i++)
1335       updateCRC(CRC, (adr[byte] >> i) & 1);
1336
1337   hashcode = 0;
1338   for (i = 0; i < 6; i++)
1339     hashcode = (hashcode << 1) + CRC[i];
1340
1341   byte = hashcode >> 3;
1342   ladrf[byte] |= (1 << (hashcode & 7));
1343
1344 #ifdef PCMCIA_DEBUG
1345   if (0)
1346     printk(KERN_DEBUG "    adr =%pM\n", adr);
1347   printk(KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1348   for (i = 0; i < 8; i++)
1349     pr_cont(" %02X", ladrf[i]);
1350   pr_cont("\n");
1351 #endif
1352 } /* BuildLAF */
1353
1354 /* ----------------------------------------------------------------------------
1355 restore_multicast_list
1356         Restores the multicast filter for MACE chip to the last
1357         set_multicast_list() call.
1358
1359 Input
1360         multicast_num_addrs
1361         multicast_ladrf[]
1362 ---------------------------------------------------------------------------- */
1363 static void restore_multicast_list(struct net_device *dev)
1364 {
1365   mace_private *lp = netdev_priv(dev);
1366   int num_addrs = lp->multicast_num_addrs;
1367   int *ladrf = lp->multicast_ladrf;
1368   unsigned int ioaddr = dev->base_addr;
1369   int i;
1370
1371   pr_debug("%s: restoring Rx mode to %d addresses.\n",
1372         dev->name, num_addrs);
1373
1374   if (num_addrs > 0) {
1375
1376     pr_debug("Attempt to restore multicast list detected.\n");
1377
1378     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1379     /* Poll ADDRCHG bit */
1380     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1381       ;
1382     /* Set LADRF register */
1383     for (i = 0; i < MACE_LADRF_LEN; i++)
1384       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1385
1386     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1387     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1388
1389   } else if (num_addrs < 0) {
1390
1391     /* Promiscuous mode: receive all packets */
1392     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1393     mace_write(lp, ioaddr, MACE_MACCC,
1394       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1395     );
1396
1397   } else {
1398
1399     /* Normal mode */
1400     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1401     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1402
1403   }
1404 } /* restore_multicast_list */
1405
1406 /* ----------------------------------------------------------------------------
1407 set_multicast_list
1408         Set or clear the multicast filter for this adaptor.
1409
1410 Input
1411         num_addrs == -1 Promiscuous mode, receive all packets
1412         num_addrs == 0  Normal mode, clear multicast list
1413         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1414                         best-effort filtering.
1415 Output
1416         multicast_num_addrs
1417         multicast_ladrf[]
1418 ---------------------------------------------------------------------------- */
1419
1420 static void set_multicast_list(struct net_device *dev)
1421 {
1422   mace_private *lp = netdev_priv(dev);
1423   int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1424   struct netdev_hw_addr *ha;
1425
1426 #ifdef PCMCIA_DEBUG
1427   {
1428     static int old;
1429     if (netdev_mc_count(dev) != old) {
1430       old = netdev_mc_count(dev);
1431       pr_debug("%s: setting Rx mode to %d addresses.\n",
1432             dev->name, old);
1433     }
1434   }
1435 #endif
1436
1437   /* Set multicast_num_addrs. */
1438   lp->multicast_num_addrs = netdev_mc_count(dev);
1439
1440   /* Set multicast_ladrf. */
1441   if (num_addrs > 0) {
1442     /* Calculate multicast logical address filter */
1443     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1444     netdev_for_each_mc_addr(ha, dev) {
1445       memcpy(adr, ha->addr, ETHER_ADDR_LEN);
1446       BuildLAF(lp->multicast_ladrf, adr);
1447     }
1448   }
1449
1450   restore_multicast_list(dev);
1451
1452 } /* set_multicast_list */
1453
1454 #endif /* BROKEN_MULTICAST */
1455
1456 static void restore_multicast_list(struct net_device *dev)
1457 {
1458   unsigned int ioaddr = dev->base_addr;
1459   mace_private *lp = netdev_priv(dev);
1460
1461   pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1462         lp->multicast_num_addrs);
1463
1464   if (dev->flags & IFF_PROMISC) {
1465     /* Promiscuous mode: receive all packets */
1466     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1467     mace_write(lp, ioaddr, MACE_MACCC,
1468       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1469     );
1470   } else {
1471     /* Normal mode */
1472     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1473     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1474   }
1475 } /* restore_multicast_list */
1476
1477 static void set_multicast_list(struct net_device *dev)
1478 {
1479   mace_private *lp = netdev_priv(dev);
1480
1481 #ifdef PCMCIA_DEBUG
1482   {
1483     static int old;
1484     if (netdev_mc_count(dev) != old) {
1485       old = netdev_mc_count(dev);
1486       pr_debug("%s: setting Rx mode to %d addresses.\n",
1487             dev->name, old);
1488     }
1489   }
1490 #endif
1491
1492   lp->multicast_num_addrs = netdev_mc_count(dev);
1493   restore_multicast_list(dev);
1494
1495 } /* set_multicast_list */
1496
1497 static const struct pcmcia_device_id nmclan_ids[] = {
1498         PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1499         PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1500         PCMCIA_DEVICE_NULL,
1501 };
1502 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1503
1504 static struct pcmcia_driver nmclan_cs_driver = {
1505         .owner          = THIS_MODULE,
1506         .name           = "nmclan_cs",
1507         .probe          = nmclan_probe,
1508         .remove         = nmclan_detach,
1509         .id_table       = nmclan_ids,
1510         .suspend        = nmclan_suspend,
1511         .resume         = nmclan_resume,
1512 };
1513
1514 static int __init init_nmclan_cs(void)
1515 {
1516         return pcmcia_register_driver(&nmclan_cs_driver);
1517 }
1518
1519 static void __exit exit_nmclan_cs(void)
1520 {
1521         pcmcia_unregister_driver(&nmclan_cs_driver);
1522 }
1523
1524 module_init(init_nmclan_cs);
1525 module_exit(exit_nmclan_cs);