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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
blobf127768e4e833d036b324c3f8c0212a3c960de61
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
19
20 /* compilation time flags */
21
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
25
26 #define DRV_MODULE_VERSION "1.70.00-0"
27 #define DRV_MODULE_RELDATE "2011/06/13"
28 #define BNX2X_BC_VER 0x040200
29
30 #if defined(CONFIG_DCB)
31 #define BCM_DCBNL
32 #endif
33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
34 #define BCM_CNIC 1
35 #include "../cnic_if.h"
36 #endif
37
38 #ifdef BCM_CNIC
39 #define BNX2X_MIN_MSIX_VEC_CNT 3
40 #define BNX2X_MSIX_VEC_FP_START 2
41 #else
42 #define BNX2X_MIN_MSIX_VEC_CNT 2
43 #define BNX2X_MSIX_VEC_FP_START 1
44 #endif
45
46 #include <linux/mdio.h>
47
48 #include "bnx2x_reg.h"
49 #include "bnx2x_fw_defs.h"
50 #include "bnx2x_hsi.h"
51 #include "bnx2x_link.h"
52 #include "bnx2x_sp.h"
53 #include "bnx2x_dcb.h"
54 #include "bnx2x_stats.h"
55
56 /* error/debug prints */
57
58 #define DRV_MODULE_NAME "bnx2x"
59
60 /* for messages that are currently off */
61 #define BNX2X_MSG_OFF 0
62 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
64 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
67 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
68
69 /* regular debug print */
70 #define DP(__mask, fmt, ...) \
71 do { \
72 if (bp->msg_enable & (__mask)) \
73 pr_notice("[%s:%d(%s)]" fmt, \
74 __func__, __LINE__, \
75 bp->dev ? (bp->dev->name) : "?", \
76 ##__VA_ARGS__); \
77 } while (0)
78
79 #define DP_CONT(__mask, fmt, ...) \
80 do { \
81 if (bp->msg_enable & (__mask)) \
82 pr_cont(fmt, ##__VA_ARGS__); \
83 } while (0)
84
85 /* errors debug print */
86 #define BNX2X_DBG_ERR(fmt, ...) \
87 do { \
88 if (netif_msg_probe(bp)) \
89 pr_err("[%s:%d(%s)]" fmt, \
90 __func__, __LINE__, \
91 bp->dev ? (bp->dev->name) : "?", \
92 ##__VA_ARGS__); \
93 } while (0)
94
95 /* for errors (never masked) */
96 #define BNX2X_ERR(fmt, ...) \
97 do { \
98 pr_err("[%s:%d(%s)]" fmt, \
99 __func__, __LINE__, \
100 bp->dev ? (bp->dev->name) : "?", \
101 ##__VA_ARGS__); \
102 } while (0)
103
104 #define BNX2X_ERROR(fmt, ...) \
105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
106
107
108 /* before we have a dev->name use dev_info() */
109 #define BNX2X_DEV_INFO(fmt, ...) \
110 do { \
111 if (netif_msg_probe(bp)) \
112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
113 } while (0)
114
115 #ifdef BNX2X_STOP_ON_ERROR
116 void bnx2x_int_disable(struct bnx2x *bp);
117 #define bnx2x_panic() \
118 do { \
119 bp->panic = 1; \
120 BNX2X_ERR("driver assert\n"); \
121 bnx2x_int_disable(bp); \
122 bnx2x_panic_dump(bp); \
123 } while (0)
124 #else
125 #define bnx2x_panic() \
126 do { \
127 bp->panic = 1; \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp); \
130 } while (0)
131 #endif
132
133 #define bnx2x_mc_addr(ha) ((ha)->addr)
134 #define bnx2x_uc_addr(ha) ((ha)->addr)
135
136 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
137 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
138 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
139
140
141 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
142
143 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
144 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
145 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
146
147 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
148 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
149 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
150
151 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
152 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
153
154 #define REG_RD_DMAE(bp, offset, valp, len32) \
155 do { \
156 bnx2x_read_dmae(bp, offset, len32);\
157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
158 } while (0)
159
160 #define REG_WR_DMAE(bp, offset, valp, len32) \
161 do { \
162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
164 offset, len32); \
165 } while (0)
166
167 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
168 REG_WR_DMAE(bp, offset, valp, len32)
169
170 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
171 do { \
172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
173 bnx2x_write_big_buf_wb(bp, addr, len32); \
174 } while (0)
175
176 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
177 offsetof(struct shmem_region, field))
178 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
179 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
180
181 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
182 offsetof(struct shmem2_region, field))
183 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
184 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
185 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
186 offsetof(struct mf_cfg, field))
187 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
188 offsetof(struct mf2_cfg, field))
189
190 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
191 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
192 MF_CFG_ADDR(bp, field), (val))
193 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
194
195 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
196 (SHMEM2_RD((bp), size) > \
197 offsetof(struct shmem2_region, field)))
198
199 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
200 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
201
202 /* SP SB indices */
203
204 /* General SP events - stats query, cfc delete, etc */
205 #define HC_SP_INDEX_ETH_DEF_CONS 3
206
207 /* EQ completions */
208 #define HC_SP_INDEX_EQ_CONS 7
209
210 /* FCoE L2 connection completions */
211 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
212 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
213 /* iSCSI L2 */
214 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
215 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
216
217 /* Special clients parameters */
218
219 /* SB indices */
220 /* FCoE L2 */
221 #define BNX2X_FCOE_L2_RX_INDEX \
222 (&bp->def_status_blk->sp_sb.\
223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
224
225 #define BNX2X_FCOE_L2_TX_INDEX \
226 (&bp->def_status_blk->sp_sb.\
227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
228
229 /**
230 * CIDs and CLIDs:
231 * CLIDs below is a CLID for func 0, then the CLID for other
232 * functions will be calculated by the formula:
233 *
234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
235 *
236 */
237 /* iSCSI L2 */
238 #define BNX2X_ISCSI_ETH_CL_ID_IDX 1
239 #define BNX2X_ISCSI_ETH_CID 49
240
241 /* FCoE L2 */
242 #define BNX2X_FCOE_ETH_CL_ID_IDX 2
243 #define BNX2X_FCOE_ETH_CID 50
244
245 /** Additional rings budgeting */
246 #ifdef BCM_CNIC
247 #define CNIC_PRESENT 1
248 #define FCOE_PRESENT 1
249 #else
250 #define CNIC_PRESENT 0
251 #define FCOE_PRESENT 0
252 #endif /* BCM_CNIC */
253 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
254
255 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
256 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
257
258 #define SM_RX_ID 0
259 #define SM_TX_ID 1
260
261 /* defines for multiple tx priority indices */
262 #define FIRST_TX_ONLY_COS_INDEX 1
263 #define FIRST_TX_COS_INDEX 0
264
265 /* defines for decodeing the fastpath index and the cos index out of the
266 * transmission queue index
267 */
268 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x
269
270 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
271 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
272
273 /* rules for calculating the cids of tx-only connections */
274 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
275 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
276
277 /* fp index inside class of service range */
278 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
279
280 /*
281 * 0..15 eth cos0
282 * 16..31 eth cos1 if applicable
283 * 32..47 eth cos2 If applicable
284 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
285 */
286 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
287 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
288
289 /* fast path */
290 struct sw_rx_bd {
291 struct sk_buff *skb;
292 DEFINE_DMA_UNMAP_ADDR(mapping);
293 };
294
295 struct sw_tx_bd {
296 struct sk_buff *skb;
297 u16 first_bd;
298 u8 flags;
299 /* Set on the first BD descriptor when there is a split BD */
300 #define BNX2X_TSO_SPLIT_BD (1<<0)
301 };
302
303 struct sw_rx_page {
304 struct page *page;
305 DEFINE_DMA_UNMAP_ADDR(mapping);
306 };
307
308 union db_prod {
309 struct doorbell_set_prod data;
310 u32 raw;
311 };
312
313
314 /* MC hsi */
315 #define BCM_PAGE_SHIFT 12
316 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
317 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
318 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
319
320 #define PAGES_PER_SGE_SHIFT 0
321 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
322 #define SGE_PAGE_SIZE PAGE_SIZE
323 #define SGE_PAGE_SHIFT PAGE_SHIFT
324 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
325
326 /* SGE ring related macros */
327 #define NUM_RX_SGE_PAGES 2
328 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
329 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
330 /* RX_SGE_CNT is promised to be a power of 2 */
331 #define RX_SGE_MASK (RX_SGE_CNT - 1)
332 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
333 #define MAX_RX_SGE (NUM_RX_SGE - 1)
334 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
335 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
336 #define RX_SGE(x) ((x) & MAX_RX_SGE)
337
338 /* Manipulate a bit vector defined as an array of u64 */
339
340 /* Number of bits in one sge_mask array element */
341 #define BIT_VEC64_ELEM_SZ 64
342 #define BIT_VEC64_ELEM_SHIFT 6
343 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
344
345
346 #define __BIT_VEC64_SET_BIT(el, bit) \
347 do { \
348 el = ((el) | ((u64)0x1 << (bit))); \
349 } while (0)
350
351 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
352 do { \
353 el = ((el) & (~((u64)0x1 << (bit)))); \
354 } while (0)
355
356
357 #define BIT_VEC64_SET_BIT(vec64, idx) \
358 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
359 (idx) & BIT_VEC64_ELEM_MASK)
360
361 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
362 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
363 (idx) & BIT_VEC64_ELEM_MASK)
364
365 #define BIT_VEC64_TEST_BIT(vec64, idx) \
366 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
367 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
368
369 /* Creates a bitmask of all ones in less significant bits.
370 idx - index of the most significant bit in the created mask */
371 #define BIT_VEC64_ONES_MASK(idx) \
372 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
373 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
374
375 /*******************************************************/
376
377
378
379 /* Number of u64 elements in SGE mask array */
380 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
381 BIT_VEC64_ELEM_SZ)
382 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
383 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
384
385 union host_hc_status_block {
386 /* pointer to fp status block e1x */
387 struct host_hc_status_block_e1x *e1x_sb;
388 /* pointer to fp status block e2 */
389 struct host_hc_status_block_e2 *e2_sb;
390 };
391
392 struct bnx2x_agg_info {
393 /*
394 * First aggregation buffer is an skb, the following - are pages.
395 * We will preallocate the skbs for each aggregation when
396 * we open the interface and will replace the BD at the consumer
397 * with this one when we receive the TPA_START CQE in order to
398 * keep the Rx BD ring consistent.
399 */
400 struct sw_rx_bd first_buf;
401 u8 tpa_state;
402 #define BNX2X_TPA_START 1
403 #define BNX2X_TPA_STOP 2
404 #define BNX2X_TPA_ERROR 3
405 u8 placement_offset;
406 u16 parsing_flags;
407 u16 vlan_tag;
408 u16 len_on_bd;
409 };
410
411 #define Q_STATS_OFFSET32(stat_name) \
412 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
413
414 struct bnx2x_fp_txdata {
415
416 struct sw_tx_bd *tx_buf_ring;
417
418 union eth_tx_bd_types *tx_desc_ring;
419 dma_addr_t tx_desc_mapping;
420
421 u32 cid;
422
423 union db_prod tx_db;
424
425 u16 tx_pkt_prod;
426 u16 tx_pkt_cons;
427 u16 tx_bd_prod;
428 u16 tx_bd_cons;
429
430 unsigned long tx_pkt;
431
432 __le16 *tx_cons_sb;
433
434 int txq_index;
435 };
436
437 struct bnx2x_fastpath {
438 struct bnx2x *bp; /* parent */
439
440 #define BNX2X_NAPI_WEIGHT 128
441 struct napi_struct napi;
442 union host_hc_status_block status_blk;
443 /* chip independed shortcuts into sb structure */
444 __le16 *sb_index_values;
445 __le16 *sb_running_index;
446 /* chip independed shortcut into rx_prods_offset memory */
447 u32 ustorm_rx_prods_offset;
448
449 u32 rx_buf_size;
450
451 dma_addr_t status_blk_mapping;
452
453 u8 max_cos; /* actual number of active tx coses */
454 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
455
456 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
457 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
458
459 struct eth_rx_bd *rx_desc_ring;
460 dma_addr_t rx_desc_mapping;
461
462 union eth_rx_cqe *rx_comp_ring;
463 dma_addr_t rx_comp_mapping;
464
465 /* SGE ring */
466 struct eth_rx_sge *rx_sge_ring;
467 dma_addr_t rx_sge_mapping;
468
469 u64 sge_mask[RX_SGE_MASK_LEN];
470
471 u32 cid;
472
473 __le16 fp_hc_idx;
474
475 u8 index; /* number in fp array */
476 u8 cl_id; /* eth client id */
477 u8 cl_qzone_id;
478 u8 fw_sb_id; /* status block number in FW */
479 u8 igu_sb_id; /* status block number in HW */
480
481 u16 rx_bd_prod;
482 u16 rx_bd_cons;
483 u16 rx_comp_prod;
484 u16 rx_comp_cons;
485 u16 rx_sge_prod;
486 /* The last maximal completed SGE */
487 u16 last_max_sge;
488 __le16 *rx_cons_sb;
489 unsigned long rx_pkt,
490 rx_calls;
491
492 /* TPA related */
493 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
494 u8 disable_tpa;
495 #ifdef BNX2X_STOP_ON_ERROR
496 u64 tpa_queue_used;
497 #endif
498
499 struct tstorm_per_queue_stats old_tclient;
500 struct ustorm_per_queue_stats old_uclient;
501 struct xstorm_per_queue_stats old_xclient;
502 struct bnx2x_eth_q_stats eth_q_stats;
503
504 /* The size is calculated using the following:
505 sizeof name field from netdev structure +
506 4 ('-Xx-' string) +
507 4 (for the digits and to make it DWORD aligned) */
508 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
509 char name[FP_NAME_SIZE];
510
511 /* MACs object */
512 struct bnx2x_vlan_mac_obj mac_obj;
513
514 /* Queue State object */
515 struct bnx2x_queue_sp_obj q_obj;
516
517 };
518
519 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
520
521 /* Use 2500 as a mini-jumbo MTU for FCoE */
522 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
523
524 /* FCoE L2 `fastpath' entry is right after the eth entries */
525 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
526 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
527 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
528 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
529 txdata[FIRST_TX_COS_INDEX].var)
530
531
532 #define IS_ETH_FP(fp) (fp->index < \
533 BNX2X_NUM_ETH_QUEUES(fp->bp))
534 #ifdef BCM_CNIC
535 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
536 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
537 #else
538 #define IS_FCOE_FP(fp) false
539 #define IS_FCOE_IDX(idx) false
540 #endif
541
542
543 /* MC hsi */
544 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
545 #define RX_COPY_THRESH 92
546
547 #define NUM_TX_RINGS 16
548 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
549 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
550 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
551 #define MAX_TX_BD (NUM_TX_BD - 1)
552 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
553 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
554 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
555 #define TX_BD(x) ((x) & MAX_TX_BD)
556 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
557
558 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
559 #define NUM_RX_RINGS 8
560 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
561 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
562 #define RX_DESC_MASK (RX_DESC_CNT - 1)
563 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
564 #define MAX_RX_BD (NUM_RX_BD - 1)
565 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
566 #define MIN_RX_AVAIL 128
567
568 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
569 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
570 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
571 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
572 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
573 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
574 MIN_RX_AVAIL))
575
576 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
577 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
578 #define RX_BD(x) ((x) & MAX_RX_BD)
579
580 /*
581 * As long as CQE is X times bigger than BD entry we have to allocate X times
582 * more pages for CQ ring in order to keep it balanced with BD ring
583 */
584 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
585 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
586 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
587 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
588 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
589 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
590 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
591 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
592 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
593 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
594
595
596 /* This is needed for determining of last_max */
597 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
598 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
599
600
601 #define BNX2X_SWCID_SHIFT 17
602 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
603
604 /* used on a CID received from the HW */
605 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
606 #define CQE_CMD(x) (le32_to_cpu(x) >> \
607 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
608
609 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
610 le32_to_cpu((bd)->addr_lo))
611 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
612
613 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
614 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
615 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
616 #error "Min DB doorbell stride is 8"
617 #endif
618 #define DPM_TRIGER_TYPE 0x40
619 #define DOORBELL(bp, cid, val) \
620 do { \
621 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
622 DPM_TRIGER_TYPE); \
623 } while (0)
624
625
626 /* TX CSUM helpers */
627 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
628 skb->csum_offset)
629 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
630 skb->csum_offset))
631
632 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
633
634 #define XMIT_PLAIN 0
635 #define XMIT_CSUM_V4 0x1
636 #define XMIT_CSUM_V6 0x2
637 #define XMIT_CSUM_TCP 0x4
638 #define XMIT_GSO_V4 0x8
639 #define XMIT_GSO_V6 0x10
640
641 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
642 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
643
644
645 /* stuff added to make the code fit 80Col */
646 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
647 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
648 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
649 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
650 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
651
652 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
653
654 #define BNX2X_IP_CSUM_ERR(cqe) \
655 (!((cqe)->fast_path_cqe.status_flags & \
656 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
657 ((cqe)->fast_path_cqe.type_error_flags & \
658 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
659
660 #define BNX2X_L4_CSUM_ERR(cqe) \
661 (!((cqe)->fast_path_cqe.status_flags & \
662 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
663 ((cqe)->fast_path_cqe.type_error_flags & \
664 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
665
666 #define BNX2X_RX_CSUM_OK(cqe) \
667 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
668
669 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
670 (((le16_to_cpu(flags) & \
671 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
672 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
673 == PRS_FLAG_OVERETH_IPV4)
674 #define BNX2X_RX_SUM_FIX(cqe) \
675 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
676
677
678 #define FP_USB_FUNC_OFF \
679 offsetof(struct cstorm_status_block_u, func)
680 #define FP_CSB_FUNC_OFF \
681 offsetof(struct cstorm_status_block_c, func)
682
683 #define HC_INDEX_TOE_RX_CQ_CONS 0 /* Formerly Ustorm TOE CQ index */
684 /* (HC_INDEX_U_TOE_RX_CQ_CONS) */
685 #define HC_INDEX_ETH_RX_CQ_CONS 1 /* Formerly Ustorm ETH CQ index */
686 /* (HC_INDEX_U_ETH_RX_CQ_CONS) */
687 #define HC_INDEX_ETH_RX_BD_CONS 2 /* Formerly Ustorm ETH BD index */
688 /* (HC_INDEX_U_ETH_RX_BD_CONS) */
689
690 #define HC_INDEX_TOE_TX_CQ_CONS 4 /* Formerly Cstorm TOE CQ index */
691 /* (HC_INDEX_C_TOE_TX_CQ_CONS) */
692 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 /* Formerly Cstorm ETH CQ index */
693 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */
694 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 /* Formerly Cstorm ETH CQ index */
695 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */
696 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 /* Formerly Cstorm ETH CQ index */
697 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */
698
699 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
700
701
702 #define BNX2X_RX_SB_INDEX \
703 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
704
705 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
706
707 #define BNX2X_TX_SB_INDEX_COS0 \
708 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
709
710 /* end of fast path */
711
712 /* common */
713
714 struct bnx2x_common {
715
716 u32 chip_id;
717 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
718 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
719
720 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
721 #define CHIP_NUM_57710 0x164e
722 #define CHIP_NUM_57711 0x164f
723 #define CHIP_NUM_57711E 0x1650
724 #define CHIP_NUM_57712 0x1662
725 #define CHIP_NUM_57712_MF 0x1663
726 #define CHIP_NUM_57713 0x1651
727 #define CHIP_NUM_57713E 0x1652
728 #define CHIP_NUM_57800 0x168a
729 #define CHIP_NUM_57800_MF 0x16a5
730 #define CHIP_NUM_57810 0x168e
731 #define CHIP_NUM_57810_MF 0x16ae
732 #define CHIP_NUM_57840 0x168d
733 #define CHIP_NUM_57840_MF 0x16ab
734 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
735 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
736 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
737 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
738 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
739 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
740 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
741 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
742 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
743 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
744 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
745 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
746 CHIP_IS_57711E(bp))
747 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
748 CHIP_IS_57712_MF(bp))
749 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
750 CHIP_IS_57800_MF(bp) || \
751 CHIP_IS_57810(bp) || \
752 CHIP_IS_57810_MF(bp) || \
753 CHIP_IS_57840(bp) || \
754 CHIP_IS_57840_MF(bp))
755 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
756 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
757 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
758
759 #define CHIP_REV_SHIFT 12
760 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
761 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
762 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
763 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
764 /* assume maximum 5 revisions */
765 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
766 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
767 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
768 !(CHIP_REV_VAL(bp) & 0x00001000))
769 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
770 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
771 (CHIP_REV_VAL(bp) & 0x00001000))
772
773 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
774 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
775
776 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
777 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
778 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
779 (CHIP_REV_SHIFT + 1)) \
780 << CHIP_REV_SHIFT)
781 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
782 CHIP_REV_SIM(bp) :\
783 CHIP_REV_VAL(bp))
784 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
785 (CHIP_REV(bp) == CHIP_REV_Bx))
786 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
787 (CHIP_REV(bp) == CHIP_REV_Ax))
788
789 int flash_size;
790 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
791 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
792 #define BNX2X_NVRAM_PAGE_SIZE 256
793
794 u32 shmem_base;
795 u32 shmem2_base;
796 u32 mf_cfg_base;
797 u32 mf2_cfg_base;
798
799 u32 hw_config;
800
801 u32 bc_ver;
802
803 u8 int_block;
804 #define INT_BLOCK_HC 0
805 #define INT_BLOCK_IGU 1
806 #define INT_BLOCK_MODE_NORMAL 0
807 #define INT_BLOCK_MODE_BW_COMP 2
808 #define CHIP_INT_MODE_IS_NBC(bp) \
809 (!CHIP_IS_E1x(bp) && \
810 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
811 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
812
813 u8 chip_port_mode;
814 #define CHIP_4_PORT_MODE 0x0
815 #define CHIP_2_PORT_MODE 0x1
816 #define CHIP_PORT_MODE_NONE 0x2
817 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
818 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
819 };
820
821 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
822 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
823 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
824
825 /* end of common */
826
827 /* port */
828
829 struct bnx2x_port {
830 u32 pmf;
831
832 u32 link_config[LINK_CONFIG_SIZE];
833
834 u32 supported[LINK_CONFIG_SIZE];
835 /* link settings - missing defines */
836 #define SUPPORTED_2500baseX_Full (1 << 15)
837
838 u32 advertising[LINK_CONFIG_SIZE];
839 /* link settings - missing defines */
840 #define ADVERTISED_2500baseX_Full (1 << 15)
841
842 u32 phy_addr;
843
844 /* used to synchronize phy accesses */
845 struct mutex phy_mutex;
846 int need_hw_lock;
847
848 u32 port_stx;
849
850 struct nig_stats old_nig_stats;
851 };
852
853 /* end of port */
854
855 #define STATS_OFFSET32(stat_name) \
856 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
857
858 /* slow path */
859
860 /* slow path work-queue */
861 extern struct workqueue_struct *bnx2x_wq;
862
863 #define BNX2X_MAX_NUM_OF_VFS 64
864 #define BNX2X_VF_ID_INVALID 0xFF
865
866 /*
867 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
868 * control by the number of fast-path status blocks supported by the
869 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
870 * status block represents an independent interrupts context that can
871 * serve a regular L2 networking queue. However special L2 queues such
872 * as the FCoE queue do not require a FP-SB and other components like
873 * the CNIC may consume FP-SB reducing the number of possible L2 queues
874 *
875 * If the maximum number of FP-SB available is X then:
876 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
877 * regular L2 queues is Y=X-1
878 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
879 * c. If the FCoE L2 queue is supported the actual number of L2 queues
880 * is Y+1
881 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
882 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
883 * FP interrupt context for the CNIC).
884 * e. The number of HW context (CID count) is always X or X+1 if FCoE
885 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
886 */
887
888 /* fast-path interrupt contexts E1x */
889 #define FP_SB_MAX_E1x 16
890 /* fast-path interrupt contexts E2 */
891 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
892
893 union cdu_context {
894 struct eth_context eth;
895 char pad[1024];
896 };
897
898 /* CDU host DB constants */
899 #define CDU_ILT_PAGE_SZ_HW 3
900 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
901 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
902
903 #ifdef BCM_CNIC
904 #define CNIC_ISCSI_CID_MAX 256
905 #define CNIC_FCOE_CID_MAX 2048
906 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
907 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
908 #endif
909
910 #define QM_ILT_PAGE_SZ_HW 0
911 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
912 #define QM_CID_ROUND 1024
913
914 #ifdef BCM_CNIC
915 /* TM (timers) host DB constants */
916 #define TM_ILT_PAGE_SZ_HW 0
917 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
918 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
919 #define TM_CONN_NUM 1024
920 #define TM_ILT_SZ (8 * TM_CONN_NUM)
921 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
922
923 /* SRC (Searcher) host DB constants */
924 #define SRC_ILT_PAGE_SZ_HW 0
925 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
926 #define SRC_HASH_BITS 10
927 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
928 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
929 #define SRC_T2_SZ SRC_ILT_SZ
930 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
931
932 #endif
933
934 #define MAX_DMAE_C 8
935
936 /* DMA memory not used in fastpath */
937 struct bnx2x_slowpath {
938 union {
939 struct mac_configuration_cmd e1x;
940 struct eth_classify_rules_ramrod_data e2;
941 } mac_rdata;
942
943
944 union {
945 struct tstorm_eth_mac_filter_config e1x;
946 struct eth_filter_rules_ramrod_data e2;
947 } rx_mode_rdata;
948
949 union {
950 struct mac_configuration_cmd e1;
951 struct eth_multicast_rules_ramrod_data e2;
952 } mcast_rdata;
953
954 struct eth_rss_update_ramrod_data rss_rdata;
955
956 /* Queue State related ramrods are always sent under rtnl_lock */
957 union {
958 struct client_init_ramrod_data init_data;
959 struct client_update_ramrod_data update_data;
960 } q_rdata;
961
962 union {
963 struct function_start_data func_start;
964 /* pfc configuration for DCBX ramrod */
965 struct flow_control_configuration pfc_config;
966 } func_rdata;
967
968 /* used by dmae command executer */
969 struct dmae_command dmae[MAX_DMAE_C];
970
971 u32 stats_comp;
972 union mac_stats mac_stats;
973 struct nig_stats nig_stats;
974 struct host_port_stats port_stats;
975 struct host_func_stats func_stats;
976 struct host_func_stats func_stats_base;
977
978 u32 wb_comp;
979 u32 wb_data[4];
980 };
981
982 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
983 #define bnx2x_sp_mapping(bp, var) \
984 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
985
986
987 /* attn group wiring */
988 #define MAX_DYNAMIC_ATTN_GRPS 8
989
990 struct attn_route {
991 u32 sig[5];
992 };
993
994 struct iro {
995 u32 base;
996 u16 m1;
997 u16 m2;
998 u16 m3;
999 u16 size;
1000 };
1001
1002 struct hw_context {
1003 union cdu_context *vcxt;
1004 dma_addr_t cxt_mapping;
1005 size_t size;
1006 };
1007
1008 /* forward */
1009 struct bnx2x_ilt;
1010
1011
1012 enum bnx2x_recovery_state {
1013 BNX2X_RECOVERY_DONE,
1014 BNX2X_RECOVERY_INIT,
1015 BNX2X_RECOVERY_WAIT,
1016 BNX2X_RECOVERY_FAILED
1017 };
1018
1019 /*
1020 * Event queue (EQ or event ring) MC hsi
1021 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1022 */
1023 #define NUM_EQ_PAGES 1
1024 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1025 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1026 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1027 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1028 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1029
1030 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1031 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1032 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1033
1034 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1035 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1036
1037 #define BNX2X_EQ_INDEX \
1038 (&bp->def_status_blk->sp_sb.\
1039 index_values[HC_SP_INDEX_EQ_CONS])
1040
1041 /* This is a data that will be used to create a link report message.
1042 * We will keep the data used for the last link report in order
1043 * to prevent reporting the same link parameters twice.
1044 */
1045 struct bnx2x_link_report_data {
1046 u16 line_speed; /* Effective line speed */
1047 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1048 };
1049
1050 enum {
1051 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1052 BNX2X_LINK_REPORT_LINK_DOWN,
1053 BNX2X_LINK_REPORT_RX_FC_ON,
1054 BNX2X_LINK_REPORT_TX_FC_ON,
1055 };
1056
1057 enum {
1058 BNX2X_PORT_QUERY_IDX,
1059 BNX2X_PF_QUERY_IDX,
1060 BNX2X_FIRST_QUEUE_QUERY_IDX,
1061 };
1062
1063 struct bnx2x_fw_stats_req {
1064 struct stats_query_header hdr;
1065 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1066 };
1067
1068 struct bnx2x_fw_stats_data {
1069 struct stats_counter storm_counters;
1070 struct per_port_stats port;
1071 struct per_pf_stats pf;
1072 struct per_queue_stats queue_stats[1];
1073 };
1074
1075 /* Public slow path states */
1076 enum {
1077 BNX2X_SP_RTNL_SETUP_TC,
1078 BNX2X_SP_RTNL_TX_TIMEOUT,
1079 };
1080
1081
1082 struct bnx2x {
1083 /* Fields used in the tx and intr/napi performance paths
1084 * are grouped together in the beginning of the structure
1085 */
1086 struct bnx2x_fastpath *fp;
1087 void __iomem *regview;
1088 void __iomem *doorbells;
1089 u16 db_size;
1090
1091 u8 pf_num; /* absolute PF number */
1092 u8 pfid; /* per-path PF number */
1093 int base_fw_ndsb; /**/
1094 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1095 #define BP_PORT(bp) (bp->pfid & 1)
1096 #define BP_FUNC(bp) (bp->pfid)
1097 #define BP_ABS_FUNC(bp) (bp->pf_num)
1098 #define BP_E1HVN(bp) (bp->pfid >> 1)
1099 #define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/
1100 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
1101 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
1102 BP_VN(bp) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1103
1104 struct net_device *dev;
1105 struct pci_dev *pdev;
1106
1107 const struct iro *iro_arr;
1108 #define IRO (bp->iro_arr)
1109
1110 enum bnx2x_recovery_state recovery_state;
1111 int is_leader;
1112 struct msix_entry *msix_table;
1113
1114 int tx_ring_size;
1115
1116 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1117 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1118 #define ETH_MIN_PACKET_SIZE 60
1119 #define ETH_MAX_PACKET_SIZE 1500
1120 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1121
1122 /* Max supported alignment is 256 (8 shift) */
1123 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
1124 L1_CACHE_SHIFT : 8)
1125 /* FW use 2 Cache lines Alignment for start packet and size */
1126 #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT)
1127 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1128
1129 struct host_sp_status_block *def_status_blk;
1130 #define DEF_SB_IGU_ID 16
1131 #define DEF_SB_ID HC_SP_SB_ID
1132 __le16 def_idx;
1133 __le16 def_att_idx;
1134 u32 attn_state;
1135 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1136
1137 /* slow path ring */
1138 struct eth_spe *spq;
1139 dma_addr_t spq_mapping;
1140 u16 spq_prod_idx;
1141 struct eth_spe *spq_prod_bd;
1142 struct eth_spe *spq_last_bd;
1143 __le16 *dsb_sp_prod;
1144 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1145 /* used to synchronize spq accesses */
1146 spinlock_t spq_lock;
1147
1148 /* event queue */
1149 union event_ring_elem *eq_ring;
1150 dma_addr_t eq_mapping;
1151 u16 eq_prod;
1152 u16 eq_cons;
1153 __le16 *eq_cons_sb;
1154 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1155
1156
1157
1158 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1159 u16 stats_pending;
1160 /* Counter for completed statistics ramrods */
1161 u16 stats_comp;
1162
1163 /* End of fields used in the performance code paths */
1164
1165 int panic;
1166 int msg_enable;
1167
1168 u32 flags;
1169 #define PCIX_FLAG (1 << 0)
1170 #define PCI_32BIT_FLAG (1 << 1)
1171 #define ONE_PORT_FLAG (1 << 2)
1172 #define NO_WOL_FLAG (1 << 3)
1173 #define USING_DAC_FLAG (1 << 4)
1174 #define USING_MSIX_FLAG (1 << 5)
1175 #define USING_MSI_FLAG (1 << 6)
1176 #define DISABLE_MSI_FLAG (1 << 7)
1177 #define TPA_ENABLE_FLAG (1 << 8)
1178 #define NO_MCP_FLAG (1 << 9)
1179
1180 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1181 #define MF_FUNC_DIS (1 << 11)
1182 #define OWN_CNIC_IRQ (1 << 12)
1183 #define NO_ISCSI_OOO_FLAG (1 << 13)
1184 #define NO_ISCSI_FLAG (1 << 14)
1185 #define NO_FCOE_FLAG (1 << 15)
1186
1187 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1188 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1189 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1190
1191 int pm_cap;
1192 int mrrs;
1193
1194 struct delayed_work sp_task;
1195 struct delayed_work sp_rtnl_task;
1196
1197 struct delayed_work period_task;
1198 struct timer_list timer;
1199 int current_interval;
1200
1201 u16 fw_seq;
1202 u16 fw_drv_pulse_wr_seq;
1203 u32 func_stx;
1204
1205 struct link_params link_params;
1206 struct link_vars link_vars;
1207 u32 link_cnt;
1208 struct bnx2x_link_report_data last_reported_link;
1209
1210 struct mdio_if_info mdio;
1211
1212 struct bnx2x_common common;
1213 struct bnx2x_port port;
1214
1215 struct cmng_struct_per_port cmng;
1216 u32 vn_weight_sum;
1217 u32 mf_config[E1HVN_MAX];
1218 u32 mf2_config[E2_FUNC_MAX];
1219 u32 path_has_ovlan; /* E3 */
1220 u16 mf_ov;
1221 u8 mf_mode;
1222 #define IS_MF(bp) (bp->mf_mode != 0)
1223 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1224 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1225
1226 u8 wol;
1227
1228 int rx_ring_size;
1229
1230 u16 tx_quick_cons_trip_int;
1231 u16 tx_quick_cons_trip;
1232 u16 tx_ticks_int;
1233 u16 tx_ticks;
1234
1235 u16 rx_quick_cons_trip_int;
1236 u16 rx_quick_cons_trip;
1237 u16 rx_ticks_int;
1238 u16 rx_ticks;
1239 /* Maximal coalescing timeout in us */
1240 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1241
1242 u32 lin_cnt;
1243
1244 u16 state;
1245 #define BNX2X_STATE_CLOSED 0
1246 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1247 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1248 #define BNX2X_STATE_OPEN 0x3000
1249 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1250 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1251
1252 #define BNX2X_STATE_DIAG 0xe000
1253 #define BNX2X_STATE_ERROR 0xf000
1254
1255 int multi_mode;
1256 #define BNX2X_MAX_PRIORITY 8
1257 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1258 #define BNX2X_MAX_COS 3
1259 #define BNX2X_MAX_TX_COS 2
1260 int num_queues;
1261 int disable_tpa;
1262
1263 u32 rx_mode;
1264 #define BNX2X_RX_MODE_NONE 0
1265 #define BNX2X_RX_MODE_NORMAL 1
1266 #define BNX2X_RX_MODE_ALLMULTI 2
1267 #define BNX2X_RX_MODE_PROMISC 3
1268 #define BNX2X_MAX_MULTICAST 64
1269
1270 u8 igu_dsb_id;
1271 u8 igu_base_sb;
1272 u8 igu_sb_cnt;
1273 dma_addr_t def_status_blk_mapping;
1274
1275 struct bnx2x_slowpath *slowpath;
1276 dma_addr_t slowpath_mapping;
1277
1278 /* Total number of FW statistics requests */
1279 u8 fw_stats_num;
1280
1281 /*
1282 * This is a memory buffer that will contain both statistics
1283 * ramrod request and data.
1284 */
1285 void *fw_stats;
1286 dma_addr_t fw_stats_mapping;
1287
1288 /*
1289 * FW statistics request shortcut (points at the
1290 * beginning of fw_stats buffer).
1291 */
1292 struct bnx2x_fw_stats_req *fw_stats_req;
1293 dma_addr_t fw_stats_req_mapping;
1294 int fw_stats_req_sz;
1295
1296 /*
1297 * FW statistics data shortcut (points at the begining of
1298 * fw_stats buffer + fw_stats_req_sz).
1299 */
1300 struct bnx2x_fw_stats_data *fw_stats_data;
1301 dma_addr_t fw_stats_data_mapping;
1302 int fw_stats_data_sz;
1303
1304 struct hw_context context;
1305
1306 struct bnx2x_ilt *ilt;
1307 #define BP_ILT(bp) ((bp)->ilt)
1308 #define ILT_MAX_LINES 256
1309 /*
1310 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1311 * to CNIC.
1312 */
1313 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1314
1315 /*
1316 * Maximum CID count that might be required by the bnx2x:
1317 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1318 */
1319 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1320 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1321 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1322 ILT_PAGE_CIDS))
1323 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1324
1325 int qm_cid_count;
1326
1327 int dropless_fc;
1328
1329 #ifdef BCM_CNIC
1330 u32 cnic_flags;
1331 #define BNX2X_CNIC_FLAG_MAC_SET 1
1332 void *t2;
1333 dma_addr_t t2_mapping;
1334 struct cnic_ops __rcu *cnic_ops;
1335 void *cnic_data;
1336 u32 cnic_tag;
1337 struct cnic_eth_dev cnic_eth_dev;
1338 union host_hc_status_block cnic_sb;
1339 dma_addr_t cnic_sb_mapping;
1340 struct eth_spe *cnic_kwq;
1341 struct eth_spe *cnic_kwq_prod;
1342 struct eth_spe *cnic_kwq_cons;
1343 struct eth_spe *cnic_kwq_last;
1344 u16 cnic_kwq_pending;
1345 u16 cnic_spq_pending;
1346 u8 fip_mac[ETH_ALEN];
1347 struct mutex cnic_mutex;
1348 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1349
1350 /* Start index of the "special" (CNIC related) L2 cleints */
1351 u8 cnic_base_cl_id;
1352 #endif
1353
1354 int dmae_ready;
1355 /* used to synchronize dmae accesses */
1356 spinlock_t dmae_lock;
1357
1358 /* used to protect the FW mail box */
1359 struct mutex fw_mb_mutex;
1360
1361 /* used to synchronize stats collecting */
1362 int stats_state;
1363
1364 /* used for synchronization of concurrent threads statistics handling */
1365 spinlock_t stats_lock;
1366
1367 /* used by dmae command loader */
1368 struct dmae_command stats_dmae;
1369 int executer_idx;
1370
1371 u16 stats_counter;
1372 struct bnx2x_eth_stats eth_stats;
1373
1374 struct z_stream_s *strm;
1375 void *gunzip_buf;
1376 dma_addr_t gunzip_mapping;
1377 int gunzip_outlen;
1378 #define FW_BUF_SIZE 0x8000
1379 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1380 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1381 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1382
1383 struct raw_op *init_ops;
1384 /* Init blocks offsets inside init_ops */
1385 u16 *init_ops_offsets;
1386 /* Data blob - has 32 bit granularity */
1387 u32 *init_data;
1388 u32 init_mode_flags;
1389 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1390 /* Zipped PRAM blobs - raw data */
1391 const u8 *tsem_int_table_data;
1392 const u8 *tsem_pram_data;
1393 const u8 *usem_int_table_data;
1394 const u8 *usem_pram_data;
1395 const u8 *xsem_int_table_data;
1396 const u8 *xsem_pram_data;
1397 const u8 *csem_int_table_data;
1398 const u8 *csem_pram_data;
1399 #define INIT_OPS(bp) (bp->init_ops)
1400 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1401 #define INIT_DATA(bp) (bp->init_data)
1402 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1403 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1404 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1405 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1406 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1407 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1408 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1409 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1410
1411 #define PHY_FW_VER_LEN 20
1412 char fw_ver[32];
1413 const struct firmware *firmware;
1414
1415 /* DCB support on/off */
1416 u16 dcb_state;
1417 #define BNX2X_DCB_STATE_OFF 0
1418 #define BNX2X_DCB_STATE_ON 1
1419
1420 /* DCBX engine mode */
1421 int dcbx_enabled;
1422 #define BNX2X_DCBX_ENABLED_OFF 0
1423 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1424 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1425 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1426
1427 bool dcbx_mode_uset;
1428
1429 struct bnx2x_config_dcbx_params dcbx_config_params;
1430 struct bnx2x_dcbx_port_params dcbx_port_params;
1431 int dcb_version;
1432
1433 /* CAM credit pools */
1434 struct bnx2x_credit_pool_obj macs_pool;
1435
1436 /* RX_MODE object */
1437 struct bnx2x_rx_mode_obj rx_mode_obj;
1438
1439 /* MCAST object */
1440 struct bnx2x_mcast_obj mcast_obj;
1441
1442 /* RSS configuration object */
1443 struct bnx2x_rss_config_obj rss_conf_obj;
1444
1445 /* Function State controlling object */
1446 struct bnx2x_func_sp_obj func_obj;
1447
1448 unsigned long sp_state;
1449
1450 /* operation indication for the sp_rtnl task */
1451 unsigned long sp_rtnl_state;
1452
1453 /* DCBX Negotation results */
1454 struct dcbx_features dcbx_local_feat;
1455 u32 dcbx_error;
1456
1457 #ifdef BCM_DCBNL
1458 struct dcbx_features dcbx_remote_feat;
1459 u32 dcbx_remote_flags;
1460 #endif
1461 u32 pending_max;
1462
1463 /* multiple tx classes of service */
1464 u8 max_cos;
1465
1466 /* priority to cos mapping */
1467 u8 prio_to_cos[8];
1468 };
1469
1470 /* Tx queues may be less or equal to Rx queues */
1471 extern int num_queues;
1472 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1473 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1474 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1475
1476 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1477
1478 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1479 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1480
1481 #define RSS_IPV4_CAP_MASK \
1482 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1483
1484 #define RSS_IPV4_TCP_CAP_MASK \
1485 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1486
1487 #define RSS_IPV6_CAP_MASK \
1488 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1489
1490 #define RSS_IPV6_TCP_CAP_MASK \
1491 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1492
1493 /* func init flags */
1494 #define FUNC_FLG_RSS 0x0001
1495 #define FUNC_FLG_STATS 0x0002
1496 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1497 #define FUNC_FLG_TPA 0x0008
1498 #define FUNC_FLG_SPQ 0x0010
1499 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1500
1501
1502 struct bnx2x_func_init_params {
1503 /* dma */
1504 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1505 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1506
1507 u16 func_flgs;
1508 u16 func_id; /* abs fid */
1509 u16 pf_id;
1510 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1511 };
1512
1513 #define for_each_eth_queue(bp, var) \
1514 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1515
1516 #define for_each_nondefault_eth_queue(bp, var) \
1517 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1518
1519 #define for_each_queue(bp, var) \
1520 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1521 if (skip_queue(bp, var)) \
1522 continue; \
1523 else
1524
1525 /* Skip forwarding FP */
1526 #define for_each_rx_queue(bp, var) \
1527 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1528 if (skip_rx_queue(bp, var)) \
1529 continue; \
1530 else
1531
1532 /* Skip OOO FP */
1533 #define for_each_tx_queue(bp, var) \
1534 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1535 if (skip_tx_queue(bp, var)) \
1536 continue; \
1537 else
1538
1539 #define for_each_nondefault_queue(bp, var) \
1540 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1541 if (skip_queue(bp, var)) \
1542 continue; \
1543 else
1544
1545 #define for_each_cos_in_tx_queue(fp, var) \
1546 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1547
1548 /* skip rx queue
1549 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1550 */
1551 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1552
1553 /* skip tx queue
1554 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1555 */
1556 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1557
1558 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1559
1560
1561
1562
1563 /**
1564 * bnx2x_set_mac_one - configure a single MAC address
1565 *
1566 * @bp: driver handle
1567 * @mac: MAC to configure
1568 * @obj: MAC object handle
1569 * @set: if 'true' add a new MAC, otherwise - delete
1570 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1571 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1572 *
1573 * Configures one MAC according to provided parameters or continues the
1574 * execution of previously scheduled commands if RAMROD_CONT is set in
1575 * ramrod_flags.
1576 *
1577 * Returns zero if operation has successfully completed, a positive value if the
1578 * operation has been successfully scheduled and a negative - if a requested
1579 * operations has failed.
1580 */
1581 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1582 struct bnx2x_vlan_mac_obj *obj, bool set,
1583 int mac_type, unsigned long *ramrod_flags);
1584 /**
1585 * Deletes all MACs configured for the specific MAC object.
1586 *
1587 * @param bp Function driver instance
1588 * @param mac_obj MAC object to cleanup
1589 *
1590 * @return zero if all MACs were cleaned
1591 */
1592
1593 /**
1594 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1595 *
1596 * @bp: driver handle
1597 * @mac_obj: MAC object handle
1598 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1599 * @wait_for_comp: if 'true' block until completion
1600 *
1601 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1602 *
1603 * Returns zero if operation has successfully completed, a positive value if the
1604 * operation has been successfully scheduled and a negative - if a requested
1605 * operations has failed.
1606 */
1607 int bnx2x_del_all_macs(struct bnx2x *bp,
1608 struct bnx2x_vlan_mac_obj *mac_obj,
1609 int mac_type, bool wait_for_comp);
1610
1611 /* Init Function API */
1612 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1613 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1614 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1615 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1616 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1617 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1618
1619
1620 /* dmae */
1621 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1622 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1623 u32 len32);
1624 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1625 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1626 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1627 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1628 bool with_comp, u8 comp_type);
1629
1630
1631 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1632 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1633 u32 data_hi, u32 data_lo, int cmd_type);
1634 void bnx2x_update_coalesce(struct bnx2x *bp);
1635 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1636
1637 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1638 int wait)
1639 {
1640 u32 val;
1641
1642 do {
1643 val = REG_RD(bp, reg);
1644 if (val == expected)
1645 break;
1646 ms -= wait;
1647 msleep(wait);
1648
1649 } while (ms > 0);
1650
1651 return val;
1652 }
1653
1654 #define BNX2X_ILT_ZALLOC(x, y, size) \
1655 do { \
1656 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1657 if (x) \
1658 memset(x, 0, size); \
1659 } while (0)
1660
1661 #define BNX2X_ILT_FREE(x, y, size) \
1662 do { \
1663 if (x) { \
1664 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1665 x = NULL; \
1666 y = 0; \
1667 } \
1668 } while (0)
1669
1670 #define ILOG2(x) (ilog2((x)))
1671
1672 #define ILT_NUM_PAGE_ENTRIES (3072)
1673 /* In 57710/11 we use whole table since we have 8 func
1674 * In 57712 we have only 4 func, but use same size per func, then only half of
1675 * the table in use
1676 */
1677 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1678
1679 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1680 /*
1681 * the phys address is shifted right 12 bits and has an added
1682 * 1=valid bit added to the 53rd bit
1683 * then since this is a wide register(TM)
1684 * we split it into two 32 bit writes
1685 */
1686 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1687 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1688
1689 /* load/unload mode */
1690 #define LOAD_NORMAL 0
1691 #define LOAD_OPEN 1
1692 #define LOAD_DIAG 2
1693 #define UNLOAD_NORMAL 0
1694 #define UNLOAD_CLOSE 1
1695 #define UNLOAD_RECOVERY 2
1696
1697
1698 /* DMAE command defines */
1699 #define DMAE_TIMEOUT -1
1700 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1701 #define DMAE_NOT_RDY -3
1702 #define DMAE_PCI_ERR_FLAG 0x80000000
1703
1704 #define DMAE_SRC_PCI 0
1705 #define DMAE_SRC_GRC 1
1706
1707 #define DMAE_DST_NONE 0
1708 #define DMAE_DST_PCI 1
1709 #define DMAE_DST_GRC 2
1710
1711 #define DMAE_COMP_PCI 0
1712 #define DMAE_COMP_GRC 1
1713
1714 /* E2 and onward - PCI error handling in the completion */
1715
1716 #define DMAE_COMP_REGULAR 0
1717 #define DMAE_COM_SET_ERR 1
1718
1719 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1720 DMAE_COMMAND_SRC_SHIFT)
1721 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1722 DMAE_COMMAND_SRC_SHIFT)
1723
1724 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1725 DMAE_COMMAND_DST_SHIFT)
1726 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1727 DMAE_COMMAND_DST_SHIFT)
1728
1729 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1730 DMAE_COMMAND_C_DST_SHIFT)
1731 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1732 DMAE_COMMAND_C_DST_SHIFT)
1733
1734 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1735
1736 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1737 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1738 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1739 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1740
1741 #define DMAE_CMD_PORT_0 0
1742 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1743
1744 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1745 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1746 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1747
1748 #define DMAE_SRC_PF 0
1749 #define DMAE_SRC_VF 1
1750
1751 #define DMAE_DST_PF 0
1752 #define DMAE_DST_VF 1
1753
1754 #define DMAE_C_SRC 0
1755 #define DMAE_C_DST 1
1756
1757 #define DMAE_LEN32_RD_MAX 0x80
1758 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1759
1760 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1761 indicates eror */
1762
1763 #define MAX_DMAE_C_PER_PORT 8
1764 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1765 BP_E1HVN(bp))
1766 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1767 E1HVN_MAX)
1768
1769 /* PCIE link and speed */
1770 #define PCICFG_LINK_WIDTH 0x1f00000
1771 #define PCICFG_LINK_WIDTH_SHIFT 20
1772 #define PCICFG_LINK_SPEED 0xf0000
1773 #define PCICFG_LINK_SPEED_SHIFT 16
1774
1775
1776 #define BNX2X_NUM_TESTS 7
1777
1778 #define BNX2X_PHY_LOOPBACK 0
1779 #define BNX2X_MAC_LOOPBACK 1
1780 #define BNX2X_PHY_LOOPBACK_FAILED 1
1781 #define BNX2X_MAC_LOOPBACK_FAILED 2
1782 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1783 BNX2X_PHY_LOOPBACK_FAILED)
1784
1785
1786 #define STROM_ASSERT_ARRAY_SIZE 50
1787
1788
1789 /* must be used on a CID before placing it on a HW ring */
1790 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1791 (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \
1792 (x))
1793
1794 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1795 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1796
1797
1798 #define BNX2X_BTR 4
1799 #define MAX_SPQ_PENDING 8
1800
1801 /* CMNG constants, as derived from system spec calculations */
1802 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1803 #define DEF_MIN_RATE 100
1804 /* resolution of the rate shaping timer - 400 usec */
1805 #define RS_PERIODIC_TIMEOUT_USEC 400
1806 /* number of bytes in single QM arbitration cycle -
1807 * coefficient for calculating the fairness timer */
1808 #define QM_ARB_BYTES 160000
1809 /* resolution of Min algorithm 1:100 */
1810 #define MIN_RES 100
1811 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1812 #define MIN_ABOVE_THRESH 32768
1813 /* Fairness algorithm integration time coefficient -
1814 * for calculating the actual Tfair */
1815 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1816 /* Memory of fairness algorithm . 2 cycles */
1817 #define FAIR_MEM 2
1818
1819
1820 #define ATTN_NIG_FOR_FUNC (1L << 8)
1821 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1822 #define GPIO_2_FUNC (1L << 10)
1823 #define GPIO_3_FUNC (1L << 11)
1824 #define GPIO_4_FUNC (1L << 12)
1825 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1826 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1827 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1828 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1829 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1830 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1831
1832 #define ATTN_HARD_WIRED_MASK 0xff00
1833 #define ATTENTION_ID 4
1834
1835
1836 /* stuff added to make the code fit 80Col */
1837
1838 #define BNX2X_PMF_LINK_ASSERT \
1839 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1840
1841 #define BNX2X_MC_ASSERT_BITS \
1842 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1843 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1844 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1845 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1846
1847 #define BNX2X_MCP_ASSERT \
1848 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1849
1850 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1851 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1852 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1853 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1854 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1855 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1856 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1857
1858 #define HW_INTERRUT_ASSERT_SET_0 \
1859 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1860 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1861 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1862 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1863 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1864 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1865 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1866 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1867 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1868 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1869 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1870 #define HW_INTERRUT_ASSERT_SET_1 \
1871 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1872 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1873 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1874 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1875 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1876 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1877 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1878 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1879 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1880 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1881 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1882 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1883 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1884 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1885 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1886 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1887 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1888 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1889 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1890 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1891 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1892 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1893 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1894 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1895 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1896 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1897 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1898 #define HW_INTERRUT_ASSERT_SET_2 \
1899 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1900 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1901 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1902 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1903 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1904 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1905 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1906 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1907 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1908 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1909 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1910 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1911 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1912
1913 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1914 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1915 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1916 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1917
1918 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1919 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1920
1921 #define RSS_FLAGS(bp) \
1922 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1923 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1924 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1925 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1926 (bp->multi_mode << \
1927 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1928 #define MULTI_MASK 0x7f
1929
1930
1931 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
1932 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
1933 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
1934 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
1935
1936 #define DEF_USB_IGU_INDEX_OFF \
1937 offsetof(struct cstorm_def_status_block_u, igu_index)
1938 #define DEF_CSB_IGU_INDEX_OFF \
1939 offsetof(struct cstorm_def_status_block_c, igu_index)
1940 #define DEF_XSB_IGU_INDEX_OFF \
1941 offsetof(struct xstorm_def_status_block, igu_index)
1942 #define DEF_TSB_IGU_INDEX_OFF \
1943 offsetof(struct tstorm_def_status_block, igu_index)
1944
1945 #define DEF_USB_SEGMENT_OFF \
1946 offsetof(struct cstorm_def_status_block_u, segment)
1947 #define DEF_CSB_SEGMENT_OFF \
1948 offsetof(struct cstorm_def_status_block_c, segment)
1949 #define DEF_XSB_SEGMENT_OFF \
1950 offsetof(struct xstorm_def_status_block, segment)
1951 #define DEF_TSB_SEGMENT_OFF \
1952 offsetof(struct tstorm_def_status_block, segment)
1953
1954 #define BNX2X_SP_DSB_INDEX \
1955 (&bp->def_status_blk->sp_sb.\
1956 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1957
1958 #define SET_FLAG(value, mask, flag) \
1959 do {\
1960 (value) &= ~(mask);\
1961 (value) |= ((flag) << (mask##_SHIFT));\
1962 } while (0)
1963
1964 #define GET_FLAG(value, mask) \
1965 (((value) & (mask)) >> (mask##_SHIFT))
1966
1967 #define GET_FIELD(value, fname) \
1968 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1969
1970 #define CAM_IS_INVALID(x) \
1971 (GET_FLAG(x.flags, \
1972 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1973 (T_ETH_MAC_COMMAND_INVALIDATE))
1974
1975 /* Number of u32 elements in MC hash array */
1976 #define MC_HASH_SIZE 8
1977 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1978 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1979
1980
1981 #ifndef PXP2_REG_PXP2_INT_STS
1982 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1983 #endif
1984
1985 #ifndef ETH_MAX_RX_CLIENTS_E2
1986 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1987 #endif
1988
1989 #define BNX2X_VPD_LEN 128
1990 #define VENDOR_ID_LEN 4
1991
1992 /* Congestion management fairness mode */
1993 #define CMNG_FNS_NONE 0
1994 #define CMNG_FNS_MINMAX 1
1995
1996 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1997 #define HC_SEG_ACCESS_ATTN 4
1998 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1999
2000 static const u32 dmae_reg_go_c[] = {
2001 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2002 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2003 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2004 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2005 };
2006
2007 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2008 void bnx2x_notify_link_changed(struct bnx2x *bp);
2009 #endif /* bnx2x.h */
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