1 /* bnx2x_cmn.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
27 /* This is used as a replacement for an MCP if it's not present */
28 extern int load_count
[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
30 extern int num_queues
;
32 /************************ Macros ********************************/
33 #define BNX2X_PCI_FREE(x, y, size) \
36 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
42 #define BNX2X_FREE(x) \
50 #define BNX2X_PCI_ALLOC(x, y, size) \
52 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
55 memset((void *)x, 0, size); \
58 #define BNX2X_ALLOC(x, size) \
60 x = kzalloc(size, GFP_KERNEL); \
65 /*********************** Interfaces ****************************
66 * Functions that need to be implemented by each driver version
71 * bnx2x_send_unload_req - request unload mode from the MCP.
74 * @unload_mode: requested function's unload mode
76 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
78 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
);
81 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
85 void bnx2x_send_unload_done(struct bnx2x
*bp
);
88 * bnx2x_config_rss_pf - configure RSS parameters.
91 * @ind_table: indirection table to configure
92 * @config_hash: re-configure RSS hash keys configuration
94 int bnx2x_config_rss_pf(struct bnx2x
*bp
, u8
*ind_table
, bool config_hash
);
97 * bnx2x__init_func_obj - init function object
101 * Initializes the Function Object with the appropriate
102 * parameters which include a function slow path driver
105 void bnx2x__init_func_obj(struct bnx2x
*bp
);
108 * bnx2x_setup_queue - setup eth queue.
111 * @fp: pointer to the fastpath structure
115 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
119 * bnx2x_setup_leading - bring up a leading eth queue.
123 int bnx2x_setup_leading(struct bnx2x
*bp
);
126 * bnx2x_fw_command - send the MCP a request
130 * @param: request's parameter
132 * block until there is a reply
134 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
);
137 * bnx2x_initial_phy_init - initialize link parameters structure variables.
140 * @load_mode: current mode
142 u8
bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
);
145 * bnx2x_link_set - configure hw according to link parameters structure.
149 void bnx2x_link_set(struct bnx2x
*bp
);
152 * bnx2x_link_test - query link status.
157 * Returns 0 if link is UP.
159 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
);
162 * bnx2x_drv_pulse - write driver pulse to shmem
166 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
169 void bnx2x_drv_pulse(struct bnx2x
*bp
);
172 * bnx2x_igu_ack_sb - update IGU with current SB value
176 * @segment: SB segment
179 * @update: is HW update required
181 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
182 u16 index
, u8 op
, u8 update
);
184 /* Disable transactions from chip to host */
185 void bnx2x_pf_disable(struct bnx2x
*bp
);
188 * bnx2x__link_status_update - handles link status change.
192 void bnx2x__link_status_update(struct bnx2x
*bp
);
195 * bnx2x_link_report - report link status to upper layer.
199 void bnx2x_link_report(struct bnx2x
*bp
);
201 /* None-atomic version of bnx2x_link_report() */
202 void __bnx2x_link_report(struct bnx2x
*bp
);
205 * bnx2x_get_mf_speed - calculate MF speed.
209 * Takes into account current linespeed and MF configuration.
211 u16
bnx2x_get_mf_speed(struct bnx2x
*bp
);
214 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
217 * @dev_instance: private instance
219 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
);
222 * bnx2x_interrupt - non MSI-X interrupt handler
225 * @dev_instance: private instance
227 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
);
231 * bnx2x_cnic_notify - send command to cnic driver
236 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
);
239 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
243 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
);
247 * bnx2x_int_enable - enable HW interrupts.
251 void bnx2x_int_enable(struct bnx2x
*bp
);
254 * bnx2x_int_disable_sync - disable interrupts.
257 * @disable_hw: true, disable HW interrupts.
259 * This function ensures that there are no
260 * ISRs or SP DPCs (sp_task) are running after it returns.
262 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
);
265 * bnx2x_nic_init - init driver internals.
268 * @load_code: COMMON, PORT or FUNCTION
275 void bnx2x_nic_init(struct bnx2x
*bp
, u32 load_code
);
278 * bnx2x_alloc_mem - allocate driver's memory.
282 int bnx2x_alloc_mem(struct bnx2x
*bp
);
285 * bnx2x_free_mem - release driver's memory.
289 void bnx2x_free_mem(struct bnx2x
*bp
);
292 * bnx2x_set_num_queues - set number of queues according to mode.
296 void bnx2x_set_num_queues(struct bnx2x
*bp
);
299 * bnx2x_chip_cleanup - cleanup chip internals.
302 * @unload_mode: COMMON, PORT, FUNCTION
304 * - Cleanup MAC configuration.
308 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
);
311 * bnx2x_acquire_hw_lock - acquire HW lock.
314 * @resource: resource bit which was locked
316 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
);
319 * bnx2x_release_hw_lock - release HW lock.
322 * @resource: resource bit which was locked
324 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
);
327 * bnx2x_release_leader_lock - release recovery leader lock
331 int bnx2x_release_leader_lock(struct bnx2x
*bp
);
334 * bnx2x_set_eth_mac - configure eth MAC address in the HW
339 * Configures according to the value in netdev->dev_addr.
341 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
);
344 * bnx2x_set_rx_mode - set MAC filtering configurations.
348 * called with netif_tx_lock from dev_mcast.c
349 * If bp->state is OPEN, should be called with
350 * netif_addr_lock_bh()
352 void bnx2x_set_rx_mode(struct net_device
*dev
);
355 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW.
359 * If bp->state is OPEN, should be called with
360 * netif_addr_lock_bh().
362 void bnx2x_set_storm_rx_mode(struct bnx2x
*bp
);
365 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue.
369 * @rx_mode_flags: rx mode configuration
370 * @rx_accept_flags: rx accept configuration
371 * @tx_accept_flags: tx accept configuration (tx switch)
372 * @ramrod_flags: ramrod configuration
374 void bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
375 unsigned long rx_mode_flags
,
376 unsigned long rx_accept_flags
,
377 unsigned long tx_accept_flags
,
378 unsigned long ramrod_flags
);
380 /* Parity errors related */
381 void bnx2x_inc_load_cnt(struct bnx2x
*bp
);
382 u32
bnx2x_dec_load_cnt(struct bnx2x
*bp
);
383 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
);
384 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
);
385 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
);
386 void bnx2x_set_reset_global(struct bnx2x
*bp
);
387 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
);
390 * bnx2x_sp_event - handle ramrods completion.
392 * @fp: fastpath handle for the event
393 * @rr_cqe: eth_rx_cqe
395 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
);
398 * bnx2x_ilt_set_info - prepare ILT configurations.
402 void bnx2x_ilt_set_info(struct bnx2x
*bp
);
405 * bnx2x_dcbx_init - initialize dcbx protocol.
409 void bnx2x_dcbx_init(struct bnx2x
*bp
);
412 * bnx2x_set_power_state - set power state to the requested value.
415 * @state: required state D0 or D3hot
417 * Currently only D0 and D3hot are supported.
419 int bnx2x_set_power_state(struct bnx2x
*bp
, pci_power_t state
);
422 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
427 void bnx2x_update_max_mf_config(struct bnx2x
*bp
, u32 value
);
429 void bnx2x_panic_dump(struct bnx2x
*bp
);
431 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
);
433 /* dev_close main block */
434 int bnx2x_nic_unload(struct bnx2x
*bp
, int unload_mode
);
436 /* dev_open main block */
437 int bnx2x_nic_load(struct bnx2x
*bp
, int load_mode
);
439 /* hard_xmit callback */
440 netdev_tx_t
bnx2x_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
442 /* setup_tc callback */
443 int bnx2x_setup_tc(struct net_device
*dev
, u8 num_tc
);
445 /* select_queue callback */
446 u16
bnx2x_select_queue(struct net_device
*dev
, struct sk_buff
*skb
);
449 int bnx2x_reload_if_running(struct net_device
*dev
);
451 int bnx2x_change_mac_addr(struct net_device
*dev
, void *p
);
453 /* NAPI poll Rx part */
454 int bnx2x_rx_int(struct bnx2x_fastpath
*fp
, int budget
);
456 void bnx2x_update_rx_prod(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
457 u16 bd_prod
, u16 rx_comp_prod
, u16 rx_sge_prod
);
459 /* NAPI poll Tx part */
460 int bnx2x_tx_int(struct bnx2x
*bp
, struct bnx2x_fp_txdata
*txdata
);
462 /* suspend/resume callbacks */
463 int bnx2x_suspend(struct pci_dev
*pdev
, pm_message_t state
);
464 int bnx2x_resume(struct pci_dev
*pdev
);
466 /* Release IRQ vectors */
467 void bnx2x_free_irq(struct bnx2x
*bp
);
469 void bnx2x_free_fp_mem(struct bnx2x
*bp
);
470 int bnx2x_alloc_fp_mem(struct bnx2x
*bp
);
471 void bnx2x_init_rx_rings(struct bnx2x
*bp
);
472 void bnx2x_free_skbs(struct bnx2x
*bp
);
473 void bnx2x_netif_stop(struct bnx2x
*bp
, int disable_hw
);
474 void bnx2x_netif_start(struct bnx2x
*bp
);
477 * bnx2x_enable_msix - set msix configuration.
481 * fills msix_table, requests vectors, updates num_queues
482 * according to number of available vectors.
484 int bnx2x_enable_msix(struct bnx2x
*bp
);
487 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
491 int bnx2x_enable_msi(struct bnx2x
*bp
);
494 * bnx2x_poll - NAPI callback
496 * @napi: napi structure
500 int bnx2x_poll(struct napi_struct
*napi
, int budget
);
503 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
507 int __devinit
bnx2x_alloc_mem_bp(struct bnx2x
*bp
);
510 * bnx2x_free_mem_bp - release memories outsize main driver structure
514 void bnx2x_free_mem_bp(struct bnx2x
*bp
);
517 * bnx2x_change_mtu - change mtu netdev callback
520 * @new_mtu: requested mtu
523 int bnx2x_change_mtu(struct net_device
*dev
, int new_mtu
);
525 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
527 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
530 * @wwn: output buffer
531 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
534 int bnx2x_fcoe_get_wwn(struct net_device
*dev
, u64
*wwn
, int type
);
536 u32
bnx2x_fix_features(struct net_device
*dev
, u32 features
);
537 int bnx2x_set_features(struct net_device
*dev
, u32 features
);
540 * bnx2x_tx_timeout - tx timeout netdev callback
544 void bnx2x_tx_timeout(struct net_device
*dev
);
546 /*********************** Inlines **********************************/
547 /*********************** Fast path ********************************/
548 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath
*fp
)
550 barrier(); /* status block is written to by the chip */
551 fp
->fp_hc_idx
= fp
->sb_running_index
[SM_RX_ID
];
554 static inline void bnx2x_update_rx_prod_gen(struct bnx2x
*bp
,
555 struct bnx2x_fastpath
*fp
, u16 bd_prod
,
556 u16 rx_comp_prod
, u16 rx_sge_prod
, u32 start
)
558 struct ustorm_eth_rx_producers rx_prods
= {0};
561 /* Update producers */
562 rx_prods
.bd_prod
= bd_prod
;
563 rx_prods
.cqe_prod
= rx_comp_prod
;
564 rx_prods
.sge_prod
= rx_sge_prod
;
567 * Make sure that the BD and SGE data is updated before updating the
568 * producers since FW might read the BD/SGE right after the producer
570 * This is only applicable for weak-ordered memory model archs such
571 * as IA-64. The following barrier is also mandatory since FW will
572 * assumes BDs must have buffers.
576 for (i
= 0; i
< sizeof(rx_prods
)/4; i
++)
577 REG_WR(bp
, start
+ i
*4, ((u32
*)&rx_prods
)[i
]);
579 mmiowb(); /* keep prod updates ordered */
581 DP(NETIF_MSG_RX_STATUS
,
582 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
583 fp
->index
, bd_prod
, rx_comp_prod
, rx_sge_prod
);
586 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x
*bp
, u8 igu_sb_id
,
587 u8 segment
, u16 index
, u8 op
,
588 u8 update
, u32 igu_addr
)
590 struct igu_regular cmd_data
= {0};
592 cmd_data
.sb_id_and_flags
=
593 ((index
<< IGU_REGULAR_SB_INDEX_SHIFT
) |
594 (segment
<< IGU_REGULAR_SEGMENT_ACCESS_SHIFT
) |
595 (update
<< IGU_REGULAR_BUPDATE_SHIFT
) |
596 (op
<< IGU_REGULAR_ENABLE_INT_SHIFT
));
598 DP(NETIF_MSG_HW
, "write 0x%08x to IGU addr 0x%x\n",
599 cmd_data
.sb_id_and_flags
, igu_addr
);
600 REG_WR(bp
, igu_addr
, cmd_data
.sb_id_and_flags
);
602 /* Make sure that ACK is written */
607 static inline void bnx2x_igu_clear_sb_gen(struct bnx2x
*bp
, u8 func
,
608 u8 idu_sb_id
, bool is_Pf
)
610 u32 data
, ctl
, cnt
= 100;
611 u32 igu_addr_data
= IGU_REG_COMMAND_REG_32LSB_DATA
;
612 u32 igu_addr_ctl
= IGU_REG_COMMAND_REG_CTRL
;
613 u32 igu_addr_ack
= IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
+ (idu_sb_id
/32)*4;
614 u32 sb_bit
= 1 << (idu_sb_id
%32);
615 u32 func_encode
= func
|
616 ((is_Pf
== true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT
);
617 u32 addr_encode
= IGU_CMD_E2_PROD_UPD_BASE
+ idu_sb_id
;
619 /* Not supported in BC mode */
620 if (CHIP_INT_MODE_IS_BC(bp
))
623 data
= (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
624 << IGU_REGULAR_CLEANUP_TYPE_SHIFT
) |
625 IGU_REGULAR_CLEANUP_SET
|
626 IGU_REGULAR_BCLEANUP
;
628 ctl
= addr_encode
<< IGU_CTRL_REG_ADDRESS_SHIFT
|
629 func_encode
<< IGU_CTRL_REG_FID_SHIFT
|
630 IGU_CTRL_CMD_TYPE_WR
<< IGU_CTRL_REG_TYPE_SHIFT
;
632 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
633 data
, igu_addr_data
);
634 REG_WR(bp
, igu_addr_data
, data
);
637 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
639 REG_WR(bp
, igu_addr_ctl
, ctl
);
643 /* wait for clean up to finish */
644 while (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
) && --cnt
)
648 if (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
)) {
649 DP(NETIF_MSG_HW
, "Unable to finish IGU cleanup: "
650 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
651 idu_sb_id
, idu_sb_id
/32, idu_sb_id
%32, cnt
);
655 static inline void bnx2x_hc_ack_sb(struct bnx2x
*bp
, u8 sb_id
,
656 u8 storm
, u16 index
, u8 op
, u8 update
)
658 u32 hc_addr
= (HC_REG_COMMAND_REG
+ BP_PORT(bp
)*32 +
659 COMMAND_REG_INT_ACK
);
660 struct igu_ack_register igu_ack
;
662 igu_ack
.status_block_index
= index
;
663 igu_ack
.sb_id_and_flags
=
664 ((sb_id
<< IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT
) |
665 (storm
<< IGU_ACK_REGISTER_STORM_ID_SHIFT
) |
666 (update
<< IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT
) |
667 (op
<< IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT
));
669 DP(BNX2X_MSG_OFF
, "write 0x%08x to HC addr 0x%x\n",
670 (*(u32
*)&igu_ack
), hc_addr
);
671 REG_WR(bp
, hc_addr
, (*(u32
*)&igu_ack
));
673 /* Make sure that ACK is written */
678 static inline void bnx2x_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 storm
,
679 u16 index
, u8 op
, u8 update
)
681 if (bp
->common
.int_block
== INT_BLOCK_HC
)
682 bnx2x_hc_ack_sb(bp
, igu_sb_id
, storm
, index
, op
, update
);
686 if (CHIP_INT_MODE_IS_BC(bp
))
688 else if (igu_sb_id
!= bp
->igu_dsb_id
)
689 segment
= IGU_SEG_ACCESS_DEF
;
690 else if (storm
== ATTENTION_ID
)
691 segment
= IGU_SEG_ACCESS_ATTN
;
693 segment
= IGU_SEG_ACCESS_DEF
;
694 bnx2x_igu_ack_sb(bp
, igu_sb_id
, segment
, index
, op
, update
);
698 static inline u16
bnx2x_hc_ack_int(struct bnx2x
*bp
)
700 u32 hc_addr
= (HC_REG_COMMAND_REG
+ BP_PORT(bp
)*32 +
701 COMMAND_REG_SIMD_MASK
);
702 u32 result
= REG_RD(bp
, hc_addr
);
704 DP(BNX2X_MSG_OFF
, "read 0x%08x from HC addr 0x%x\n",
711 static inline u16
bnx2x_igu_ack_int(struct bnx2x
*bp
)
713 u32 igu_addr
= (BAR_IGU_INTMEM
+ IGU_REG_SISR_MDPC_WMASK_LSB_UPPER
*8);
714 u32 result
= REG_RD(bp
, igu_addr
);
716 DP(NETIF_MSG_HW
, "read 0x%08x from IGU addr 0x%x\n",
723 static inline u16
bnx2x_ack_int(struct bnx2x
*bp
)
726 if (bp
->common
.int_block
== INT_BLOCK_HC
)
727 return bnx2x_hc_ack_int(bp
);
729 return bnx2x_igu_ack_int(bp
);
732 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata
*txdata
)
734 /* Tell compiler that consumer and producer can change */
736 return txdata
->tx_pkt_prod
!= txdata
->tx_pkt_cons
;
739 static inline u16
bnx2x_tx_avail(struct bnx2x
*bp
,
740 struct bnx2x_fp_txdata
*txdata
)
746 prod
= txdata
->tx_bd_prod
;
747 cons
= txdata
->tx_bd_cons
;
749 /* NUM_TX_RINGS = number of "next-page" entries
750 It will be used as a threshold */
751 used
= SUB_S16(prod
, cons
) + (s16
)NUM_TX_RINGS
;
753 #ifdef BNX2X_STOP_ON_ERROR
755 WARN_ON(used
> bp
->tx_ring_size
);
756 WARN_ON((bp
->tx_ring_size
- used
) > MAX_TX_AVAIL
);
759 return (s16
)(bp
->tx_ring_size
) - used
;
762 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata
*txdata
)
766 /* Tell compiler that status block fields can change */
768 hw_cons
= le16_to_cpu(*txdata
->tx_cons_sb
);
769 return hw_cons
!= txdata
->tx_pkt_cons
;
772 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath
*fp
)
775 for_each_cos_in_tx_queue(fp
, cos
)
776 if (bnx2x_tx_queue_has_work(&fp
->txdata
[cos
]))
781 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath
*fp
)
785 /* Tell compiler that status block fields can change */
787 rx_cons_sb
= le16_to_cpu(*fp
->rx_cons_sb
);
788 if ((rx_cons_sb
& MAX_RCQ_DESC_CNT
) == MAX_RCQ_DESC_CNT
)
790 return (fp
->rx_comp_cons
!= rx_cons_sb
);
794 * bnx2x_tx_disable - disables tx from stack point of view
798 static inline void bnx2x_tx_disable(struct bnx2x
*bp
)
800 netif_tx_disable(bp
->dev
);
801 netif_carrier_off(bp
->dev
);
804 static inline void bnx2x_free_rx_sge(struct bnx2x
*bp
,
805 struct bnx2x_fastpath
*fp
, u16 index
)
807 struct sw_rx_page
*sw_buf
= &fp
->rx_page_ring
[index
];
808 struct page
*page
= sw_buf
->page
;
809 struct eth_rx_sge
*sge
= &fp
->rx_sge_ring
[index
];
811 /* Skip "next page" elements */
815 dma_unmap_page(&bp
->pdev
->dev
, dma_unmap_addr(sw_buf
, mapping
),
816 SGE_PAGE_SIZE
*PAGES_PER_SGE
, DMA_FROM_DEVICE
);
817 __free_pages(page
, PAGES_PER_SGE_SHIFT
);
824 static inline void bnx2x_add_all_napi(struct bnx2x
*bp
)
828 /* Add NAPI objects */
829 for_each_rx_queue(bp
, i
)
830 netif_napi_add(bp
->dev
, &bnx2x_fp(bp
, i
, napi
),
831 bnx2x_poll
, BNX2X_NAPI_WEIGHT
);
834 static inline void bnx2x_del_all_napi(struct bnx2x
*bp
)
838 for_each_rx_queue(bp
, i
)
839 netif_napi_del(&bnx2x_fp(bp
, i
, napi
));
842 static inline void bnx2x_disable_msi(struct bnx2x
*bp
)
844 if (bp
->flags
& USING_MSIX_FLAG
) {
845 pci_disable_msix(bp
->pdev
);
846 bp
->flags
&= ~USING_MSIX_FLAG
;
847 } else if (bp
->flags
& USING_MSI_FLAG
) {
848 pci_disable_msi(bp
->pdev
);
849 bp
->flags
&= ~USING_MSI_FLAG
;
853 static inline int bnx2x_calc_num_queues(struct bnx2x
*bp
)
856 min_t(int, num_queues
, BNX2X_MAX_QUEUES(bp
)) :
857 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp
));
860 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath
*fp
)
864 for (i
= 1; i
<= NUM_RX_SGE_PAGES
; i
++) {
865 int idx
= RX_SGE_CNT
* i
- 1;
867 for (j
= 0; j
< 2; j
++) {
868 BIT_VEC64_CLEAR_BIT(fp
->sge_mask
, idx
);
874 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath
*fp
)
876 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
877 memset(fp
->sge_mask
, 0xff,
878 (NUM_RX_SGE
>> BIT_VEC64_ELEM_SHIFT
)*sizeof(u64
));
880 /* Clear the two last indices in the page to 1:
881 these are the indices that correspond to the "next" element,
882 hence will never be indicated and should be removed from
884 bnx2x_clear_sge_mask_next_elems(fp
);
887 static inline int bnx2x_alloc_rx_sge(struct bnx2x
*bp
,
888 struct bnx2x_fastpath
*fp
, u16 index
)
890 struct page
*page
= alloc_pages(GFP_ATOMIC
, PAGES_PER_SGE_SHIFT
);
891 struct sw_rx_page
*sw_buf
= &fp
->rx_page_ring
[index
];
892 struct eth_rx_sge
*sge
= &fp
->rx_sge_ring
[index
];
895 if (unlikely(page
== NULL
))
898 mapping
= dma_map_page(&bp
->pdev
->dev
, page
, 0,
899 SGE_PAGE_SIZE
*PAGES_PER_SGE
, DMA_FROM_DEVICE
);
900 if (unlikely(dma_mapping_error(&bp
->pdev
->dev
, mapping
))) {
901 __free_pages(page
, PAGES_PER_SGE_SHIFT
);
906 dma_unmap_addr_set(sw_buf
, mapping
, mapping
);
908 sge
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
909 sge
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
914 static inline int bnx2x_alloc_rx_skb(struct bnx2x
*bp
,
915 struct bnx2x_fastpath
*fp
, u16 index
)
918 struct sw_rx_bd
*rx_buf
= &fp
->rx_buf_ring
[index
];
919 struct eth_rx_bd
*rx_bd
= &fp
->rx_desc_ring
[index
];
922 skb
= netdev_alloc_skb(bp
->dev
, fp
->rx_buf_size
);
923 if (unlikely(skb
== NULL
))
926 mapping
= dma_map_single(&bp
->pdev
->dev
, skb
->data
, fp
->rx_buf_size
,
928 if (unlikely(dma_mapping_error(&bp
->pdev
->dev
, mapping
))) {
929 dev_kfree_skb_any(skb
);
934 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
936 rx_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
937 rx_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
942 /* note that we are not allocating a new skb,
943 * we are just moving one from cons to prod
944 * we are not creating a new mapping,
945 * so there is no need to check for dma_mapping_error().
947 static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath
*fp
,
950 struct sw_rx_bd
*cons_rx_buf
= &fp
->rx_buf_ring
[cons
];
951 struct sw_rx_bd
*prod_rx_buf
= &fp
->rx_buf_ring
[prod
];
952 struct eth_rx_bd
*cons_bd
= &fp
->rx_desc_ring
[cons
];
953 struct eth_rx_bd
*prod_bd
= &fp
->rx_desc_ring
[prod
];
955 dma_unmap_addr_set(prod_rx_buf
, mapping
,
956 dma_unmap_addr(cons_rx_buf
, mapping
));
957 prod_rx_buf
->skb
= cons_rx_buf
->skb
;
961 /************************* Init ******************************************/
964 * bnx2x_func_start - init function
968 * Must be called before sending CLIENT_SETUP for the first client.
970 static inline int bnx2x_func_start(struct bnx2x
*bp
)
972 struct bnx2x_func_state_params func_params
= {0};
973 struct bnx2x_func_start_params
*start_params
=
974 &func_params
.params
.start
;
976 /* Prepare parameters for function state transitions */
977 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
979 func_params
.f_obj
= &bp
->func_obj
;
980 func_params
.cmd
= BNX2X_F_CMD_START
;
982 /* Function parameters */
983 start_params
->mf_mode
= bp
->mf_mode
;
984 start_params
->sd_vlan_tag
= bp
->mf_ov
;
986 start_params
->network_cos_mode
= OVERRIDE_COS
;
988 start_params
->network_cos_mode
= STATIC_COS
;
990 return bnx2x_func_state_change(bp
, &func_params
);
995 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
997 * @fw_hi: pointer to upper part
998 * @fw_mid: pointer to middle part
999 * @fw_lo: pointer to lower part
1000 * @mac: pointer to MAC address
1002 static inline void bnx2x_set_fw_mac_addr(u16
*fw_hi
, u16
*fw_mid
, u16
*fw_lo
,
1005 ((u8
*)fw_hi
)[0] = mac
[1];
1006 ((u8
*)fw_hi
)[1] = mac
[0];
1007 ((u8
*)fw_mid
)[0] = mac
[3];
1008 ((u8
*)fw_mid
)[1] = mac
[2];
1009 ((u8
*)fw_lo
)[0] = mac
[5];
1010 ((u8
*)fw_lo
)[1] = mac
[4];
1013 static inline void bnx2x_free_rx_sge_range(struct bnx2x
*bp
,
1014 struct bnx2x_fastpath
*fp
, int last
)
1018 if (fp
->disable_tpa
)
1021 for (i
= 0; i
< last
; i
++)
1022 bnx2x_free_rx_sge(bp
, fp
, i
);
1025 static inline void bnx2x_free_tpa_pool(struct bnx2x
*bp
,
1026 struct bnx2x_fastpath
*fp
, int last
)
1030 for (i
= 0; i
< last
; i
++) {
1031 struct bnx2x_agg_info
*tpa_info
= &fp
->tpa_info
[i
];
1032 struct sw_rx_bd
*first_buf
= &tpa_info
->first_buf
;
1033 struct sk_buff
*skb
= first_buf
->skb
;
1036 DP(NETIF_MSG_IFDOWN
, "tpa bin %d empty on free\n", i
);
1039 if (tpa_info
->tpa_state
== BNX2X_TPA_START
)
1040 dma_unmap_single(&bp
->pdev
->dev
,
1041 dma_unmap_addr(first_buf
, mapping
),
1042 fp
->rx_buf_size
, DMA_FROM_DEVICE
);
1044 first_buf
->skb
= NULL
;
1048 static inline void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata
*txdata
)
1052 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
1053 struct eth_tx_next_bd
*tx_next_bd
=
1054 &txdata
->tx_desc_ring
[TX_DESC_CNT
* i
- 1].next_bd
;
1056 tx_next_bd
->addr_hi
=
1057 cpu_to_le32(U64_HI(txdata
->tx_desc_mapping
+
1058 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
1059 tx_next_bd
->addr_lo
=
1060 cpu_to_le32(U64_LO(txdata
->tx_desc_mapping
+
1061 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
1064 SET_FLAG(txdata
->tx_db
.data
.header
.header
, DOORBELL_HDR_DB_TYPE
, 1);
1065 txdata
->tx_db
.data
.zero_fill1
= 0;
1066 txdata
->tx_db
.data
.prod
= 0;
1068 txdata
->tx_pkt_prod
= 0;
1069 txdata
->tx_pkt_cons
= 0;
1070 txdata
->tx_bd_prod
= 0;
1071 txdata
->tx_bd_cons
= 0;
1075 static inline void bnx2x_init_tx_rings(struct bnx2x
*bp
)
1080 for_each_tx_queue(bp
, i
)
1081 for_each_cos_in_tx_queue(&bp
->fp
[i
], cos
)
1082 bnx2x_init_tx_ring_one(&bp
->fp
[i
].txdata
[cos
]);
1085 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath
*fp
)
1089 for (i
= 1; i
<= NUM_RX_RINGS
; i
++) {
1090 struct eth_rx_bd
*rx_bd
;
1092 rx_bd
= &fp
->rx_desc_ring
[RX_DESC_CNT
* i
- 2];
1094 cpu_to_le32(U64_HI(fp
->rx_desc_mapping
+
1095 BCM_PAGE_SIZE
*(i
% NUM_RX_RINGS
)));
1097 cpu_to_le32(U64_LO(fp
->rx_desc_mapping
+
1098 BCM_PAGE_SIZE
*(i
% NUM_RX_RINGS
)));
1102 static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath
*fp
)
1106 for (i
= 1; i
<= NUM_RX_SGE_PAGES
; i
++) {
1107 struct eth_rx_sge
*sge
;
1109 sge
= &fp
->rx_sge_ring
[RX_SGE_CNT
* i
- 2];
1111 cpu_to_le32(U64_HI(fp
->rx_sge_mapping
+
1112 BCM_PAGE_SIZE
*(i
% NUM_RX_SGE_PAGES
)));
1115 cpu_to_le32(U64_LO(fp
->rx_sge_mapping
+
1116 BCM_PAGE_SIZE
*(i
% NUM_RX_SGE_PAGES
)));
1120 static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath
*fp
)
1123 for (i
= 1; i
<= NUM_RCQ_RINGS
; i
++) {
1124 struct eth_rx_cqe_next_page
*nextpg
;
1126 nextpg
= (struct eth_rx_cqe_next_page
*)
1127 &fp
->rx_comp_ring
[RCQ_DESC_CNT
* i
- 1];
1129 cpu_to_le32(U64_HI(fp
->rx_comp_mapping
+
1130 BCM_PAGE_SIZE
*(i
% NUM_RCQ_RINGS
)));
1132 cpu_to_le32(U64_LO(fp
->rx_comp_mapping
+
1133 BCM_PAGE_SIZE
*(i
% NUM_RCQ_RINGS
)));
1137 /* Returns the number of actually allocated BDs */
1138 static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath
*fp
,
1141 struct bnx2x
*bp
= fp
->bp
;
1142 u16 ring_prod
, cqe_ring_prod
;
1145 fp
->rx_comp_cons
= 0;
1146 cqe_ring_prod
= ring_prod
= 0;
1148 /* This routine is called only during fo init so
1149 * fp->eth_q_stats.rx_skb_alloc_failed = 0
1151 for (i
= 0; i
< rx_ring_size
; i
++) {
1152 if (bnx2x_alloc_rx_skb(bp
, fp
, ring_prod
) < 0) {
1153 fp
->eth_q_stats
.rx_skb_alloc_failed
++;
1156 ring_prod
= NEXT_RX_IDX(ring_prod
);
1157 cqe_ring_prod
= NEXT_RCQ_IDX(cqe_ring_prod
);
1158 WARN_ON(ring_prod
<= (i
- fp
->eth_q_stats
.rx_skb_alloc_failed
));
1161 if (fp
->eth_q_stats
.rx_skb_alloc_failed
)
1162 BNX2X_ERR("was only able to allocate "
1163 "%d rx skbs on queue[%d]\n",
1164 (i
- fp
->eth_q_stats
.rx_skb_alloc_failed
), fp
->index
);
1166 fp
->rx_bd_prod
= ring_prod
;
1167 /* Limit the CQE producer by the CQE ring size */
1168 fp
->rx_comp_prod
= min_t(u16
, NUM_RCQ_RINGS
*RCQ_DESC_CNT
,
1170 fp
->rx_pkt
= fp
->rx_calls
= 0;
1172 return i
- fp
->eth_q_stats
.rx_skb_alloc_failed
;
1175 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
1178 static inline u8
bnx2x_stats_id(struct bnx2x_fastpath
*fp
)
1180 if (!CHIP_IS_E1x(fp
->bp
))
1183 return fp
->cl_id
+ BP_PORT(fp
->bp
) * FP_SB_MAX_E1x
;
1186 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath
*fp
,
1187 bnx2x_obj_type obj_type
)
1189 struct bnx2x
*bp
= fp
->bp
;
1191 /* Configure classification DBs */
1192 bnx2x_init_mac_obj(bp
, &fp
->mac_obj
, fp
->cl_id
, fp
->cid
,
1193 BP_FUNC(bp
), bnx2x_sp(bp
, mac_rdata
),
1194 bnx2x_sp_mapping(bp
, mac_rdata
),
1195 BNX2X_FILTER_MAC_PENDING
,
1196 &bp
->sp_state
, obj_type
,
1201 * bnx2x_get_path_func_num - get number of active functions
1203 * @bp: driver handle
1205 * Calculates the number of active (not hidden) functions on the
1208 static inline u8
bnx2x_get_path_func_num(struct bnx2x
*bp
)
1212 /* 57710 has only one function per-port */
1216 /* Calculate a number of functions enabled on the current
1219 if (CHIP_REV_IS_SLOW(bp
)) {
1225 for (i
= 0; i
< E1H_FUNC_MAX
/ 2; i
++) {
1228 func_mf_config
[BP_PORT(bp
) + 2 * i
].
1231 ((func_config
& FUNC_MF_CFG_FUNC_HIDE
) ? 0 : 1);
1240 static inline void bnx2x_init_bp_objs(struct bnx2x
*bp
)
1242 /* RX_MODE controlling object */
1243 bnx2x_init_rx_mode_obj(bp
, &bp
->rx_mode_obj
);
1245 /* multicast configuration controlling object */
1246 bnx2x_init_mcast_obj(bp
, &bp
->mcast_obj
, bp
->fp
->cl_id
, bp
->fp
->cid
,
1247 BP_FUNC(bp
), BP_FUNC(bp
),
1248 bnx2x_sp(bp
, mcast_rdata
),
1249 bnx2x_sp_mapping(bp
, mcast_rdata
),
1250 BNX2X_FILTER_MCAST_PENDING
, &bp
->sp_state
,
1253 /* Setup CAM credit pools */
1254 bnx2x_init_mac_credit_pool(bp
, &bp
->macs_pool
, BP_FUNC(bp
),
1255 bnx2x_get_path_func_num(bp
));
1257 /* RSS configuration object */
1258 bnx2x_init_rss_config_obj(bp
, &bp
->rss_conf_obj
, bp
->fp
->cl_id
,
1259 bp
->fp
->cid
, BP_FUNC(bp
), BP_FUNC(bp
),
1260 bnx2x_sp(bp
, rss_rdata
),
1261 bnx2x_sp_mapping(bp
, rss_rdata
),
1262 BNX2X_FILTER_RSS_CONF_PENDING
, &bp
->sp_state
,
1266 static inline u8
bnx2x_fp_qzone_id(struct bnx2x_fastpath
*fp
)
1268 if (CHIP_IS_E1x(fp
->bp
))
1269 return fp
->cl_id
+ BP_PORT(fp
->bp
) * ETH_MAX_RX_CLIENTS_E1H
;
1274 static inline u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
)
1276 struct bnx2x
*bp
= fp
->bp
;
1278 if (!CHIP_IS_E1x(bp
))
1279 return USTORM_RX_PRODS_E2_OFFSET(fp
->cl_qzone_id
);
1281 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp
), fp
->cl_id
);
1284 static inline void bnx2x_init_txdata(struct bnx2x
*bp
,
1285 struct bnx2x_fp_txdata
*txdata
, u32 cid
, int txq_index
,
1289 txdata
->txq_index
= txq_index
;
1290 txdata
->tx_cons_sb
= tx_cons_sb
;
1292 DP(BNX2X_MSG_SP
, "created tx data cid %d, txq %d\n",
1293 txdata
->cid
, txdata
->txq_index
);
1297 static inline u8
bnx2x_cnic_eth_cl_id(struct bnx2x
*bp
, u8 cl_idx
)
1299 return bp
->cnic_base_cl_id
+ cl_idx
+
1300 (bp
->pf_num
>> 1) * NON_ETH_CONTEXT_USE
;
1303 static inline u8
bnx2x_cnic_fw_sb_id(struct bnx2x
*bp
)
1306 /* the 'first' id is allocated for the cnic */
1307 return bp
->base_fw_ndsb
;
1310 static inline u8
bnx2x_cnic_igu_sb_id(struct bnx2x
*bp
)
1312 return bp
->igu_base_sb
;
1316 static inline void bnx2x_init_fcoe_fp(struct bnx2x
*bp
)
1318 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
1319 unsigned long q_type
= 0;
1321 bnx2x_fcoe(bp
, cl_id
) = bnx2x_cnic_eth_cl_id(bp
,
1322 BNX2X_FCOE_ETH_CL_ID_IDX
);
1323 /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than
1324 * 16 ETH clients per function when CNIC is enabled!
1328 bnx2x_fcoe(bp
, cid
) = BNX2X_FCOE_ETH_CID
;
1329 bnx2x_fcoe(bp
, fw_sb_id
) = DEF_SB_ID
;
1330 bnx2x_fcoe(bp
, igu_sb_id
) = bp
->igu_dsb_id
;
1331 bnx2x_fcoe(bp
, rx_cons_sb
) = BNX2X_FCOE_L2_RX_INDEX
;
1333 bnx2x_init_txdata(bp
, &bnx2x_fcoe(bp
, txdata
[0]),
1334 fp
->cid
, FCOE_TXQ_IDX(bp
), BNX2X_FCOE_L2_TX_INDEX
);
1336 DP(BNX2X_MSG_SP
, "created fcoe tx data (fp index %d)\n", fp
->index
);
1338 /* qZone id equals to FW (per path) client id */
1339 bnx2x_fcoe(bp
, cl_qzone_id
) = bnx2x_fp_qzone_id(fp
);
1341 bnx2x_fcoe(bp
, ustorm_rx_prods_offset
) =
1342 bnx2x_rx_ustorm_prods_offset(fp
);
1344 /* Configure Queue State object */
1345 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
1346 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
1348 /* No multi-CoS for FCoE L2 client */
1349 BUG_ON(fp
->max_cos
!= 1);
1351 bnx2x_init_queue_obj(bp
, &fp
->q_obj
, fp
->cl_id
, &fp
->cid
, 1,
1352 BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
1353 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
1355 DP(NETIF_MSG_IFUP
, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d "
1357 fp
->index
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
1362 static inline int bnx2x_clean_tx_queue(struct bnx2x
*bp
,
1363 struct bnx2x_fp_txdata
*txdata
)
1367 while (bnx2x_has_tx_work_unload(txdata
)) {
1369 BNX2X_ERR("timeout waiting for queue[%d]: "
1370 "txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1371 txdata
->txq_index
, txdata
->tx_pkt_prod
,
1372 txdata
->tx_pkt_cons
);
1373 #ifdef BNX2X_STOP_ON_ERROR
1381 usleep_range(1000, 1000);
1387 int bnx2x_get_link_cfg_idx(struct bnx2x
*bp
);
1389 static inline void __storm_memset_struct(struct bnx2x
*bp
,
1390 u32 addr
, size_t size
, u32
*data
)
1393 for (i
= 0; i
< size
/4; i
++)
1394 REG_WR(bp
, addr
+ (i
* 4), data
[i
]);
1397 static inline void storm_memset_func_cfg(struct bnx2x
*bp
,
1398 struct tstorm_eth_function_common_config
*tcfg
,
1401 size_t size
= sizeof(struct tstorm_eth_function_common_config
);
1403 u32 addr
= BAR_TSTRORM_INTMEM
+
1404 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid
);
1406 __storm_memset_struct(bp
, addr
, size
, (u32
*)tcfg
);
1409 static inline void storm_memset_cmng(struct bnx2x
*bp
,
1410 struct cmng_struct_per_port
*cmng
,
1413 size_t size
= sizeof(struct cmng_struct_per_port
);
1415 u32 addr
= BAR_XSTRORM_INTMEM
+
1416 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
);
1418 __storm_memset_struct(bp
, addr
, size
, (u32
*)cmng
);
1422 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1424 * @bp: driver handle
1425 * @mask: bits that need to be cleared
1427 static inline bool bnx2x_wait_sp_comp(struct bnx2x
*bp
, unsigned long mask
)
1429 int tout
= 5000; /* Wait for 5 secs tops */
1433 netif_addr_lock_bh(bp
->dev
);
1434 if (!(bp
->sp_state
& mask
)) {
1435 netif_addr_unlock_bh(bp
->dev
);
1438 netif_addr_unlock_bh(bp
->dev
);
1440 usleep_range(1000, 1000);
1445 netif_addr_lock_bh(bp
->dev
);
1446 if (bp
->sp_state
& mask
) {
1447 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, "
1448 "mask 0x%lx\n", bp
->sp_state
, mask
);
1449 netif_addr_unlock_bh(bp
->dev
);
1452 netif_addr_unlock_bh(bp
->dev
);
1458 * bnx2x_set_ctx_validation - set CDU context validation values
1460 * @bp: driver handle
1461 * @cxt: context of the connection on the host memory
1462 * @cid: SW CID of the connection to be configured
1464 void bnx2x_set_ctx_validation(struct bnx2x
*bp
, struct eth_context
*cxt
,
1467 void bnx2x_update_coalesce_sb_index(struct bnx2x
*bp
, u8 fw_sb_id
,
1468 u8 sb_index
, u8 disable
, u16 usec
);
1469 void bnx2x_acquire_phy_lock(struct bnx2x
*bp
);
1470 void bnx2x_release_phy_lock(struct bnx2x
*bp
);
1473 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1475 * @bp: driver handle
1476 * @mf_cfg: MF configuration
1479 static inline u16
bnx2x_extract_max_cfg(struct bnx2x
*bp
, u32 mf_cfg
)
1481 u16 max_cfg
= (mf_cfg
& FUNC_MF_CFG_MAX_BW_MASK
) >>
1482 FUNC_MF_CFG_MAX_BW_SHIFT
;
1485 "Max BW configured to 0 - using 100 instead\n");
1491 #endif /* BNX2X_CMN_H */