?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.c
blob8e9b87be3002b0e06c596d848b2107fce2734528
1 /* Copyright 2008-2011 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29
30
31 /********************************************************/
32 #define ETH_HLEN 14
33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
34 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
35 #define ETH_MIN_PACKET_SIZE 60
36 #define ETH_MAX_PACKET_SIZE 1500
37 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
38 #define MDIO_ACCESS_TIMEOUT 1000
39 #define BMAC_CONTROL_RX_ENABLE 2
40 #define WC_LANE_MAX 4
41 #define I2C_SWITCH_WIDTH 2
42 #define I2C_BSC0 0
43 #define I2C_BSC1 1
44 #define I2C_WA_RETRY_CNT 3
45 #define MCPR_IMC_COMMAND_READ_OP 1
46 #define MCPR_IMC_COMMAND_WRITE_OP 2
47
48 /***********************************************************/
49 /* Shortcut definitions */
50 /***********************************************************/
51
52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
53
54 #define NIG_STATUS_EMAC0_MI_INT \
55 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
56 #define NIG_STATUS_XGXS0_LINK10G \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
58 #define NIG_STATUS_XGXS0_LINK_STATUS \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
62 #define NIG_STATUS_SERDES0_LINK_STATUS \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
64 #define NIG_MASK_MI_INT \
65 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
66 #define NIG_MASK_XGXS0_LINK10G \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
68 #define NIG_MASK_XGXS0_LINK_STATUS \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
70 #define NIG_MASK_SERDES0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
72
73 #define MDIO_AN_CL73_OR_37_COMPLETE \
74 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
75 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
76
77 #define XGXS_RESET_BITS \
78 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
83
84 #define SERDES_RESET_BITS \
85 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
89
90 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
91 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
92 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
93 #define AUTONEG_PARALLEL \
94 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
95 #define AUTONEG_SGMII_FIBER_AUTODET \
96 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
97 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
98
99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
103 #define GP_STATUS_SPEED_MASK \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
105 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
106 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
107 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
108 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
109 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
110 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
111 #define GP_STATUS_10G_HIG \
112 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
113 #define GP_STATUS_10G_CX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
116 #define GP_STATUS_10G_KX4 \
117 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
119 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
121 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
122 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
123 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
124 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
125 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
126 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
127 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
128 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
129 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
130 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
131 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
132 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
133 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
134 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
135 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
136 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
137
138
139
140 /* */
141 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
144
145
146 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
147 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
148 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
149 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
150
151 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
152 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
154
155 #define SFP_EEPROM_OPTIONS_ADDR 0x40
156 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
157 #define SFP_EEPROM_OPTIONS_SIZE 2
158
159 #define EDC_MODE_LINEAR 0x0022
160 #define EDC_MODE_LIMITING 0x0044
161 #define EDC_MODE_PASSIVE_DAC 0x0055
162
163
164 /* BRB thresholds for E2*/
165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
167
168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
170
171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
173
174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
176
177 /* BRB thresholds for E3A0 */
178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
180
181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
183
184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
186
187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
189
190
191 /* BRB thresholds for E3B0 2 port mode*/
192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
194
195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
197
198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
200
201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
203
204 /* only for E3B0*/
205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
207
208 /* Lossy +Lossless GUARANTIED == GUART */
209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
210 /* Lossless +Lossless*/
211 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
212 /* Lossy +Lossy*/
213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
214
215 /* Lossy +Lossless*/
216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
217 /* Lossless +Lossless*/
218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
219 /* Lossy +Lossy*/
220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
222
223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
225
226 /* BRB thresholds for E3B0 4 port mode */
227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
229
230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
232
233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
235
236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
238
239
240 /* only for E3B0*/
241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
243 #define PFC_E3B0_4P_LB_GUART 120
244
245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
247
248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
250
251 #define DCBX_INVALID_COS (0xFF)
252
253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
254 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
257 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
258
259 #define MAX_PACKET_SIZE (9700)
260 #define WC_UC_TIMEOUT 100
261
262 /**********************************************************/
263 /* INTERFACE */
264 /**********************************************************/
265
266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
267 bnx2x_cl45_write(_bp, _phy, \
268 (_phy)->def_md_devad, \
269 (_bank + (_addr & 0xf)), \
270 _val)
271
272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
273 bnx2x_cl45_read(_bp, _phy, \
274 (_phy)->def_md_devad, \
275 (_bank + (_addr & 0xf)), \
276 _val)
277
278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
279 {
280 u32 val = REG_RD(bp, reg);
281
282 val |= bits;
283 REG_WR(bp, reg, val);
284 return val;
285 }
286
287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
288 {
289 u32 val = REG_RD(bp, reg);
290
291 val &= ~bits;
292 REG_WR(bp, reg, val);
293 return val;
294 }
295
296 /******************************************************************/
297 /* EPIO/GPIO section */
298 /******************************************************************/
299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
300 {
301 u32 epio_mask, gp_oenable;
302 *en = 0;
303 /* Sanity check */
304 if (epio_pin > 31) {
305 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
306 return;
307 }
308
309 epio_mask = 1 << epio_pin;
310 /* Set this EPIO to output */
311 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
312 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
313
314 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
315 }
316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
317 {
318 u32 epio_mask, gp_output, gp_oenable;
319
320 /* Sanity check */
321 if (epio_pin > 31) {
322 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
323 return;
324 }
325 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
326 epio_mask = 1 << epio_pin;
327 /* Set this EPIO to output */
328 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
329 if (en)
330 gp_output |= epio_mask;
331 else
332 gp_output &= ~epio_mask;
333
334 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
335
336 /* Set the value for this EPIO */
337 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
338 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
339 }
340
341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
342 {
343 if (pin_cfg == PIN_CFG_NA)
344 return;
345 if (pin_cfg >= PIN_CFG_EPIO0) {
346 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
347 } else {
348 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
349 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
350 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
351 }
352 }
353
354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
355 {
356 if (pin_cfg == PIN_CFG_NA)
357 return -EINVAL;
358 if (pin_cfg >= PIN_CFG_EPIO0) {
359 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
360 } else {
361 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
362 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
363 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
364 }
365 return 0;
366
367 }
368 /******************************************************************/
369 /* ETS section */
370 /******************************************************************/
371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
372 {
373 /* ETS disabled configuration*/
374 struct bnx2x *bp = params->bp;
375
376 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
377
378 /*
379 * mapping between entry priority to client number (0,1,2 -debug and
380 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
381 * 3bits client num.
382 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
383 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
384 */
385
386 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
387 /*
388 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
389 * as strict. Bits 0,1,2 - debug and management entries, 3 -
390 * COS0 entry, 4 - COS1 entry.
391 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
392 * bit4 bit3 bit2 bit1 bit0
393 * MCP and debug are strict
394 */
395
396 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
397 /* defines which entries (clients) are subjected to WFQ arbitration */
398 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
399 /*
400 * For strict priority entries defines the number of consecutive
401 * slots for the highest priority.
402 */
403 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
404 /*
405 * mapping between the CREDIT_WEIGHT registers and actual client
406 * numbers
407 */
408 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
409 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
410 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
411
412 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
413 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
414 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
415 /* ETS mode disable */
416 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
417 /*
418 * If ETS mode is enabled (there is no strict priority) defines a WFQ
419 * weight for COS0/COS1.
420 */
421 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
422 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
423 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
424 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
425 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
426 /* Defines the number of consecutive slots for the strict priority */
427 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
428 }
429 /******************************************************************************
430 * Description:
431 * Getting min_w_val will be set according to line speed .
432 *.
433 ******************************************************************************/
434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
435 {
436 u32 min_w_val = 0;
437 /* Calculate min_w_val.*/
438 if (vars->link_up) {
439 if (SPEED_20000 == vars->line_speed)
440 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
441 else
442 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
443 } else
444 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
445 /**
446 * If the link isn't up (static configuration for example ) The
447 * link will be according to 20GBPS.
448 */
449 return min_w_val;
450 }
451 /******************************************************************************
452 * Description:
453 * Getting credit upper bound form min_w_val.
454 *.
455 ******************************************************************************/
456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
457 {
458 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
459 MAX_PACKET_SIZE);
460 return credit_upper_bound;
461 }
462 /******************************************************************************
463 * Description:
464 * Set credit upper bound for NIG.
465 *.
466 ******************************************************************************/
467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
468 const struct link_params *params,
469 const u32 min_w_val)
470 {
471 struct bnx2x *bp = params->bp;
472 const u8 port = params->port;
473 const u32 credit_upper_bound =
474 bnx2x_ets_get_credit_upper_bound(min_w_val);
475
476 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
477 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
478 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
479 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
480 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
481 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
482 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
483 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
484 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
485 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
486 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
487 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
488
489 if (0 == port) {
490 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
491 credit_upper_bound);
492 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
493 credit_upper_bound);
494 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
495 credit_upper_bound);
496 }
497 }
498 /******************************************************************************
499 * Description:
500 * Will return the NIG ETS registers to init values.Except
501 * credit_upper_bound.
502 * That isn't used in this configuration (No WFQ is enabled) and will be
503 * configured acording to spec
504 *.
505 ******************************************************************************/
506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
507 const struct link_vars *vars)
508 {
509 struct bnx2x *bp = params->bp;
510 const u8 port = params->port;
511 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
512 /**
513 * mapping between entry priority to client number (0,1,2 -debug and
514 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
515 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
516 * reset value or init tool
517 */
518 if (port) {
519 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
520 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
521 } else {
522 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
523 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
524 }
525 /**
526 * For strict priority entries defines the number of consecutive
527 * slots for the highest priority.
528 */
529 /* TODO_ETS - Should be done by reset value or init tool */
530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
531 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
532 /**
533 * mapping between the CREDIT_WEIGHT registers and actual client
534 * numbers
535 */
536 /* TODO_ETS - Should be done by reset value or init tool */
537 if (port) {
538 /*Port 1 has 6 COS*/
539 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
540 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
541 } else {
542 /*Port 0 has 9 COS*/
543 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
544 0x43210876);
545 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
546 }
547
548 /**
549 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
550 * as strict. Bits 0,1,2 - debug and management entries, 3 -
551 * COS0 entry, 4 - COS1 entry.
552 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
553 * bit4 bit3 bit2 bit1 bit0
554 * MCP and debug are strict
555 */
556 if (port)
557 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
558 else
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
560 /* defines which entries (clients) are subjected to WFQ arbitration */
561 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
562 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
563
564 /**
565 * Please notice the register address are note continuous and a
566 * for here is note appropriate.In 2 port mode port0 only COS0-5
567 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
568 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
569 * are never used for WFQ
570 */
571 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
572 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
573 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
574 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
575 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
578 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
579 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
581 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
582 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
583 if (0 == port) {
584 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
586 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
587 }
588
589 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
590 }
591 /******************************************************************************
592 * Description:
593 * Set credit upper bound for PBF.
594 *.
595 ******************************************************************************/
596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
597 const struct link_params *params,
598 const u32 min_w_val)
599 {
600 struct bnx2x *bp = params->bp;
601 const u32 credit_upper_bound =
602 bnx2x_ets_get_credit_upper_bound(min_w_val);
603 const u8 port = params->port;
604 u32 base_upper_bound = 0;
605 u8 max_cos = 0;
606 u8 i = 0;
607 /**
608 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
609 * port mode port1 has COS0-2 that can be used for WFQ.
610 */
611 if (0 == port) {
612 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
613 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
614 } else {
615 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
616 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
617 }
618
619 for (i = 0; i < max_cos; i++)
620 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
621 }
622
623 /******************************************************************************
624 * Description:
625 * Will return the PBF ETS registers to init values.Except
626 * credit_upper_bound.
627 * That isn't used in this configuration (No WFQ is enabled) and will be
628 * configured acording to spec
629 *.
630 ******************************************************************************/
631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
632 {
633 struct bnx2x *bp = params->bp;
634 const u8 port = params->port;
635 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
636 u8 i = 0;
637 u32 base_weight = 0;
638 u8 max_cos = 0;
639
640 /**
641 * mapping between entry priority to client number 0 - COS0
642 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
643 * TODO_ETS - Should be done by reset value or init tool
644 */
645 if (port)
646 /* 0x688 (|011|0 10|00 1|000) */
647 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
648 else
649 /* (10 1|100 |011|0 10|00 1|000) */
650 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
651
652 /* TODO_ETS - Should be done by reset value or init tool */
653 if (port)
654 /* 0x688 (|011|0 10|00 1|000)*/
655 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
656 else
657 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
658 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
659
660 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
661 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
662
663
664 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
665 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
666
667 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
668 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
669 /**
670 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
671 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
672 */
673 if (0 == port) {
674 base_weight = PBF_REG_COS0_WEIGHT_P0;
675 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
676 } else {
677 base_weight = PBF_REG_COS0_WEIGHT_P1;
678 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
679 }
680
681 for (i = 0; i < max_cos; i++)
682 REG_WR(bp, base_weight + (0x4 * i), 0);
683
684 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
685 }
686 /******************************************************************************
687 * Description:
688 * E3B0 disable will return basicly the values to init values.
689 *.
690 ******************************************************************************/
691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
692 const struct link_vars *vars)
693 {
694 struct bnx2x *bp = params->bp;
695
696 if (!CHIP_IS_E3B0(bp)) {
697 DP(NETIF_MSG_LINK,
698 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
699 return -EINVAL;
700 }
701
702 bnx2x_ets_e3b0_nig_disabled(params, vars);
703
704 bnx2x_ets_e3b0_pbf_disabled(params);
705
706 return 0;
707 }
708
709 /******************************************************************************
710 * Description:
711 * Disable will return basicly the values to init values.
712 *.
713 ******************************************************************************/
714 int bnx2x_ets_disabled(struct link_params *params,
715 struct link_vars *vars)
716 {
717 struct bnx2x *bp = params->bp;
718 int bnx2x_status = 0;
719
720 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
721 bnx2x_ets_e2e3a0_disabled(params);
722 else if (CHIP_IS_E3B0(bp))
723 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
724 else {
725 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
726 return -EINVAL;
727 }
728
729 return bnx2x_status;
730 }
731
732 /******************************************************************************
733 * Description
734 * Set the COS mappimg to SP and BW until this point all the COS are not
735 * set as SP or BW.
736 ******************************************************************************/
737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
738 const struct bnx2x_ets_params *ets_params,
739 const u8 cos_sp_bitmap,
740 const u8 cos_bw_bitmap)
741 {
742 struct bnx2x *bp = params->bp;
743 const u8 port = params->port;
744 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
745 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
746 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
747 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
748
749 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
750 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
751
752 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
753 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
754
755 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
756 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
757 nig_cli_subject2wfq_bitmap);
758
759 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
760 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
761 pbf_cli_subject2wfq_bitmap);
762
763 return 0;
764 }
765
766 /******************************************************************************
767 * Description:
768 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
769 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
770 ******************************************************************************/
771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
772 const u8 cos_entry,
773 const u32 min_w_val_nig,
774 const u32 min_w_val_pbf,
775 const u16 total_bw,
776 const u8 bw,
777 const u8 port)
778 {
779 u32 nig_reg_adress_crd_weight = 0;
780 u32 pbf_reg_adress_crd_weight = 0;
781 /* Calculate and set BW for this COS*/
782 const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
783 const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
784
785 switch (cos_entry) {
786 case 0:
787 nig_reg_adress_crd_weight =
788 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
789 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
790 pbf_reg_adress_crd_weight = (port) ?
791 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
792 break;
793 case 1:
794 nig_reg_adress_crd_weight = (port) ?
795 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
796 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
797 pbf_reg_adress_crd_weight = (port) ?
798 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
799 break;
800 case 2:
801 nig_reg_adress_crd_weight = (port) ?
802 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
803 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
804
805 pbf_reg_adress_crd_weight = (port) ?
806 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
807 break;
808 case 3:
809 if (port)
810 return -EINVAL;
811 nig_reg_adress_crd_weight =
812 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
813 pbf_reg_adress_crd_weight =
814 PBF_REG_COS3_WEIGHT_P0;
815 break;
816 case 4:
817 if (port)
818 return -EINVAL;
819 nig_reg_adress_crd_weight =
820 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
821 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
822 break;
823 case 5:
824 if (port)
825 return -EINVAL;
826 nig_reg_adress_crd_weight =
827 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
828 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
829 break;
830 }
831
832 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
833
834 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
835
836 return 0;
837 }
838 /******************************************************************************
839 * Description:
840 * Calculate the total BW.A value of 0 isn't legal.
841 *.
842 ******************************************************************************/
843 static int bnx2x_ets_e3b0_get_total_bw(
844 const struct link_params *params,
845 const struct bnx2x_ets_params *ets_params,
846 u16 *total_bw)
847 {
848 struct bnx2x *bp = params->bp;
849 u8 cos_idx = 0;
850
851 *total_bw = 0 ;
852 /* Calculate total BW requested */
853 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
854 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
855
856 if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
857 DP(NETIF_MSG_LINK,
858 "bnx2x_ets_E3B0_config BW was set to 0\n");
859 return -EINVAL;
860 }
861 *total_bw +=
862 ets_params->cos[cos_idx].params.bw_params.bw;
863 }
864 }
865
866 /*Check taotl BW is valid */
867 if ((100 != *total_bw) || (0 == *total_bw)) {
868 if (0 == *total_bw) {
869 DP(NETIF_MSG_LINK,
870 "bnx2x_ets_E3B0_config toatl BW shouldn't be 0\n");
871 return -EINVAL;
872 }
873 DP(NETIF_MSG_LINK,
874 "bnx2x_ets_E3B0_config toatl BW should be 100\n");
875 /**
876 * We can handle a case whre the BW isn't 100 this can happen
877 * if the TC are joined.
878 */
879 }
880 return 0;
881 }
882
883 /******************************************************************************
884 * Description:
885 * Invalidate all the sp_pri_to_cos.
886 *.
887 ******************************************************************************/
888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
889 {
890 u8 pri = 0;
891 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
892 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
893 }
894 /******************************************************************************
895 * Description:
896 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
897 * according to sp_pri_to_cos.
898 *.
899 ******************************************************************************/
900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
901 u8 *sp_pri_to_cos, const u8 pri,
902 const u8 cos_entry)
903 {
904 struct bnx2x *bp = params->bp;
905 const u8 port = params->port;
906 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
907 DCBX_E3B0_MAX_NUM_COS_PORT0;
908
909 if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
910 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
911 "parameter There can't be two COS's with "
912 "the same strict pri\n");
913 return -EINVAL;
914 }
915
916 if (pri > max_num_of_cos) {
917 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
918 "parameter Illegal strict priority\n");
919 return -EINVAL;
920 }
921
922 sp_pri_to_cos[pri] = cos_entry;
923 return 0;
924
925 }
926
927 /******************************************************************************
928 * Description:
929 * Returns the correct value according to COS and priority in
930 * the sp_pri_cli register.
931 *.
932 ******************************************************************************/
933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
934 const u8 pri_set,
935 const u8 pri_offset,
936 const u8 entry_size)
937 {
938 u64 pri_cli_nig = 0;
939 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
940 (pri_set + pri_offset));
941
942 return pri_cli_nig;
943 }
944 /******************************************************************************
945 * Description:
946 * Returns the correct value according to COS and priority in the
947 * sp_pri_cli register for NIG.
948 *.
949 ******************************************************************************/
950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
951 {
952 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
953 const u8 nig_cos_offset = 3;
954 const u8 nig_pri_offset = 3;
955
956 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
957 nig_pri_offset, 4);
958
959 }
960 /******************************************************************************
961 * Description:
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for PBF.
964 *.
965 ******************************************************************************/
966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
967 {
968 const u8 pbf_cos_offset = 0;
969 const u8 pbf_pri_offset = 0;
970
971 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
972 pbf_pri_offset, 3);
973
974 }
975
976 /******************************************************************************
977 * Description:
978 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
979 * according to sp_pri_to_cos.(which COS has higher priority)
980 *.
981 ******************************************************************************/
982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
983 u8 *sp_pri_to_cos)
984 {
985 struct bnx2x *bp = params->bp;
986 u8 i = 0;
987 const u8 port = params->port;
988 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
989 u64 pri_cli_nig = 0x210;
990 u32 pri_cli_pbf = 0x0;
991 u8 pri_set = 0;
992 u8 pri_bitmask = 0;
993 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
994 DCBX_E3B0_MAX_NUM_COS_PORT0;
995
996 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
997
998 /* Set all the strict priority first */
999 for (i = 0; i < max_num_of_cos; i++) {
1000 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001 if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1002 DP(NETIF_MSG_LINK,
1003 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004 "invalid cos entry\n");
1005 return -EINVAL;
1006 }
1007
1008 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009 sp_pri_to_cos[i], pri_set);
1010
1011 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012 sp_pri_to_cos[i], pri_set);
1013 pri_bitmask = 1 << sp_pri_to_cos[i];
1014 /* COS is used remove it from bitmap.*/
1015 if (0 == (pri_bitmask & cos_bit_to_set)) {
1016 DP(NETIF_MSG_LINK,
1017 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018 "invalid There can't be two COS's with"
1019 " the same strict pri\n");
1020 return -EINVAL;
1021 }
1022 cos_bit_to_set &= ~pri_bitmask;
1023 pri_set++;
1024 }
1025 }
1026
1027 /* Set all the Non strict priority i= COS*/
1028 for (i = 0; i < max_num_of_cos; i++) {
1029 pri_bitmask = 1 << i;
1030 /* Check if COS was already used for SP */
1031 if (pri_bitmask & cos_bit_to_set) {
1032 /* COS wasn't used for SP */
1033 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1034 i, pri_set);
1035
1036 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1037 i, pri_set);
1038 /* COS is used remove it from bitmap.*/
1039 cos_bit_to_set &= ~pri_bitmask;
1040 pri_set++;
1041 }
1042 }
1043
1044 if (pri_set != max_num_of_cos) {
1045 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046 "entries were set\n");
1047 return -EINVAL;
1048 }
1049
1050 if (port) {
1051 /* Only 6 usable clients*/
1052 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1053 (u32)pri_cli_nig);
1054
1055 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1056 } else {
1057 /* Only 9 usable clients*/
1058 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1060
1061 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1062 pri_cli_nig_lsb);
1063 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1064 pri_cli_nig_msb);
1065
1066 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1067 }
1068 return 0;
1069 }
1070
1071 /******************************************************************************
1072 * Description:
1073 * Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076 const struct link_vars *vars,
1077 const struct bnx2x_ets_params *ets_params)
1078 {
1079 struct bnx2x *bp = params->bp;
1080 int bnx2x_status = 0;
1081 const u8 port = params->port;
1082 u16 total_bw = 0;
1083 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085 u8 cos_bw_bitmap = 0;
1086 u8 cos_sp_bitmap = 0;
1087 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089 DCBX_E3B0_MAX_NUM_COS_PORT0;
1090 u8 cos_entry = 0;
1091
1092 if (!CHIP_IS_E3B0(bp)) {
1093 DP(NETIF_MSG_LINK,
1094 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1095 return -EINVAL;
1096 }
1097
1098 if ((ets_params->num_of_cos > max_num_of_cos)) {
1099 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100 "isn't supported\n");
1101 return -EINVAL;
1102 }
1103
1104 /* Prepare sp strict priority parameters*/
1105 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1106
1107 /* Prepare BW parameters*/
1108 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1109 &total_bw);
1110 if (0 != bnx2x_status) {
1111 DP(NETIF_MSG_LINK,
1112 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1113 return -EINVAL;
1114 }
1115
1116 /**
1117 * Upper bound is set according to current link speed (min_w_val
1118 * should be the same for upper bound and COS credit val).
1119 */
1120 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1122
1123
1124 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126 cos_bw_bitmap |= (1 << cos_entry);
1127 /**
1128 * The function also sets the BW in HW(not the mappin
1129 * yet)
1130 */
1131 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1133 total_bw,
1134 ets_params->cos[cos_entry].params.bw_params.bw,
1135 port);
1136 } else if (bnx2x_cos_state_strict ==
1137 ets_params->cos[cos_entry].state){
1138 cos_sp_bitmap |= (1 << cos_entry);
1139
1140 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1141 params,
1142 sp_pri_to_cos,
1143 ets_params->cos[cos_entry].params.sp_params.pri,
1144 cos_entry);
1145
1146 } else {
1147 DP(NETIF_MSG_LINK,
1148 "bnx2x_ets_e3b0_config cos state not valid\n");
1149 return -EINVAL;
1150 }
1151 if (0 != bnx2x_status) {
1152 DP(NETIF_MSG_LINK,
1153 "bnx2x_ets_e3b0_config set cos bw failed\n");
1154 return bnx2x_status;
1155 }
1156 }
1157
1158 /* Set SP register (which COS has higher priority) */
1159 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1160 sp_pri_to_cos);
1161
1162 if (0 != bnx2x_status) {
1163 DP(NETIF_MSG_LINK,
1164 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1165 return bnx2x_status;
1166 }
1167
1168 /* Set client mapping of BW and strict */
1169 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1170 cos_sp_bitmap,
1171 cos_bw_bitmap);
1172
1173 if (0 != bnx2x_status) {
1174 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175 return bnx2x_status;
1176 }
1177 return 0;
1178 }
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1180 {
1181 /* ETS disabled configuration */
1182 struct bnx2x *bp = params->bp;
1183 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1184 /*
1185 * defines which entries (clients) are subjected to WFQ arbitration
1186 * COS0 0x8
1187 * COS1 0x10
1188 */
1189 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1190 /*
1191 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192 * client numbers (WEIGHT_0 does not actually have to represent
1193 * client 0)
1194 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1195 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1196 */
1197 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1198
1199 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1203
1204 /* ETS mode enabled*/
1205 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1206
1207 /* Defines the number of consecutive slots for the strict priority */
1208 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1209 /*
1210 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1212 * entry, 4 - COS1 entry.
1213 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214 * bit4 bit3 bit2 bit1 bit0
1215 * MCP and debug are strict
1216 */
1217 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1218
1219 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1224 }
1225
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1227 const u32 cos1_bw)
1228 {
1229 /* ETS disabled configuration*/
1230 struct bnx2x *bp = params->bp;
1231 const u32 total_bw = cos0_bw + cos1_bw;
1232 u32 cos0_credit_weight = 0;
1233 u32 cos1_credit_weight = 0;
1234
1235 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1236
1237 if ((0 == total_bw) ||
1238 (0 == cos0_bw) ||
1239 (0 == cos1_bw)) {
1240 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1241 return;
1242 }
1243
1244 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1245 total_bw;
1246 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1247 total_bw;
1248
1249 bnx2x_ets_bw_limit_common(params);
1250
1251 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1253
1254 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1256 }
1257
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1259 {
1260 /* ETS disabled configuration*/
1261 struct bnx2x *bp = params->bp;
1262 u32 val = 0;
1263
1264 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1265 /*
1266 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267 * as strict. Bits 0,1,2 - debug and management entries,
1268 * 3 - COS0 entry, 4 - COS1 entry.
1269 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270 * bit4 bit3 bit2 bit1 bit0
1271 * MCP and debug are strict
1272 */
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1274 /*
1275 * For strict priority entries defines the number of consecutive slots
1276 * for the highest priority.
1277 */
1278 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279 /* ETS mode disable */
1280 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281 /* Defines the number of consecutive slots for the strict priority */
1282 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1283
1284 /* Defines the number of consecutive slots for the strict priority */
1285 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1286
1287 /*
1288 * mapping between entry priority to client number (0,1,2 -debug and
1289 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1290 * 3bits client num.
1291 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1292 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1293 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1294 */
1295 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1297
1298 return 0;
1299 }
1300 /******************************************************************/
1301 /* PFC section */
1302 /******************************************************************/
1303
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305 struct link_vars *vars,
1306 u8 is_lb)
1307 {
1308 struct bnx2x *bp = params->bp;
1309 u32 xmac_base;
1310 u32 pause_val, pfc0_val, pfc1_val;
1311
1312 /* XMAC base adrr */
1313 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1314
1315 /* Initialize pause and pfc registers */
1316 pause_val = 0x18000;
1317 pfc0_val = 0xFFFF8000;
1318 pfc1_val = 0x2;
1319
1320 /* No PFC support */
1321 if (!(params->feature_config_flags &
1322 FEATURE_CONFIG_PFC_ENABLED)) {
1323
1324 /*
1325 * RX flow control - Process pause frame in receive direction
1326 */
1327 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1329
1330 /*
1331 * TX flow control - Send pause packet when buffer is full
1332 */
1333 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335 } else {/* PFC support */
1336 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1340 }
1341
1342 /* Write pause and PFC registers */
1343 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1346
1347
1348 /* Set MAC address for source TX Pause/PFC frames */
1349 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1350 ((params->mac_addr[2] << 24) |
1351 (params->mac_addr[3] << 16) |
1352 (params->mac_addr[4] << 8) |
1353 (params->mac_addr[5])));
1354 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1355 ((params->mac_addr[0] << 8) |
1356 (params->mac_addr[1])));
1357
1358 udelay(30);
1359 }
1360
1361
1362 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1363 u32 pfc_frames_sent[2],
1364 u32 pfc_frames_received[2])
1365 {
1366 /* Read pfc statistic */
1367 struct bnx2x *bp = params->bp;
1368 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1369 u32 val_xon = 0;
1370 u32 val_xoff = 0;
1371
1372 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1373
1374 /* PFC received frames */
1375 val_xoff = REG_RD(bp, emac_base +
1376 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1377 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1378 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1379 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1380
1381 pfc_frames_received[0] = val_xon + val_xoff;
1382
1383 /* PFC received sent */
1384 val_xoff = REG_RD(bp, emac_base +
1385 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1386 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1387 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1388 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1389
1390 pfc_frames_sent[0] = val_xon + val_xoff;
1391 }
1392
1393 /* Read pfc statistic*/
1394 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1395 u32 pfc_frames_sent[2],
1396 u32 pfc_frames_received[2])
1397 {
1398 /* Read pfc statistic */
1399 struct bnx2x *bp = params->bp;
1400
1401 DP(NETIF_MSG_LINK, "pfc statistic\n");
1402
1403 if (!vars->link_up)
1404 return;
1405
1406 if (MAC_TYPE_EMAC == vars->mac_type) {
1407 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1408 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1409 pfc_frames_received);
1410 }
1411 }
1412 /******************************************************************/
1413 /* MAC/PBF section */
1414 /******************************************************************/
1415 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1416 {
1417 u32 mode, emac_base;
1418 /**
1419 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1420 * (a value of 49==0x31) and make sure that the AUTO poll is off
1421 */
1422
1423 if (CHIP_IS_E2(bp))
1424 emac_base = GRCBASE_EMAC0;
1425 else
1426 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1427 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1428 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1429 EMAC_MDIO_MODE_CLOCK_CNT);
1430 if (USES_WARPCORE(bp))
1431 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1432 else
1433 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1434
1435 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1437
1438 udelay(40);
1439 }
1440
1441 static void bnx2x_emac_init(struct link_params *params,
1442 struct link_vars *vars)
1443 {
1444 /* reset and unreset the emac core */
1445 struct bnx2x *bp = params->bp;
1446 u8 port = params->port;
1447 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1448 u32 val;
1449 u16 timeout;
1450
1451 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1452 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1453 udelay(5);
1454 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1455 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1456
1457 /* init emac - use read-modify-write */
1458 /* self clear reset */
1459 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1460 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1461
1462 timeout = 200;
1463 do {
1464 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1465 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1466 if (!timeout) {
1467 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1468 return;
1469 }
1470 timeout--;
1471 } while (val & EMAC_MODE_RESET);
1472 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1473 /* Set mac address */
1474 val = ((params->mac_addr[0] << 8) |
1475 params->mac_addr[1]);
1476 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1477
1478 val = ((params->mac_addr[2] << 24) |
1479 (params->mac_addr[3] << 16) |
1480 (params->mac_addr[4] << 8) |
1481 params->mac_addr[5]);
1482 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1483 }
1484
1485 static void bnx2x_set_xumac_nig(struct link_params *params,
1486 u16 tx_pause_en,
1487 u8 enable)
1488 {
1489 struct bnx2x *bp = params->bp;
1490
1491 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1492 enable);
1493 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1494 enable);
1495 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1496 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1497 }
1498
1499 static void bnx2x_umac_enable(struct link_params *params,
1500 struct link_vars *vars, u8 lb)
1501 {
1502 u32 val;
1503 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1504 struct bnx2x *bp = params->bp;
1505 /* Reset UMAC */
1506 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1507 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1508 usleep_range(1000, 1000);
1509
1510 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1511 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1512
1513 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1514
1515 /**
1516 * This register determines on which events the MAC will assert
1517 * error on the i/f to the NIG along w/ EOP.
1518 */
1519
1520 /**
1521 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1522 * params->port*0x14, 0xfffff.
1523 */
1524 /* This register opens the gate for the UMAC despite its name */
1525 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1526
1527 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1528 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1529 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1530 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1531 switch (vars->line_speed) {
1532 case SPEED_10:
1533 val |= (0<<2);
1534 break;
1535 case SPEED_100:
1536 val |= (1<<2);
1537 break;
1538 case SPEED_1000:
1539 val |= (2<<2);
1540 break;
1541 case SPEED_2500:
1542 val |= (3<<2);
1543 break;
1544 default:
1545 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1546 vars->line_speed);
1547 break;
1548 }
1549 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1550 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1551
1552 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1553 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1554
1555 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1556 udelay(50);
1557
1558 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1559 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1560 ((params->mac_addr[2] << 24) |
1561 (params->mac_addr[3] << 16) |
1562 (params->mac_addr[4] << 8) |
1563 (params->mac_addr[5])));
1564 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1565 ((params->mac_addr[0] << 8) |
1566 (params->mac_addr[1])));
1567
1568 /* Enable RX and TX */
1569 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1570 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1571 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1572 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1573 udelay(50);
1574
1575 /* Remove SW Reset */
1576 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1577
1578 /* Check loopback mode */
1579 if (lb)
1580 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1581 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1582
1583 /*
1584 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1585 * length used by the MAC receive logic to check frames.
1586 */
1587 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1588 bnx2x_set_xumac_nig(params,
1589 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1590 vars->mac_type = MAC_TYPE_UMAC;
1591
1592 }
1593
1594 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1595 {
1596 u32 port4mode_ovwr_val;
1597 /* Check 4-port override enabled */
1598 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1599 if (port4mode_ovwr_val & (1<<0)) {
1600 /* Return 4-port mode override value */
1601 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1602 }
1603 /* Return 4-port mode from input pin */
1604 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1605 }
1606
1607 /* Define the XMAC mode */
1608 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1609 {
1610 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1611
1612 /**
1613 * In 4-port mode, need to set the mode only once, so if XMAC is
1614 * already out of reset, it means the mode has already been set,
1615 * and it must not* reset the XMAC again, since it controls both
1616 * ports of the path
1617 **/
1618
1619 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1620 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1621 DP(NETIF_MSG_LINK,
1622 "XMAC already out of reset in 4-port mode\n");
1623 return;
1624 }
1625
1626 /* Hard reset */
1627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1628 MISC_REGISTERS_RESET_REG_2_XMAC);
1629 usleep_range(1000, 1000);
1630
1631 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1632 MISC_REGISTERS_RESET_REG_2_XMAC);
1633 if (is_port4mode) {
1634 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1635
1636 /* Set the number of ports on the system side to up to 2 */
1637 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1638
1639 /* Set the number of ports on the Warp Core to 10G */
1640 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1641 } else {
1642 /* Set the number of ports on the system side to 1 */
1643 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1644 if (max_speed == SPEED_10000) {
1645 DP(NETIF_MSG_LINK,
1646 "Init XMAC to 10G x 1 port per path\n");
1647 /* Set the number of ports on the Warp Core to 10G */
1648 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1649 } else {
1650 DP(NETIF_MSG_LINK,
1651 "Init XMAC to 20G x 2 ports per path\n");
1652 /* Set the number of ports on the Warp Core to 20G */
1653 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1654 }
1655 }
1656 /* Soft reset */
1657 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1658 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1659 usleep_range(1000, 1000);
1660
1661 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1662 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1663
1664 }
1665
1666 static void bnx2x_xmac_disable(struct link_params *params)
1667 {
1668 u8 port = params->port;
1669 struct bnx2x *bp = params->bp;
1670 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1671
1672 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1673 MISC_REGISTERS_RESET_REG_2_XMAC) {
1674 /*
1675 * Send an indication to change the state in the NIG back to XON
1676 * Clearing this bit enables the next set of this bit to get
1677 * rising edge
1678 */
1679 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1680 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1681 (pfc_ctrl & ~(1<<1)));
1682 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1683 (pfc_ctrl | (1<<1)));
1684 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1685 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1686 usleep_range(1000, 1000);
1687 bnx2x_set_xumac_nig(params, 0, 0);
1688 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1689 XMAC_CTRL_REG_SOFT_RESET);
1690 }
1691 }
1692
1693 static int bnx2x_xmac_enable(struct link_params *params,
1694 struct link_vars *vars, u8 lb)
1695 {
1696 u32 val, xmac_base;
1697 struct bnx2x *bp = params->bp;
1698 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1699
1700 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1701
1702 bnx2x_xmac_init(bp, vars->line_speed);
1703
1704 /*
1705 * This register determines on which events the MAC will assert
1706 * error on the i/f to the NIG along w/ EOP.
1707 */
1708
1709 /*
1710 * This register tells the NIG whether to send traffic to UMAC
1711 * or XMAC
1712 */
1713 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1714
1715 /* Set Max packet size */
1716 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1717
1718 /* CRC append for Tx packets */
1719 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1720
1721 /* update PFC */
1722 bnx2x_update_pfc_xmac(params, vars, 0);
1723
1724 /* Enable TX and RX */
1725 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1726
1727 /* Check loopback mode */
1728 if (lb)
1729 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1730 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1731 bnx2x_set_xumac_nig(params,
1732 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1733
1734 vars->mac_type = MAC_TYPE_XMAC;
1735
1736 return 0;
1737 }
1738 static int bnx2x_emac_enable(struct link_params *params,
1739 struct link_vars *vars, u8 lb)
1740 {
1741 struct bnx2x *bp = params->bp;
1742 u8 port = params->port;
1743 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1744 u32 val;
1745
1746 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1747
1748 /* Disable BMAC */
1749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1750 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1751
1752 /* enable emac and not bmac */
1753 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1754
1755 /* ASIC */
1756 if (vars->phy_flags & PHY_XGXS_FLAG) {
1757 u32 ser_lane = ((params->lane_config &
1758 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1759 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1760
1761 DP(NETIF_MSG_LINK, "XGXS\n");
1762 /* select the master lanes (out of 0-3) */
1763 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1764 /* select XGXS */
1765 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1766
1767 } else { /* SerDes */
1768 DP(NETIF_MSG_LINK, "SerDes\n");
1769 /* select SerDes */
1770 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1771 }
1772
1773 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1774 EMAC_RX_MODE_RESET);
1775 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1776 EMAC_TX_MODE_RESET);
1777
1778 if (CHIP_REV_IS_SLOW(bp)) {
1779 /* config GMII mode */
1780 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1781 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1782 } else { /* ASIC */
1783 /* pause enable/disable */
1784 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1785 EMAC_RX_MODE_FLOW_EN);
1786
1787 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1788 (EMAC_TX_MODE_EXT_PAUSE_EN |
1789 EMAC_TX_MODE_FLOW_EN));
1790 if (!(params->feature_config_flags &
1791 FEATURE_CONFIG_PFC_ENABLED)) {
1792 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1793 bnx2x_bits_en(bp, emac_base +
1794 EMAC_REG_EMAC_RX_MODE,
1795 EMAC_RX_MODE_FLOW_EN);
1796
1797 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1798 bnx2x_bits_en(bp, emac_base +
1799 EMAC_REG_EMAC_TX_MODE,
1800 (EMAC_TX_MODE_EXT_PAUSE_EN |
1801 EMAC_TX_MODE_FLOW_EN));
1802 } else
1803 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1804 EMAC_TX_MODE_FLOW_EN);
1805 }
1806
1807 /* KEEP_VLAN_TAG, promiscuous */
1808 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1809 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1810
1811 /*
1812 * Setting this bit causes MAC control frames (except for pause
1813 * frames) to be passed on for processing. This setting has no
1814 * affect on the operation of the pause frames. This bit effects
1815 * all packets regardless of RX Parser packet sorting logic.
1816 * Turn the PFC off to make sure we are in Xon state before
1817 * enabling it.
1818 */
1819 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1820 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1821 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1822 /* Enable PFC again */
1823 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1824 EMAC_REG_RX_PFC_MODE_RX_EN |
1825 EMAC_REG_RX_PFC_MODE_TX_EN |
1826 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1827
1828 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1829 ((0x0101 <<
1830 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1831 (0x00ff <<
1832 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1833 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1834 }
1835 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1836
1837 /* Set Loopback */
1838 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1839 if (lb)
1840 val |= 0x810;
1841 else
1842 val &= ~0x810;
1843 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1844
1845 /* enable emac */
1846 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1847
1848 /* enable emac for jumbo packets */
1849 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1850 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1851 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1852
1853 /* strip CRC */
1854 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1855
1856 /* disable the NIG in/out to the bmac */
1857 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1858 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1859 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1860
1861 /* enable the NIG in/out to the emac */
1862 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1863 val = 0;
1864 if ((params->feature_config_flags &
1865 FEATURE_CONFIG_PFC_ENABLED) ||
1866 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1867 val = 1;
1868
1869 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1870 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1871
1872 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1873
1874 vars->mac_type = MAC_TYPE_EMAC;
1875 return 0;
1876 }
1877
1878 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1879 struct link_vars *vars)
1880 {
1881 u32 wb_data[2];
1882 struct bnx2x *bp = params->bp;
1883 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1884 NIG_REG_INGRESS_BMAC0_MEM;
1885
1886 u32 val = 0x14;
1887 if ((!(params->feature_config_flags &
1888 FEATURE_CONFIG_PFC_ENABLED)) &&
1889 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1890 /* Enable BigMAC to react on received Pause packets */
1891 val |= (1<<5);
1892 wb_data[0] = val;
1893 wb_data[1] = 0;
1894 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1895
1896 /* tx control */
1897 val = 0xc0;
1898 if (!(params->feature_config_flags &
1899 FEATURE_CONFIG_PFC_ENABLED) &&
1900 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1901 val |= 0x800000;
1902 wb_data[0] = val;
1903 wb_data[1] = 0;
1904 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1905 }
1906
1907 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1908 struct link_vars *vars,
1909 u8 is_lb)
1910 {
1911 /*
1912 * Set rx control: Strip CRC and enable BigMAC to relay
1913 * control packets to the system as well
1914 */
1915 u32 wb_data[2];
1916 struct bnx2x *bp = params->bp;
1917 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1918 NIG_REG_INGRESS_BMAC0_MEM;
1919 u32 val = 0x14;
1920
1921 if ((!(params->feature_config_flags &
1922 FEATURE_CONFIG_PFC_ENABLED)) &&
1923 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1924 /* Enable BigMAC to react on received Pause packets */
1925 val |= (1<<5);
1926 wb_data[0] = val;
1927 wb_data[1] = 0;
1928 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1929 udelay(30);
1930
1931 /* Tx control */
1932 val = 0xc0;
1933 if (!(params->feature_config_flags &
1934 FEATURE_CONFIG_PFC_ENABLED) &&
1935 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1936 val |= 0x800000;
1937 wb_data[0] = val;
1938 wb_data[1] = 0;
1939 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1940
1941 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1942 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1943 /* Enable PFC RX & TX & STATS and set 8 COS */
1944 wb_data[0] = 0x0;
1945 wb_data[0] |= (1<<0); /* RX */
1946 wb_data[0] |= (1<<1); /* TX */
1947 wb_data[0] |= (1<<2); /* Force initial Xon */
1948 wb_data[0] |= (1<<3); /* 8 cos */
1949 wb_data[0] |= (1<<5); /* STATS */
1950 wb_data[1] = 0;
1951 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1952 wb_data, 2);
1953 /* Clear the force Xon */
1954 wb_data[0] &= ~(1<<2);
1955 } else {
1956 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1957 /* disable PFC RX & TX & STATS and set 8 COS */
1958 wb_data[0] = 0x8;
1959 wb_data[1] = 0;
1960 }
1961
1962 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1963
1964 /*
1965 * Set Time (based unit is 512 bit time) between automatic
1966 * re-sending of PP packets amd enable automatic re-send of
1967 * Per-Priroity Packet as long as pp_gen is asserted and
1968 * pp_disable is low.
1969 */
1970 val = 0x8000;
1971 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1972 val |= (1<<16); /* enable automatic re-send */
1973
1974 wb_data[0] = val;
1975 wb_data[1] = 0;
1976 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1977 wb_data, 2);
1978
1979 /* mac control */
1980 val = 0x3; /* Enable RX and TX */
1981 if (is_lb) {
1982 val |= 0x4; /* Local loopback */
1983 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1984 }
1985 /* When PFC enabled, Pass pause frames towards the NIG. */
1986 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1987 val |= ((1<<6)|(1<<5));
1988
1989 wb_data[0] = val;
1990 wb_data[1] = 0;
1991 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1992 }
1993
1994
1995 /* PFC BRB internal port configuration params */
1996 struct bnx2x_pfc_brb_threshold_val {
1997 u32 pause_xoff;
1998 u32 pause_xon;
1999 u32 full_xoff;
2000 u32 full_xon;
2001 };
2002
2003 struct bnx2x_pfc_brb_e3b0_val {
2004 u32 full_lb_xoff_th;
2005 u32 full_lb_xon_threshold;
2006 u32 lb_guarantied;
2007 u32 mac_0_class_t_guarantied;
2008 u32 mac_0_class_t_guarantied_hyst;
2009 u32 mac_1_class_t_guarantied;
2010 u32 mac_1_class_t_guarantied_hyst;
2011 };
2012
2013 struct bnx2x_pfc_brb_th_val {
2014 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2015 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2016 };
2017 static int bnx2x_pfc_brb_get_config_params(
2018 struct link_params *params,
2019 struct bnx2x_pfc_brb_th_val *config_val)
2020 {
2021 struct bnx2x *bp = params->bp;
2022 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2023 if (CHIP_IS_E2(bp)) {
2024 config_val->pauseable_th.pause_xoff =
2025 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2026 config_val->pauseable_th.pause_xon =
2027 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2028 config_val->pauseable_th.full_xoff =
2029 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2030 config_val->pauseable_th.full_xon =
2031 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2032 /* non pause able*/
2033 config_val->non_pauseable_th.pause_xoff =
2034 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2035 config_val->non_pauseable_th.pause_xon =
2036 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2037 config_val->non_pauseable_th.full_xoff =
2038 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2039 config_val->non_pauseable_th.full_xon =
2040 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2041 } else if (CHIP_IS_E3A0(bp)) {
2042 config_val->pauseable_th.pause_xoff =
2043 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2044 config_val->pauseable_th.pause_xon =
2045 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2046 config_val->pauseable_th.full_xoff =
2047 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2048 config_val->pauseable_th.full_xon =
2049 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2050 /* non pause able*/
2051 config_val->non_pauseable_th.pause_xoff =
2052 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2053 config_val->non_pauseable_th.pause_xon =
2054 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2055 config_val->non_pauseable_th.full_xoff =
2056 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2057 config_val->non_pauseable_th.full_xon =
2058 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2059 } else if (CHIP_IS_E3B0(bp)) {
2060 if (params->phy[INT_PHY].flags &
2061 FLAGS_4_PORT_MODE) {
2062 config_val->pauseable_th.pause_xoff =
2063 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2064 config_val->pauseable_th.pause_xon =
2065 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2066 config_val->pauseable_th.full_xoff =
2067 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2068 config_val->pauseable_th.full_xon =
2069 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2070 /* non pause able*/
2071 config_val->non_pauseable_th.pause_xoff =
2072 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2073 config_val->non_pauseable_th.pause_xon =
2074 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2075 config_val->non_pauseable_th.full_xoff =
2076 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2077 config_val->non_pauseable_th.full_xon =
2078 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2079 } else {
2080 config_val->pauseable_th.pause_xoff =
2081 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2082 config_val->pauseable_th.pause_xon =
2083 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2084 config_val->pauseable_th.full_xoff =
2085 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2086 config_val->pauseable_th.full_xon =
2087 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2088 /* non pause able*/
2089 config_val->non_pauseable_th.pause_xoff =
2090 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2091 config_val->non_pauseable_th.pause_xon =
2092 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2093 config_val->non_pauseable_th.full_xoff =
2094 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2095 config_val->non_pauseable_th.full_xon =
2096 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2097 }
2098 } else
2099 return -EINVAL;
2100
2101 return 0;
2102 }
2103
2104
2105 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2106 struct bnx2x_pfc_brb_e3b0_val
2107 *e3b0_val,
2108 u32 cos0_pauseable,
2109 u32 cos1_pauseable)
2110 {
2111 if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2112 e3b0_val->full_lb_xoff_th =
2113 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2114 e3b0_val->full_lb_xon_threshold =
2115 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2116 e3b0_val->lb_guarantied =
2117 PFC_E3B0_4P_LB_GUART;
2118 e3b0_val->mac_0_class_t_guarantied =
2119 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2120 e3b0_val->mac_0_class_t_guarantied_hyst =
2121 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2122 e3b0_val->mac_1_class_t_guarantied =
2123 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2124 e3b0_val->mac_1_class_t_guarantied_hyst =
2125 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2126 } else {
2127 e3b0_val->full_lb_xoff_th =
2128 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2129 e3b0_val->full_lb_xon_threshold =
2130 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2131 e3b0_val->mac_0_class_t_guarantied_hyst =
2132 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2133 e3b0_val->mac_1_class_t_guarantied =
2134 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2135 e3b0_val->mac_1_class_t_guarantied_hyst =
2136 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2137
2138 if (cos0_pauseable != cos1_pauseable) {
2139 /* nonpauseable= Lossy + pauseable = Lossless*/
2140 e3b0_val->lb_guarantied =
2141 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2142 e3b0_val->mac_0_class_t_guarantied =
2143 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2144 } else if (cos0_pauseable) {
2145 /* Lossless +Lossless*/
2146 e3b0_val->lb_guarantied =
2147 PFC_E3B0_2P_PAUSE_LB_GUART;
2148 e3b0_val->mac_0_class_t_guarantied =
2149 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2150 } else {
2151 /* Lossy +Lossy*/
2152 e3b0_val->lb_guarantied =
2153 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2154 e3b0_val->mac_0_class_t_guarantied =
2155 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2156 }
2157 }
2158 }
2159 static int bnx2x_update_pfc_brb(struct link_params *params,
2160 struct link_vars *vars,
2161 struct bnx2x_nig_brb_pfc_port_params
2162 *pfc_params)
2163 {
2164 struct bnx2x *bp = params->bp;
2165 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2166 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2167 &config_val.pauseable_th;
2168 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2169 int set_pfc = params->feature_config_flags &
2170 FEATURE_CONFIG_PFC_ENABLED;
2171 int bnx2x_status = 0;
2172 u8 port = params->port;
2173
2174 /* default - pause configuration */
2175 reg_th_config = &config_val.pauseable_th;
2176 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2177 if (0 != bnx2x_status)
2178 return bnx2x_status;
2179
2180 if (set_pfc && pfc_params)
2181 /* First COS */
2182 if (!pfc_params->cos0_pauseable)
2183 reg_th_config = &config_val.non_pauseable_th;
2184 /*
2185 * The number of free blocks below which the pause signal to class 0
2186 * of MAC #n is asserted. n=0,1
2187 */
2188 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2189 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2190 reg_th_config->pause_xoff);
2191 /*
2192 * The number of free blocks above which the pause signal to class 0
2193 * of MAC #n is de-asserted. n=0,1
2194 */
2195 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2196 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2197 /*
2198 * The number of free blocks below which the full signal to class 0
2199 * of MAC #n is asserted. n=0,1
2200 */
2201 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2202 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2203 /*
2204 * The number of free blocks above which the full signal to class 0
2205 * of MAC #n is de-asserted. n=0,1
2206 */
2207 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2208 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2209
2210 if (set_pfc && pfc_params) {
2211 /* Second COS */
2212 if (pfc_params->cos1_pauseable)
2213 reg_th_config = &config_val.pauseable_th;
2214 else
2215 reg_th_config = &config_val.non_pauseable_th;
2216 /*
2217 * The number of free blocks below which the pause signal to
2218 * class 1 of MAC #n is asserted. n=0,1
2219 **/
2220 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2221 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2222 reg_th_config->pause_xoff);
2223 /*
2224 * The number of free blocks above which the pause signal to
2225 * class 1 of MAC #n is de-asserted. n=0,1
2226 */
2227 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2228 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2229 reg_th_config->pause_xon);
2230 /*
2231 * The number of free blocks below which the full signal to
2232 * class 1 of MAC #n is asserted. n=0,1
2233 */
2234 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2235 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2236 reg_th_config->full_xoff);
2237 /*
2238 * The number of free blocks above which the full signal to
2239 * class 1 of MAC #n is de-asserted. n=0,1
2240 */
2241 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2242 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2243 reg_th_config->full_xon);
2244
2245
2246 if (CHIP_IS_E3B0(bp)) {
2247 /*Should be done by init tool */
2248 /*
2249 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2250 * reset value
2251 * 944
2252 */
2253
2254 /**
2255 * The hysteresis on the guarantied buffer space for the Lb port
2256 * before signaling XON.
2257 **/
2258 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2259
2260 bnx2x_pfc_brb_get_e3b0_config_params(
2261 params,
2262 &e3b0_val,
2263 pfc_params->cos0_pauseable,
2264 pfc_params->cos1_pauseable);
2265 /**
2266 * The number of free blocks below which the full signal to the
2267 * LB port is asserted.
2268 */
2269 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2270 e3b0_val.full_lb_xoff_th);
2271 /**
2272 * The number of free blocks above which the full signal to the
2273 * LB port is de-asserted.
2274 */
2275 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2276 e3b0_val.full_lb_xon_threshold);
2277 /**
2278 * The number of blocks guarantied for the MAC #n port. n=0,1
2279 */
2280
2281 /*The number of blocks guarantied for the LB port.*/
2282 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2283 e3b0_val.lb_guarantied);
2284
2285 /**
2286 * The number of blocks guarantied for the MAC #n port.
2287 */
2288 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2289 2 * e3b0_val.mac_0_class_t_guarantied);
2290 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2291 2 * e3b0_val.mac_1_class_t_guarantied);
2292 /**
2293 * The number of blocks guarantied for class #t in MAC0. t=0,1
2294 */
2295 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2296 e3b0_val.mac_0_class_t_guarantied);
2297 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2298 e3b0_val.mac_0_class_t_guarantied);
2299 /**
2300 * The hysteresis on the guarantied buffer space for class in
2301 * MAC0. t=0,1
2302 */
2303 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2304 e3b0_val.mac_0_class_t_guarantied_hyst);
2305 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2306 e3b0_val.mac_0_class_t_guarantied_hyst);
2307
2308 /**
2309 * The number of blocks guarantied for class #t in MAC1.t=0,1
2310 */
2311 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2312 e3b0_val.mac_1_class_t_guarantied);
2313 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2314 e3b0_val.mac_1_class_t_guarantied);
2315 /**
2316 * The hysteresis on the guarantied buffer space for class #t
2317 * in MAC1. t=0,1
2318 */
2319 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2320 e3b0_val.mac_1_class_t_guarantied_hyst);
2321 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2322 e3b0_val.mac_1_class_t_guarantied_hyst);
2323
2324 }
2325
2326 }
2327
2328 return bnx2x_status;
2329 }
2330
2331 /******************************************************************************
2332 * Description:
2333 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2334 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2335 ******************************************************************************/
2336 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2337 u8 cos_entry,
2338 u32 priority_mask, u8 port)
2339 {
2340 u32 nig_reg_rx_priority_mask_add = 0;
2341
2342 switch (cos_entry) {
2343 case 0:
2344 nig_reg_rx_priority_mask_add = (port) ?
2345 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2346 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2347 break;
2348 case 1:
2349 nig_reg_rx_priority_mask_add = (port) ?
2350 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2351 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2352 break;
2353 case 2:
2354 nig_reg_rx_priority_mask_add = (port) ?
2355 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2356 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2357 break;
2358 case 3:
2359 if (port)
2360 return -EINVAL;
2361 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2362 break;
2363 case 4:
2364 if (port)
2365 return -EINVAL;
2366 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2367 break;
2368 case 5:
2369 if (port)
2370 return -EINVAL;
2371 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2372 break;
2373 }
2374
2375 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2376
2377 return 0;
2378 }
2379 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2380 {
2381 struct bnx2x *bp = params->bp;
2382
2383 REG_WR(bp, params->shmem_base +
2384 offsetof(struct shmem_region,
2385 port_mb[params->port].link_status), link_status);
2386 }
2387
2388 static void bnx2x_update_pfc_nig(struct link_params *params,
2389 struct link_vars *vars,
2390 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2391 {
2392 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2393 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2394 u32 pkt_priority_to_cos = 0;
2395 struct bnx2x *bp = params->bp;
2396 u8 port = params->port;
2397
2398 int set_pfc = params->feature_config_flags &
2399 FEATURE_CONFIG_PFC_ENABLED;
2400 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2401
2402 /*
2403 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2404 * MAC control frames (that are not pause packets)
2405 * will be forwarded to the XCM.
2406 */
2407 xcm_mask = REG_RD(bp,
2408 port ? NIG_REG_LLH1_XCM_MASK :
2409 NIG_REG_LLH0_XCM_MASK);
2410 /*
2411 * nig params will override non PFC params, since it's possible to
2412 * do transition from PFC to SAFC
2413 */
2414 if (set_pfc) {
2415 pause_enable = 0;
2416 llfc_out_en = 0;
2417 llfc_enable = 0;
2418 if (CHIP_IS_E3(bp))
2419 ppp_enable = 0;
2420 else
2421 ppp_enable = 1;
2422 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2423 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2424 xcm0_out_en = 0;
2425 p0_hwpfc_enable = 1;
2426 } else {
2427 if (nig_params) {
2428 llfc_out_en = nig_params->llfc_out_en;
2429 llfc_enable = nig_params->llfc_enable;
2430 pause_enable = nig_params->pause_enable;
2431 } else /*defaul non PFC mode - PAUSE */
2432 pause_enable = 1;
2433
2434 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2435 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2436 xcm0_out_en = 1;
2437 }
2438
2439 if (CHIP_IS_E3(bp))
2440 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2441 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2442 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2443 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2444 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2445 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2446 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2447 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2448
2449 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2450 NIG_REG_PPP_ENABLE_0, ppp_enable);
2451
2452 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2453 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2454
2455 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2456
2457 /* output enable for RX_XCM # IF */
2458 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2459
2460 /* HW PFC TX enable */
2461 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2462
2463 if (nig_params) {
2464 u8 i = 0;
2465 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2466
2467 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2468 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2469 nig_params->rx_cos_priority_mask[i], port);
2470
2471 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2472 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2473 nig_params->llfc_high_priority_classes);
2474
2475 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2476 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2477 nig_params->llfc_low_priority_classes);
2478 }
2479 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2480 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2481 pkt_priority_to_cos);
2482 }
2483
2484 int bnx2x_update_pfc(struct link_params *params,
2485 struct link_vars *vars,
2486 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2487 {
2488 /*
2489 * The PFC and pause are orthogonal to one another, meaning when
2490 * PFC is enabled, the pause are disabled, and when PFC is
2491 * disabled, pause are set according to the pause result.
2492 */
2493 u32 val;
2494 struct bnx2x *bp = params->bp;
2495 int bnx2x_status = 0;
2496 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2497
2498 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2499 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2500 else
2501 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2502
2503 bnx2x_update_mng(params, vars->link_status);
2504
2505 /* update NIG params */
2506 bnx2x_update_pfc_nig(params, vars, pfc_params);
2507
2508 /* update BRB params */
2509 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2510 if (0 != bnx2x_status)
2511 return bnx2x_status;
2512
2513 if (!vars->link_up)
2514 return bnx2x_status;
2515
2516 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2517 if (CHIP_IS_E3(bp))
2518 bnx2x_update_pfc_xmac(params, vars, 0);
2519 else {
2520 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2521 if ((val &
2522 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2523 == 0) {
2524 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2525 bnx2x_emac_enable(params, vars, 0);
2526 return bnx2x_status;
2527 }
2528
2529 if (CHIP_IS_E2(bp))
2530 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2531 else
2532 bnx2x_update_pfc_bmac1(params, vars);
2533
2534 val = 0;
2535 if ((params->feature_config_flags &
2536 FEATURE_CONFIG_PFC_ENABLED) ||
2537 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2538 val = 1;
2539 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2540 }
2541 return bnx2x_status;
2542 }
2543
2544
2545 static int bnx2x_bmac1_enable(struct link_params *params,
2546 struct link_vars *vars,
2547 u8 is_lb)
2548 {
2549 struct bnx2x *bp = params->bp;
2550 u8 port = params->port;
2551 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2552 NIG_REG_INGRESS_BMAC0_MEM;
2553 u32 wb_data[2];
2554 u32 val;
2555
2556 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2557
2558 /* XGXS control */
2559 wb_data[0] = 0x3c;
2560 wb_data[1] = 0;
2561 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2562 wb_data, 2);
2563
2564 /* tx MAC SA */
2565 wb_data[0] = ((params->mac_addr[2] << 24) |
2566 (params->mac_addr[3] << 16) |
2567 (params->mac_addr[4] << 8) |
2568 params->mac_addr[5]);
2569 wb_data[1] = ((params->mac_addr[0] << 8) |
2570 params->mac_addr[1]);
2571 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2572
2573 /* mac control */
2574 val = 0x3;
2575 if (is_lb) {
2576 val |= 0x4;
2577 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2578 }
2579 wb_data[0] = val;
2580 wb_data[1] = 0;
2581 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2582
2583 /* set rx mtu */
2584 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2585 wb_data[1] = 0;
2586 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2587
2588 bnx2x_update_pfc_bmac1(params, vars);
2589
2590 /* set tx mtu */
2591 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2592 wb_data[1] = 0;
2593 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2594
2595 /* set cnt max size */
2596 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2597 wb_data[1] = 0;
2598 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2599
2600 /* configure safc */
2601 wb_data[0] = 0x1000200;
2602 wb_data[1] = 0;
2603 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2604 wb_data, 2);
2605
2606 return 0;
2607 }
2608
2609 static int bnx2x_bmac2_enable(struct link_params *params,
2610 struct link_vars *vars,
2611 u8 is_lb)
2612 {
2613 struct bnx2x *bp = params->bp;
2614 u8 port = params->port;
2615 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2616 NIG_REG_INGRESS_BMAC0_MEM;
2617 u32 wb_data[2];
2618
2619 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2620
2621 wb_data[0] = 0;
2622 wb_data[1] = 0;
2623 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2624 udelay(30);
2625
2626 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2627 wb_data[0] = 0x3c;
2628 wb_data[1] = 0;
2629 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2630 wb_data, 2);
2631
2632 udelay(30);
2633
2634 /* tx MAC SA */
2635 wb_data[0] = ((params->mac_addr[2] << 24) |
2636 (params->mac_addr[3] << 16) |
2637 (params->mac_addr[4] << 8) |
2638 params->mac_addr[5]);
2639 wb_data[1] = ((params->mac_addr[0] << 8) |
2640 params->mac_addr[1]);
2641 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2642 wb_data, 2);
2643
2644 udelay(30);
2645
2646 /* Configure SAFC */
2647 wb_data[0] = 0x1000200;
2648 wb_data[1] = 0;
2649 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2650 wb_data, 2);
2651 udelay(30);
2652
2653 /* set rx mtu */
2654 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2655 wb_data[1] = 0;
2656 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2657 udelay(30);
2658
2659 /* set tx mtu */
2660 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2661 wb_data[1] = 0;
2662 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2663 udelay(30);
2664 /* set cnt max size */
2665 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2666 wb_data[1] = 0;
2667 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2668 udelay(30);
2669 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2670
2671 return 0;
2672 }
2673
2674 static int bnx2x_bmac_enable(struct link_params *params,
2675 struct link_vars *vars,
2676 u8 is_lb)
2677 {
2678 int rc = 0;
2679 u8 port = params->port;
2680 struct bnx2x *bp = params->bp;
2681 u32 val;
2682 /* reset and unreset the BigMac */
2683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2684 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685 msleep(1);
2686
2687 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2688 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2689
2690 /* enable access for bmac registers */
2691 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2692
2693 /* Enable BMAC according to BMAC type*/
2694 if (CHIP_IS_E2(bp))
2695 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2696 else
2697 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2698 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2699 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2700 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2701 val = 0;
2702 if ((params->feature_config_flags &
2703 FEATURE_CONFIG_PFC_ENABLED) ||
2704 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2705 val = 1;
2706 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2707 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2708 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2709 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2710 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2711 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2712
2713 vars->mac_type = MAC_TYPE_BMAC;
2714 return rc;
2715 }
2716
2717 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2718 {
2719 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2720 NIG_REG_INGRESS_BMAC0_MEM;
2721 u32 wb_data[2];
2722 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2723
2724 /* Only if the bmac is out of reset */
2725 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2726 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2727 nig_bmac_enable) {
2728
2729 if (CHIP_IS_E2(bp)) {
2730 /* Clear Rx Enable bit in BMAC_CONTROL register */
2731 REG_RD_DMAE(bp, bmac_addr +
2732 BIGMAC2_REGISTER_BMAC_CONTROL,
2733 wb_data, 2);
2734 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2735 REG_WR_DMAE(bp, bmac_addr +
2736 BIGMAC2_REGISTER_BMAC_CONTROL,
2737 wb_data, 2);
2738 } else {
2739 /* Clear Rx Enable bit in BMAC_CONTROL register */
2740 REG_RD_DMAE(bp, bmac_addr +
2741 BIGMAC_REGISTER_BMAC_CONTROL,
2742 wb_data, 2);
2743 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2744 REG_WR_DMAE(bp, bmac_addr +
2745 BIGMAC_REGISTER_BMAC_CONTROL,
2746 wb_data, 2);
2747 }
2748 msleep(1);
2749 }
2750 }
2751
2752 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2753 u32 line_speed)
2754 {
2755 struct bnx2x *bp = params->bp;
2756 u8 port = params->port;
2757 u32 init_crd, crd;
2758 u32 count = 1000;
2759
2760 /* disable port */
2761 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2762
2763 /* wait for init credit */
2764 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2765 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2766 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2767
2768 while ((init_crd != crd) && count) {
2769 msleep(5);
2770
2771 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2772 count--;
2773 }
2774 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2775 if (init_crd != crd) {
2776 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2777 init_crd, crd);
2778 return -EINVAL;
2779 }
2780
2781 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2782 line_speed == SPEED_10 ||
2783 line_speed == SPEED_100 ||
2784 line_speed == SPEED_1000 ||
2785 line_speed == SPEED_2500) {
2786 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2787 /* update threshold */
2788 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2789 /* update init credit */
2790 init_crd = 778; /* (800-18-4) */
2791
2792 } else {
2793 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2794 ETH_OVREHEAD)/16;
2795 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2796 /* update threshold */
2797 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2798 /* update init credit */
2799 switch (line_speed) {
2800 case SPEED_10000:
2801 init_crd = thresh + 553 - 22;
2802 break;
2803 default:
2804 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2805 line_speed);
2806 return -EINVAL;
2807 }
2808 }
2809 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2810 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2811 line_speed, init_crd);
2812
2813 /* probe the credit changes */
2814 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2815 msleep(5);
2816 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2817
2818 /* enable port */
2819 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2820 return 0;
2821 }
2822
2823 /**
2824 * bnx2x_get_emac_base - retrive emac base address
2825 *
2826 * @bp: driver handle
2827 * @mdc_mdio_access: access type
2828 * @port: port id
2829 *
2830 * This function selects the MDC/MDIO access (through emac0 or
2831 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2832 * phy has a default access mode, which could also be overridden
2833 * by nvram configuration. This parameter, whether this is the
2834 * default phy configuration, or the nvram overrun
2835 * configuration, is passed here as mdc_mdio_access and selects
2836 * the emac_base for the CL45 read/writes operations
2837 */
2838 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2839 u32 mdc_mdio_access, u8 port)
2840 {
2841 u32 emac_base = 0;
2842 switch (mdc_mdio_access) {
2843 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2844 break;
2845 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2846 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2847 emac_base = GRCBASE_EMAC1;
2848 else
2849 emac_base = GRCBASE_EMAC0;
2850 break;
2851 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2852 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2853 emac_base = GRCBASE_EMAC0;
2854 else
2855 emac_base = GRCBASE_EMAC1;
2856 break;
2857 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2858 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2859 break;
2860 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2861 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2862 break;
2863 default:
2864 break;
2865 }
2866 return emac_base;
2867
2868 }
2869
2870 /******************************************************************/
2871 /* CL22 access functions */
2872 /******************************************************************/
2873 static int bnx2x_cl22_write(struct bnx2x *bp,
2874 struct bnx2x_phy *phy,
2875 u16 reg, u16 val)
2876 {
2877 u32 tmp, mode;
2878 u8 i;
2879 int rc = 0;
2880 /* Switch to CL22 */
2881 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2882 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2883 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2884
2885 /* address */
2886 tmp = ((phy->addr << 21) | (reg << 16) | val |
2887 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2888 EMAC_MDIO_COMM_START_BUSY);
2889 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2890
2891 for (i = 0; i < 50; i++) {
2892 udelay(10);
2893
2894 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2895 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2896 udelay(5);
2897 break;
2898 }
2899 }
2900 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2901 DP(NETIF_MSG_LINK, "write phy register failed\n");
2902 rc = -EFAULT;
2903 }
2904 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2905 return rc;
2906 }
2907
2908 static int bnx2x_cl22_read(struct bnx2x *bp,
2909 struct bnx2x_phy *phy,
2910 u16 reg, u16 *ret_val)
2911 {
2912 u32 val, mode;
2913 u16 i;
2914 int rc = 0;
2915
2916 /* Switch to CL22 */
2917 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2918 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2919 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2920
2921 /* address */
2922 val = ((phy->addr << 21) | (reg << 16) |
2923 EMAC_MDIO_COMM_COMMAND_READ_22 |
2924 EMAC_MDIO_COMM_START_BUSY);
2925 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2926
2927 for (i = 0; i < 50; i++) {
2928 udelay(10);
2929
2930 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2931 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2932 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2933 udelay(5);
2934 break;
2935 }
2936 }
2937 if (val & EMAC_MDIO_COMM_START_BUSY) {
2938 DP(NETIF_MSG_LINK, "read phy register failed\n");
2939
2940 *ret_val = 0;
2941 rc = -EFAULT;
2942 }
2943 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2944 return rc;
2945 }
2946
2947 /******************************************************************/
2948 /* CL45 access functions */
2949 /******************************************************************/
2950 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2951 u8 devad, u16 reg, u16 *ret_val)
2952 {
2953 u32 val;
2954 u16 i;
2955 int rc = 0;
2956 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2957 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2958 EMAC_MDIO_STATUS_10MB);
2959 /* address */
2960 val = ((phy->addr << 21) | (devad << 16) | reg |
2961 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2962 EMAC_MDIO_COMM_START_BUSY);
2963 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2964
2965 for (i = 0; i < 50; i++) {
2966 udelay(10);
2967
2968 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2969 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2970 udelay(5);
2971 break;
2972 }
2973 }
2974 if (val & EMAC_MDIO_COMM_START_BUSY) {
2975 DP(NETIF_MSG_LINK, "read phy register failed\n");
2976 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2977 *ret_val = 0;
2978 rc = -EFAULT;
2979 } else {
2980 /* data */
2981 val = ((phy->addr << 21) | (devad << 16) |
2982 EMAC_MDIO_COMM_COMMAND_READ_45 |
2983 EMAC_MDIO_COMM_START_BUSY);
2984 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2985
2986 for (i = 0; i < 50; i++) {
2987 udelay(10);
2988
2989 val = REG_RD(bp, phy->mdio_ctrl +
2990 EMAC_REG_EMAC_MDIO_COMM);
2991 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2992 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2993 break;
2994 }
2995 }
2996 if (val & EMAC_MDIO_COMM_START_BUSY) {
2997 DP(NETIF_MSG_LINK, "read phy register failed\n");
2998 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2999 *ret_val = 0;
3000 rc = -EFAULT;
3001 }
3002 }
3003 /* Work around for E3 A0 */
3004 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3005 phy->flags ^= FLAGS_DUMMY_READ;
3006 if (phy->flags & FLAGS_DUMMY_READ) {
3007 u16 temp_val;
3008 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3009 }
3010 }
3011
3012 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3013 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3014 EMAC_MDIO_STATUS_10MB);
3015 return rc;
3016 }
3017
3018 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3019 u8 devad, u16 reg, u16 val)
3020 {
3021 u32 tmp;
3022 u8 i;
3023 int rc = 0;
3024 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3025 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3026 EMAC_MDIO_STATUS_10MB);
3027
3028 /* address */
3029
3030 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3031 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3032 EMAC_MDIO_COMM_START_BUSY);
3033 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3034
3035 for (i = 0; i < 50; i++) {
3036 udelay(10);
3037
3038 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3039 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3040 udelay(5);
3041 break;
3042 }
3043 }
3044 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3045 DP(NETIF_MSG_LINK, "write phy register failed\n");
3046 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3047 rc = -EFAULT;
3048
3049 } else {
3050 /* data */
3051 tmp = ((phy->addr << 21) | (devad << 16) | val |
3052 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3053 EMAC_MDIO_COMM_START_BUSY);
3054 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3055
3056 for (i = 0; i < 50; i++) {
3057 udelay(10);
3058
3059 tmp = REG_RD(bp, phy->mdio_ctrl +
3060 EMAC_REG_EMAC_MDIO_COMM);
3061 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3062 udelay(5);
3063 break;
3064 }
3065 }
3066 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3067 DP(NETIF_MSG_LINK, "write phy register failed\n");
3068 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3069 rc = -EFAULT;
3070 }
3071 }
3072 /* Work around for E3 A0 */
3073 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3074 phy->flags ^= FLAGS_DUMMY_READ;
3075 if (phy->flags & FLAGS_DUMMY_READ) {
3076 u16 temp_val;
3077 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3078 }
3079 }
3080 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3081 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3082 EMAC_MDIO_STATUS_10MB);
3083 return rc;
3084 }
3085
3086
3087 /******************************************************************/
3088 /* BSC access functions from E3 */
3089 /******************************************************************/
3090 static void bnx2x_bsc_module_sel(struct link_params *params)
3091 {
3092 int idx;
3093 u32 board_cfg, sfp_ctrl;
3094 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3095 struct bnx2x *bp = params->bp;
3096 u8 port = params->port;
3097 /* Read I2C output PINs */
3098 board_cfg = REG_RD(bp, params->shmem_base +
3099 offsetof(struct shmem_region,
3100 dev_info.shared_hw_config.board));
3101 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3102 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3103 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3104
3105 /* Read I2C output value */
3106 sfp_ctrl = REG_RD(bp, params->shmem_base +
3107 offsetof(struct shmem_region,
3108 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3109 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3110 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3111 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3112 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3113 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3114 }
3115
3116 static int bnx2x_bsc_read(struct link_params *params,
3117 struct bnx2x_phy *phy,
3118 u8 sl_devid,
3119 u16 sl_addr,
3120 u8 lc_addr,
3121 u8 xfer_cnt,
3122 u32 *data_array)
3123 {
3124 u32 val, i;
3125 int rc = 0;
3126 struct bnx2x *bp = params->bp;
3127
3128 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3129 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3130 return -EINVAL;
3131 }
3132
3133 if (xfer_cnt > 16) {
3134 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3135 xfer_cnt);
3136 return -EINVAL;
3137 }
3138 bnx2x_bsc_module_sel(params);
3139
3140 xfer_cnt = 16 - lc_addr;
3141
3142 /* enable the engine */
3143 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3144 val |= MCPR_IMC_COMMAND_ENABLE;
3145 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3146
3147 /* program slave device ID */
3148 val = (sl_devid << 16) | sl_addr;
3149 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3150
3151 /* start xfer with 0 byte to update the address pointer ???*/
3152 val = (MCPR_IMC_COMMAND_ENABLE) |
3153 (MCPR_IMC_COMMAND_WRITE_OP <<
3154 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3155 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3156 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3157
3158 /* poll for completion */
3159 i = 0;
3160 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3161 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3162 udelay(10);
3163 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3164 if (i++ > 1000) {
3165 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3166 i);
3167 rc = -EFAULT;
3168 break;
3169 }
3170 }
3171 if (rc == -EFAULT)
3172 return rc;
3173
3174 /* start xfer with read op */
3175 val = (MCPR_IMC_COMMAND_ENABLE) |
3176 (MCPR_IMC_COMMAND_READ_OP <<
3177 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3178 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3179 (xfer_cnt);
3180 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3181
3182 /* poll for completion */
3183 i = 0;
3184 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3185 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3186 udelay(10);
3187 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3188 if (i++ > 1000) {
3189 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3190 rc = -EFAULT;
3191 break;
3192 }
3193 }
3194 if (rc == -EFAULT)
3195 return rc;
3196
3197 for (i = (lc_addr >> 2); i < 4; i++) {
3198 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3199 #ifdef __BIG_ENDIAN
3200 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3201 ((data_array[i] & 0x0000ff00) << 8) |
3202 ((data_array[i] & 0x00ff0000) >> 8) |
3203 ((data_array[i] & 0xff000000) >> 24);
3204 #endif
3205 }
3206 return rc;
3207 }
3208
3209 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3210 u8 devad, u16 reg, u16 or_val)
3211 {
3212 u16 val;
3213 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3214 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3215 }
3216
3217 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3218 u8 devad, u16 reg, u16 *ret_val)
3219 {
3220 u8 phy_index;
3221 /*
3222 * Probe for the phy according to the given phy_addr, and execute
3223 * the read request on it
3224 */
3225 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3226 if (params->phy[phy_index].addr == phy_addr) {
3227 return bnx2x_cl45_read(params->bp,
3228 &params->phy[phy_index], devad,
3229 reg, ret_val);
3230 }
3231 }
3232 return -EINVAL;
3233 }
3234
3235 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3236 u8 devad, u16 reg, u16 val)
3237 {
3238 u8 phy_index;
3239 /*
3240 * Probe for the phy according to the given phy_addr, and execute
3241 * the write request on it
3242 */
3243 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3244 if (params->phy[phy_index].addr == phy_addr) {
3245 return bnx2x_cl45_write(params->bp,
3246 &params->phy[phy_index], devad,
3247 reg, val);
3248 }
3249 }
3250 return -EINVAL;
3251 }
3252 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3253 struct link_params *params)
3254 {
3255 u8 lane = 0;
3256 struct bnx2x *bp = params->bp;
3257 u32 path_swap, path_swap_ovr;
3258 u8 path, port;
3259
3260 path = BP_PATH(bp);
3261 port = params->port;
3262
3263 if (bnx2x_is_4_port_mode(bp)) {
3264 u32 port_swap, port_swap_ovr;
3265
3266 /*figure out path swap value */
3267 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3268 if (path_swap_ovr & 0x1)
3269 path_swap = (path_swap_ovr & 0x2);
3270 else
3271 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3272
3273 if (path_swap)
3274 path = path ^ 1;
3275
3276 /*figure out port swap value */
3277 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3278 if (port_swap_ovr & 0x1)
3279 port_swap = (port_swap_ovr & 0x2);
3280 else
3281 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3282
3283 if (port_swap)
3284 port = port ^ 1;
3285
3286 lane = (port<<1) + path;
3287 } else { /* two port mode - no port swap */
3288
3289 /*figure out path swap value */
3290 path_swap_ovr =
3291 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3292 if (path_swap_ovr & 0x1) {
3293 path_swap = (path_swap_ovr & 0x2);
3294 } else {
3295 path_swap =
3296 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3297 }
3298 if (path_swap)
3299 path = path ^ 1;
3300
3301 lane = path << 1 ;
3302 }
3303 return lane;
3304 }
3305
3306 static void bnx2x_set_aer_mmd(struct link_params *params,
3307 struct bnx2x_phy *phy)
3308 {
3309 u32 ser_lane;
3310 u16 offset, aer_val;
3311 struct bnx2x *bp = params->bp;
3312 ser_lane = ((params->lane_config &
3313 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3314 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3315
3316 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3317 (phy->addr + ser_lane) : 0;
3318
3319 if (USES_WARPCORE(bp)) {
3320 aer_val = bnx2x_get_warpcore_lane(phy, params);
3321 /*
3322 * In Dual-lane mode, two lanes are joined together,
3323 * so in order to configure them, the AER broadcast method is
3324 * used here.
3325 * 0x200 is the broadcast address for lanes 0,1
3326 * 0x201 is the broadcast address for lanes 2,3
3327 */
3328 if (phy->flags & FLAGS_WC_DUAL_MODE)
3329 aer_val = (aer_val >> 1) | 0x200;
3330 } else if (CHIP_IS_E2(bp))
3331 aer_val = 0x3800 + offset - 1;
3332 else
3333 aer_val = 0x3800 + offset;
3334 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3335 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3336 MDIO_AER_BLOCK_AER_REG, aer_val);
3337
3338 }
3339
3340 /******************************************************************/
3341 /* Internal phy section */
3342 /******************************************************************/
3343
3344 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3345 {
3346 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3347
3348 /* Set Clause 22 */
3349 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3350 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3351 udelay(500);
3352 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3353 udelay(500);
3354 /* Set Clause 45 */
3355 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3356 }
3357
3358 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3359 {
3360 u32 val;
3361
3362 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3363
3364 val = SERDES_RESET_BITS << (port*16);
3365
3366 /* reset and unreset the SerDes/XGXS */
3367 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3368 udelay(500);
3369 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3370
3371 bnx2x_set_serdes_access(bp, port);
3372
3373 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3374 DEFAULT_PHY_DEV_ADDR);
3375 }
3376
3377 static void bnx2x_xgxs_deassert(struct link_params *params)
3378 {
3379 struct bnx2x *bp = params->bp;
3380 u8 port;
3381 u32 val;
3382 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3383 port = params->port;
3384
3385 val = XGXS_RESET_BITS << (port*16);
3386
3387 /* reset and unreset the SerDes/XGXS */
3388 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3389 udelay(500);
3390 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3391
3392 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3393 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3394 params->phy[INT_PHY].def_md_devad);
3395 }
3396
3397 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3398 struct link_params *params, u16 *ieee_fc)
3399 {
3400 struct bnx2x *bp = params->bp;
3401 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3402 /**
3403 * resolve pause mode and advertisement Please refer to Table
3404 * 28B-3 of the 802.3ab-1999 spec
3405 */
3406
3407 switch (phy->req_flow_ctrl) {
3408 case BNX2X_FLOW_CTRL_AUTO:
3409 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3410 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3411 else
3412 *ieee_fc |=
3413 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3414 break;
3415
3416 case BNX2X_FLOW_CTRL_TX:
3417 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3418 break;
3419
3420 case BNX2X_FLOW_CTRL_RX:
3421 case BNX2X_FLOW_CTRL_BOTH:
3422 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3423 break;
3424
3425 case BNX2X_FLOW_CTRL_NONE:
3426 default:
3427 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3428 break;
3429 }
3430 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3431 }
3432
3433 static void set_phy_vars(struct link_params *params,
3434 struct link_vars *vars)
3435 {
3436 struct bnx2x *bp = params->bp;
3437 u8 actual_phy_idx, phy_index, link_cfg_idx;
3438 u8 phy_config_swapped = params->multi_phy_config &
3439 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3440 for (phy_index = INT_PHY; phy_index < params->num_phys;
3441 phy_index++) {
3442 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3443 actual_phy_idx = phy_index;
3444 if (phy_config_swapped) {
3445 if (phy_index == EXT_PHY1)
3446 actual_phy_idx = EXT_PHY2;
3447 else if (phy_index == EXT_PHY2)
3448 actual_phy_idx = EXT_PHY1;
3449 }
3450 params->phy[actual_phy_idx].req_flow_ctrl =
3451 params->req_flow_ctrl[link_cfg_idx];
3452
3453 params->phy[actual_phy_idx].req_line_speed =
3454 params->req_line_speed[link_cfg_idx];
3455
3456 params->phy[actual_phy_idx].speed_cap_mask =
3457 params->speed_cap_mask[link_cfg_idx];
3458
3459 params->phy[actual_phy_idx].req_duplex =
3460 params->req_duplex[link_cfg_idx];
3461
3462 if (params->req_line_speed[link_cfg_idx] ==
3463 SPEED_AUTO_NEG)
3464 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3465
3466 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3467 " speed_cap_mask %x\n",
3468 params->phy[actual_phy_idx].req_flow_ctrl,
3469 params->phy[actual_phy_idx].req_line_speed,
3470 params->phy[actual_phy_idx].speed_cap_mask);
3471 }
3472 }
3473
3474 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3475 struct bnx2x_phy *phy,
3476 struct link_vars *vars)
3477 {
3478 u16 val;
3479 struct bnx2x *bp = params->bp;
3480 /* read modify write pause advertizing */
3481 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3482
3483 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3484
3485 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3486 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3487 if ((vars->ieee_fc &
3488 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3489 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3490 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3491 }
3492 if ((vars->ieee_fc &
3493 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3494 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3495 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3496 }
3497 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3498 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3499 }
3500
3501 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3502 { /* LD LP */
3503 switch (pause_result) { /* ASYM P ASYM P */
3504 case 0xb: /* 1 0 1 1 */
3505 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3506 break;
3507
3508 case 0xe: /* 1 1 1 0 */
3509 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3510 break;
3511
3512 case 0x5: /* 0 1 0 1 */
3513 case 0x7: /* 0 1 1 1 */
3514 case 0xd: /* 1 1 0 1 */
3515 case 0xf: /* 1 1 1 1 */
3516 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3517 break;
3518
3519 default:
3520 break;
3521 }
3522 if (pause_result & (1<<0))
3523 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3524 if (pause_result & (1<<1))
3525 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3526 }
3527
3528 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3529 struct link_params *params,
3530 struct link_vars *vars)
3531 {
3532 struct bnx2x *bp = params->bp;
3533 u16 ld_pause; /* local */
3534 u16 lp_pause; /* link partner */
3535 u16 pause_result;
3536 u8 ret = 0;
3537 /* read twice */
3538
3539 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3540
3541 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3542 vars->flow_ctrl = phy->req_flow_ctrl;
3543 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3544 vars->flow_ctrl = params->req_fc_auto_adv;
3545 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3546 ret = 1;
3547 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3548 bnx2x_cl22_read(bp, phy,
3549 0x4, &ld_pause);
3550 bnx2x_cl22_read(bp, phy,
3551 0x5, &lp_pause);
3552 } else {
3553 bnx2x_cl45_read(bp, phy,
3554 MDIO_AN_DEVAD,
3555 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3556 bnx2x_cl45_read(bp, phy,
3557 MDIO_AN_DEVAD,
3558 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3559 }
3560 pause_result = (ld_pause &
3561 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3562 pause_result |= (lp_pause &
3563 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3564 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3565 pause_result);
3566 bnx2x_pause_resolve(vars, pause_result);
3567 }
3568 return ret;
3569 }
3570 /******************************************************************/
3571 /* Warpcore section */
3572 /******************************************************************/
3573 /* The init_internal_warpcore should mirror the xgxs,
3574 * i.e. reset the lane (if needed), set aer for the
3575 * init configuration, and set/clear SGMII flag. Internal
3576 * phy init is done purely in phy_init stage.
3577 */
3578 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3579 struct link_params *params,
3580 struct link_vars *vars) {
3581 u16 val16 = 0, lane, bam37 = 0;
3582 struct bnx2x *bp = params->bp;
3583 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3584 /* Check adding advertisement for 1G KX */
3585 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3586 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3587 (vars->line_speed == SPEED_1000)) {
3588 u16 sd_digital;
3589 val16 |= (1<<5);
3590
3591 /* Enable CL37 1G Parallel Detect */
3592 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3593 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3594 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3595 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3596 (sd_digital | 0x1));
3597
3598 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3599 }
3600 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3601 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3602 (vars->line_speed == SPEED_10000)) {
3603 /* Check adding advertisement for 10G KR */
3604 val16 |= (1<<7);
3605 /* Enable 10G Parallel Detect */
3606 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3607 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3608
3609 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3610 }
3611
3612 /* Set Transmit PMD settings */
3613 lane = bnx2x_get_warpcore_lane(phy, params);
3614 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3615 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3616 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3617 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3618 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3619 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3620 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3621 0x03f0);
3622 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3623 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3624 0x03f0);
3625 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3626 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3627 0x383f);
3628
3629 /* Advertised speeds */
3630 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3631 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3632
3633 /* Enable CL37 BAM */
3634 if (REG_RD(bp, params->shmem_base +
3635 offsetof(struct shmem_region, dev_info.
3636 port_hw_config[params->port].default_cfg)) &
3637 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3638 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3639 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3641 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3642 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3643 }
3644
3645 /* Advertise pause */
3646 bnx2x_ext_phy_set_pause(params, phy, vars);
3647
3648 /* Enable Autoneg */
3649 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3651
3652 /* Over 1G - AN local device user page 1 */
3653 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3654 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3655
3656 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3657 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3658
3659 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3660 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3661 }
3662
3663 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3664 struct link_params *params,
3665 struct link_vars *vars)
3666 {
3667 struct bnx2x *bp = params->bp;
3668 u16 val;
3669
3670 /* Disable Autoneg */
3671 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3672 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3673
3674 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3675 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3676
3677 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3679
3680 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3681 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3682
3683 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3684 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3685
3686 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3687 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3688
3689 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3690 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3691
3692 /* Disable CL36 PCS Tx */
3693 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3695
3696 /* Double Wide Single Data Rate @ pll rate */
3697 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3698 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3699
3700 /* Leave cl72 training enable, needed for KR */
3701 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3702 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3703 0x2);
3704
3705 /* Leave CL72 enabled */
3706 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3707 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3708 &val);
3709 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3710 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3711 val | 0x3800);
3712
3713 /* Set speed via PMA/PMD register */
3714 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3715 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3716
3717 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3718 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3719
3720 /*Enable encoded forced speed */
3721 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3723
3724 /* Turn TX scramble payload only the 64/66 scrambler */
3725 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3726 MDIO_WC_REG_TX66_CONTROL, 0x9);
3727
3728 /* Turn RX scramble payload only the 64/66 scrambler */
3729 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3730 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3731
3732 /* set and clear loopback to cause a reset to 64/66 decoder */
3733 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3734 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3735 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3736 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3737
3738 }
3739
3740 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3741 struct link_params *params,
3742 u8 is_xfi)
3743 {
3744 struct bnx2x *bp = params->bp;
3745 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3746 /* Hold rxSeqStart */
3747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3748 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3749 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3750 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3751
3752 /* Hold tx_fifo_reset */
3753 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3754 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3755 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3757
3758 /* Disable CL73 AN */
3759 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3760
3761 /* Disable 100FX Enable and Auto-Detect */
3762 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3763 MDIO_WC_REG_FX100_CTRL1, &val);
3764 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3765 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3766
3767 /* Disable 100FX Idle detect */
3768 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3769 MDIO_WC_REG_FX100_CTRL3, &val);
3770 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3772
3773 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3774 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3775 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3778
3779 /* Turn off auto-detect & fiber mode */
3780 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3781 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3784 (val & 0xFFEE));
3785
3786 /* Set filter_force_link, disable_false_link and parallel_detect */
3787 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3788 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3789 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3790 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3791 ((val | 0x0006) & 0xFFFE));
3792
3793 /* Set XFI / SFI */
3794 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3795 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3796
3797 misc1_val &= ~(0x1f);
3798
3799 if (is_xfi) {
3800 misc1_val |= 0x5;
3801 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3802 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3803 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3804 tx_driver_val =
3805 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3806 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3807 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3808
3809 } else {
3810 misc1_val |= 0x9;
3811 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3812 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3813 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3814 tx_driver_val =
3815 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3816 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3817 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3818 }
3819 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3821
3822 /* Set Transmit PMD settings */
3823 lane = bnx2x_get_warpcore_lane(phy, params);
3824 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3825 MDIO_WC_REG_TX_FIR_TAP,
3826 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3827 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3829 tx_driver_val);
3830
3831 /* Enable fiber mode, enable and invert sig_det */
3832 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3833 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3834 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3835 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3836
3837 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3838 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3839 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3840 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3842
3843 /* 10G XFI Full Duplex */
3844 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3845 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3846
3847 /* Release tx_fifo_reset */
3848 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3849 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3852
3853 /* Release rxSeqStart */
3854 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3855 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3858 }
3859
3860 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3861 struct bnx2x_phy *phy)
3862 {
3863 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3864 }
3865
3866 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3867 struct bnx2x_phy *phy,
3868 u16 lane)
3869 {
3870 /* Rx0 anaRxControl1G */
3871 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3872 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3873
3874 /* Rx2 anaRxControl1G */
3875 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3877
3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879 MDIO_WC_REG_RX66_SCW0, 0xE070);
3880
3881 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3882 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3883
3884 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3885 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3886
3887 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888 MDIO_WC_REG_RX66_SCW3, 0x8090);
3889
3890 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3892
3893 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3895
3896 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3897 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3898
3899 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3901
3902 /* Serdes Digital Misc1 */
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3905
3906 /* Serdes Digital4 Misc3 */
3907 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3909
3910 /* Set Transmit PMD settings */
3911 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3912 MDIO_WC_REG_TX_FIR_TAP,
3913 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3914 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3915 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3916 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3917 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3918 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3919 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3920 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3921 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3922 }
3923
3924 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3925 struct link_params *params,
3926 u8 fiber_mode)
3927 {
3928 struct bnx2x *bp = params->bp;
3929 u16 val16, digctrl_kx1, digctrl_kx2;
3930 u8 lane;
3931
3932 lane = bnx2x_get_warpcore_lane(phy, params);
3933
3934 /* Clear XFI clock comp in non-10G single lane mode. */
3935 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3936 MDIO_WC_REG_RX66_CONTROL, &val16);
3937 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3939
3940 if (phy->req_line_speed == SPEED_AUTO_NEG) {
3941 /* SGMII Autoneg */
3942 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3943 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3944 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3946 val16 | 0x1000);
3947 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3948 } else {
3949 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3950 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3951 val16 &= 0xcfbf;
3952 switch (phy->req_line_speed) {
3953 case SPEED_10:
3954 break;
3955 case SPEED_100:
3956 val16 |= 0x2000;
3957 break;
3958 case SPEED_1000:
3959 val16 |= 0x0040;
3960 break;
3961 default:
3962 DP(NETIF_MSG_LINK,
3963 "Speed not supported: 0x%x\n", phy->req_line_speed);
3964 return;
3965 }
3966
3967 if (phy->req_duplex == DUPLEX_FULL)
3968 val16 |= 0x0100;
3969
3970 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3971 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3972
3973 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3974 phy->req_line_speed);
3975 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3976 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3977 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
3978 }
3979
3980 /* SGMII Slave mode and disable signal detect */
3981 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3982 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3983 if (fiber_mode)
3984 digctrl_kx1 = 1;
3985 else
3986 digctrl_kx1 &= 0xff4a;
3987
3988 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990 digctrl_kx1);
3991
3992 /* Turn off parallel detect */
3993 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3995 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997 (digctrl_kx2 & ~(1<<2)));
3998
3999 /* Re-enable parallel detect */
4000 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4001 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4002 (digctrl_kx2 | (1<<2)));
4003
4004 /* Enable autodet */
4005 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4007 (digctrl_kx1 | 0x10));
4008 }
4009
4010 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4011 struct bnx2x_phy *phy,
4012 u8 reset)
4013 {
4014 u16 val;
4015 /* Take lane out of reset after configuration is finished */
4016 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4018 if (reset)
4019 val |= 0xC000;
4020 else
4021 val &= 0x3FFF;
4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023 MDIO_WC_REG_DIGITAL5_MISC6, val);
4024 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4026 }
4027
4028
4029 /* Clear SFI/XFI link settings registers */
4030 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4031 struct link_params *params,
4032 u16 lane)
4033 {
4034 struct bnx2x *bp = params->bp;
4035 u16 val16;
4036
4037 /* Set XFI clock comp as default. */
4038 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4039 MDIO_WC_REG_RX66_CONTROL, &val16);
4040 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4042
4043 bnx2x_warpcore_reset_lane(bp, phy, 1);
4044 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4045 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4047 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4049 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4051 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4052 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4053 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4054 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4055 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4056 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4057 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4058 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4059 lane = bnx2x_get_warpcore_lane(phy, params);
4060 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4061 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4062 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4063 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4066 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4068 bnx2x_warpcore_reset_lane(bp, phy, 0);
4069 }
4070
4071 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4072 u32 chip_id,
4073 u32 shmem_base, u8 port,
4074 u8 *gpio_num, u8 *gpio_port)
4075 {
4076 u32 cfg_pin;
4077 *gpio_num = 0;
4078 *gpio_port = 0;
4079 if (CHIP_IS_E3(bp)) {
4080 cfg_pin = (REG_RD(bp, shmem_base +
4081 offsetof(struct shmem_region,
4082 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4083 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4084 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4085
4086 /*
4087 * Should not happen. This function called upon interrupt
4088 * triggered by GPIO ( since EPIO can only generate interrupts
4089 * to MCP).
4090 * So if this function was called and none of the GPIOs was set,
4091 * it means the shit hit the fan.
4092 */
4093 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4094 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4095 DP(NETIF_MSG_LINK,
4096 "ERROR: Invalid cfg pin %x for module detect indication\n",
4097 cfg_pin);
4098 return -EINVAL;
4099 }
4100
4101 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4102 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4103 } else {
4104 *gpio_num = MISC_REGISTERS_GPIO_3;
4105 *gpio_port = port;
4106 }
4107 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4108 return 0;
4109 }
4110
4111 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4112 struct link_params *params)
4113 {
4114 struct bnx2x *bp = params->bp;
4115 u8 gpio_num, gpio_port;
4116 u32 gpio_val;
4117 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4118 params->shmem_base, params->port,
4119 &gpio_num, &gpio_port) != 0)
4120 return 0;
4121 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4122
4123 /* Call the handling function in case module is detected */
4124 if (gpio_val == 0)
4125 return 1;
4126 else
4127 return 0;
4128 }
4129
4130 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4131 struct link_params *params,
4132 struct link_vars *vars)
4133 {
4134 struct bnx2x *bp = params->bp;
4135 u32 serdes_net_if;
4136 u8 fiber_mode;
4137 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4138 serdes_net_if = (REG_RD(bp, params->shmem_base +
4139 offsetof(struct shmem_region, dev_info.
4140 port_hw_config[params->port].default_cfg)) &
4141 PORT_HW_CFG_NET_SERDES_IF_MASK);
4142 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4143 "serdes_net_if = 0x%x\n",
4144 vars->line_speed, serdes_net_if);
4145 bnx2x_set_aer_mmd(params, phy);
4146
4147 vars->phy_flags |= PHY_XGXS_FLAG;
4148 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4149 (phy->req_line_speed &&
4150 ((phy->req_line_speed == SPEED_100) ||
4151 (phy->req_line_speed == SPEED_10)))) {
4152 vars->phy_flags |= PHY_SGMII_FLAG;
4153 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4154 bnx2x_warpcore_clear_regs(phy, params, lane);
4155 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4156 } else {
4157 switch (serdes_net_if) {
4158 case PORT_HW_CFG_NET_SERDES_IF_KR:
4159 /* Enable KR Auto Neg */
4160 if (params->loopback_mode == LOOPBACK_NONE)
4161 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4162 else {
4163 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4164 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4165 }
4166 break;
4167
4168 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4169 bnx2x_warpcore_clear_regs(phy, params, lane);
4170 if (vars->line_speed == SPEED_10000) {
4171 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4172 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4173 } else {
4174 if (SINGLE_MEDIA_DIRECT(params)) {
4175 DP(NETIF_MSG_LINK, "1G Fiber\n");
4176 fiber_mode = 1;
4177 } else {
4178 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4179 fiber_mode = 0;
4180 }
4181 bnx2x_warpcore_set_sgmii_speed(phy,
4182 params,
4183 fiber_mode);
4184 }
4185
4186 break;
4187
4188 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4189
4190 bnx2x_warpcore_clear_regs(phy, params, lane);
4191 if (vars->line_speed == SPEED_10000) {
4192 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4193 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4194 } else if (vars->line_speed == SPEED_1000) {
4195 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4196 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4197 }
4198 /* Issue Module detection */
4199 if (bnx2x_is_sfp_module_plugged(phy, params))
4200 bnx2x_sfp_module_detection(phy, params);
4201 break;
4202
4203 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4204 if (vars->line_speed != SPEED_20000) {
4205 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4206 return;
4207 }
4208 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4209 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4210 /* Issue Module detection */
4211
4212 bnx2x_sfp_module_detection(phy, params);
4213 break;
4214
4215 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4216 if (vars->line_speed != SPEED_20000) {
4217 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4218 return;
4219 }
4220 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4221 bnx2x_warpcore_set_20G_KR2(bp, phy);
4222 break;
4223
4224 default:
4225 DP(NETIF_MSG_LINK,
4226 "Unsupported Serdes Net Interface 0x%x\n",
4227 serdes_net_if);
4228 return;
4229 }
4230 }
4231
4232 /* Take lane out of reset after configuration is finished */
4233 bnx2x_warpcore_reset_lane(bp, phy, 0);
4234 DP(NETIF_MSG_LINK, "Exit config init\n");
4235 }
4236
4237 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4238 struct bnx2x_phy *phy,
4239 u8 tx_en)
4240 {
4241 struct bnx2x *bp = params->bp;
4242 u32 cfg_pin;
4243 u8 port = params->port;
4244
4245 cfg_pin = REG_RD(bp, params->shmem_base +
4246 offsetof(struct shmem_region,
4247 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4248 PORT_HW_CFG_TX_LASER_MASK;
4249 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4250 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4251 /* For 20G, the expected pin to be used is 3 pins after the current */
4252
4253 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4254 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4255 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4256 }
4257
4258 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4259 struct link_params *params)
4260 {
4261 struct bnx2x *bp = params->bp;
4262 u16 val16;
4263 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4264 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4265 bnx2x_set_aer_mmd(params, phy);
4266 /* Global register */
4267 bnx2x_warpcore_reset_lane(bp, phy, 1);
4268
4269 /* Clear loopback settings (if any) */
4270 /* 10G & 20G */
4271 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4272 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4273 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4274 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4275 0xBFFF);
4276
4277 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4278 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4279 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4280 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4281
4282 /* Update those 1-copy registers */
4283 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4284 MDIO_AER_BLOCK_AER_REG, 0);
4285 /* Enable 1G MDIO (1-copy) */
4286 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4287 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4288 &val16);
4289 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4290 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4291 val16 & ~0x10);
4292
4293 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4294 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4295 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4296 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4297 val16 & 0xff00);
4298
4299 }
4300
4301 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4302 struct link_params *params)
4303 {
4304 struct bnx2x *bp = params->bp;
4305 u16 val16;
4306 u32 lane;
4307 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4308 params->loopback_mode, phy->req_line_speed);
4309
4310 if (phy->req_line_speed < SPEED_10000) {
4311 /* 10/100/1000 */
4312
4313 /* Update those 1-copy registers */
4314 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4315 MDIO_AER_BLOCK_AER_REG, 0);
4316 /* Enable 1G MDIO (1-copy) */
4317 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4318 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4319 &val16);
4320 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4321 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4322 val16 | 0x10);
4323 /* Set 1G loopback based on lane (1-copy) */
4324 lane = bnx2x_get_warpcore_lane(phy, params);
4325 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4326 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4327 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4328 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4329 val16 | (1<<lane));
4330
4331 /* Switch back to 4-copy registers */
4332 bnx2x_set_aer_mmd(params, phy);
4333 /* Global loopback, not recommended. */
4334 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4335 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4336 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4337 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4338 0x4000);
4339 } else {
4340 /* 10G & 20G */
4341 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4342 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4343 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4344 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4345 0x4000);
4346
4347 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4348 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4349 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4350 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4351 }
4352 }
4353
4354
4355 void bnx2x_link_status_update(struct link_params *params,
4356 struct link_vars *vars)
4357 {
4358 struct bnx2x *bp = params->bp;
4359 u8 link_10g_plus;
4360 u8 port = params->port;
4361 u32 sync_offset, media_types;
4362 /* Update PHY configuration */
4363 set_phy_vars(params, vars);
4364
4365 vars->link_status = REG_RD(bp, params->shmem_base +
4366 offsetof(struct shmem_region,
4367 port_mb[port].link_status));
4368
4369 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4370 vars->phy_flags = PHY_XGXS_FLAG;
4371 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4372 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4373
4374 if (vars->link_up) {
4375 DP(NETIF_MSG_LINK, "phy link up\n");
4376
4377 vars->phy_link_up = 1;
4378 vars->duplex = DUPLEX_FULL;
4379 switch (vars->link_status &
4380 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4381 case LINK_10THD:
4382 vars->duplex = DUPLEX_HALF;
4383 /* fall thru */
4384 case LINK_10TFD:
4385 vars->line_speed = SPEED_10;
4386 break;
4387
4388 case LINK_100TXHD:
4389 vars->duplex = DUPLEX_HALF;
4390 /* fall thru */
4391 case LINK_100T4:
4392 case LINK_100TXFD:
4393 vars->line_speed = SPEED_100;
4394 break;
4395
4396 case LINK_1000THD:
4397 vars->duplex = DUPLEX_HALF;
4398 /* fall thru */
4399 case LINK_1000TFD:
4400 vars->line_speed = SPEED_1000;
4401 break;
4402
4403 case LINK_2500THD:
4404 vars->duplex = DUPLEX_HALF;
4405 /* fall thru */
4406 case LINK_2500TFD:
4407 vars->line_speed = SPEED_2500;
4408 break;
4409
4410 case LINK_10GTFD:
4411 vars->line_speed = SPEED_10000;
4412 break;
4413 case LINK_20GTFD:
4414 vars->line_speed = SPEED_20000;
4415 break;
4416 default:
4417 break;
4418 }
4419 vars->flow_ctrl = 0;
4420 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4421 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4422
4423 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4424 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4425
4426 if (!vars->flow_ctrl)
4427 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4428
4429 if (vars->line_speed &&
4430 ((vars->line_speed == SPEED_10) ||
4431 (vars->line_speed == SPEED_100))) {
4432 vars->phy_flags |= PHY_SGMII_FLAG;
4433 } else {
4434 vars->phy_flags &= ~PHY_SGMII_FLAG;
4435 }
4436 if (vars->line_speed &&
4437 USES_WARPCORE(bp) &&
4438 (vars->line_speed == SPEED_1000))
4439 vars->phy_flags |= PHY_SGMII_FLAG;
4440 /* anything 10 and over uses the bmac */
4441 link_10g_plus = (vars->line_speed >= SPEED_10000);
4442
4443 if (link_10g_plus) {
4444 if (USES_WARPCORE(bp))
4445 vars->mac_type = MAC_TYPE_XMAC;
4446 else
4447 vars->mac_type = MAC_TYPE_BMAC;
4448 } else {
4449 if (USES_WARPCORE(bp))
4450 vars->mac_type = MAC_TYPE_UMAC;
4451 else
4452 vars->mac_type = MAC_TYPE_EMAC;
4453 }
4454 } else { /* link down */
4455 DP(NETIF_MSG_LINK, "phy link down\n");
4456
4457 vars->phy_link_up = 0;
4458
4459 vars->line_speed = 0;
4460 vars->duplex = DUPLEX_FULL;
4461 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4462
4463 /* indicate no mac active */
4464 vars->mac_type = MAC_TYPE_NONE;
4465 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4466 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4467 }
4468
4469 /* Sync media type */
4470 sync_offset = params->shmem_base +
4471 offsetof(struct shmem_region,
4472 dev_info.port_hw_config[port].media_type);
4473 media_types = REG_RD(bp, sync_offset);
4474
4475 params->phy[INT_PHY].media_type =
4476 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4477 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4478 params->phy[EXT_PHY1].media_type =
4479 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4480 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4481 params->phy[EXT_PHY2].media_type =
4482 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4483 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4484 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4485
4486 /* Sync AEU offset */
4487 sync_offset = params->shmem_base +
4488 offsetof(struct shmem_region,
4489 dev_info.port_hw_config[port].aeu_int_mask);
4490
4491 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4492
4493 /* Sync PFC status */
4494 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4495 params->feature_config_flags |=
4496 FEATURE_CONFIG_PFC_ENABLED;
4497 else
4498 params->feature_config_flags &=
4499 ~FEATURE_CONFIG_PFC_ENABLED;
4500
4501 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4502 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4503 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4504 vars->line_speed, vars->duplex, vars->flow_ctrl);
4505 }
4506
4507
4508 static void bnx2x_set_master_ln(struct link_params *params,
4509 struct bnx2x_phy *phy)
4510 {
4511 struct bnx2x *bp = params->bp;
4512 u16 new_master_ln, ser_lane;
4513 ser_lane = ((params->lane_config &
4514 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4515 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4516
4517 /* set the master_ln for AN */
4518 CL22_RD_OVER_CL45(bp, phy,
4519 MDIO_REG_BANK_XGXS_BLOCK2,
4520 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4521 &new_master_ln);
4522
4523 CL22_WR_OVER_CL45(bp, phy,
4524 MDIO_REG_BANK_XGXS_BLOCK2 ,
4525 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4526 (new_master_ln | ser_lane));
4527 }
4528
4529 static int bnx2x_reset_unicore(struct link_params *params,
4530 struct bnx2x_phy *phy,
4531 u8 set_serdes)
4532 {
4533 struct bnx2x *bp = params->bp;
4534 u16 mii_control;
4535 u16 i;
4536 CL22_RD_OVER_CL45(bp, phy,
4537 MDIO_REG_BANK_COMBO_IEEE0,
4538 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4539
4540 /* reset the unicore */
4541 CL22_WR_OVER_CL45(bp, phy,
4542 MDIO_REG_BANK_COMBO_IEEE0,
4543 MDIO_COMBO_IEEE0_MII_CONTROL,
4544 (mii_control |
4545 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4546 if (set_serdes)
4547 bnx2x_set_serdes_access(bp, params->port);
4548
4549 /* wait for the reset to self clear */
4550 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4551 udelay(5);
4552
4553 /* the reset erased the previous bank value */
4554 CL22_RD_OVER_CL45(bp, phy,
4555 MDIO_REG_BANK_COMBO_IEEE0,
4556 MDIO_COMBO_IEEE0_MII_CONTROL,
4557 &mii_control);
4558
4559 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4560 udelay(5);
4561 return 0;
4562 }
4563 }
4564
4565 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4566 " Port %d\n",
4567 params->port);
4568 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4569 return -EINVAL;
4570
4571 }
4572
4573 static void bnx2x_set_swap_lanes(struct link_params *params,
4574 struct bnx2x_phy *phy)
4575 {
4576 struct bnx2x *bp = params->bp;
4577 /*
4578 * Each two bits represents a lane number:
4579 * No swap is 0123 => 0x1b no need to enable the swap
4580 */
4581 u16 ser_lane, rx_lane_swap, tx_lane_swap;
4582
4583 ser_lane = ((params->lane_config &
4584 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4585 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4586 rx_lane_swap = ((params->lane_config &
4587 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4588 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4589 tx_lane_swap = ((params->lane_config &
4590 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4591 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4592
4593 if (rx_lane_swap != 0x1b) {
4594 CL22_WR_OVER_CL45(bp, phy,
4595 MDIO_REG_BANK_XGXS_BLOCK2,
4596 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4597 (rx_lane_swap |
4598 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4599 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4600 } else {
4601 CL22_WR_OVER_CL45(bp, phy,
4602 MDIO_REG_BANK_XGXS_BLOCK2,
4603 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4604 }
4605
4606 if (tx_lane_swap != 0x1b) {
4607 CL22_WR_OVER_CL45(bp, phy,
4608 MDIO_REG_BANK_XGXS_BLOCK2,
4609 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4610 (tx_lane_swap |
4611 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4612 } else {
4613 CL22_WR_OVER_CL45(bp, phy,
4614 MDIO_REG_BANK_XGXS_BLOCK2,
4615 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4616 }
4617 }
4618
4619 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4620 struct link_params *params)
4621 {
4622 struct bnx2x *bp = params->bp;
4623 u16 control2;
4624 CL22_RD_OVER_CL45(bp, phy,
4625 MDIO_REG_BANK_SERDES_DIGITAL,
4626 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4627 &control2);
4628 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4629 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4630 else
4631 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4632 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4633 phy->speed_cap_mask, control2);
4634 CL22_WR_OVER_CL45(bp, phy,
4635 MDIO_REG_BANK_SERDES_DIGITAL,
4636 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4637 control2);
4638
4639 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4640 (phy->speed_cap_mask &
4641 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4642 DP(NETIF_MSG_LINK, "XGXS\n");
4643
4644 CL22_WR_OVER_CL45(bp, phy,
4645 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4646 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4647 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4648
4649 CL22_RD_OVER_CL45(bp, phy,
4650 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4651 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4652 &control2);
4653
4654
4655 control2 |=
4656 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4657
4658 CL22_WR_OVER_CL45(bp, phy,
4659 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4660 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4661 control2);
4662
4663 /* Disable parallel detection of HiG */
4664 CL22_WR_OVER_CL45(bp, phy,
4665 MDIO_REG_BANK_XGXS_BLOCK2,
4666 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4667 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4668 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4669 }
4670 }
4671
4672 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4673 struct link_params *params,
4674 struct link_vars *vars,
4675 u8 enable_cl73)
4676 {
4677 struct bnx2x *bp = params->bp;
4678 u16 reg_val;
4679
4680 /* CL37 Autoneg */
4681 CL22_RD_OVER_CL45(bp, phy,
4682 MDIO_REG_BANK_COMBO_IEEE0,
4683 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4684
4685 /* CL37 Autoneg Enabled */
4686 if (vars->line_speed == SPEED_AUTO_NEG)
4687 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4688 else /* CL37 Autoneg Disabled */
4689 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4690 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4691
4692 CL22_WR_OVER_CL45(bp, phy,
4693 MDIO_REG_BANK_COMBO_IEEE0,
4694 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4695
4696 /* Enable/Disable Autodetection */
4697
4698 CL22_RD_OVER_CL45(bp, phy,
4699 MDIO_REG_BANK_SERDES_DIGITAL,
4700 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4701 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4702 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4703 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4704 if (vars->line_speed == SPEED_AUTO_NEG)
4705 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4706 else
4707 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4708
4709 CL22_WR_OVER_CL45(bp, phy,
4710 MDIO_REG_BANK_SERDES_DIGITAL,
4711 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4712
4713 /* Enable TetonII and BAM autoneg */
4714 CL22_RD_OVER_CL45(bp, phy,
4715 MDIO_REG_BANK_BAM_NEXT_PAGE,
4716 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4717 &reg_val);
4718 if (vars->line_speed == SPEED_AUTO_NEG) {
4719 /* Enable BAM aneg Mode and TetonII aneg Mode */
4720 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4721 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4722 } else {
4723 /* TetonII and BAM Autoneg Disabled */
4724 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4725 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4726 }
4727 CL22_WR_OVER_CL45(bp, phy,
4728 MDIO_REG_BANK_BAM_NEXT_PAGE,
4729 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4730 reg_val);
4731
4732 if (enable_cl73) {
4733 /* Enable Cl73 FSM status bits */
4734 CL22_WR_OVER_CL45(bp, phy,
4735 MDIO_REG_BANK_CL73_USERB0,
4736 MDIO_CL73_USERB0_CL73_UCTRL,
4737 0xe);
4738
4739 /* Enable BAM Station Manager*/
4740 CL22_WR_OVER_CL45(bp, phy,
4741 MDIO_REG_BANK_CL73_USERB0,
4742 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4743 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4745 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4746
4747 /* Advertise CL73 link speeds */
4748 CL22_RD_OVER_CL45(bp, phy,
4749 MDIO_REG_BANK_CL73_IEEEB1,
4750 MDIO_CL73_IEEEB1_AN_ADV2,
4751 &reg_val);
4752 if (phy->speed_cap_mask &
4753 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4754 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4755 if (phy->speed_cap_mask &
4756 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4757 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4758
4759 CL22_WR_OVER_CL45(bp, phy,
4760 MDIO_REG_BANK_CL73_IEEEB1,
4761 MDIO_CL73_IEEEB1_AN_ADV2,
4762 reg_val);
4763
4764 /* CL73 Autoneg Enabled */
4765 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4766
4767 } else /* CL73 Autoneg Disabled */
4768 reg_val = 0;
4769
4770 CL22_WR_OVER_CL45(bp, phy,
4771 MDIO_REG_BANK_CL73_IEEEB0,
4772 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4773 }
4774
4775 /* program SerDes, forced speed */
4776 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4777 struct link_params *params,
4778 struct link_vars *vars)
4779 {
4780 struct bnx2x *bp = params->bp;
4781 u16 reg_val;
4782
4783 /* program duplex, disable autoneg and sgmii*/
4784 CL22_RD_OVER_CL45(bp, phy,
4785 MDIO_REG_BANK_COMBO_IEEE0,
4786 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4787 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4788 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4789 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4790 if (phy->req_duplex == DUPLEX_FULL)
4791 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4792 CL22_WR_OVER_CL45(bp, phy,
4793 MDIO_REG_BANK_COMBO_IEEE0,
4794 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4795
4796 /*
4797 * program speed
4798 * - needed only if the speed is greater than 1G (2.5G or 10G)
4799 */
4800 CL22_RD_OVER_CL45(bp, phy,
4801 MDIO_REG_BANK_SERDES_DIGITAL,
4802 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4803 /* clearing the speed value before setting the right speed */
4804 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4805
4806 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4807 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4808
4809 if (!((vars->line_speed == SPEED_1000) ||
4810 (vars->line_speed == SPEED_100) ||
4811 (vars->line_speed == SPEED_10))) {
4812
4813 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4814 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4815 if (vars->line_speed == SPEED_10000)
4816 reg_val |=
4817 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4818 }
4819
4820 CL22_WR_OVER_CL45(bp, phy,
4821 MDIO_REG_BANK_SERDES_DIGITAL,
4822 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4823
4824 }
4825
4826 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4827 struct link_params *params)
4828 {
4829 struct bnx2x *bp = params->bp;
4830 u16 val = 0;
4831
4832 /* configure the 48 bits for BAM AN */
4833
4834 /* set extended capabilities */
4835 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4836 val |= MDIO_OVER_1G_UP1_2_5G;
4837 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4838 val |= MDIO_OVER_1G_UP1_10G;
4839 CL22_WR_OVER_CL45(bp, phy,
4840 MDIO_REG_BANK_OVER_1G,
4841 MDIO_OVER_1G_UP1, val);
4842
4843 CL22_WR_OVER_CL45(bp, phy,
4844 MDIO_REG_BANK_OVER_1G,
4845 MDIO_OVER_1G_UP3, 0x400);
4846 }
4847
4848 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4849 struct link_params *params,
4850 u16 ieee_fc)
4851 {
4852 struct bnx2x *bp = params->bp;
4853 u16 val;
4854 /* for AN, we are always publishing full duplex */
4855
4856 CL22_WR_OVER_CL45(bp, phy,
4857 MDIO_REG_BANK_COMBO_IEEE0,
4858 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4859 CL22_RD_OVER_CL45(bp, phy,
4860 MDIO_REG_BANK_CL73_IEEEB1,
4861 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4862 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4863 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4864 CL22_WR_OVER_CL45(bp, phy,
4865 MDIO_REG_BANK_CL73_IEEEB1,
4866 MDIO_CL73_IEEEB1_AN_ADV1, val);
4867 }
4868
4869 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4870 struct link_params *params,
4871 u8 enable_cl73)
4872 {
4873 struct bnx2x *bp = params->bp;
4874 u16 mii_control;
4875
4876 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4877 /* Enable and restart BAM/CL37 aneg */
4878
4879 if (enable_cl73) {
4880 CL22_RD_OVER_CL45(bp, phy,
4881 MDIO_REG_BANK_CL73_IEEEB0,
4882 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4883 &mii_control);
4884
4885 CL22_WR_OVER_CL45(bp, phy,
4886 MDIO_REG_BANK_CL73_IEEEB0,
4887 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4888 (mii_control |
4889 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4890 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4891 } else {
4892
4893 CL22_RD_OVER_CL45(bp, phy,
4894 MDIO_REG_BANK_COMBO_IEEE0,
4895 MDIO_COMBO_IEEE0_MII_CONTROL,
4896 &mii_control);
4897 DP(NETIF_MSG_LINK,
4898 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4899 mii_control);
4900 CL22_WR_OVER_CL45(bp, phy,
4901 MDIO_REG_BANK_COMBO_IEEE0,
4902 MDIO_COMBO_IEEE0_MII_CONTROL,
4903 (mii_control |
4904 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4905 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4906 }
4907 }
4908
4909 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4910 struct link_params *params,
4911 struct link_vars *vars)
4912 {
4913 struct bnx2x *bp = params->bp;
4914 u16 control1;
4915
4916 /* in SGMII mode, the unicore is always slave */
4917
4918 CL22_RD_OVER_CL45(bp, phy,
4919 MDIO_REG_BANK_SERDES_DIGITAL,
4920 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4921 &control1);
4922 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4923 /* set sgmii mode (and not fiber) */
4924 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4925 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4926 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4927 CL22_WR_OVER_CL45(bp, phy,
4928 MDIO_REG_BANK_SERDES_DIGITAL,
4929 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4930 control1);
4931
4932 /* if forced speed */
4933 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4934 /* set speed, disable autoneg */
4935 u16 mii_control;
4936
4937 CL22_RD_OVER_CL45(bp, phy,
4938 MDIO_REG_BANK_COMBO_IEEE0,
4939 MDIO_COMBO_IEEE0_MII_CONTROL,
4940 &mii_control);
4941 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4942 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4943 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4944
4945 switch (vars->line_speed) {
4946 case SPEED_100:
4947 mii_control |=
4948 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4949 break;
4950 case SPEED_1000:
4951 mii_control |=
4952 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4953 break;
4954 case SPEED_10:
4955 /* there is nothing to set for 10M */
4956 break;
4957 default:
4958 /* invalid speed for SGMII */
4959 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4960 vars->line_speed);
4961 break;
4962 }
4963
4964 /* setting the full duplex */
4965 if (phy->req_duplex == DUPLEX_FULL)
4966 mii_control |=
4967 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4968 CL22_WR_OVER_CL45(bp, phy,
4969 MDIO_REG_BANK_COMBO_IEEE0,
4970 MDIO_COMBO_IEEE0_MII_CONTROL,
4971 mii_control);
4972
4973 } else { /* AN mode */
4974 /* enable and restart AN */
4975 bnx2x_restart_autoneg(phy, params, 0);
4976 }
4977 }
4978
4979
4980 /*
4981 * link management
4982 */
4983
4984 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4985 struct link_params *params)
4986 {
4987 struct bnx2x *bp = params->bp;
4988 u16 pd_10g, status2_1000x;
4989 if (phy->req_line_speed != SPEED_AUTO_NEG)
4990 return 0;
4991 CL22_RD_OVER_CL45(bp, phy,
4992 MDIO_REG_BANK_SERDES_DIGITAL,
4993 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4994 &status2_1000x);
4995 CL22_RD_OVER_CL45(bp, phy,
4996 MDIO_REG_BANK_SERDES_DIGITAL,
4997 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4998 &status2_1000x);
4999 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5000 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5001 params->port);
5002 return 1;
5003 }
5004
5005 CL22_RD_OVER_CL45(bp, phy,
5006 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5007 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5008 &pd_10g);
5009
5010 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5011 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5012 params->port);
5013 return 1;
5014 }
5015 return 0;
5016 }
5017
5018 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5019 struct link_params *params,
5020 struct link_vars *vars,
5021 u32 gp_status)
5022 {
5023 struct bnx2x *bp = params->bp;
5024 u16 ld_pause; /* local driver */
5025 u16 lp_pause; /* link partner */
5026 u16 pause_result;
5027
5028 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5029
5030 /* resolve from gp_status in case of AN complete and not sgmii */
5031 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5032 vars->flow_ctrl = phy->req_flow_ctrl;
5033 else if (phy->req_line_speed != SPEED_AUTO_NEG)
5034 vars->flow_ctrl = params->req_fc_auto_adv;
5035 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5036 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5037 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5038 vars->flow_ctrl = params->req_fc_auto_adv;
5039 return;
5040 }
5041 if ((gp_status &
5042 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5043 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5044 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5045 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5046
5047 CL22_RD_OVER_CL45(bp, phy,
5048 MDIO_REG_BANK_CL73_IEEEB1,
5049 MDIO_CL73_IEEEB1_AN_ADV1,
5050 &ld_pause);
5051 CL22_RD_OVER_CL45(bp, phy,
5052 MDIO_REG_BANK_CL73_IEEEB1,
5053 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5054 &lp_pause);
5055 pause_result = (ld_pause &
5056 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5057 >> 8;
5058 pause_result |= (lp_pause &
5059 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5060 >> 10;
5061 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5062 pause_result);
5063 } else {
5064 CL22_RD_OVER_CL45(bp, phy,
5065 MDIO_REG_BANK_COMBO_IEEE0,
5066 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5067 &ld_pause);
5068 CL22_RD_OVER_CL45(bp, phy,
5069 MDIO_REG_BANK_COMBO_IEEE0,
5070 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5071 &lp_pause);
5072 pause_result = (ld_pause &
5073 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5074 pause_result |= (lp_pause &
5075 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5076 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5077 pause_result);
5078 }
5079 bnx2x_pause_resolve(vars, pause_result);
5080 }
5081 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5082 }
5083
5084 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5085 struct link_params *params)
5086 {
5087 struct bnx2x *bp = params->bp;
5088 u16 rx_status, ustat_val, cl37_fsm_received;
5089 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5090 /* Step 1: Make sure signal is detected */
5091 CL22_RD_OVER_CL45(bp, phy,
5092 MDIO_REG_BANK_RX0,
5093 MDIO_RX0_RX_STATUS,
5094 &rx_status);
5095 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5096 (MDIO_RX0_RX_STATUS_SIGDET)) {
5097 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5098 "rx_status(0x80b0) = 0x%x\n", rx_status);
5099 CL22_WR_OVER_CL45(bp, phy,
5100 MDIO_REG_BANK_CL73_IEEEB0,
5101 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5102 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5103 return;
5104 }
5105 /* Step 2: Check CL73 state machine */
5106 CL22_RD_OVER_CL45(bp, phy,
5107 MDIO_REG_BANK_CL73_USERB0,
5108 MDIO_CL73_USERB0_CL73_USTAT1,
5109 &ustat_val);
5110 if ((ustat_val &
5111 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5112 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5113 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5114 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5115 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5116 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5117 return;
5118 }
5119 /*
5120 * Step 3: Check CL37 Message Pages received to indicate LP
5121 * supports only CL37
5122 */
5123 CL22_RD_OVER_CL45(bp, phy,
5124 MDIO_REG_BANK_REMOTE_PHY,
5125 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5126 &cl37_fsm_received);
5127 if ((cl37_fsm_received &
5128 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5129 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5130 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5131 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5132 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5133 "misc_rx_status(0x8330) = 0x%x\n",
5134 cl37_fsm_received);
5135 return;
5136 }
5137 /*
5138 * The combined cl37/cl73 fsm state information indicating that
5139 * we are connected to a device which does not support cl73, but
5140 * does support cl37 BAM. In this case we disable cl73 and
5141 * restart cl37 auto-neg
5142 */
5143
5144 /* Disable CL73 */
5145 CL22_WR_OVER_CL45(bp, phy,
5146 MDIO_REG_BANK_CL73_IEEEB0,
5147 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5148 0);
5149 /* Restart CL37 autoneg */
5150 bnx2x_restart_autoneg(phy, params, 0);
5151 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5152 }
5153
5154 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5155 struct link_params *params,
5156 struct link_vars *vars,
5157 u32 gp_status)
5158 {
5159 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5160 vars->link_status |=
5161 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5162
5163 if (bnx2x_direct_parallel_detect_used(phy, params))
5164 vars->link_status |=
5165 LINK_STATUS_PARALLEL_DETECTION_USED;
5166 }
5167 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5168 struct link_params *params,
5169 struct link_vars *vars,
5170 u16 is_link_up,
5171 u16 speed_mask,
5172 u16 is_duplex)
5173 {
5174 struct bnx2x *bp = params->bp;
5175 if (phy->req_line_speed == SPEED_AUTO_NEG)
5176 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5177 if (is_link_up) {
5178 DP(NETIF_MSG_LINK, "phy link up\n");
5179
5180 vars->phy_link_up = 1;
5181 vars->link_status |= LINK_STATUS_LINK_UP;
5182
5183 switch (speed_mask) {
5184 case GP_STATUS_10M:
5185 vars->line_speed = SPEED_10;
5186 if (vars->duplex == DUPLEX_FULL)
5187 vars->link_status |= LINK_10TFD;
5188 else
5189 vars->link_status |= LINK_10THD;
5190 break;
5191
5192 case GP_STATUS_100M:
5193 vars->line_speed = SPEED_100;
5194 if (vars->duplex == DUPLEX_FULL)
5195 vars->link_status |= LINK_100TXFD;
5196 else
5197 vars->link_status |= LINK_100TXHD;
5198 break;
5199
5200 case GP_STATUS_1G:
5201 case GP_STATUS_1G_KX:
5202 vars->line_speed = SPEED_1000;
5203 if (vars->duplex == DUPLEX_FULL)
5204 vars->link_status |= LINK_1000TFD;
5205 else
5206 vars->link_status |= LINK_1000THD;
5207 break;
5208
5209 case GP_STATUS_2_5G:
5210 vars->line_speed = SPEED_2500;
5211 if (vars->duplex == DUPLEX_FULL)
5212 vars->link_status |= LINK_2500TFD;
5213 else
5214 vars->link_status |= LINK_2500THD;
5215 break;
5216
5217 case GP_STATUS_5G:
5218 case GP_STATUS_6G:
5219 DP(NETIF_MSG_LINK,
5220 "link speed unsupported gp_status 0x%x\n",
5221 speed_mask);
5222 return -EINVAL;
5223
5224 case GP_STATUS_10G_KX4:
5225 case GP_STATUS_10G_HIG:
5226 case GP_STATUS_10G_CX4:
5227 case GP_STATUS_10G_KR:
5228 case GP_STATUS_10G_SFI:
5229 case GP_STATUS_10G_XFI:
5230 vars->line_speed = SPEED_10000;
5231 vars->link_status |= LINK_10GTFD;
5232 break;
5233 case GP_STATUS_20G_DXGXS:
5234 vars->line_speed = SPEED_20000;
5235 vars->link_status |= LINK_20GTFD;
5236 break;
5237 default:
5238 DP(NETIF_MSG_LINK,
5239 "link speed unsupported gp_status 0x%x\n",
5240 speed_mask);
5241 return -EINVAL;
5242 }
5243 } else { /* link_down */
5244 DP(NETIF_MSG_LINK, "phy link down\n");
5245
5246 vars->phy_link_up = 0;
5247
5248 vars->duplex = DUPLEX_FULL;
5249 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5250 vars->mac_type = MAC_TYPE_NONE;
5251 }
5252 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5253 vars->phy_link_up, vars->line_speed);
5254 return 0;
5255 }
5256
5257 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5258 struct link_params *params,
5259 struct link_vars *vars)
5260 {
5261
5262 struct bnx2x *bp = params->bp;
5263
5264 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5265 int rc = 0;
5266
5267 /* Read gp_status */
5268 CL22_RD_OVER_CL45(bp, phy,
5269 MDIO_REG_BANK_GP_STATUS,
5270 MDIO_GP_STATUS_TOP_AN_STATUS1,
5271 &gp_status);
5272 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5273 duplex = DUPLEX_FULL;
5274 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5275 link_up = 1;
5276 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5277 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5278 gp_status, link_up, speed_mask);
5279 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5280 duplex);
5281 if (rc == -EINVAL)
5282 return rc;
5283
5284 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5285 if (SINGLE_MEDIA_DIRECT(params)) {
5286 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5287 if (phy->req_line_speed == SPEED_AUTO_NEG)
5288 bnx2x_xgxs_an_resolve(phy, params, vars,
5289 gp_status);
5290 }
5291 } else { /* link_down */
5292 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5293 SINGLE_MEDIA_DIRECT(params)) {
5294 /* Check signal is detected */
5295 bnx2x_check_fallback_to_cl37(phy, params);
5296 }
5297 }
5298
5299 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5300 vars->duplex, vars->flow_ctrl, vars->link_status);
5301 return rc;
5302 }
5303
5304 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5305 struct link_params *params,
5306 struct link_vars *vars)
5307 {
5308
5309 struct bnx2x *bp = params->bp;
5310
5311 u8 lane;
5312 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5313 int rc = 0;
5314 lane = bnx2x_get_warpcore_lane(phy, params);
5315 /* Read gp_status */
5316 if (phy->req_line_speed > SPEED_10000) {
5317 u16 temp_link_up;
5318 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5319 1, &temp_link_up);
5320 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5321 1, &link_up);
5322 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5323 temp_link_up, link_up);
5324 link_up &= (1<<2);
5325 if (link_up)
5326 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5327 } else {
5328 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5329 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5330 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5331 /* Check for either KR or generic link up. */
5332 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5333 ((gp_status1 >> 12) & 0xf);
5334 link_up = gp_status1 & (1 << lane);
5335 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5336 u16 pd, gp_status4;
5337 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5338 /* Check Autoneg complete */
5339 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5340 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5341 &gp_status4);
5342 if (gp_status4 & ((1<<12)<<lane))
5343 vars->link_status |=
5344 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5345
5346 /* Check parallel detect used */
5347 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5348 MDIO_WC_REG_PAR_DET_10G_STATUS,
5349 &pd);
5350 if (pd & (1<<15))
5351 vars->link_status |=
5352 LINK_STATUS_PARALLEL_DETECTION_USED;
5353 }
5354 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5355 }
5356 }
5357
5358 if (lane < 2) {
5359 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5360 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5361 } else {
5362 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5363 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5364 }
5365 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5366
5367 if ((lane & 1) == 0)
5368 gp_speed <<= 8;
5369 gp_speed &= 0x3f00;
5370
5371
5372 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5373 duplex);
5374
5375 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5376 vars->duplex, vars->flow_ctrl, vars->link_status);
5377 return rc;
5378 }
5379 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5380 {
5381 struct bnx2x *bp = params->bp;
5382 struct bnx2x_phy *phy = &params->phy[INT_PHY];
5383 u16 lp_up2;
5384 u16 tx_driver;
5385 u16 bank;
5386
5387 /* read precomp */
5388 CL22_RD_OVER_CL45(bp, phy,
5389 MDIO_REG_BANK_OVER_1G,
5390 MDIO_OVER_1G_LP_UP2, &lp_up2);
5391
5392 /* bits [10:7] at lp_up2, positioned at [15:12] */
5393 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5394 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5395 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5396
5397 if (lp_up2 == 0)
5398 return;
5399
5400 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5401 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5402 CL22_RD_OVER_CL45(bp, phy,
5403 bank,
5404 MDIO_TX0_TX_DRIVER, &tx_driver);
5405
5406 /* replace tx_driver bits [15:12] */
5407 if (lp_up2 !=
5408 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5409 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5410 tx_driver |= lp_up2;
5411 CL22_WR_OVER_CL45(bp, phy,
5412 bank,
5413 MDIO_TX0_TX_DRIVER, tx_driver);
5414 }
5415 }
5416 }
5417
5418 static int bnx2x_emac_program(struct link_params *params,
5419 struct link_vars *vars)
5420 {
5421 struct bnx2x *bp = params->bp;
5422 u8 port = params->port;
5423 u16 mode = 0;
5424
5425 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5426 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5427 EMAC_REG_EMAC_MODE,
5428 (EMAC_MODE_25G_MODE |
5429 EMAC_MODE_PORT_MII_10M |
5430 EMAC_MODE_HALF_DUPLEX));
5431 switch (vars->line_speed) {
5432 case SPEED_10:
5433 mode |= EMAC_MODE_PORT_MII_10M;
5434 break;
5435
5436 case SPEED_100:
5437 mode |= EMAC_MODE_PORT_MII;
5438 break;
5439
5440 case SPEED_1000:
5441 mode |= EMAC_MODE_PORT_GMII;
5442 break;
5443
5444 case SPEED_2500:
5445 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5446 break;
5447
5448 default:
5449 /* 10G not valid for EMAC */
5450 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5451 vars->line_speed);
5452 return -EINVAL;
5453 }
5454
5455 if (vars->duplex == DUPLEX_HALF)
5456 mode |= EMAC_MODE_HALF_DUPLEX;
5457 bnx2x_bits_en(bp,
5458 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5459 mode);
5460
5461 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5462 return 0;
5463 }
5464
5465 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5466 struct link_params *params)
5467 {
5468
5469 u16 bank, i = 0;
5470 struct bnx2x *bp = params->bp;
5471
5472 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5473 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5474 CL22_WR_OVER_CL45(bp, phy,
5475 bank,
5476 MDIO_RX0_RX_EQ_BOOST,
5477 phy->rx_preemphasis[i]);
5478 }
5479
5480 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5481 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5482 CL22_WR_OVER_CL45(bp, phy,
5483 bank,
5484 MDIO_TX0_TX_DRIVER,
5485 phy->tx_preemphasis[i]);
5486 }
5487 }
5488
5489 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5490 struct link_params *params,
5491 struct link_vars *vars)
5492 {
5493 struct bnx2x *bp = params->bp;
5494 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5495 (params->loopback_mode == LOOPBACK_XGXS));
5496 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5497 if (SINGLE_MEDIA_DIRECT(params) &&
5498 (params->feature_config_flags &
5499 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5500 bnx2x_set_preemphasis(phy, params);
5501
5502 /* forced speed requested? */
5503 if (vars->line_speed != SPEED_AUTO_NEG ||
5504 (SINGLE_MEDIA_DIRECT(params) &&
5505 params->loopback_mode == LOOPBACK_EXT)) {
5506 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5507
5508 /* disable autoneg */
5509 bnx2x_set_autoneg(phy, params, vars, 0);
5510
5511 /* program speed and duplex */
5512 bnx2x_program_serdes(phy, params, vars);
5513
5514 } else { /* AN_mode */
5515 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5516
5517 /* AN enabled */
5518 bnx2x_set_brcm_cl37_advertisement(phy, params);
5519
5520 /* program duplex & pause advertisement (for aneg) */
5521 bnx2x_set_ieee_aneg_advertisement(phy, params,
5522 vars->ieee_fc);
5523
5524 /* enable autoneg */
5525 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5526
5527 /* enable and restart AN */
5528 bnx2x_restart_autoneg(phy, params, enable_cl73);
5529 }
5530
5531 } else { /* SGMII mode */
5532 DP(NETIF_MSG_LINK, "SGMII\n");
5533
5534 bnx2x_initialize_sgmii_process(phy, params, vars);
5535 }
5536 }
5537
5538 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5539 struct link_params *params,
5540 struct link_vars *vars)
5541 {
5542 int rc;
5543 vars->phy_flags |= PHY_XGXS_FLAG;
5544 if ((phy->req_line_speed &&
5545 ((phy->req_line_speed == SPEED_100) ||
5546 (phy->req_line_speed == SPEED_10))) ||
5547 (!phy->req_line_speed &&
5548 (phy->speed_cap_mask >=
5549 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5550 (phy->speed_cap_mask <
5551 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5552 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5553 vars->phy_flags |= PHY_SGMII_FLAG;
5554 else
5555 vars->phy_flags &= ~PHY_SGMII_FLAG;
5556
5557 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5558 bnx2x_set_aer_mmd(params, phy);
5559 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5560 bnx2x_set_master_ln(params, phy);
5561
5562 rc = bnx2x_reset_unicore(params, phy, 0);
5563 /* reset the SerDes and wait for reset bit return low */
5564 if (rc != 0)
5565 return rc;
5566
5567 bnx2x_set_aer_mmd(params, phy);
5568 /* setting the masterLn_def again after the reset */
5569 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5570 bnx2x_set_master_ln(params, phy);
5571 bnx2x_set_swap_lanes(params, phy);
5572 }
5573
5574 return rc;
5575 }
5576
5577 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5578 struct bnx2x_phy *phy,
5579 struct link_params *params)
5580 {
5581 u16 cnt, ctrl;
5582 /* Wait for soft reset to get cleared up to 1 sec */
5583 for (cnt = 0; cnt < 1000; cnt++) {
5584 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5585 bnx2x_cl22_read(bp, phy,
5586 MDIO_PMA_REG_CTRL, &ctrl);
5587 else
5588 bnx2x_cl45_read(bp, phy,
5589 MDIO_PMA_DEVAD,
5590 MDIO_PMA_REG_CTRL, &ctrl);
5591 if (!(ctrl & (1<<15)))
5592 break;
5593 msleep(1);
5594 }
5595
5596 if (cnt == 1000)
5597 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5598 " Port %d\n",
5599 params->port);
5600 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5601 return cnt;
5602 }
5603
5604 static void bnx2x_link_int_enable(struct link_params *params)
5605 {
5606 u8 port = params->port;
5607 u32 mask;
5608 struct bnx2x *bp = params->bp;
5609
5610 /* Setting the status to report on link up for either XGXS or SerDes */
5611 if (CHIP_IS_E3(bp)) {
5612 mask = NIG_MASK_XGXS0_LINK_STATUS;
5613 if (!(SINGLE_MEDIA_DIRECT(params)))
5614 mask |= NIG_MASK_MI_INT;
5615 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5616 mask = (NIG_MASK_XGXS0_LINK10G |
5617 NIG_MASK_XGXS0_LINK_STATUS);
5618 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5619 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5620 params->phy[INT_PHY].type !=
5621 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5622 mask |= NIG_MASK_MI_INT;
5623 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5624 }
5625
5626 } else { /* SerDes */
5627 mask = NIG_MASK_SERDES0_LINK_STATUS;
5628 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5629 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5630 params->phy[INT_PHY].type !=
5631 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5632 mask |= NIG_MASK_MI_INT;
5633 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5634 }
5635 }
5636 bnx2x_bits_en(bp,
5637 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5638 mask);
5639
5640 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5641 (params->switch_cfg == SWITCH_CFG_10G),
5642 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5643 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5644 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5645 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5646 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5647 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5648 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5649 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5650 }
5651
5652 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5653 u8 exp_mi_int)
5654 {
5655 u32 latch_status = 0;
5656
5657 /*
5658 * Disable the MI INT ( external phy int ) by writing 1 to the
5659 * status register. Link down indication is high-active-signal,
5660 * so in this case we need to write the status to clear the XOR
5661 */
5662 /* Read Latched signals */
5663 latch_status = REG_RD(bp,
5664 NIG_REG_LATCH_STATUS_0 + port*8);
5665 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5666 /* Handle only those with latched-signal=up.*/
5667 if (exp_mi_int)
5668 bnx2x_bits_en(bp,
5669 NIG_REG_STATUS_INTERRUPT_PORT0
5670 + port*4,
5671 NIG_STATUS_EMAC0_MI_INT);
5672 else
5673 bnx2x_bits_dis(bp,
5674 NIG_REG_STATUS_INTERRUPT_PORT0
5675 + port*4,
5676 NIG_STATUS_EMAC0_MI_INT);
5677
5678 if (latch_status & 1) {
5679
5680 /* For all latched-signal=up : Re-Arm Latch signals */
5681 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5682 (latch_status & 0xfffe) | (latch_status & 1));
5683 }
5684 /* For all latched-signal=up,Write original_signal to status */
5685 }
5686
5687 static void bnx2x_link_int_ack(struct link_params *params,
5688 struct link_vars *vars, u8 is_10g_plus)
5689 {
5690 struct bnx2x *bp = params->bp;
5691 u8 port = params->port;
5692 u32 mask;
5693 /*
5694 * First reset all status we assume only one line will be
5695 * change at a time
5696 */
5697 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5698 (NIG_STATUS_XGXS0_LINK10G |
5699 NIG_STATUS_XGXS0_LINK_STATUS |
5700 NIG_STATUS_SERDES0_LINK_STATUS));
5701 if (vars->phy_link_up) {
5702 if (USES_WARPCORE(bp))
5703 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5704 else {
5705 if (is_10g_plus)
5706 mask = NIG_STATUS_XGXS0_LINK10G;
5707 else if (params->switch_cfg == SWITCH_CFG_10G) {
5708 /*
5709 * Disable the link interrupt by writing 1 to
5710 * the relevant lane in the status register
5711 */
5712 u32 ser_lane =
5713 ((params->lane_config &
5714 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5715 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5716 mask = ((1 << ser_lane) <<
5717 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5718 } else
5719 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5720 }
5721 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5722 mask);
5723 bnx2x_bits_en(bp,
5724 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5725 mask);
5726 }
5727 }
5728
5729 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5730 {
5731 u8 *str_ptr = str;
5732 u32 mask = 0xf0000000;
5733 u8 shift = 8*4;
5734 u8 digit;
5735 u8 remove_leading_zeros = 1;
5736 if (*len < 10) {
5737 /* Need more than 10chars for this format */
5738 *str_ptr = '\0';
5739 (*len)--;
5740 return -EINVAL;
5741 }
5742 while (shift > 0) {
5743
5744 shift -= 4;
5745 digit = ((num & mask) >> shift);
5746 if (digit == 0 && remove_leading_zeros) {
5747 mask = mask >> 4;
5748 continue;
5749 } else if (digit < 0xa)
5750 *str_ptr = digit + '0';
5751 else
5752 *str_ptr = digit - 0xa + 'a';
5753 remove_leading_zeros = 0;
5754 str_ptr++;
5755 (*len)--;
5756 mask = mask >> 4;
5757 if (shift == 4*4) {
5758 *str_ptr = '.';
5759 str_ptr++;
5760 (*len)--;
5761 remove_leading_zeros = 1;
5762 }
5763 }
5764 return 0;
5765 }
5766
5767
5768 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5769 {
5770 str[0] = '\0';
5771 (*len)--;
5772 return 0;
5773 }
5774
5775 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5776 u8 *version, u16 len)
5777 {
5778 struct bnx2x *bp;
5779 u32 spirom_ver = 0;
5780 int status = 0;
5781 u8 *ver_p = version;
5782 u16 remain_len = len;
5783 if (version == NULL || params == NULL)
5784 return -EINVAL;
5785 bp = params->bp;
5786
5787 /* Extract first external phy*/
5788 version[0] = '\0';
5789 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5790
5791 if (params->phy[EXT_PHY1].format_fw_ver) {
5792 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5793 ver_p,
5794 &remain_len);
5795 ver_p += (len - remain_len);
5796 }
5797 if ((params->num_phys == MAX_PHYS) &&
5798 (params->phy[EXT_PHY2].ver_addr != 0)) {
5799 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5800 if (params->phy[EXT_PHY2].format_fw_ver) {
5801 *ver_p = '/';
5802 ver_p++;
5803 remain_len--;
5804 status |= params->phy[EXT_PHY2].format_fw_ver(
5805 spirom_ver,
5806 ver_p,
5807 &remain_len);
5808 ver_p = version + (len - remain_len);
5809 }
5810 }
5811 *ver_p = '\0';
5812 return status;
5813 }
5814
5815 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5816 struct link_params *params)
5817 {
5818 u8 port = params->port;
5819 struct bnx2x *bp = params->bp;
5820
5821 if (phy->req_line_speed != SPEED_1000) {
5822 u32 md_devad = 0;
5823
5824 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5825
5826 if (!CHIP_IS_E3(bp)) {
5827 /* change the uni_phy_addr in the nig */
5828 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5829 port*0x18));
5830
5831 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5832 0x5);
5833 }
5834
5835 bnx2x_cl45_write(bp, phy,
5836 5,
5837 (MDIO_REG_BANK_AER_BLOCK +
5838 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5839 0x2800);
5840
5841 bnx2x_cl45_write(bp, phy,
5842 5,
5843 (MDIO_REG_BANK_CL73_IEEEB0 +
5844 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5845 0x6041);
5846 msleep(200);
5847 /* set aer mmd back */
5848 bnx2x_set_aer_mmd(params, phy);
5849
5850 if (!CHIP_IS_E3(bp)) {
5851 /* and md_devad */
5852 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5853 md_devad);
5854 }
5855 } else {
5856 u16 mii_ctrl;
5857 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5858 bnx2x_cl45_read(bp, phy, 5,
5859 (MDIO_REG_BANK_COMBO_IEEE0 +
5860 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5861 &mii_ctrl);
5862 bnx2x_cl45_write(bp, phy, 5,
5863 (MDIO_REG_BANK_COMBO_IEEE0 +
5864 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5865 mii_ctrl |
5866 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5867 }
5868 }
5869
5870 int bnx2x_set_led(struct link_params *params,
5871 struct link_vars *vars, u8 mode, u32 speed)
5872 {
5873 u8 port = params->port;
5874 u16 hw_led_mode = params->hw_led_mode;
5875 int rc = 0;
5876 u8 phy_idx;
5877 u32 tmp;
5878 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5879 struct bnx2x *bp = params->bp;
5880 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5881 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5882 speed, hw_led_mode);
5883 /* In case */
5884 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5885 if (params->phy[phy_idx].set_link_led) {
5886 params->phy[phy_idx].set_link_led(
5887 &params->phy[phy_idx], params, mode);
5888 }
5889 }
5890
5891 switch (mode) {
5892 case LED_MODE_FRONT_PANEL_OFF:
5893 case LED_MODE_OFF:
5894 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5895 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5896 SHARED_HW_CFG_LED_MAC1);
5897
5898 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5899 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5900 break;
5901
5902 case LED_MODE_OPER:
5903 /*
5904 * For all other phys, OPER mode is same as ON, so in case
5905 * link is down, do nothing
5906 */
5907 if (!vars->link_up)
5908 break;
5909 case LED_MODE_ON:
5910 if (((params->phy[EXT_PHY1].type ==
5911 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5912 (params->phy[EXT_PHY1].type ==
5913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5914 CHIP_IS_E2(bp) && params->num_phys == 2) {
5915 /*
5916 * This is a work-around for E2+8727 Configurations
5917 */
5918 if (mode == LED_MODE_ON ||
5919 speed == SPEED_10000){
5920 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5921 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5922
5923 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5924 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5925 (tmp | EMAC_LED_OVERRIDE));
5926 /*
5927 * return here without enabling traffic
5928 * LED blink andsetting rate in ON mode.
5929 * In oper mode, enabling LED blink
5930 * and setting rate is needed.
5931 */
5932 if (mode == LED_MODE_ON)
5933 return rc;
5934 }
5935 } else if (SINGLE_MEDIA_DIRECT(params)) {
5936 /*
5937 * This is a work-around for HW issue found when link
5938 * is up in CL73
5939 */
5940 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5941 if (CHIP_IS_E1x(bp) ||
5942 CHIP_IS_E2(bp) ||
5943 (mode == LED_MODE_ON))
5944 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5945 else
5946 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5947 hw_led_mode);
5948 } else
5949 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5950
5951 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5952 /* Set blinking rate to ~15.9Hz */
5953 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5954 LED_BLINK_RATE_VAL);
5955 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5956 port*4, 1);
5957 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5958 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5959
5960 if (CHIP_IS_E1(bp) &&
5961 ((speed == SPEED_2500) ||
5962 (speed == SPEED_1000) ||
5963 (speed == SPEED_100) ||
5964 (speed == SPEED_10))) {
5965 /*
5966 * On Everest 1 Ax chip versions for speeds less than
5967 * 10G LED scheme is different
5968 */
5969 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5970 + port*4, 1);
5971 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5972 port*4, 0);
5973 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5974 port*4, 1);
5975 }
5976 break;
5977
5978 default:
5979 rc = -EINVAL;
5980 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5981 mode);
5982 break;
5983 }
5984 return rc;
5985
5986 }
5987
5988 /*
5989 * This function comes to reflect the actual link state read DIRECTLY from the
5990 * HW
5991 */
5992 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5993 u8 is_serdes)
5994 {
5995 struct bnx2x *bp = params->bp;
5996 u16 gp_status = 0, phy_index = 0;
5997 u8 ext_phy_link_up = 0, serdes_phy_type;
5998 struct link_vars temp_vars;
5999 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6000
6001 if (CHIP_IS_E3(bp)) {
6002 u16 link_up;
6003 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6004 > SPEED_10000) {
6005 /* Check 20G link */
6006 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6007 1, &link_up);
6008 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6009 1, &link_up);
6010 link_up &= (1<<2);
6011 } else {
6012 /* Check 10G link and below*/
6013 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6014 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6015 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6016 &gp_status);
6017 gp_status = ((gp_status >> 8) & 0xf) |
6018 ((gp_status >> 12) & 0xf);
6019 link_up = gp_status & (1 << lane);
6020 }
6021 if (!link_up)
6022 return -ESRCH;
6023 } else {
6024 CL22_RD_OVER_CL45(bp, int_phy,
6025 MDIO_REG_BANK_GP_STATUS,
6026 MDIO_GP_STATUS_TOP_AN_STATUS1,
6027 &gp_status);
6028 /* link is up only if both local phy and external phy are up */
6029 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6030 return -ESRCH;
6031 }
6032 /* In XGXS loopback mode, do not check external PHY */
6033 if (params->loopback_mode == LOOPBACK_XGXS)
6034 return 0;
6035
6036 switch (params->num_phys) {
6037 case 1:
6038 /* No external PHY */
6039 return 0;
6040 case 2:
6041 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6042 &params->phy[EXT_PHY1],
6043 params, &temp_vars);
6044 break;
6045 case 3: /* Dual Media */
6046 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6047 phy_index++) {
6048 serdes_phy_type = ((params->phy[phy_index].media_type ==
6049 ETH_PHY_SFP_FIBER) ||
6050 (params->phy[phy_index].media_type ==
6051 ETH_PHY_XFP_FIBER) ||
6052 (params->phy[phy_index].media_type ==
6053 ETH_PHY_DA_TWINAX));
6054
6055 if (is_serdes != serdes_phy_type)
6056 continue;
6057 if (params->phy[phy_index].read_status) {
6058 ext_phy_link_up |=
6059 params->phy[phy_index].read_status(
6060 &params->phy[phy_index],
6061 params, &temp_vars);
6062 }
6063 }
6064 break;
6065 }
6066 if (ext_phy_link_up)
6067 return 0;
6068 return -ESRCH;
6069 }
6070
6071 static int bnx2x_link_initialize(struct link_params *params,
6072 struct link_vars *vars)
6073 {
6074 int rc = 0;
6075 u8 phy_index, non_ext_phy;
6076 struct bnx2x *bp = params->bp;
6077 /*
6078 * In case of external phy existence, the line speed would be the
6079 * line speed linked up by the external phy. In case it is direct
6080 * only, then the line_speed during initialization will be
6081 * equal to the req_line_speed
6082 */
6083 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6084
6085 /*
6086 * Initialize the internal phy in case this is a direct board
6087 * (no external phys), or this board has external phy which requires
6088 * to first.
6089 */
6090 if (!USES_WARPCORE(bp))
6091 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6092 /* init ext phy and enable link state int */
6093 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6094 (params->loopback_mode == LOOPBACK_XGXS));
6095
6096 if (non_ext_phy ||
6097 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6098 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6099 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6100 if (vars->line_speed == SPEED_AUTO_NEG &&
6101 (CHIP_IS_E1x(bp) ||
6102 CHIP_IS_E2(bp)))
6103 bnx2x_set_parallel_detection(phy, params);
6104 if (params->phy[INT_PHY].config_init)
6105 params->phy[INT_PHY].config_init(phy,
6106 params,
6107 vars);
6108 }
6109
6110 /* Init external phy*/
6111 if (non_ext_phy) {
6112 if (params->phy[INT_PHY].supported &
6113 SUPPORTED_FIBRE)
6114 vars->link_status |= LINK_STATUS_SERDES_LINK;
6115 } else {
6116 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6117 phy_index++) {
6118 /*
6119 * No need to initialize second phy in case of first
6120 * phy only selection. In case of second phy, we do
6121 * need to initialize the first phy, since they are
6122 * connected.
6123 */
6124 if (params->phy[phy_index].supported &
6125 SUPPORTED_FIBRE)
6126 vars->link_status |= LINK_STATUS_SERDES_LINK;
6127
6128 if (phy_index == EXT_PHY2 &&
6129 (bnx2x_phy_selection(params) ==
6130 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6131 DP(NETIF_MSG_LINK,
6132 "Not initializing second phy\n");
6133 continue;
6134 }
6135 params->phy[phy_index].config_init(
6136 &params->phy[phy_index],
6137 params, vars);
6138 }
6139 }
6140 /* Reset the interrupt indication after phy was initialized */
6141 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6142 params->port*4,
6143 (NIG_STATUS_XGXS0_LINK10G |
6144 NIG_STATUS_XGXS0_LINK_STATUS |
6145 NIG_STATUS_SERDES0_LINK_STATUS |
6146 NIG_MASK_MI_INT));
6147 bnx2x_update_mng(params, vars->link_status);
6148 return rc;
6149 }
6150
6151 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6152 struct link_params *params)
6153 {
6154 /* reset the SerDes/XGXS */
6155 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6156 (0x1ff << (params->port*16)));
6157 }
6158
6159 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6160 struct link_params *params)
6161 {
6162 struct bnx2x *bp = params->bp;
6163 u8 gpio_port;
6164 /* HW reset */
6165 if (CHIP_IS_E2(bp))
6166 gpio_port = BP_PATH(bp);
6167 else
6168 gpio_port = params->port;
6169 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6170 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6171 gpio_port);
6172 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6173 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6174 gpio_port);
6175 DP(NETIF_MSG_LINK, "reset external PHY\n");
6176 }
6177
6178 static int bnx2x_update_link_down(struct link_params *params,
6179 struct link_vars *vars)
6180 {
6181 struct bnx2x *bp = params->bp;
6182 u8 port = params->port;
6183
6184 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6185 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6186 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6187 /* indicate no mac active */
6188 vars->mac_type = MAC_TYPE_NONE;
6189
6190 /* update shared memory */
6191 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6192 LINK_STATUS_LINK_UP |
6193 LINK_STATUS_PHYSICAL_LINK_FLAG |
6194 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6195 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6196 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6197 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6198 vars->line_speed = 0;
6199 bnx2x_update_mng(params, vars->link_status);
6200
6201 /* activate nig drain */
6202 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6203
6204 /* disable emac */
6205 if (!CHIP_IS_E3(bp))
6206 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6207
6208 msleep(10);
6209 /* reset BigMac/Xmac */
6210 if (CHIP_IS_E1x(bp) ||
6211 CHIP_IS_E2(bp)) {
6212 bnx2x_bmac_rx_disable(bp, params->port);
6213 REG_WR(bp, GRCBASE_MISC +
6214 MISC_REGISTERS_RESET_REG_2_CLEAR,
6215 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6216 }
6217 if (CHIP_IS_E3(bp))
6218 bnx2x_xmac_disable(params);
6219
6220 return 0;
6221 }
6222
6223 static int bnx2x_update_link_up(struct link_params *params,
6224 struct link_vars *vars,
6225 u8 link_10g)
6226 {
6227 struct bnx2x *bp = params->bp;
6228 u8 port = params->port;
6229 int rc = 0;
6230
6231 vars->link_status |= (LINK_STATUS_LINK_UP |
6232 LINK_STATUS_PHYSICAL_LINK_FLAG);
6233 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6234
6235 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6236 vars->link_status |=
6237 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6238
6239 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6240 vars->link_status |=
6241 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6242 if (USES_WARPCORE(bp)) {
6243 if (link_10g) {
6244 if (bnx2x_xmac_enable(params, vars, 0) ==
6245 -ESRCH) {
6246 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6247 vars->link_up = 0;
6248 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6249 vars->link_status &= ~LINK_STATUS_LINK_UP;
6250 }
6251 } else
6252 bnx2x_umac_enable(params, vars, 0);
6253 bnx2x_set_led(params, vars,
6254 LED_MODE_OPER, vars->line_speed);
6255 }
6256 if ((CHIP_IS_E1x(bp) ||
6257 CHIP_IS_E2(bp))) {
6258 if (link_10g) {
6259 if (bnx2x_bmac_enable(params, vars, 0) ==
6260 -ESRCH) {
6261 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6262 vars->link_up = 0;
6263 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6264 vars->link_status &= ~LINK_STATUS_LINK_UP;
6265 }
6266
6267 bnx2x_set_led(params, vars,
6268 LED_MODE_OPER, SPEED_10000);
6269 } else {
6270 rc = bnx2x_emac_program(params, vars);
6271 bnx2x_emac_enable(params, vars, 0);
6272
6273 /* AN complete? */
6274 if ((vars->link_status &
6275 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6276 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6277 SINGLE_MEDIA_DIRECT(params))
6278 bnx2x_set_gmii_tx_driver(params);
6279 }
6280 }
6281
6282 /* PBF - link up */
6283 if (CHIP_IS_E1x(bp))
6284 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6285 vars->line_speed);
6286
6287 /* disable drain */
6288 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6289
6290 /* update shared memory */
6291 bnx2x_update_mng(params, vars->link_status);
6292 msleep(20);
6293 return rc;
6294 }
6295 /*
6296 * The bnx2x_link_update function should be called upon link
6297 * interrupt.
6298 * Link is considered up as follows:
6299 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6300 * to be up
6301 * - SINGLE_MEDIA - The link between the 577xx and the external
6302 * phy (XGXS) need to up as well as the external link of the
6303 * phy (PHY_EXT1)
6304 * - DUAL_MEDIA - The link between the 577xx and the first
6305 * external phy needs to be up, and at least one of the 2
6306 * external phy link must be up.
6307 */
6308 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6309 {
6310 struct bnx2x *bp = params->bp;
6311 struct link_vars phy_vars[MAX_PHYS];
6312 u8 port = params->port;
6313 u8 link_10g_plus, phy_index;
6314 u8 ext_phy_link_up = 0, cur_link_up;
6315 int rc = 0;
6316 u8 is_mi_int = 0;
6317 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6318 u8 active_external_phy = INT_PHY;
6319 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6320 for (phy_index = INT_PHY; phy_index < params->num_phys;
6321 phy_index++) {
6322 phy_vars[phy_index].flow_ctrl = 0;
6323 phy_vars[phy_index].link_status = 0;
6324 phy_vars[phy_index].line_speed = 0;
6325 phy_vars[phy_index].duplex = DUPLEX_FULL;
6326 phy_vars[phy_index].phy_link_up = 0;
6327 phy_vars[phy_index].link_up = 0;
6328 phy_vars[phy_index].fault_detected = 0;
6329 }
6330
6331 if (USES_WARPCORE(bp))
6332 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6333
6334 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6335 port, (vars->phy_flags & PHY_XGXS_FLAG),
6336 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6337
6338 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6339 port*0x18) > 0);
6340 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6341 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6342 is_mi_int,
6343 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6344
6345 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6346 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6347 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6348
6349 /* disable emac */
6350 if (!CHIP_IS_E3(bp))
6351 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6352
6353 /*
6354 * Step 1:
6355 * Check external link change only for external phys, and apply
6356 * priority selection between them in case the link on both phys
6357 * is up. Note that instead of the common vars, a temporary
6358 * vars argument is used since each phy may have different link/
6359 * speed/duplex result
6360 */
6361 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6362 phy_index++) {
6363 struct bnx2x_phy *phy = &params->phy[phy_index];
6364 if (!phy->read_status)
6365 continue;
6366 /* Read link status and params of this ext phy */
6367 cur_link_up = phy->read_status(phy, params,
6368 &phy_vars[phy_index]);
6369 if (cur_link_up) {
6370 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6371 phy_index);
6372 } else {
6373 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6374 phy_index);
6375 continue;
6376 }
6377
6378 if (!ext_phy_link_up) {
6379 ext_phy_link_up = 1;
6380 active_external_phy = phy_index;
6381 } else {
6382 switch (bnx2x_phy_selection(params)) {
6383 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6384 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6385 /*
6386 * In this option, the first PHY makes sure to pass the
6387 * traffic through itself only.
6388 * Its not clear how to reset the link on the second phy
6389 */
6390 active_external_phy = EXT_PHY1;
6391 break;
6392 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6393 /*
6394 * In this option, the first PHY makes sure to pass the
6395 * traffic through the second PHY.
6396 */
6397 active_external_phy = EXT_PHY2;
6398 break;
6399 default:
6400 /*
6401 * Link indication on both PHYs with the following cases
6402 * is invalid:
6403 * - FIRST_PHY means that second phy wasn't initialized,
6404 * hence its link is expected to be down
6405 * - SECOND_PHY means that first phy should not be able
6406 * to link up by itself (using configuration)
6407 * - DEFAULT should be overriden during initialiazation
6408 */
6409 DP(NETIF_MSG_LINK, "Invalid link indication"
6410 "mpc=0x%x. DISABLING LINK !!!\n",
6411 params->multi_phy_config);
6412 ext_phy_link_up = 0;
6413 break;
6414 }
6415 }
6416 }
6417 prev_line_speed = vars->line_speed;
6418 /*
6419 * Step 2:
6420 * Read the status of the internal phy. In case of
6421 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6422 * otherwise this is the link between the 577xx and the first
6423 * external phy
6424 */
6425 if (params->phy[INT_PHY].read_status)
6426 params->phy[INT_PHY].read_status(
6427 &params->phy[INT_PHY],
6428 params, vars);
6429 /*
6430 * The INT_PHY flow control reside in the vars. This include the
6431 * case where the speed or flow control are not set to AUTO.
6432 * Otherwise, the active external phy flow control result is set
6433 * to the vars. The ext_phy_line_speed is needed to check if the
6434 * speed is different between the internal phy and external phy.
6435 * This case may be result of intermediate link speed change.
6436 */
6437 if (active_external_phy > INT_PHY) {
6438 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6439 /*
6440 * Link speed is taken from the XGXS. AN and FC result from
6441 * the external phy.
6442 */
6443 vars->link_status |= phy_vars[active_external_phy].link_status;
6444
6445 /*
6446 * if active_external_phy is first PHY and link is up - disable
6447 * disable TX on second external PHY
6448 */
6449 if (active_external_phy == EXT_PHY1) {
6450 if (params->phy[EXT_PHY2].phy_specific_func) {
6451 DP(NETIF_MSG_LINK,
6452 "Disabling TX on EXT_PHY2\n");
6453 params->phy[EXT_PHY2].phy_specific_func(
6454 &params->phy[EXT_PHY2],
6455 params, DISABLE_TX);
6456 }
6457 }
6458
6459 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6460 vars->duplex = phy_vars[active_external_phy].duplex;
6461 if (params->phy[active_external_phy].supported &
6462 SUPPORTED_FIBRE)
6463 vars->link_status |= LINK_STATUS_SERDES_LINK;
6464 else
6465 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6466 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6467 active_external_phy);
6468 }
6469
6470 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6471 phy_index++) {
6472 if (params->phy[phy_index].flags &
6473 FLAGS_REARM_LATCH_SIGNAL) {
6474 bnx2x_rearm_latch_signal(bp, port,
6475 phy_index ==
6476 active_external_phy);
6477 break;
6478 }
6479 }
6480 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6481 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6482 vars->link_status, ext_phy_line_speed);
6483 /*
6484 * Upon link speed change set the NIG into drain mode. Comes to
6485 * deals with possible FIFO glitch due to clk change when speed
6486 * is decreased without link down indicator
6487 */
6488
6489 if (vars->phy_link_up) {
6490 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6491 (ext_phy_line_speed != vars->line_speed)) {
6492 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6493 " different than the external"
6494 " link speed %d\n", vars->line_speed,
6495 ext_phy_line_speed);
6496 vars->phy_link_up = 0;
6497 } else if (prev_line_speed != vars->line_speed) {
6498 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6499 0);
6500 msleep(1);
6501 }
6502 }
6503
6504 /* anything 10 and over uses the bmac */
6505 link_10g_plus = (vars->line_speed >= SPEED_10000);
6506
6507 bnx2x_link_int_ack(params, vars, link_10g_plus);
6508
6509 /*
6510 * In case external phy link is up, and internal link is down
6511 * (not initialized yet probably after link initialization, it
6512 * needs to be initialized.
6513 * Note that after link down-up as result of cable plug, the xgxs
6514 * link would probably become up again without the need
6515 * initialize it
6516 */
6517 if (!(SINGLE_MEDIA_DIRECT(params))) {
6518 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6519 " init_preceding = %d\n", ext_phy_link_up,
6520 vars->phy_link_up,
6521 params->phy[EXT_PHY1].flags &
6522 FLAGS_INIT_XGXS_FIRST);
6523 if (!(params->phy[EXT_PHY1].flags &
6524 FLAGS_INIT_XGXS_FIRST)
6525 && ext_phy_link_up && !vars->phy_link_up) {
6526 vars->line_speed = ext_phy_line_speed;
6527 if (vars->line_speed < SPEED_1000)
6528 vars->phy_flags |= PHY_SGMII_FLAG;
6529 else
6530 vars->phy_flags &= ~PHY_SGMII_FLAG;
6531
6532 if (params->phy[INT_PHY].config_init)
6533 params->phy[INT_PHY].config_init(
6534 &params->phy[INT_PHY], params,
6535 vars);
6536 }
6537 }
6538 /*
6539 * Link is up only if both local phy and external phy (in case of
6540 * non-direct board) are up and no fault detected on active PHY.
6541 */
6542 vars->link_up = (vars->phy_link_up &&
6543 (ext_phy_link_up ||
6544 SINGLE_MEDIA_DIRECT(params)) &&
6545 (phy_vars[active_external_phy].fault_detected == 0));
6546
6547 if (vars->link_up)
6548 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6549 else
6550 rc = bnx2x_update_link_down(params, vars);
6551
6552 return rc;
6553 }
6554
6555
6556 /*****************************************************************************/
6557 /* External Phy section */
6558 /*****************************************************************************/
6559 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6560 {
6561 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6562 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6563 msleep(1);
6564 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6565 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6566 }
6567
6568 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6569 u32 spirom_ver, u32 ver_addr)
6570 {
6571 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6572 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6573
6574 if (ver_addr)
6575 REG_WR(bp, ver_addr, spirom_ver);
6576 }
6577
6578 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6579 struct bnx2x_phy *phy,
6580 u8 port)
6581 {
6582 u16 fw_ver1, fw_ver2;
6583
6584 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6585 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6586 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6587 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6588 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6589 phy->ver_addr);
6590 }
6591
6592 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6593 struct bnx2x_phy *phy,
6594 struct link_vars *vars)
6595 {
6596 u16 val;
6597 bnx2x_cl45_read(bp, phy,
6598 MDIO_AN_DEVAD,
6599 MDIO_AN_REG_STATUS, &val);
6600 bnx2x_cl45_read(bp, phy,
6601 MDIO_AN_DEVAD,
6602 MDIO_AN_REG_STATUS, &val);
6603 if (val & (1<<5))
6604 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6605 if ((val & (1<<0)) == 0)
6606 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6607 }
6608
6609 /******************************************************************/
6610 /* common BCM8073/BCM8727 PHY SECTION */
6611 /******************************************************************/
6612 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6613 struct link_params *params,
6614 struct link_vars *vars)
6615 {
6616 struct bnx2x *bp = params->bp;
6617 if (phy->req_line_speed == SPEED_10 ||
6618 phy->req_line_speed == SPEED_100) {
6619 vars->flow_ctrl = phy->req_flow_ctrl;
6620 return;
6621 }
6622
6623 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6624 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6625 u16 pause_result;
6626 u16 ld_pause; /* local */
6627 u16 lp_pause; /* link partner */
6628 bnx2x_cl45_read(bp, phy,
6629 MDIO_AN_DEVAD,
6630 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6631
6632 bnx2x_cl45_read(bp, phy,
6633 MDIO_AN_DEVAD,
6634 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6635 pause_result = (ld_pause &
6636 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6637 pause_result |= (lp_pause &
6638 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6639
6640 bnx2x_pause_resolve(vars, pause_result);
6641 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6642 pause_result);
6643 }
6644 }
6645 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6646 struct bnx2x_phy *phy,
6647 u8 port)
6648 {
6649 u32 count = 0;
6650 u16 fw_ver1, fw_msgout;
6651 int rc = 0;
6652
6653 /* Boot port from external ROM */
6654 /* EDC grst */
6655 bnx2x_cl45_write(bp, phy,
6656 MDIO_PMA_DEVAD,
6657 MDIO_PMA_REG_GEN_CTRL,
6658 0x0001);
6659
6660 /* ucode reboot and rst */
6661 bnx2x_cl45_write(bp, phy,
6662 MDIO_PMA_DEVAD,
6663 MDIO_PMA_REG_GEN_CTRL,
6664 0x008c);
6665
6666 bnx2x_cl45_write(bp, phy,
6667 MDIO_PMA_DEVAD,
6668 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6669
6670 /* Reset internal microprocessor */
6671 bnx2x_cl45_write(bp, phy,
6672 MDIO_PMA_DEVAD,
6673 MDIO_PMA_REG_GEN_CTRL,
6674 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6675
6676 /* Release srst bit */
6677 bnx2x_cl45_write(bp, phy,
6678 MDIO_PMA_DEVAD,
6679 MDIO_PMA_REG_GEN_CTRL,
6680 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6681
6682 /* Delay 100ms per the PHY specifications */
6683 msleep(100);
6684
6685 /* 8073 sometimes taking longer to download */
6686 do {
6687 count++;
6688 if (count > 300) {
6689 DP(NETIF_MSG_LINK,
6690 "bnx2x_8073_8727_external_rom_boot port %x:"
6691 "Download failed. fw version = 0x%x\n",
6692 port, fw_ver1);
6693 rc = -EINVAL;
6694 break;
6695 }
6696
6697 bnx2x_cl45_read(bp, phy,
6698 MDIO_PMA_DEVAD,
6699 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6700 bnx2x_cl45_read(bp, phy,
6701 MDIO_PMA_DEVAD,
6702 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6703
6704 msleep(1);
6705 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6706 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6707 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6708
6709 /* Clear ser_boot_ctl bit */
6710 bnx2x_cl45_write(bp, phy,
6711 MDIO_PMA_DEVAD,
6712 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6713 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6714
6715 DP(NETIF_MSG_LINK,
6716 "bnx2x_8073_8727_external_rom_boot port %x:"
6717 "Download complete. fw version = 0x%x\n",
6718 port, fw_ver1);
6719
6720 return rc;
6721 }
6722
6723 /******************************************************************/
6724 /* BCM8073 PHY SECTION */
6725 /******************************************************************/
6726 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6727 {
6728 /* This is only required for 8073A1, version 102 only */
6729 u16 val;
6730
6731 /* Read 8073 HW revision*/
6732 bnx2x_cl45_read(bp, phy,
6733 MDIO_PMA_DEVAD,
6734 MDIO_PMA_REG_8073_CHIP_REV, &val);
6735
6736 if (val != 1) {
6737 /* No need to workaround in 8073 A1 */
6738 return 0;
6739 }
6740
6741 bnx2x_cl45_read(bp, phy,
6742 MDIO_PMA_DEVAD,
6743 MDIO_PMA_REG_ROM_VER2, &val);
6744
6745 /* SNR should be applied only for version 0x102 */
6746 if (val != 0x102)
6747 return 0;
6748
6749 return 1;
6750 }
6751
6752 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6753 {
6754 u16 val, cnt, cnt1 ;
6755
6756 bnx2x_cl45_read(bp, phy,
6757 MDIO_PMA_DEVAD,
6758 MDIO_PMA_REG_8073_CHIP_REV, &val);
6759
6760 if (val > 0) {
6761 /* No need to workaround in 8073 A1 */
6762 return 0;
6763 }
6764 /* XAUI workaround in 8073 A0: */
6765
6766 /*
6767 * After loading the boot ROM and restarting Autoneg, poll
6768 * Dev1, Reg $C820:
6769 */
6770
6771 for (cnt = 0; cnt < 1000; cnt++) {
6772 bnx2x_cl45_read(bp, phy,
6773 MDIO_PMA_DEVAD,
6774 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6775 &val);
6776 /*
6777 * If bit [14] = 0 or bit [13] = 0, continue on with
6778 * system initialization (XAUI work-around not required, as
6779 * these bits indicate 2.5G or 1G link up).
6780 */
6781 if (!(val & (1<<14)) || !(val & (1<<13))) {
6782 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6783 return 0;
6784 } else if (!(val & (1<<15))) {
6785 DP(NETIF_MSG_LINK, "bit 15 went off\n");
6786 /*
6787 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6788 * MSB (bit15) goes to 1 (indicating that the XAUI
6789 * workaround has completed), then continue on with
6790 * system initialization.
6791 */
6792 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6793 bnx2x_cl45_read(bp, phy,
6794 MDIO_PMA_DEVAD,
6795 MDIO_PMA_REG_8073_XAUI_WA, &val);
6796 if (val & (1<<15)) {
6797 DP(NETIF_MSG_LINK,
6798 "XAUI workaround has completed\n");
6799 return 0;
6800 }
6801 msleep(3);
6802 }
6803 break;
6804 }
6805 msleep(3);
6806 }
6807 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6808 return -EINVAL;
6809 }
6810
6811 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6812 {
6813 /* Force KR or KX */
6814 bnx2x_cl45_write(bp, phy,
6815 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6816 bnx2x_cl45_write(bp, phy,
6817 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6818 bnx2x_cl45_write(bp, phy,
6819 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6820 bnx2x_cl45_write(bp, phy,
6821 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6822 }
6823
6824 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6825 struct bnx2x_phy *phy,
6826 struct link_vars *vars)
6827 {
6828 u16 cl37_val;
6829 struct bnx2x *bp = params->bp;
6830 bnx2x_cl45_read(bp, phy,
6831 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6832
6833 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6834 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6835 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6836 if ((vars->ieee_fc &
6837 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6838 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6839 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6840 }
6841 if ((vars->ieee_fc &
6842 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6843 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6844 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6845 }
6846 if ((vars->ieee_fc &
6847 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6848 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6849 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6850 }
6851 DP(NETIF_MSG_LINK,
6852 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6853
6854 bnx2x_cl45_write(bp, phy,
6855 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6856 msleep(500);
6857 }
6858
6859 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6860 struct link_params *params,
6861 struct link_vars *vars)
6862 {
6863 struct bnx2x *bp = params->bp;
6864 u16 val = 0, tmp1;
6865 u8 gpio_port;
6866 DP(NETIF_MSG_LINK, "Init 8073\n");
6867
6868 if (CHIP_IS_E2(bp))
6869 gpio_port = BP_PATH(bp);
6870 else
6871 gpio_port = params->port;
6872 /* Restore normal power mode*/
6873 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6874 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6875
6876 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6877 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6878
6879 /* enable LASI */
6880 bnx2x_cl45_write(bp, phy,
6881 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6882 bnx2x_cl45_write(bp, phy,
6883 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
6884
6885 bnx2x_8073_set_pause_cl37(params, phy, vars);
6886
6887 bnx2x_cl45_read(bp, phy,
6888 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6889
6890 bnx2x_cl45_read(bp, phy,
6891 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6892
6893 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6894
6895 /* Swap polarity if required - Must be done only in non-1G mode */
6896 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6897 /* Configure the 8073 to swap _P and _N of the KR lines */
6898 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6899 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6900 bnx2x_cl45_read(bp, phy,
6901 MDIO_PMA_DEVAD,
6902 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6903 bnx2x_cl45_write(bp, phy,
6904 MDIO_PMA_DEVAD,
6905 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6906 (val | (3<<9)));
6907 }
6908
6909
6910 /* Enable CL37 BAM */
6911 if (REG_RD(bp, params->shmem_base +
6912 offsetof(struct shmem_region, dev_info.
6913 port_hw_config[params->port].default_cfg)) &
6914 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6915
6916 bnx2x_cl45_read(bp, phy,
6917 MDIO_AN_DEVAD,
6918 MDIO_AN_REG_8073_BAM, &val);
6919 bnx2x_cl45_write(bp, phy,
6920 MDIO_AN_DEVAD,
6921 MDIO_AN_REG_8073_BAM, val | 1);
6922 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6923 }
6924 if (params->loopback_mode == LOOPBACK_EXT) {
6925 bnx2x_807x_force_10G(bp, phy);
6926 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6927 return 0;
6928 } else {
6929 bnx2x_cl45_write(bp, phy,
6930 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6931 }
6932 if (phy->req_line_speed != SPEED_AUTO_NEG) {
6933 if (phy->req_line_speed == SPEED_10000) {
6934 val = (1<<7);
6935 } else if (phy->req_line_speed == SPEED_2500) {
6936 val = (1<<5);
6937 /*
6938 * Note that 2.5G works only when used with 1G
6939 * advertisement
6940 */
6941 } else
6942 val = (1<<5);
6943 } else {
6944 val = 0;
6945 if (phy->speed_cap_mask &
6946 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6947 val |= (1<<7);
6948
6949 /* Note that 2.5G works only when used with 1G advertisement */
6950 if (phy->speed_cap_mask &
6951 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6952 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6953 val |= (1<<5);
6954 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6955 }
6956
6957 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6958 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6959
6960 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6961 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6962 (phy->req_line_speed == SPEED_2500)) {
6963 u16 phy_ver;
6964 /* Allow 2.5G for A1 and above */
6965 bnx2x_cl45_read(bp, phy,
6966 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6967 &phy_ver);
6968 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6969 if (phy_ver > 0)
6970 tmp1 |= 1;
6971 else
6972 tmp1 &= 0xfffe;
6973 } else {
6974 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6975 tmp1 &= 0xfffe;
6976 }
6977
6978 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6979 /* Add support for CL37 (passive mode) II */
6980
6981 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6982 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6983 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6984 0x20 : 0x40)));
6985
6986 /* Add support for CL37 (passive mode) III */
6987 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6988
6989 /*
6990 * The SNR will improve about 2db by changing BW and FEE main
6991 * tap. Rest commands are executed after link is up
6992 * Change FFE main cursor to 5 in EDC register
6993 */
6994 if (bnx2x_8073_is_snr_needed(bp, phy))
6995 bnx2x_cl45_write(bp, phy,
6996 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6997 0xFB0C);
6998
6999 /* Enable FEC (Forware Error Correction) Request in the AN */
7000 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7001 tmp1 |= (1<<15);
7002 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7003
7004 bnx2x_ext_phy_set_pause(params, phy, vars);
7005
7006 /* Restart autoneg */
7007 msleep(500);
7008 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7009 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7010 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7011 return 0;
7012 }
7013
7014 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7015 struct link_params *params,
7016 struct link_vars *vars)
7017 {
7018 struct bnx2x *bp = params->bp;
7019 u8 link_up = 0;
7020 u16 val1, val2;
7021 u16 link_status = 0;
7022 u16 an1000_status = 0;
7023
7024 bnx2x_cl45_read(bp, phy,
7025 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7026
7027 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7028
7029 /* clear the interrupt LASI status register */
7030 bnx2x_cl45_read(bp, phy,
7031 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7032 bnx2x_cl45_read(bp, phy,
7033 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7034 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7035 /* Clear MSG-OUT */
7036 bnx2x_cl45_read(bp, phy,
7037 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7038
7039 /* Check the LASI */
7040 bnx2x_cl45_read(bp, phy,
7041 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7042
7043 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7044
7045 /* Check the link status */
7046 bnx2x_cl45_read(bp, phy,
7047 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7048 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7049
7050 bnx2x_cl45_read(bp, phy,
7051 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7052 bnx2x_cl45_read(bp, phy,
7053 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7054 link_up = ((val1 & 4) == 4);
7055 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7056
7057 if (link_up &&
7058 ((phy->req_line_speed != SPEED_10000))) {
7059 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7060 return 0;
7061 }
7062 bnx2x_cl45_read(bp, phy,
7063 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7064 bnx2x_cl45_read(bp, phy,
7065 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7066
7067 /* Check the link status on 1.1.2 */
7068 bnx2x_cl45_read(bp, phy,
7069 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7070 bnx2x_cl45_read(bp, phy,
7071 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7072 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7073 "an_link_status=0x%x\n", val2, val1, an1000_status);
7074
7075 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7076 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7077 /*
7078 * The SNR will improve about 2dbby changing the BW and FEE main
7079 * tap. The 1st write to change FFE main tap is set before
7080 * restart AN. Change PLL Bandwidth in EDC register
7081 */
7082 bnx2x_cl45_write(bp, phy,
7083 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7084 0x26BC);
7085
7086 /* Change CDR Bandwidth in EDC register */
7087 bnx2x_cl45_write(bp, phy,
7088 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7089 0x0333);
7090 }
7091 bnx2x_cl45_read(bp, phy,
7092 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7093 &link_status);
7094
7095 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7096 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7097 link_up = 1;
7098 vars->line_speed = SPEED_10000;
7099 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7100 params->port);
7101 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7102 link_up = 1;
7103 vars->line_speed = SPEED_2500;
7104 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7105 params->port);
7106 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7107 link_up = 1;
7108 vars->line_speed = SPEED_1000;
7109 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7110 params->port);
7111 } else {
7112 link_up = 0;
7113 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7114 params->port);
7115 }
7116
7117 if (link_up) {
7118 /* Swap polarity if required */
7119 if (params->lane_config &
7120 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7121 /* Configure the 8073 to swap P and N of the KR lines */
7122 bnx2x_cl45_read(bp, phy,
7123 MDIO_XS_DEVAD,
7124 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7125 /*
7126 * Set bit 3 to invert Rx in 1G mode and clear this bit
7127 * when it`s in 10G mode.
7128 */
7129 if (vars->line_speed == SPEED_1000) {
7130 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7131 "the 8073\n");
7132 val1 |= (1<<3);
7133 } else
7134 val1 &= ~(1<<3);
7135
7136 bnx2x_cl45_write(bp, phy,
7137 MDIO_XS_DEVAD,
7138 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7139 val1);
7140 }
7141 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7142 bnx2x_8073_resolve_fc(phy, params, vars);
7143 vars->duplex = DUPLEX_FULL;
7144 }
7145 return link_up;
7146 }
7147
7148 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7149 struct link_params *params)
7150 {
7151 struct bnx2x *bp = params->bp;
7152 u8 gpio_port;
7153 if (CHIP_IS_E2(bp))
7154 gpio_port = BP_PATH(bp);
7155 else
7156 gpio_port = params->port;
7157 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7158 gpio_port);
7159 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7160 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7161 gpio_port);
7162 }
7163
7164 /******************************************************************/
7165 /* BCM8705 PHY SECTION */
7166 /******************************************************************/
7167 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7168 struct link_params *params,
7169 struct link_vars *vars)
7170 {
7171 struct bnx2x *bp = params->bp;
7172 DP(NETIF_MSG_LINK, "init 8705\n");
7173 /* Restore normal power mode*/
7174 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7175 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7176 /* HW reset */
7177 bnx2x_ext_phy_hw_reset(bp, params->port);
7178 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7179 bnx2x_wait_reset_complete(bp, phy, params);
7180
7181 bnx2x_cl45_write(bp, phy,
7182 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7183 bnx2x_cl45_write(bp, phy,
7184 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7185 bnx2x_cl45_write(bp, phy,
7186 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7187 bnx2x_cl45_write(bp, phy,
7188 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7189 /* BCM8705 doesn't have microcode, hence the 0 */
7190 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7191 return 0;
7192 }
7193
7194 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7195 struct link_params *params,
7196 struct link_vars *vars)
7197 {
7198 u8 link_up = 0;
7199 u16 val1, rx_sd;
7200 struct bnx2x *bp = params->bp;
7201 DP(NETIF_MSG_LINK, "read status 8705\n");
7202 bnx2x_cl45_read(bp, phy,
7203 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7204 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7205
7206 bnx2x_cl45_read(bp, phy,
7207 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7208 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7209
7210 bnx2x_cl45_read(bp, phy,
7211 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7212
7213 bnx2x_cl45_read(bp, phy,
7214 MDIO_PMA_DEVAD, 0xc809, &val1);
7215 bnx2x_cl45_read(bp, phy,
7216 MDIO_PMA_DEVAD, 0xc809, &val1);
7217
7218 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7219 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7220 if (link_up) {
7221 vars->line_speed = SPEED_10000;
7222 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7223 }
7224 return link_up;
7225 }
7226
7227 /******************************************************************/
7228 /* SFP+ module Section */
7229 /******************************************************************/
7230 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7231 struct bnx2x_phy *phy,
7232 u8 pmd_dis)
7233 {
7234 struct bnx2x *bp = params->bp;
7235 /*
7236 * Disable transmitter only for bootcodes which can enable it afterwards
7237 * (for D3 link)
7238 */
7239 if (pmd_dis) {
7240 if (params->feature_config_flags &
7241 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7242 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7243 else {
7244 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7245 return;
7246 }
7247 } else
7248 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7249 bnx2x_cl45_write(bp, phy,
7250 MDIO_PMA_DEVAD,
7251 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7252 }
7253
7254 static u8 bnx2x_get_gpio_port(struct link_params *params)
7255 {
7256 u8 gpio_port;
7257 u32 swap_val, swap_override;
7258 struct bnx2x *bp = params->bp;
7259 if (CHIP_IS_E2(bp))
7260 gpio_port = BP_PATH(bp);
7261 else
7262 gpio_port = params->port;
7263 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7264 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7265 return gpio_port ^ (swap_val && swap_override);
7266 }
7267
7268 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7269 struct bnx2x_phy *phy,
7270 u8 tx_en)
7271 {
7272 u16 val;
7273 u8 port = params->port;
7274 struct bnx2x *bp = params->bp;
7275 u32 tx_en_mode;
7276
7277 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7278 tx_en_mode = REG_RD(bp, params->shmem_base +
7279 offsetof(struct shmem_region,
7280 dev_info.port_hw_config[port].sfp_ctrl)) &
7281 PORT_HW_CFG_TX_LASER_MASK;
7282 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7283 "mode = %x\n", tx_en, port, tx_en_mode);
7284 switch (tx_en_mode) {
7285 case PORT_HW_CFG_TX_LASER_MDIO:
7286
7287 bnx2x_cl45_read(bp, phy,
7288 MDIO_PMA_DEVAD,
7289 MDIO_PMA_REG_PHY_IDENTIFIER,
7290 &val);
7291
7292 if (tx_en)
7293 val &= ~(1<<15);
7294 else
7295 val |= (1<<15);
7296
7297 bnx2x_cl45_write(bp, phy,
7298 MDIO_PMA_DEVAD,
7299 MDIO_PMA_REG_PHY_IDENTIFIER,
7300 val);
7301 break;
7302 case PORT_HW_CFG_TX_LASER_GPIO0:
7303 case PORT_HW_CFG_TX_LASER_GPIO1:
7304 case PORT_HW_CFG_TX_LASER_GPIO2:
7305 case PORT_HW_CFG_TX_LASER_GPIO3:
7306 {
7307 u16 gpio_pin;
7308 u8 gpio_port, gpio_mode;
7309 if (tx_en)
7310 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7311 else
7312 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7313
7314 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7315 gpio_port = bnx2x_get_gpio_port(params);
7316 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7317 break;
7318 }
7319 default:
7320 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7321 break;
7322 }
7323 }
7324
7325 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7326 struct bnx2x_phy *phy,
7327 u8 tx_en)
7328 {
7329 struct bnx2x *bp = params->bp;
7330 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7331 if (CHIP_IS_E3(bp))
7332 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7333 else
7334 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7335 }
7336
7337 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7338 struct link_params *params,
7339 u16 addr, u8 byte_cnt, u8 *o_buf)
7340 {
7341 struct bnx2x *bp = params->bp;
7342 u16 val = 0;
7343 u16 i;
7344 if (byte_cnt > 16) {
7345 DP(NETIF_MSG_LINK,
7346 "Reading from eeprom is limited to 0xf\n");
7347 return -EINVAL;
7348 }
7349 /* Set the read command byte count */
7350 bnx2x_cl45_write(bp, phy,
7351 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7352 (byte_cnt | 0xa000));
7353
7354 /* Set the read command address */
7355 bnx2x_cl45_write(bp, phy,
7356 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7357 addr);
7358
7359 /* Activate read command */
7360 bnx2x_cl45_write(bp, phy,
7361 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7362 0x2c0f);
7363
7364 /* Wait up to 500us for command complete status */
7365 for (i = 0; i < 100; i++) {
7366 bnx2x_cl45_read(bp, phy,
7367 MDIO_PMA_DEVAD,
7368 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7369 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7370 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7371 break;
7372 udelay(5);
7373 }
7374
7375 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7376 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7377 DP(NETIF_MSG_LINK,
7378 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7379 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7380 return -EINVAL;
7381 }
7382
7383 /* Read the buffer */
7384 for (i = 0; i < byte_cnt; i++) {
7385 bnx2x_cl45_read(bp, phy,
7386 MDIO_PMA_DEVAD,
7387 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7388 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7389 }
7390
7391 for (i = 0; i < 100; i++) {
7392 bnx2x_cl45_read(bp, phy,
7393 MDIO_PMA_DEVAD,
7394 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7395 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7396 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7397 return 0;
7398 msleep(1);
7399 }
7400 return -EINVAL;
7401 }
7402
7403 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7404 struct link_params *params,
7405 u16 addr, u8 byte_cnt,
7406 u8 *o_buf)
7407 {
7408 int rc = 0;
7409 u8 i, j = 0, cnt = 0;
7410 u32 data_array[4];
7411 u16 addr32;
7412 struct bnx2x *bp = params->bp;
7413 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7414 " addr %d, cnt %d\n",
7415 addr, byte_cnt);*/
7416 if (byte_cnt > 16) {
7417 DP(NETIF_MSG_LINK,
7418 "Reading from eeprom is limited to 16 bytes\n");
7419 return -EINVAL;
7420 }
7421
7422 /* 4 byte aligned address */
7423 addr32 = addr & (~0x3);
7424 do {
7425 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7426 data_array);
7427 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7428
7429 if (rc == 0) {
7430 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7431 o_buf[j] = *((u8 *)data_array + i);
7432 j++;
7433 }
7434 }
7435
7436 return rc;
7437 }
7438
7439 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7440 struct link_params *params,
7441 u16 addr, u8 byte_cnt, u8 *o_buf)
7442 {
7443 struct bnx2x *bp = params->bp;
7444 u16 val, i;
7445
7446 if (byte_cnt > 16) {
7447 DP(NETIF_MSG_LINK,
7448 "Reading from eeprom is limited to 0xf\n");
7449 return -EINVAL;
7450 }
7451
7452 /* Need to read from 1.8000 to clear it */
7453 bnx2x_cl45_read(bp, phy,
7454 MDIO_PMA_DEVAD,
7455 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7456 &val);
7457
7458 /* Set the read command byte count */
7459 bnx2x_cl45_write(bp, phy,
7460 MDIO_PMA_DEVAD,
7461 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7462 ((byte_cnt < 2) ? 2 : byte_cnt));
7463
7464 /* Set the read command address */
7465 bnx2x_cl45_write(bp, phy,
7466 MDIO_PMA_DEVAD,
7467 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7468 addr);
7469 /* Set the destination address */
7470 bnx2x_cl45_write(bp, phy,
7471 MDIO_PMA_DEVAD,
7472 0x8004,
7473 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7474
7475 /* Activate read command */
7476 bnx2x_cl45_write(bp, phy,
7477 MDIO_PMA_DEVAD,
7478 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7479 0x8002);
7480 /*
7481 * Wait appropriate time for two-wire command to finish before
7482 * polling the status register
7483 */
7484 msleep(1);
7485
7486 /* Wait up to 500us for command complete status */
7487 for (i = 0; i < 100; i++) {
7488 bnx2x_cl45_read(bp, phy,
7489 MDIO_PMA_DEVAD,
7490 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7491 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7492 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7493 break;
7494 udelay(5);
7495 }
7496
7497 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7498 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7499 DP(NETIF_MSG_LINK,
7500 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7501 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7502 return -EFAULT;
7503 }
7504
7505 /* Read the buffer */
7506 for (i = 0; i < byte_cnt; i++) {
7507 bnx2x_cl45_read(bp, phy,
7508 MDIO_PMA_DEVAD,
7509 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7510 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7511 }
7512
7513 for (i = 0; i < 100; i++) {
7514 bnx2x_cl45_read(bp, phy,
7515 MDIO_PMA_DEVAD,
7516 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7517 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7518 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7519 return 0;
7520 msleep(1);
7521 }
7522
7523 return -EINVAL;
7524 }
7525
7526 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7527 struct link_params *params, u16 addr,
7528 u8 byte_cnt, u8 *o_buf)
7529 {
7530 int rc = -EINVAL;
7531 switch (phy->type) {
7532 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7533 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7534 byte_cnt, o_buf);
7535 break;
7536 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7537 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7538 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7539 byte_cnt, o_buf);
7540 break;
7541 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7542 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7543 byte_cnt, o_buf);
7544 break;
7545 }
7546 return rc;
7547 }
7548
7549 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7550 struct link_params *params,
7551 u16 *edc_mode)
7552 {
7553 struct bnx2x *bp = params->bp;
7554 u32 sync_offset = 0, phy_idx, media_types;
7555 u8 val, check_limiting_mode = 0;
7556 *edc_mode = EDC_MODE_LIMITING;
7557
7558 phy->media_type = ETH_PHY_UNSPECIFIED;
7559 /* First check for copper cable */
7560 if (bnx2x_read_sfp_module_eeprom(phy,
7561 params,
7562 SFP_EEPROM_CON_TYPE_ADDR,
7563 1,
7564 &val) != 0) {
7565 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7566 return -EINVAL;
7567 }
7568
7569 switch (val) {
7570 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7571 {
7572 u8 copper_module_type;
7573 phy->media_type = ETH_PHY_DA_TWINAX;
7574 /*
7575 * Check if its active cable (includes SFP+ module)
7576 * of passive cable
7577 */
7578 if (bnx2x_read_sfp_module_eeprom(phy,
7579 params,
7580 SFP_EEPROM_FC_TX_TECH_ADDR,
7581 1,
7582 &copper_module_type) != 0) {
7583 DP(NETIF_MSG_LINK,
7584 "Failed to read copper-cable-type"
7585 " from SFP+ EEPROM\n");
7586 return -EINVAL;
7587 }
7588
7589 if (copper_module_type &
7590 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7591 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7592 check_limiting_mode = 1;
7593 } else if (copper_module_type &
7594 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7595 DP(NETIF_MSG_LINK,
7596 "Passive Copper cable detected\n");
7597 *edc_mode =
7598 EDC_MODE_PASSIVE_DAC;
7599 } else {
7600 DP(NETIF_MSG_LINK,
7601 "Unknown copper-cable-type 0x%x !!!\n",
7602 copper_module_type);
7603 return -EINVAL;
7604 }
7605 break;
7606 }
7607 case SFP_EEPROM_CON_TYPE_VAL_LC:
7608 phy->media_type = ETH_PHY_SFP_FIBER;
7609 DP(NETIF_MSG_LINK, "Optic module detected\n");
7610 check_limiting_mode = 1;
7611 break;
7612 default:
7613 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7614 val);
7615 return -EINVAL;
7616 }
7617 sync_offset = params->shmem_base +
7618 offsetof(struct shmem_region,
7619 dev_info.port_hw_config[params->port].media_type);
7620 media_types = REG_RD(bp, sync_offset);
7621 /* Update media type for non-PMF sync */
7622 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7623 if (&(params->phy[phy_idx]) == phy) {
7624 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7625 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7626 media_types |= ((phy->media_type &
7627 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7628 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7629 break;
7630 }
7631 }
7632 REG_WR(bp, sync_offset, media_types);
7633 if (check_limiting_mode) {
7634 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7635 if (bnx2x_read_sfp_module_eeprom(phy,
7636 params,
7637 SFP_EEPROM_OPTIONS_ADDR,
7638 SFP_EEPROM_OPTIONS_SIZE,
7639 options) != 0) {
7640 DP(NETIF_MSG_LINK,
7641 "Failed to read Option field from module EEPROM\n");
7642 return -EINVAL;
7643 }
7644 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7645 *edc_mode = EDC_MODE_LINEAR;
7646 else
7647 *edc_mode = EDC_MODE_LIMITING;
7648 }
7649 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7650 return 0;
7651 }
7652 /*
7653 * This function read the relevant field from the module (SFP+), and verify it
7654 * is compliant with this board
7655 */
7656 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7657 struct link_params *params)
7658 {
7659 struct bnx2x *bp = params->bp;
7660 u32 val, cmd;
7661 u32 fw_resp, fw_cmd_param;
7662 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7663 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7664 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7665 val = REG_RD(bp, params->shmem_base +
7666 offsetof(struct shmem_region, dev_info.
7667 port_feature_config[params->port].config));
7668 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7669 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7670 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7671 return 0;
7672 }
7673
7674 if (params->feature_config_flags &
7675 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7676 /* Use specific phy request */
7677 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7678 } else if (params->feature_config_flags &
7679 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7680 /* Use first phy request only in case of non-dual media*/
7681 if (DUAL_MEDIA(params)) {
7682 DP(NETIF_MSG_LINK,
7683 "FW does not support OPT MDL verification\n");
7684 return -EINVAL;
7685 }
7686 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7687 } else {
7688 /* No support in OPT MDL detection */
7689 DP(NETIF_MSG_LINK,
7690 "FW does not support OPT MDL verification\n");
7691 return -EINVAL;
7692 }
7693
7694 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7695 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7696 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7697 DP(NETIF_MSG_LINK, "Approved module\n");
7698 return 0;
7699 }
7700
7701 /* format the warning message */
7702 if (bnx2x_read_sfp_module_eeprom(phy,
7703 params,
7704 SFP_EEPROM_VENDOR_NAME_ADDR,
7705 SFP_EEPROM_VENDOR_NAME_SIZE,
7706 (u8 *)vendor_name))
7707 vendor_name[0] = '\0';
7708 else
7709 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7710 if (bnx2x_read_sfp_module_eeprom(phy,
7711 params,
7712 SFP_EEPROM_PART_NO_ADDR,
7713 SFP_EEPROM_PART_NO_SIZE,
7714 (u8 *)vendor_pn))
7715 vendor_pn[0] = '\0';
7716 else
7717 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7718
7719 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7720 " Port %d from %s part number %s\n",
7721 params->port, vendor_name, vendor_pn);
7722 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7723 return -EINVAL;
7724 }
7725
7726 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7727 struct link_params *params)
7728
7729 {
7730 u8 val;
7731 struct bnx2x *bp = params->bp;
7732 u16 timeout;
7733 /*
7734 * Initialization time after hot-plug may take up to 300ms for
7735 * some phys type ( e.g. JDSU )
7736 */
7737
7738 for (timeout = 0; timeout < 60; timeout++) {
7739 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7740 == 0) {
7741 DP(NETIF_MSG_LINK,
7742 "SFP+ module initialization took %d ms\n",
7743 timeout * 5);
7744 return 0;
7745 }
7746 msleep(5);
7747 }
7748 return -EINVAL;
7749 }
7750
7751 static void bnx2x_8727_power_module(struct bnx2x *bp,
7752 struct bnx2x_phy *phy,
7753 u8 is_power_up) {
7754 /* Make sure GPIOs are not using for LED mode */
7755 u16 val;
7756 /*
7757 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7758 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7759 * output
7760 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7761 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7762 * where the 1st bit is the over-current(only input), and 2nd bit is
7763 * for power( only output )
7764 *
7765 * In case of NOC feature is disabled and power is up, set GPIO control
7766 * as input to enable listening of over-current indication
7767 */
7768 if (phy->flags & FLAGS_NOC)
7769 return;
7770 if (is_power_up)
7771 val = (1<<4);
7772 else
7773 /*
7774 * Set GPIO control to OUTPUT, and set the power bit
7775 * to according to the is_power_up
7776 */
7777 val = (1<<1);
7778
7779 bnx2x_cl45_write(bp, phy,
7780 MDIO_PMA_DEVAD,
7781 MDIO_PMA_REG_8727_GPIO_CTRL,
7782 val);
7783 }
7784
7785 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7786 struct bnx2x_phy *phy,
7787 u16 edc_mode)
7788 {
7789 u16 cur_limiting_mode;
7790
7791 bnx2x_cl45_read(bp, phy,
7792 MDIO_PMA_DEVAD,
7793 MDIO_PMA_REG_ROM_VER2,
7794 &cur_limiting_mode);
7795 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7796 cur_limiting_mode);
7797
7798 if (edc_mode == EDC_MODE_LIMITING) {
7799 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7800 bnx2x_cl45_write(bp, phy,
7801 MDIO_PMA_DEVAD,
7802 MDIO_PMA_REG_ROM_VER2,
7803 EDC_MODE_LIMITING);
7804 } else { /* LRM mode ( default )*/
7805
7806 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7807
7808 /*
7809 * Changing to LRM mode takes quite few seconds. So do it only
7810 * if current mode is limiting (default is LRM)
7811 */
7812 if (cur_limiting_mode != EDC_MODE_LIMITING)
7813 return 0;
7814
7815 bnx2x_cl45_write(bp, phy,
7816 MDIO_PMA_DEVAD,
7817 MDIO_PMA_REG_LRM_MODE,
7818 0);
7819 bnx2x_cl45_write(bp, phy,
7820 MDIO_PMA_DEVAD,
7821 MDIO_PMA_REG_ROM_VER2,
7822 0x128);
7823 bnx2x_cl45_write(bp, phy,
7824 MDIO_PMA_DEVAD,
7825 MDIO_PMA_REG_MISC_CTRL0,
7826 0x4008);
7827 bnx2x_cl45_write(bp, phy,
7828 MDIO_PMA_DEVAD,
7829 MDIO_PMA_REG_LRM_MODE,
7830 0xaaaa);
7831 }
7832 return 0;
7833 }
7834
7835 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7836 struct bnx2x_phy *phy,
7837 u16 edc_mode)
7838 {
7839 u16 phy_identifier;
7840 u16 rom_ver2_val;
7841 bnx2x_cl45_read(bp, phy,
7842 MDIO_PMA_DEVAD,
7843 MDIO_PMA_REG_PHY_IDENTIFIER,
7844 &phy_identifier);
7845
7846 bnx2x_cl45_write(bp, phy,
7847 MDIO_PMA_DEVAD,
7848 MDIO_PMA_REG_PHY_IDENTIFIER,
7849 (phy_identifier & ~(1<<9)));
7850
7851 bnx2x_cl45_read(bp, phy,
7852 MDIO_PMA_DEVAD,
7853 MDIO_PMA_REG_ROM_VER2,
7854 &rom_ver2_val);
7855 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7856 bnx2x_cl45_write(bp, phy,
7857 MDIO_PMA_DEVAD,
7858 MDIO_PMA_REG_ROM_VER2,
7859 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7860
7861 bnx2x_cl45_write(bp, phy,
7862 MDIO_PMA_DEVAD,
7863 MDIO_PMA_REG_PHY_IDENTIFIER,
7864 (phy_identifier | (1<<9)));
7865
7866 return 0;
7867 }
7868
7869 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7870 struct link_params *params,
7871 u32 action)
7872 {
7873 struct bnx2x *bp = params->bp;
7874
7875 switch (action) {
7876 case DISABLE_TX:
7877 bnx2x_sfp_set_transmitter(params, phy, 0);
7878 break;
7879 case ENABLE_TX:
7880 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7881 bnx2x_sfp_set_transmitter(params, phy, 1);
7882 break;
7883 default:
7884 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7885 action);
7886 return;
7887 }
7888 }
7889
7890 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7891 u8 gpio_mode)
7892 {
7893 struct bnx2x *bp = params->bp;
7894
7895 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7896 offsetof(struct shmem_region,
7897 dev_info.port_hw_config[params->port].sfp_ctrl)) &
7898 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7899 switch (fault_led_gpio) {
7900 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7901 return;
7902 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7903 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7904 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7905 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7906 {
7907 u8 gpio_port = bnx2x_get_gpio_port(params);
7908 u16 gpio_pin = fault_led_gpio -
7909 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7910 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7911 "pin %x port %x mode %x\n",
7912 gpio_pin, gpio_port, gpio_mode);
7913 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7914 }
7915 break;
7916 default:
7917 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7918 fault_led_gpio);
7919 }
7920 }
7921
7922 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7923 u8 gpio_mode)
7924 {
7925 u32 pin_cfg;
7926 u8 port = params->port;
7927 struct bnx2x *bp = params->bp;
7928 pin_cfg = (REG_RD(bp, params->shmem_base +
7929 offsetof(struct shmem_region,
7930 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7931 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7932 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7933 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7934 gpio_mode, pin_cfg);
7935 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7936 }
7937
7938 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7939 u8 gpio_mode)
7940 {
7941 struct bnx2x *bp = params->bp;
7942 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7943 if (CHIP_IS_E3(bp)) {
7944 /*
7945 * Low ==> if SFP+ module is supported otherwise
7946 * High ==> if SFP+ module is not on the approved vendor list
7947 */
7948 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7949 } else
7950 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7951 }
7952
7953 static void bnx2x_warpcore_power_module(struct link_params *params,
7954 struct bnx2x_phy *phy,
7955 u8 power)
7956 {
7957 u32 pin_cfg;
7958 struct bnx2x *bp = params->bp;
7959
7960 pin_cfg = (REG_RD(bp, params->shmem_base +
7961 offsetof(struct shmem_region,
7962 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7963 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7964 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7965
7966 if (pin_cfg == PIN_CFG_NA)
7967 return;
7968 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7969 power, pin_cfg);
7970 /*
7971 * Low ==> corresponding SFP+ module is powered
7972 * high ==> the SFP+ module is powered down
7973 */
7974 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7975 }
7976
7977 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7978 struct link_params *params)
7979 {
7980 bnx2x_warpcore_power_module(params, phy, 0);
7981 }
7982
7983 static void bnx2x_power_sfp_module(struct link_params *params,
7984 struct bnx2x_phy *phy,
7985 u8 power)
7986 {
7987 struct bnx2x *bp = params->bp;
7988 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7989
7990 switch (phy->type) {
7991 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7992 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7993 bnx2x_8727_power_module(params->bp, phy, power);
7994 break;
7995 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7996 bnx2x_warpcore_power_module(params, phy, power);
7997 break;
7998 default:
7999 break;
8000 }
8001 }
8002 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8003 struct bnx2x_phy *phy,
8004 u16 edc_mode)
8005 {
8006 u16 val = 0;
8007 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8008 struct bnx2x *bp = params->bp;
8009
8010 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8011 /* This is a global register which controls all lanes */
8012 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8013 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8014 val &= ~(0xf << (lane << 2));
8015
8016 switch (edc_mode) {
8017 case EDC_MODE_LINEAR:
8018 case EDC_MODE_LIMITING:
8019 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8020 break;
8021 case EDC_MODE_PASSIVE_DAC:
8022 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8023 break;
8024 default:
8025 break;
8026 }
8027
8028 val |= (mode << (lane << 2));
8029 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8030 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8031 /* A must read */
8032 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8033 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8034
8035 /* Restart microcode to re-read the new mode */
8036 bnx2x_warpcore_reset_lane(bp, phy, 1);
8037 bnx2x_warpcore_reset_lane(bp, phy, 0);
8038
8039 }
8040
8041 static void bnx2x_set_limiting_mode(struct link_params *params,
8042 struct bnx2x_phy *phy,
8043 u16 edc_mode)
8044 {
8045 switch (phy->type) {
8046 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8047 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8048 break;
8049 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8050 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8051 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8052 break;
8053 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8054 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8055 break;
8056 }
8057 }
8058
8059 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8060 struct link_params *params)
8061 {
8062 struct bnx2x *bp = params->bp;
8063 u16 edc_mode;
8064 int rc = 0;
8065
8066 u32 val = REG_RD(bp, params->shmem_base +
8067 offsetof(struct shmem_region, dev_info.
8068 port_feature_config[params->port].config));
8069
8070 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8071 params->port);
8072 /* Power up module */
8073 bnx2x_power_sfp_module(params, phy, 1);
8074 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8075 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8076 return -EINVAL;
8077 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8078 /* check SFP+ module compatibility */
8079 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8080 rc = -EINVAL;
8081 /* Turn on fault module-detected led */
8082 bnx2x_set_sfp_module_fault_led(params,
8083 MISC_REGISTERS_GPIO_HIGH);
8084
8085 /* Check if need to power down the SFP+ module */
8086 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8087 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8088 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8089 bnx2x_power_sfp_module(params, phy, 0);
8090 return rc;
8091 }
8092 } else {
8093 /* Turn off fault module-detected led */
8094 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8095 }
8096
8097 /*
8098 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8099 * is done automatically
8100 */
8101 bnx2x_set_limiting_mode(params, phy, edc_mode);
8102
8103 /*
8104 * Enable transmit for this module if the module is approved, or
8105 * if unapproved modules should also enable the Tx laser
8106 */
8107 if (rc == 0 ||
8108 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8109 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8110 bnx2x_sfp_set_transmitter(params, phy, 1);
8111 else
8112 bnx2x_sfp_set_transmitter(params, phy, 0);
8113
8114 return rc;
8115 }
8116
8117 void bnx2x_handle_module_detect_int(struct link_params *params)
8118 {
8119 struct bnx2x *bp = params->bp;
8120 struct bnx2x_phy *phy;
8121 u32 gpio_val;
8122 u8 gpio_num, gpio_port;
8123 if (CHIP_IS_E3(bp))
8124 phy = &params->phy[INT_PHY];
8125 else
8126 phy = &params->phy[EXT_PHY1];
8127
8128 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8129 params->port, &gpio_num, &gpio_port) ==
8130 -EINVAL) {
8131 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8132 return;
8133 }
8134
8135 /* Set valid module led off */
8136 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8137
8138 /* Get current gpio val reflecting module plugged in / out*/
8139 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8140
8141 /* Call the handling function in case module is detected */
8142 if (gpio_val == 0) {
8143 bnx2x_power_sfp_module(params, phy, 1);
8144 bnx2x_set_gpio_int(bp, gpio_num,
8145 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8146 gpio_port);
8147 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8148 bnx2x_sfp_module_detection(phy, params);
8149 else
8150 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8151 } else {
8152 u32 val = REG_RD(bp, params->shmem_base +
8153 offsetof(struct shmem_region, dev_info.
8154 port_feature_config[params->port].
8155 config));
8156 bnx2x_set_gpio_int(bp, gpio_num,
8157 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8158 gpio_port);
8159 /*
8160 * Module was plugged out.
8161 * Disable transmit for this module
8162 */
8163 phy->media_type = ETH_PHY_NOT_PRESENT;
8164 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8165 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8166 CHIP_IS_E3(bp))
8167 bnx2x_sfp_set_transmitter(params, phy, 0);
8168 }
8169 }
8170
8171 /******************************************************************/
8172 /* Used by 8706 and 8727 */
8173 /******************************************************************/
8174 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8175 struct bnx2x_phy *phy,
8176 u16 alarm_status_offset,
8177 u16 alarm_ctrl_offset)
8178 {
8179 u16 alarm_status, val;
8180 bnx2x_cl45_read(bp, phy,
8181 MDIO_PMA_DEVAD, alarm_status_offset,
8182 &alarm_status);
8183 bnx2x_cl45_read(bp, phy,
8184 MDIO_PMA_DEVAD, alarm_status_offset,
8185 &alarm_status);
8186 /* Mask or enable the fault event. */
8187 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8188 if (alarm_status & (1<<0))
8189 val &= ~(1<<0);
8190 else
8191 val |= (1<<0);
8192 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8193 }
8194 /******************************************************************/
8195 /* common BCM8706/BCM8726 PHY SECTION */
8196 /******************************************************************/
8197 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8198 struct link_params *params,
8199 struct link_vars *vars)
8200 {
8201 u8 link_up = 0;
8202 u16 val1, val2, rx_sd, pcs_status;
8203 struct bnx2x *bp = params->bp;
8204 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8205 /* Clear RX Alarm*/
8206 bnx2x_cl45_read(bp, phy,
8207 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8208
8209 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8210 MDIO_PMA_LASI_TXCTRL);
8211
8212 /* clear LASI indication*/
8213 bnx2x_cl45_read(bp, phy,
8214 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8215 bnx2x_cl45_read(bp, phy,
8216 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8217 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8218
8219 bnx2x_cl45_read(bp, phy,
8220 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8221 bnx2x_cl45_read(bp, phy,
8222 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8223 bnx2x_cl45_read(bp, phy,
8224 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8225 bnx2x_cl45_read(bp, phy,
8226 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8227
8228 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8229 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8230 /*
8231 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8232 * are set, or if the autoneg bit 1 is set
8233 */
8234 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8235 if (link_up) {
8236 if (val2 & (1<<1))
8237 vars->line_speed = SPEED_1000;
8238 else
8239 vars->line_speed = SPEED_10000;
8240 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8241 vars->duplex = DUPLEX_FULL;
8242 }
8243
8244 /* Capture 10G link fault. Read twice to clear stale value. */
8245 if (vars->line_speed == SPEED_10000) {
8246 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8247 MDIO_PMA_LASI_TXSTAT, &val1);
8248 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8249 MDIO_PMA_LASI_TXSTAT, &val1);
8250 if (val1 & (1<<0))
8251 vars->fault_detected = 1;
8252 }
8253
8254 return link_up;
8255 }
8256
8257 /******************************************************************/
8258 /* BCM8706 PHY SECTION */
8259 /******************************************************************/
8260 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8261 struct link_params *params,
8262 struct link_vars *vars)
8263 {
8264 u32 tx_en_mode;
8265 u16 cnt, val, tmp1;
8266 struct bnx2x *bp = params->bp;
8267
8268 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8269 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8270 /* HW reset */
8271 bnx2x_ext_phy_hw_reset(bp, params->port);
8272 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8273 bnx2x_wait_reset_complete(bp, phy, params);
8274
8275 /* Wait until fw is loaded */
8276 for (cnt = 0; cnt < 100; cnt++) {
8277 bnx2x_cl45_read(bp, phy,
8278 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8279 if (val)
8280 break;
8281 msleep(10);
8282 }
8283 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8284 if ((params->feature_config_flags &
8285 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8286 u8 i;
8287 u16 reg;
8288 for (i = 0; i < 4; i++) {
8289 reg = MDIO_XS_8706_REG_BANK_RX0 +
8290 i*(MDIO_XS_8706_REG_BANK_RX1 -
8291 MDIO_XS_8706_REG_BANK_RX0);
8292 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8293 /* Clear first 3 bits of the control */
8294 val &= ~0x7;
8295 /* Set control bits according to configuration */
8296 val |= (phy->rx_preemphasis[i] & 0x7);
8297 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8298 " reg 0x%x <-- val 0x%x\n", reg, val);
8299 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8300 }
8301 }
8302 /* Force speed */
8303 if (phy->req_line_speed == SPEED_10000) {
8304 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8305
8306 bnx2x_cl45_write(bp, phy,
8307 MDIO_PMA_DEVAD,
8308 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8309 bnx2x_cl45_write(bp, phy,
8310 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8311 0);
8312 /* Arm LASI for link and Tx fault. */
8313 bnx2x_cl45_write(bp, phy,
8314 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8315 } else {
8316 /* Force 1Gbps using autoneg with 1G advertisement */
8317
8318 /* Allow CL37 through CL73 */
8319 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8320 bnx2x_cl45_write(bp, phy,
8321 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8322
8323 /* Enable Full-Duplex advertisement on CL37 */
8324 bnx2x_cl45_write(bp, phy,
8325 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8326 /* Enable CL37 AN */
8327 bnx2x_cl45_write(bp, phy,
8328 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8329 /* 1G support */
8330 bnx2x_cl45_write(bp, phy,
8331 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8332
8333 /* Enable clause 73 AN */
8334 bnx2x_cl45_write(bp, phy,
8335 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8336 bnx2x_cl45_write(bp, phy,
8337 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8338 0x0400);
8339 bnx2x_cl45_write(bp, phy,
8340 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8341 0x0004);
8342 }
8343 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8344
8345 /*
8346 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8347 * power mode, if TX Laser is disabled
8348 */
8349
8350 tx_en_mode = REG_RD(bp, params->shmem_base +
8351 offsetof(struct shmem_region,
8352 dev_info.port_hw_config[params->port].sfp_ctrl))
8353 & PORT_HW_CFG_TX_LASER_MASK;
8354
8355 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8356 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8357 bnx2x_cl45_read(bp, phy,
8358 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8359 tmp1 |= 0x1;
8360 bnx2x_cl45_write(bp, phy,
8361 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8362 }
8363
8364 return 0;
8365 }
8366
8367 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8368 struct link_params *params,
8369 struct link_vars *vars)
8370 {
8371 return bnx2x_8706_8726_read_status(phy, params, vars);
8372 }
8373
8374 /******************************************************************/
8375 /* BCM8726 PHY SECTION */
8376 /******************************************************************/
8377 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8378 struct link_params *params)
8379 {
8380 struct bnx2x *bp = params->bp;
8381 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8382 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8383 }
8384
8385 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8386 struct link_params *params)
8387 {
8388 struct bnx2x *bp = params->bp;
8389 /* Need to wait 100ms after reset */
8390 msleep(100);
8391
8392 /* Micro controller re-boot */
8393 bnx2x_cl45_write(bp, phy,
8394 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8395
8396 /* Set soft reset */
8397 bnx2x_cl45_write(bp, phy,
8398 MDIO_PMA_DEVAD,
8399 MDIO_PMA_REG_GEN_CTRL,
8400 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8401
8402 bnx2x_cl45_write(bp, phy,
8403 MDIO_PMA_DEVAD,
8404 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8405
8406 bnx2x_cl45_write(bp, phy,
8407 MDIO_PMA_DEVAD,
8408 MDIO_PMA_REG_GEN_CTRL,
8409 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8410
8411 /* wait for 150ms for microcode load */
8412 msleep(150);
8413
8414 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8415 bnx2x_cl45_write(bp, phy,
8416 MDIO_PMA_DEVAD,
8417 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8418
8419 msleep(200);
8420 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8421 }
8422
8423 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8424 struct link_params *params,
8425 struct link_vars *vars)
8426 {
8427 struct bnx2x *bp = params->bp;
8428 u16 val1;
8429 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8430 if (link_up) {
8431 bnx2x_cl45_read(bp, phy,
8432 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8433 &val1);
8434 if (val1 & (1<<15)) {
8435 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8436 link_up = 0;
8437 vars->line_speed = 0;
8438 }
8439 }
8440 return link_up;
8441 }
8442
8443
8444 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8445 struct link_params *params,
8446 struct link_vars *vars)
8447 {
8448 struct bnx2x *bp = params->bp;
8449 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8450
8451 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8452 bnx2x_wait_reset_complete(bp, phy, params);
8453
8454 bnx2x_8726_external_rom_boot(phy, params);
8455
8456 /*
8457 * Need to call module detected on initialization since the module
8458 * detection triggered by actual module insertion might occur before
8459 * driver is loaded, and when driver is loaded, it reset all
8460 * registers, including the transmitter
8461 */
8462 bnx2x_sfp_module_detection(phy, params);
8463
8464 if (phy->req_line_speed == SPEED_1000) {
8465 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8466 bnx2x_cl45_write(bp, phy,
8467 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8468 bnx2x_cl45_write(bp, phy,
8469 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8470 bnx2x_cl45_write(bp, phy,
8471 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8472 bnx2x_cl45_write(bp, phy,
8473 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8474 0x400);
8475 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8476 (phy->speed_cap_mask &
8477 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8478 ((phy->speed_cap_mask &
8479 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8480 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8481 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8482 /* Set Flow control */
8483 bnx2x_ext_phy_set_pause(params, phy, vars);
8484 bnx2x_cl45_write(bp, phy,
8485 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8486 bnx2x_cl45_write(bp, phy,
8487 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8488 bnx2x_cl45_write(bp, phy,
8489 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8490 bnx2x_cl45_write(bp, phy,
8491 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8492 bnx2x_cl45_write(bp, phy,
8493 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8494 /*
8495 * Enable RX-ALARM control to receive interrupt for 1G speed
8496 * change
8497 */
8498 bnx2x_cl45_write(bp, phy,
8499 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8500 bnx2x_cl45_write(bp, phy,
8501 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8502 0x400);
8503
8504 } else { /* Default 10G. Set only LASI control */
8505 bnx2x_cl45_write(bp, phy,
8506 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8507 }
8508
8509 /* Set TX PreEmphasis if needed */
8510 if ((params->feature_config_flags &
8511 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8512 DP(NETIF_MSG_LINK,
8513 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8514 phy->tx_preemphasis[0],
8515 phy->tx_preemphasis[1]);
8516 bnx2x_cl45_write(bp, phy,
8517 MDIO_PMA_DEVAD,
8518 MDIO_PMA_REG_8726_TX_CTRL1,
8519 phy->tx_preemphasis[0]);
8520
8521 bnx2x_cl45_write(bp, phy,
8522 MDIO_PMA_DEVAD,
8523 MDIO_PMA_REG_8726_TX_CTRL2,
8524 phy->tx_preemphasis[1]);
8525 }
8526
8527 return 0;
8528
8529 }
8530
8531 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8532 struct link_params *params)
8533 {
8534 struct bnx2x *bp = params->bp;
8535 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8536 /* Set serial boot control for external load */
8537 bnx2x_cl45_write(bp, phy,
8538 MDIO_PMA_DEVAD,
8539 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8540 }
8541
8542 /******************************************************************/
8543 /* BCM8727 PHY SECTION */
8544 /******************************************************************/
8545
8546 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8547 struct link_params *params, u8 mode)
8548 {
8549 struct bnx2x *bp = params->bp;
8550 u16 led_mode_bitmask = 0;
8551 u16 gpio_pins_bitmask = 0;
8552 u16 val;
8553 /* Only NOC flavor requires to set the LED specifically */
8554 if (!(phy->flags & FLAGS_NOC))
8555 return;
8556 switch (mode) {
8557 case LED_MODE_FRONT_PANEL_OFF:
8558 case LED_MODE_OFF:
8559 led_mode_bitmask = 0;
8560 gpio_pins_bitmask = 0x03;
8561 break;
8562 case LED_MODE_ON:
8563 led_mode_bitmask = 0;
8564 gpio_pins_bitmask = 0x02;
8565 break;
8566 case LED_MODE_OPER:
8567 led_mode_bitmask = 0x60;
8568 gpio_pins_bitmask = 0x11;
8569 break;
8570 }
8571 bnx2x_cl45_read(bp, phy,
8572 MDIO_PMA_DEVAD,
8573 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8574 &val);
8575 val &= 0xff8f;
8576 val |= led_mode_bitmask;
8577 bnx2x_cl45_write(bp, phy,
8578 MDIO_PMA_DEVAD,
8579 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8580 val);
8581 bnx2x_cl45_read(bp, phy,
8582 MDIO_PMA_DEVAD,
8583 MDIO_PMA_REG_8727_GPIO_CTRL,
8584 &val);
8585 val &= 0xffe0;
8586 val |= gpio_pins_bitmask;
8587 bnx2x_cl45_write(bp, phy,
8588 MDIO_PMA_DEVAD,
8589 MDIO_PMA_REG_8727_GPIO_CTRL,
8590 val);
8591 }
8592 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8593 struct link_params *params) {
8594 u32 swap_val, swap_override;
8595 u8 port;
8596 /*
8597 * The PHY reset is controlled by GPIO 1. Fake the port number
8598 * to cancel the swap done in set_gpio()
8599 */
8600 struct bnx2x *bp = params->bp;
8601 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8602 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8603 port = (swap_val && swap_override) ^ 1;
8604 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8605 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8606 }
8607
8608 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8609 struct link_params *params,
8610 struct link_vars *vars)
8611 {
8612 u32 tx_en_mode;
8613 u16 tmp1, val, mod_abs, tmp2;
8614 u16 rx_alarm_ctrl_val;
8615 u16 lasi_ctrl_val;
8616 struct bnx2x *bp = params->bp;
8617 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8618
8619 bnx2x_wait_reset_complete(bp, phy, params);
8620 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8621 /* Should be 0x6 to enable XS on Tx side. */
8622 lasi_ctrl_val = 0x0006;
8623
8624 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8625 /* enable LASI */
8626 bnx2x_cl45_write(bp, phy,
8627 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8628 rx_alarm_ctrl_val);
8629 bnx2x_cl45_write(bp, phy,
8630 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8631 0);
8632 bnx2x_cl45_write(bp, phy,
8633 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8634
8635 /*
8636 * Initially configure MOD_ABS to interrupt when module is
8637 * presence( bit 8)
8638 */
8639 bnx2x_cl45_read(bp, phy,
8640 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8641 /*
8642 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8643 * When the EDC is off it locks onto a reference clock and avoids
8644 * becoming 'lost'
8645 */
8646 mod_abs &= ~(1<<8);
8647 if (!(phy->flags & FLAGS_NOC))
8648 mod_abs &= ~(1<<9);
8649 bnx2x_cl45_write(bp, phy,
8650 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8651
8652
8653 /* Enable/Disable PHY transmitter output */
8654 bnx2x_set_disable_pmd_transmit(params, phy, 0);
8655
8656 /* Make MOD_ABS give interrupt on change */
8657 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8658 &val);
8659 val |= (1<<12);
8660 if (phy->flags & FLAGS_NOC)
8661 val |= (3<<5);
8662
8663 /*
8664 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8665 * status which reflect SFP+ module over-current
8666 */
8667 if (!(phy->flags & FLAGS_NOC))
8668 val &= 0xff8f; /* Reset bits 4-6 */
8669 bnx2x_cl45_write(bp, phy,
8670 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8671
8672 bnx2x_8727_power_module(bp, phy, 1);
8673
8674 bnx2x_cl45_read(bp, phy,
8675 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8676
8677 bnx2x_cl45_read(bp, phy,
8678 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8679
8680 /* Set option 1G speed */
8681 if (phy->req_line_speed == SPEED_1000) {
8682 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8683 bnx2x_cl45_write(bp, phy,
8684 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8685 bnx2x_cl45_write(bp, phy,
8686 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8687 bnx2x_cl45_read(bp, phy,
8688 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8689 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8690 /*
8691 * Power down the XAUI until link is up in case of dual-media
8692 * and 1G
8693 */
8694 if (DUAL_MEDIA(params)) {
8695 bnx2x_cl45_read(bp, phy,
8696 MDIO_PMA_DEVAD,
8697 MDIO_PMA_REG_8727_PCS_GP, &val);
8698 val |= (3<<10);
8699 bnx2x_cl45_write(bp, phy,
8700 MDIO_PMA_DEVAD,
8701 MDIO_PMA_REG_8727_PCS_GP, val);
8702 }
8703 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8704 ((phy->speed_cap_mask &
8705 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8706 ((phy->speed_cap_mask &
8707 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8708 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8709
8710 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8711 bnx2x_cl45_write(bp, phy,
8712 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8713 bnx2x_cl45_write(bp, phy,
8714 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8715 } else {
8716 /*
8717 * Since the 8727 has only single reset pin, need to set the 10G
8718 * registers although it is default
8719 */
8720 bnx2x_cl45_write(bp, phy,
8721 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8722 0x0020);
8723 bnx2x_cl45_write(bp, phy,
8724 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8725 bnx2x_cl45_write(bp, phy,
8726 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8727 bnx2x_cl45_write(bp, phy,
8728 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8729 0x0008);
8730 }
8731
8732 /*
8733 * Set 2-wire transfer rate of SFP+ module EEPROM
8734 * to 100Khz since some DACs(direct attached cables) do
8735 * not work at 400Khz.
8736 */
8737 bnx2x_cl45_write(bp, phy,
8738 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8739 0xa001);
8740
8741 /* Set TX PreEmphasis if needed */
8742 if ((params->feature_config_flags &
8743 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8744 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8745 phy->tx_preemphasis[0],
8746 phy->tx_preemphasis[1]);
8747 bnx2x_cl45_write(bp, phy,
8748 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8749 phy->tx_preemphasis[0]);
8750
8751 bnx2x_cl45_write(bp, phy,
8752 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8753 phy->tx_preemphasis[1]);
8754 }
8755
8756 /*
8757 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8758 * power mode, if TX Laser is disabled
8759 */
8760 tx_en_mode = REG_RD(bp, params->shmem_base +
8761 offsetof(struct shmem_region,
8762 dev_info.port_hw_config[params->port].sfp_ctrl))
8763 & PORT_HW_CFG_TX_LASER_MASK;
8764
8765 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8766
8767 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8768 bnx2x_cl45_read(bp, phy,
8769 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8770 tmp2 |= 0x1000;
8771 tmp2 &= 0xFFEF;
8772 bnx2x_cl45_write(bp, phy,
8773 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8774 }
8775
8776 return 0;
8777 }
8778
8779 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8780 struct link_params *params)
8781 {
8782 struct bnx2x *bp = params->bp;
8783 u16 mod_abs, rx_alarm_status;
8784 u32 val = REG_RD(bp, params->shmem_base +
8785 offsetof(struct shmem_region, dev_info.
8786 port_feature_config[params->port].
8787 config));
8788 bnx2x_cl45_read(bp, phy,
8789 MDIO_PMA_DEVAD,
8790 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8791 if (mod_abs & (1<<8)) {
8792
8793 /* Module is absent */
8794 DP(NETIF_MSG_LINK,
8795 "MOD_ABS indication show module is absent\n");
8796 phy->media_type = ETH_PHY_NOT_PRESENT;
8797 /*
8798 * 1. Set mod_abs to detect next module
8799 * presence event
8800 * 2. Set EDC off by setting OPTXLOS signal input to low
8801 * (bit 9).
8802 * When the EDC is off it locks onto a reference clock and
8803 * avoids becoming 'lost'.
8804 */
8805 mod_abs &= ~(1<<8);
8806 if (!(phy->flags & FLAGS_NOC))
8807 mod_abs &= ~(1<<9);
8808 bnx2x_cl45_write(bp, phy,
8809 MDIO_PMA_DEVAD,
8810 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8811
8812 /*
8813 * Clear RX alarm since it stays up as long as
8814 * the mod_abs wasn't changed
8815 */
8816 bnx2x_cl45_read(bp, phy,
8817 MDIO_PMA_DEVAD,
8818 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8819
8820 } else {
8821 /* Module is present */
8822 DP(NETIF_MSG_LINK,
8823 "MOD_ABS indication show module is present\n");
8824 /*
8825 * First disable transmitter, and if the module is ok, the
8826 * module_detection will enable it
8827 * 1. Set mod_abs to detect next module absent event ( bit 8)
8828 * 2. Restore the default polarity of the OPRXLOS signal and
8829 * this signal will then correctly indicate the presence or
8830 * absence of the Rx signal. (bit 9)
8831 */
8832 mod_abs |= (1<<8);
8833 if (!(phy->flags & FLAGS_NOC))
8834 mod_abs |= (1<<9);
8835 bnx2x_cl45_write(bp, phy,
8836 MDIO_PMA_DEVAD,
8837 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8838
8839 /*
8840 * Clear RX alarm since it stays up as long as the mod_abs
8841 * wasn't changed. This is need to be done before calling the
8842 * module detection, otherwise it will clear* the link update
8843 * alarm
8844 */
8845 bnx2x_cl45_read(bp, phy,
8846 MDIO_PMA_DEVAD,
8847 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8848
8849
8850 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8851 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8852 bnx2x_sfp_set_transmitter(params, phy, 0);
8853
8854 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8855 bnx2x_sfp_module_detection(phy, params);
8856 else
8857 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8858 }
8859
8860 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8861 rx_alarm_status);
8862 /* No need to check link status in case of module plugged in/out */
8863 }
8864
8865 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8866 struct link_params *params,
8867 struct link_vars *vars)
8868
8869 {
8870 struct bnx2x *bp = params->bp;
8871 u8 link_up = 0, oc_port = params->port;
8872 u16 link_status = 0;
8873 u16 rx_alarm_status, lasi_ctrl, val1;
8874
8875 /* If PHY is not initialized, do not check link status */
8876 bnx2x_cl45_read(bp, phy,
8877 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8878 &lasi_ctrl);
8879 if (!lasi_ctrl)
8880 return 0;
8881
8882 /* Check the LASI on Rx */
8883 bnx2x_cl45_read(bp, phy,
8884 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8885 &rx_alarm_status);
8886 vars->line_speed = 0;
8887 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
8888
8889 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8890 MDIO_PMA_LASI_TXCTRL);
8891
8892 bnx2x_cl45_read(bp, phy,
8893 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8894
8895 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8896
8897 /* Clear MSG-OUT */
8898 bnx2x_cl45_read(bp, phy,
8899 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8900
8901 /*
8902 * If a module is present and there is need to check
8903 * for over current
8904 */
8905 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8906 /* Check over-current using 8727 GPIO0 input*/
8907 bnx2x_cl45_read(bp, phy,
8908 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8909 &val1);
8910
8911 if ((val1 & (1<<8)) == 0) {
8912 if (!CHIP_IS_E1x(bp))
8913 oc_port = BP_PATH(bp) + (params->port << 1);
8914 DP(NETIF_MSG_LINK,
8915 "8727 Power fault has been detected on port %d\n",
8916 oc_port);
8917 netdev_err(bp->dev, "Error: Power fault on Port %d has"
8918 " been detected and the power to "
8919 "that SFP+ module has been removed"
8920 " to prevent failure of the card."
8921 " Please remove the SFP+ module and"
8922 " restart the system to clear this"
8923 " error.\n",
8924 oc_port);
8925 /* Disable all RX_ALARMs except for mod_abs */
8926 bnx2x_cl45_write(bp, phy,
8927 MDIO_PMA_DEVAD,
8928 MDIO_PMA_LASI_RXCTRL, (1<<5));
8929
8930 bnx2x_cl45_read(bp, phy,
8931 MDIO_PMA_DEVAD,
8932 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8933 /* Wait for module_absent_event */
8934 val1 |= (1<<8);
8935 bnx2x_cl45_write(bp, phy,
8936 MDIO_PMA_DEVAD,
8937 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8938 /* Clear RX alarm */
8939 bnx2x_cl45_read(bp, phy,
8940 MDIO_PMA_DEVAD,
8941 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8942 return 0;
8943 }
8944 } /* Over current check */
8945
8946 /* When module absent bit is set, check module */
8947 if (rx_alarm_status & (1<<5)) {
8948 bnx2x_8727_handle_mod_abs(phy, params);
8949 /* Enable all mod_abs and link detection bits */
8950 bnx2x_cl45_write(bp, phy,
8951 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8952 ((1<<5) | (1<<2)));
8953 }
8954 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8955 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8956 /* If transmitter is disabled, ignore false link up indication */
8957 bnx2x_cl45_read(bp, phy,
8958 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8959 if (val1 & (1<<15)) {
8960 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8961 return 0;
8962 }
8963
8964 bnx2x_cl45_read(bp, phy,
8965 MDIO_PMA_DEVAD,
8966 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8967
8968 /*
8969 * Bits 0..2 --> speed detected,
8970 * Bits 13..15--> link is down
8971 */
8972 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8973 link_up = 1;
8974 vars->line_speed = SPEED_10000;
8975 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8976 params->port);
8977 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8978 link_up = 1;
8979 vars->line_speed = SPEED_1000;
8980 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8981 params->port);
8982 } else {
8983 link_up = 0;
8984 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8985 params->port);
8986 }
8987
8988 /* Capture 10G link fault. */
8989 if (vars->line_speed == SPEED_10000) {
8990 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8991 MDIO_PMA_LASI_TXSTAT, &val1);
8992
8993 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8994 MDIO_PMA_LASI_TXSTAT, &val1);
8995
8996 if (val1 & (1<<0)) {
8997 vars->fault_detected = 1;
8998 }
8999 }
9000
9001 if (link_up) {
9002 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9003 vars->duplex = DUPLEX_FULL;
9004 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9005 }
9006
9007 if ((DUAL_MEDIA(params)) &&
9008 (phy->req_line_speed == SPEED_1000)) {
9009 bnx2x_cl45_read(bp, phy,
9010 MDIO_PMA_DEVAD,
9011 MDIO_PMA_REG_8727_PCS_GP, &val1);
9012 /*
9013 * In case of dual-media board and 1G, power up the XAUI side,
9014 * otherwise power it down. For 10G it is done automatically
9015 */
9016 if (link_up)
9017 val1 &= ~(3<<10);
9018 else
9019 val1 |= (3<<10);
9020 bnx2x_cl45_write(bp, phy,
9021 MDIO_PMA_DEVAD,
9022 MDIO_PMA_REG_8727_PCS_GP, val1);
9023 }
9024 return link_up;
9025 }
9026
9027 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9028 struct link_params *params)
9029 {
9030 struct bnx2x *bp = params->bp;
9031
9032 /* Enable/Disable PHY transmitter output */
9033 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9034
9035 /* Disable Transmitter */
9036 bnx2x_sfp_set_transmitter(params, phy, 0);
9037 /* Clear LASI */
9038 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9039
9040 }
9041
9042 /******************************************************************/
9043 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9044 /******************************************************************/
9045 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9046 struct link_params *params)
9047 {
9048 u16 val, fw_ver1, fw_ver2, cnt;
9049 u8 port;
9050 struct bnx2x *bp = params->bp;
9051
9052 port = params->port;
9053
9054 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9055 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9056 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9057 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9058 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9059 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9060 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9061
9062 for (cnt = 0; cnt < 100; cnt++) {
9063 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9064 if (val & 1)
9065 break;
9066 udelay(5);
9067 }
9068 if (cnt == 100) {
9069 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9070 bnx2x_save_spirom_version(bp, port, 0,
9071 phy->ver_addr);
9072 return;
9073 }
9074
9075
9076 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9077 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9078 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9079 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9080 for (cnt = 0; cnt < 100; cnt++) {
9081 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9082 if (val & 1)
9083 break;
9084 udelay(5);
9085 }
9086 if (cnt == 100) {
9087 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9088 bnx2x_save_spirom_version(bp, port, 0,
9089 phy->ver_addr);
9090 return;
9091 }
9092
9093 /* lower 16 bits of the register SPI_FW_STATUS */
9094 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9095 /* upper 16 bits of register SPI_FW_STATUS */
9096 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9097
9098 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9099 phy->ver_addr);
9100 }
9101
9102 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9103 struct bnx2x_phy *phy)
9104 {
9105 u16 val;
9106
9107 /* PHYC_CTL_LED_CTL */
9108 bnx2x_cl45_read(bp, phy,
9109 MDIO_PMA_DEVAD,
9110 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9111 val &= 0xFE00;
9112 val |= 0x0092;
9113
9114 bnx2x_cl45_write(bp, phy,
9115 MDIO_PMA_DEVAD,
9116 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9117
9118 bnx2x_cl45_write(bp, phy,
9119 MDIO_PMA_DEVAD,
9120 MDIO_PMA_REG_8481_LED1_MASK,
9121 0x80);
9122
9123 bnx2x_cl45_write(bp, phy,
9124 MDIO_PMA_DEVAD,
9125 MDIO_PMA_REG_8481_LED2_MASK,
9126 0x18);
9127
9128 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9129 bnx2x_cl45_write(bp, phy,
9130 MDIO_PMA_DEVAD,
9131 MDIO_PMA_REG_8481_LED3_MASK,
9132 0x0006);
9133
9134 /* Select the closest activity blink rate to that in 10/100/1000 */
9135 bnx2x_cl45_write(bp, phy,
9136 MDIO_PMA_DEVAD,
9137 MDIO_PMA_REG_8481_LED3_BLINK,
9138 0);
9139
9140 bnx2x_cl45_read(bp, phy,
9141 MDIO_PMA_DEVAD,
9142 MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9143 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9144
9145 bnx2x_cl45_write(bp, phy,
9146 MDIO_PMA_DEVAD,
9147 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9148
9149 /* 'Interrupt Mask' */
9150 bnx2x_cl45_write(bp, phy,
9151 MDIO_AN_DEVAD,
9152 0xFFFB, 0xFFFD);
9153 }
9154
9155 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9156 struct link_params *params,
9157 struct link_vars *vars)
9158 {
9159 struct bnx2x *bp = params->bp;
9160 u16 autoneg_val, an_1000_val, an_10_100_val;
9161 u16 tmp_req_line_speed;
9162
9163 tmp_req_line_speed = phy->req_line_speed;
9164 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9165 if (phy->req_line_speed == SPEED_10000)
9166 phy->req_line_speed = SPEED_AUTO_NEG;
9167
9168 /*
9169 * This phy uses the NIG latch mechanism since link indication
9170 * arrives through its LED4 and not via its LASI signal, so we
9171 * get steady signal instead of clear on read
9172 */
9173 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9174 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9175
9176 bnx2x_cl45_write(bp, phy,
9177 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9178
9179 bnx2x_848xx_set_led(bp, phy);
9180
9181 /* set 1000 speed advertisement */
9182 bnx2x_cl45_read(bp, phy,
9183 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9184 &an_1000_val);
9185
9186 bnx2x_ext_phy_set_pause(params, phy, vars);
9187 bnx2x_cl45_read(bp, phy,
9188 MDIO_AN_DEVAD,
9189 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9190 &an_10_100_val);
9191 bnx2x_cl45_read(bp, phy,
9192 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9193 &autoneg_val);
9194 /* Disable forced speed */
9195 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9196 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9197
9198 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9199 (phy->speed_cap_mask &
9200 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9201 (phy->req_line_speed == SPEED_1000)) {
9202 an_1000_val |= (1<<8);
9203 autoneg_val |= (1<<9 | 1<<12);
9204 if (phy->req_duplex == DUPLEX_FULL)
9205 an_1000_val |= (1<<9);
9206 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9207 } else
9208 an_1000_val &= ~((1<<8) | (1<<9));
9209
9210 bnx2x_cl45_write(bp, phy,
9211 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9212 an_1000_val);
9213
9214 /* set 100 speed advertisement */
9215 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9216 (phy->speed_cap_mask &
9217 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9218 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9219 (phy->supported &
9220 (SUPPORTED_100baseT_Half |
9221 SUPPORTED_100baseT_Full)))) {
9222 an_10_100_val |= (1<<7);
9223 /* Enable autoneg and restart autoneg for legacy speeds */
9224 autoneg_val |= (1<<9 | 1<<12);
9225
9226 if (phy->req_duplex == DUPLEX_FULL)
9227 an_10_100_val |= (1<<8);
9228 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9229 }
9230 /* set 10 speed advertisement */
9231 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9232 (phy->speed_cap_mask &
9233 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9234 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9235 (phy->supported &
9236 (SUPPORTED_10baseT_Half |
9237 SUPPORTED_10baseT_Full)))) {
9238 an_10_100_val |= (1<<5);
9239 autoneg_val |= (1<<9 | 1<<12);
9240 if (phy->req_duplex == DUPLEX_FULL)
9241 an_10_100_val |= (1<<6);
9242 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9243 }
9244
9245 /* Only 10/100 are allowed to work in FORCE mode */
9246 if ((phy->req_line_speed == SPEED_100) &&
9247 (phy->supported &
9248 (SUPPORTED_100baseT_Half |
9249 SUPPORTED_100baseT_Full))) {
9250 autoneg_val |= (1<<13);
9251 /* Enabled AUTO-MDIX when autoneg is disabled */
9252 bnx2x_cl45_write(bp, phy,
9253 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9254 (1<<15 | 1<<9 | 7<<0));
9255 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9256 }
9257 if ((phy->req_line_speed == SPEED_10) &&
9258 (phy->supported &
9259 (SUPPORTED_10baseT_Half |
9260 SUPPORTED_10baseT_Full))) {
9261 /* Enabled AUTO-MDIX when autoneg is disabled */
9262 bnx2x_cl45_write(bp, phy,
9263 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9264 (1<<15 | 1<<9 | 7<<0));
9265 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9266 }
9267
9268 bnx2x_cl45_write(bp, phy,
9269 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9270 an_10_100_val);
9271
9272 if (phy->req_duplex == DUPLEX_FULL)
9273 autoneg_val |= (1<<8);
9274
9275 /*
9276 * Always write this if this is not 84833.
9277 * For 84833, write it only when it's a forced speed.
9278 */
9279 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9280 ((autoneg_val & (1<<12)) == 0))
9281 bnx2x_cl45_write(bp, phy,
9282 MDIO_AN_DEVAD,
9283 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9284
9285 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9286 (phy->speed_cap_mask &
9287 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9288 (phy->req_line_speed == SPEED_10000)) {
9289 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9290 /* Restart autoneg for 10G*/
9291
9292 bnx2x_cl45_write(bp, phy,
9293 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9294 0x3200);
9295 } else
9296 bnx2x_cl45_write(bp, phy,
9297 MDIO_AN_DEVAD,
9298 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9299 1);
9300
9301 /* Save spirom version */
9302 bnx2x_save_848xx_spirom_version(phy, params);
9303
9304 phy->req_line_speed = tmp_req_line_speed;
9305
9306 return 0;
9307 }
9308
9309 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9310 struct link_params *params,
9311 struct link_vars *vars)
9312 {
9313 struct bnx2x *bp = params->bp;
9314 /* Restore normal power mode*/
9315 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9316 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9317
9318 /* HW reset */
9319 bnx2x_ext_phy_hw_reset(bp, params->port);
9320 bnx2x_wait_reset_complete(bp, phy, params);
9321
9322 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9323 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9324 }
9325
9326
9327 #define PHY84833_HDSHK_WAIT 300
9328 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9329 struct link_params *params,
9330 struct link_vars *vars)
9331 {
9332 u32 idx;
9333 u32 pair_swap;
9334 u16 val;
9335 u16 data;
9336 struct bnx2x *bp = params->bp;
9337 /* Do pair swap */
9338
9339 /* Check for configuration. */
9340 pair_swap = REG_RD(bp, params->shmem_base +
9341 offsetof(struct shmem_region,
9342 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9343 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9344
9345 if (pair_swap == 0)
9346 return 0;
9347
9348 data = (u16)pair_swap;
9349
9350 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9351 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9352 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9353 PHY84833_CMD_OPEN_OVERRIDE);
9354 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9355 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9356 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9357 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9358 break;
9359 msleep(1);
9360 }
9361 if (idx >= PHY84833_HDSHK_WAIT) {
9362 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9363 return -EINVAL;
9364 }
9365
9366 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9367 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9368 data);
9369 /* Issue pair swap command */
9370 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9371 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9372 PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9373 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9374 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9375 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9376 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9377 (val == PHY84833_CMD_COMPLETE_ERROR))
9378 break;
9379 msleep(1);
9380 }
9381 if ((idx >= PHY84833_HDSHK_WAIT) ||
9382 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9383 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9384 return -EINVAL;
9385 }
9386 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9387 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9388 PHY84833_CMD_CLEAR_COMPLETE);
9389 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9390 return 0;
9391 }
9392
9393
9394 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9395 u32 shmem_base_path[],
9396 u32 chip_id)
9397 {
9398 u32 reset_pin[2];
9399 u32 idx;
9400 u8 reset_gpios;
9401 if (CHIP_IS_E3(bp)) {
9402 /* Assume that these will be GPIOs, not EPIOs. */
9403 for (idx = 0; idx < 2; idx++) {
9404 /* Map config param to register bit. */
9405 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9406 offsetof(struct shmem_region,
9407 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9408 reset_pin[idx] = (reset_pin[idx] &
9409 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9410 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9411 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9412 reset_pin[idx] = (1 << reset_pin[idx]);
9413 }
9414 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9415 } else {
9416 /* E2, look from diff place of shmem. */
9417 for (idx = 0; idx < 2; idx++) {
9418 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9419 offsetof(struct shmem_region,
9420 dev_info.port_hw_config[0].default_cfg));
9421 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9422 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9423 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9424 reset_pin[idx] = (1 << reset_pin[idx]);
9425 }
9426 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9427 }
9428
9429 return reset_gpios;
9430 }
9431
9432 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9433 struct link_params *params)
9434 {
9435 struct bnx2x *bp = params->bp;
9436 u8 reset_gpios;
9437 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9438 offsetof(struct shmem2_region,
9439 other_shmem_base_addr));
9440
9441 u32 shmem_base_path[2];
9442 shmem_base_path[0] = params->shmem_base;
9443 shmem_base_path[1] = other_shmem_base_addr;
9444
9445 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9446 params->chip_id);
9447
9448 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9449 udelay(10);
9450 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9451 reset_gpios);
9452
9453 return 0;
9454 }
9455
9456 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9457 u32 shmem_base_path[],
9458 u32 chip_id)
9459 {
9460 u8 reset_gpios;
9461
9462 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9463
9464 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9465 udelay(10);
9466 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9467 msleep(800);
9468 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9469 reset_gpios);
9470
9471 return 0;
9472 }
9473
9474 #define PHY84833_CONSTANT_LATENCY 1193
9475 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9476 struct link_params *params,
9477 struct link_vars *vars)
9478 {
9479 struct bnx2x *bp = params->bp;
9480 u8 port, initialize = 1;
9481 u16 val;
9482 u16 temp;
9483 u32 actual_phy_selection, cms_enable, idx;
9484 int rc = 0;
9485
9486 msleep(1);
9487
9488 if (!(CHIP_IS_E1(bp)))
9489 port = BP_PATH(bp);
9490 else
9491 port = params->port;
9492
9493 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9494 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9495 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9496 port);
9497 } else {
9498 /* MDIO reset */
9499 bnx2x_cl45_write(bp, phy,
9500 MDIO_PMA_DEVAD,
9501 MDIO_PMA_REG_CTRL, 0x8000);
9502 /* Bring PHY out of super isolate mode */
9503 bnx2x_cl45_read(bp, phy,
9504 MDIO_CTL_DEVAD,
9505 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9506 val &= ~MDIO_84833_SUPER_ISOLATE;
9507 bnx2x_cl45_write(bp, phy,
9508 MDIO_CTL_DEVAD,
9509 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9510 }
9511
9512 bnx2x_wait_reset_complete(bp, phy, params);
9513
9514 /* Wait for GPHY to come out of reset */
9515 msleep(50);
9516
9517 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9518 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9519
9520 /*
9521 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9522 */
9523 temp = vars->line_speed;
9524 vars->line_speed = SPEED_10000;
9525 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9526 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9527 vars->line_speed = temp;
9528
9529 /* Set dual-media configuration according to configuration */
9530
9531 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9532 MDIO_CTL_REG_84823_MEDIA, &val);
9533 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9534 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9535 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9536 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9537 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9538
9539 if (CHIP_IS_E3(bp)) {
9540 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9541 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9542 } else {
9543 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9544 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9545 }
9546
9547 actual_phy_selection = bnx2x_phy_selection(params);
9548
9549 switch (actual_phy_selection) {
9550 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9551 /* Do nothing. Essentially this is like the priority copper */
9552 break;
9553 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9554 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9555 break;
9556 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9557 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9558 break;
9559 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9560 /* Do nothing here. The first PHY won't be initialized at all */
9561 break;
9562 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9563 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9564 initialize = 0;
9565 break;
9566 }
9567 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9568 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9569
9570 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9571 MDIO_CTL_REG_84823_MEDIA, val);
9572 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9573 params->multi_phy_config, val);
9574
9575 /* AutogrEEEn */
9576 if (params->feature_config_flags &
9577 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9578 /* Ensure that f/w is ready */
9579 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9580 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9581 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9582 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9583 break;
9584 usleep_range(1000, 1000);
9585 }
9586 if (idx >= PHY84833_HDSHK_WAIT) {
9587 DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9588 return -EINVAL;
9589 }
9590
9591 /* Select EEE mode */
9592 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9593 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9594 0x2);
9595
9596 /* Set Idle and Latency */
9597 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9598 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9599 PHY84833_CONSTANT_LATENCY + 1);
9600
9601 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9602 MDIO_84833_TOP_CFG_DATA3_REG,
9603 PHY84833_CONSTANT_LATENCY + 1);
9604
9605 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9606 MDIO_84833_TOP_CFG_DATA4_REG,
9607 PHY84833_CONSTANT_LATENCY);
9608
9609 /* Send EEE instruction to command register */
9610 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9611 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9612 PHY84833_DIAG_CMD_SET_EEE_MODE);
9613
9614 /* Ensure that the command has completed */
9615 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9616 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9617 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9618 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9619 (val == PHY84833_CMD_COMPLETE_ERROR))
9620 break;
9621 usleep_range(1000, 1000);
9622 }
9623 if ((idx >= PHY84833_HDSHK_WAIT) ||
9624 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9625 DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9626 return -EINVAL;
9627 }
9628
9629 /* Reset command handler */
9630 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9631 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9632 PHY84833_CMD_CLEAR_COMPLETE);
9633 }
9634
9635 if (initialize)
9636 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9637 else
9638 bnx2x_save_848xx_spirom_version(phy, params);
9639 /* 84833 PHY has a better feature and doesn't need to support this. */
9640 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9641 cms_enable = REG_RD(bp, params->shmem_base +
9642 offsetof(struct shmem_region,
9643 dev_info.port_hw_config[params->port].default_cfg)) &
9644 PORT_HW_CFG_ENABLE_CMS_MASK;
9645
9646 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9647 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9648 if (cms_enable)
9649 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9650 else
9651 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9652 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9653 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9654 }
9655
9656 return rc;
9657 }
9658
9659 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9660 struct link_params *params,
9661 struct link_vars *vars)
9662 {
9663 struct bnx2x *bp = params->bp;
9664 u16 val, val1, val2;
9665 u8 link_up = 0;
9666
9667
9668 /* Check 10G-BaseT link status */
9669 /* Check PMD signal ok */
9670 bnx2x_cl45_read(bp, phy,
9671 MDIO_AN_DEVAD, 0xFFFA, &val1);
9672 bnx2x_cl45_read(bp, phy,
9673 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9674 &val2);
9675 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9676
9677 /* Check link 10G */
9678 if (val2 & (1<<11)) {
9679 vars->line_speed = SPEED_10000;
9680 vars->duplex = DUPLEX_FULL;
9681 link_up = 1;
9682 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9683 } else { /* Check Legacy speed link */
9684 u16 legacy_status, legacy_speed;
9685
9686 /* Enable expansion register 0x42 (Operation mode status) */
9687 bnx2x_cl45_write(bp, phy,
9688 MDIO_AN_DEVAD,
9689 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9690
9691 /* Get legacy speed operation status */
9692 bnx2x_cl45_read(bp, phy,
9693 MDIO_AN_DEVAD,
9694 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9695 &legacy_status);
9696
9697 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
9698 legacy_status);
9699 link_up = ((legacy_status & (1<<11)) == (1<<11));
9700 if (link_up) {
9701 legacy_speed = (legacy_status & (3<<9));
9702 if (legacy_speed == (0<<9))
9703 vars->line_speed = SPEED_10;
9704 else if (legacy_speed == (1<<9))
9705 vars->line_speed = SPEED_100;
9706 else if (legacy_speed == (2<<9))
9707 vars->line_speed = SPEED_1000;
9708 else /* Should not happen */
9709 vars->line_speed = 0;
9710
9711 if (legacy_status & (1<<8))
9712 vars->duplex = DUPLEX_FULL;
9713 else
9714 vars->duplex = DUPLEX_HALF;
9715
9716 DP(NETIF_MSG_LINK,
9717 "Link is up in %dMbps, is_duplex_full= %d\n",
9718 vars->line_speed,
9719 (vars->duplex == DUPLEX_FULL));
9720 /* Check legacy speed AN resolution */
9721 bnx2x_cl45_read(bp, phy,
9722 MDIO_AN_DEVAD,
9723 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9724 &val);
9725 if (val & (1<<5))
9726 vars->link_status |=
9727 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9728 bnx2x_cl45_read(bp, phy,
9729 MDIO_AN_DEVAD,
9730 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9731 &val);
9732 if ((val & (1<<0)) == 0)
9733 vars->link_status |=
9734 LINK_STATUS_PARALLEL_DETECTION_USED;
9735 }
9736 }
9737 if (link_up) {
9738 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9739 vars->line_speed);
9740 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9741 }
9742
9743 return link_up;
9744 }
9745
9746
9747 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9748 {
9749 int status = 0;
9750 u32 spirom_ver;
9751 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9752 status = bnx2x_format_ver(spirom_ver, str, len);
9753 return status;
9754 }
9755
9756 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9757 struct link_params *params)
9758 {
9759 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9760 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9761 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9762 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9763 }
9764
9765 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9766 struct link_params *params)
9767 {
9768 bnx2x_cl45_write(params->bp, phy,
9769 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9770 bnx2x_cl45_write(params->bp, phy,
9771 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9772 }
9773
9774 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9775 struct link_params *params)
9776 {
9777 struct bnx2x *bp = params->bp;
9778 u8 port;
9779 u16 val16;
9780
9781 if (!(CHIP_IS_E1(bp)))
9782 port = BP_PATH(bp);
9783 else
9784 port = params->port;
9785
9786 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9787 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9788 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9789 port);
9790 } else {
9791 bnx2x_cl45_read(bp, phy,
9792 MDIO_CTL_DEVAD,
9793 0x400f, &val16);
9794 bnx2x_cl45_write(bp, phy,
9795 MDIO_PMA_DEVAD,
9796 MDIO_PMA_REG_CTRL, 0x800);
9797 }
9798 }
9799
9800 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9801 struct link_params *params, u8 mode)
9802 {
9803 struct bnx2x *bp = params->bp;
9804 u16 val;
9805 u8 port;
9806
9807 if (!(CHIP_IS_E1(bp)))
9808 port = BP_PATH(bp);
9809 else
9810 port = params->port;
9811
9812 switch (mode) {
9813 case LED_MODE_OFF:
9814
9815 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9816
9817 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9818 SHARED_HW_CFG_LED_EXTPHY1) {
9819
9820 /* Set LED masks */
9821 bnx2x_cl45_write(bp, phy,
9822 MDIO_PMA_DEVAD,
9823 MDIO_PMA_REG_8481_LED1_MASK,
9824 0x0);
9825
9826 bnx2x_cl45_write(bp, phy,
9827 MDIO_PMA_DEVAD,
9828 MDIO_PMA_REG_8481_LED2_MASK,
9829 0x0);
9830
9831 bnx2x_cl45_write(bp, phy,
9832 MDIO_PMA_DEVAD,
9833 MDIO_PMA_REG_8481_LED3_MASK,
9834 0x0);
9835
9836 bnx2x_cl45_write(bp, phy,
9837 MDIO_PMA_DEVAD,
9838 MDIO_PMA_REG_8481_LED5_MASK,
9839 0x0);
9840
9841 } else {
9842 bnx2x_cl45_write(bp, phy,
9843 MDIO_PMA_DEVAD,
9844 MDIO_PMA_REG_8481_LED1_MASK,
9845 0x0);
9846 }
9847 break;
9848 case LED_MODE_FRONT_PANEL_OFF:
9849
9850 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9851 port);
9852
9853 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9854 SHARED_HW_CFG_LED_EXTPHY1) {
9855
9856 /* Set LED masks */
9857 bnx2x_cl45_write(bp, phy,
9858 MDIO_PMA_DEVAD,
9859 MDIO_PMA_REG_8481_LED1_MASK,
9860 0x0);
9861
9862 bnx2x_cl45_write(bp, phy,
9863 MDIO_PMA_DEVAD,
9864 MDIO_PMA_REG_8481_LED2_MASK,
9865 0x0);
9866
9867 bnx2x_cl45_write(bp, phy,
9868 MDIO_PMA_DEVAD,
9869 MDIO_PMA_REG_8481_LED3_MASK,
9870 0x0);
9871
9872 bnx2x_cl45_write(bp, phy,
9873 MDIO_PMA_DEVAD,
9874 MDIO_PMA_REG_8481_LED5_MASK,
9875 0x20);
9876
9877 } else {
9878 bnx2x_cl45_write(bp, phy,
9879 MDIO_PMA_DEVAD,
9880 MDIO_PMA_REG_8481_LED1_MASK,
9881 0x0);
9882 }
9883 break;
9884 case LED_MODE_ON:
9885
9886 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9887
9888 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9889 SHARED_HW_CFG_LED_EXTPHY1) {
9890 /* Set control reg */
9891 bnx2x_cl45_read(bp, phy,
9892 MDIO_PMA_DEVAD,
9893 MDIO_PMA_REG_8481_LINK_SIGNAL,
9894 &val);
9895 val &= 0x8000;
9896 val |= 0x2492;
9897
9898 bnx2x_cl45_write(bp, phy,
9899 MDIO_PMA_DEVAD,
9900 MDIO_PMA_REG_8481_LINK_SIGNAL,
9901 val);
9902
9903 /* Set LED masks */
9904 bnx2x_cl45_write(bp, phy,
9905 MDIO_PMA_DEVAD,
9906 MDIO_PMA_REG_8481_LED1_MASK,
9907 0x0);
9908
9909 bnx2x_cl45_write(bp, phy,
9910 MDIO_PMA_DEVAD,
9911 MDIO_PMA_REG_8481_LED2_MASK,
9912 0x20);
9913
9914 bnx2x_cl45_write(bp, phy,
9915 MDIO_PMA_DEVAD,
9916 MDIO_PMA_REG_8481_LED3_MASK,
9917 0x20);
9918
9919 bnx2x_cl45_write(bp, phy,
9920 MDIO_PMA_DEVAD,
9921 MDIO_PMA_REG_8481_LED5_MASK,
9922 0x0);
9923 } else {
9924 bnx2x_cl45_write(bp, phy,
9925 MDIO_PMA_DEVAD,
9926 MDIO_PMA_REG_8481_LED1_MASK,
9927 0x20);
9928 }
9929 break;
9930
9931 case LED_MODE_OPER:
9932
9933 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9934
9935 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9936 SHARED_HW_CFG_LED_EXTPHY1) {
9937
9938 /* Set control reg */
9939 bnx2x_cl45_read(bp, phy,
9940 MDIO_PMA_DEVAD,
9941 MDIO_PMA_REG_8481_LINK_SIGNAL,
9942 &val);
9943
9944 if (!((val &
9945 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9946 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9947 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9948 bnx2x_cl45_write(bp, phy,
9949 MDIO_PMA_DEVAD,
9950 MDIO_PMA_REG_8481_LINK_SIGNAL,
9951 0xa492);
9952 }
9953
9954 /* Set LED masks */
9955 bnx2x_cl45_write(bp, phy,
9956 MDIO_PMA_DEVAD,
9957 MDIO_PMA_REG_8481_LED1_MASK,
9958 0x10);
9959
9960 bnx2x_cl45_write(bp, phy,
9961 MDIO_PMA_DEVAD,
9962 MDIO_PMA_REG_8481_LED2_MASK,
9963 0x80);
9964
9965 bnx2x_cl45_write(bp, phy,
9966 MDIO_PMA_DEVAD,
9967 MDIO_PMA_REG_8481_LED3_MASK,
9968 0x98);
9969
9970 bnx2x_cl45_write(bp, phy,
9971 MDIO_PMA_DEVAD,
9972 MDIO_PMA_REG_8481_LED5_MASK,
9973 0x40);
9974
9975 } else {
9976 bnx2x_cl45_write(bp, phy,
9977 MDIO_PMA_DEVAD,
9978 MDIO_PMA_REG_8481_LED1_MASK,
9979 0x80);
9980
9981 /* Tell LED3 to blink on source */
9982 bnx2x_cl45_read(bp, phy,
9983 MDIO_PMA_DEVAD,
9984 MDIO_PMA_REG_8481_LINK_SIGNAL,
9985 &val);
9986 val &= ~(7<<6);
9987 val |= (1<<6); /* A83B[8:6]= 1 */
9988 bnx2x_cl45_write(bp, phy,
9989 MDIO_PMA_DEVAD,
9990 MDIO_PMA_REG_8481_LINK_SIGNAL,
9991 val);
9992 }
9993 break;
9994 }
9995
9996 /*
9997 * This is a workaround for E3+84833 until autoneg
9998 * restart is fixed in f/w
9999 */
10000 if (CHIP_IS_E3(bp)) {
10001 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10002 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10003 }
10004 }
10005
10006 /******************************************************************/
10007 /* 54618SE PHY SECTION */
10008 /******************************************************************/
10009 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10010 struct link_params *params,
10011 struct link_vars *vars)
10012 {
10013 struct bnx2x *bp = params->bp;
10014 u8 port;
10015 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10016 u32 cfg_pin;
10017
10018 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10019 usleep_range(1000, 1000);
10020
10021 /* This works with E3 only, no need to check the chip
10022 before determining the port. */
10023 port = params->port;
10024
10025 cfg_pin = (REG_RD(bp, params->shmem_base +
10026 offsetof(struct shmem_region,
10027 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10028 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10029 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10030
10031 /* Drive pin high to bring the GPHY out of reset. */
10032 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10033
10034 /* wait for GPHY to reset */
10035 msleep(50);
10036
10037 /* reset phy */
10038 bnx2x_cl22_write(bp, phy,
10039 MDIO_PMA_REG_CTRL, 0x8000);
10040 bnx2x_wait_reset_complete(bp, phy, params);
10041
10042 /*wait for GPHY to reset */
10043 msleep(50);
10044
10045 /* Configure LED4: set to INTR (0x6). */
10046 /* Accessing shadow register 0xe. */
10047 bnx2x_cl22_write(bp, phy,
10048 MDIO_REG_GPHY_SHADOW,
10049 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10050 bnx2x_cl22_read(bp, phy,
10051 MDIO_REG_GPHY_SHADOW,
10052 &temp);
10053 temp &= ~(0xf << 4);
10054 temp |= (0x6 << 4);
10055 bnx2x_cl22_write(bp, phy,
10056 MDIO_REG_GPHY_SHADOW,
10057 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10058 /* Configure INTR based on link status change. */
10059 bnx2x_cl22_write(bp, phy,
10060 MDIO_REG_INTR_MASK,
10061 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10062
10063 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10064 bnx2x_cl22_write(bp, phy,
10065 MDIO_REG_GPHY_SHADOW,
10066 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10067 bnx2x_cl22_read(bp, phy,
10068 MDIO_REG_GPHY_SHADOW,
10069 &temp);
10070 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10071 bnx2x_cl22_write(bp, phy,
10072 MDIO_REG_GPHY_SHADOW,
10073 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10074
10075 /* Set up fc */
10076 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10077 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10078 fc_val = 0;
10079 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10080 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10081 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10082
10083 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10084 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10085 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10086
10087 /* read all advertisement */
10088 bnx2x_cl22_read(bp, phy,
10089 0x09,
10090 &an_1000_val);
10091
10092 bnx2x_cl22_read(bp, phy,
10093 0x04,
10094 &an_10_100_val);
10095
10096 bnx2x_cl22_read(bp, phy,
10097 MDIO_PMA_REG_CTRL,
10098 &autoneg_val);
10099
10100 /* Disable forced speed */
10101 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10102 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10103 (1<<11));
10104
10105 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10106 (phy->speed_cap_mask &
10107 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10108 (phy->req_line_speed == SPEED_1000)) {
10109 an_1000_val |= (1<<8);
10110 autoneg_val |= (1<<9 | 1<<12);
10111 if (phy->req_duplex == DUPLEX_FULL)
10112 an_1000_val |= (1<<9);
10113 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10114 } else
10115 an_1000_val &= ~((1<<8) | (1<<9));
10116
10117 bnx2x_cl22_write(bp, phy,
10118 0x09,
10119 an_1000_val);
10120 bnx2x_cl22_read(bp, phy,
10121 0x09,
10122 &an_1000_val);
10123
10124 /* set 100 speed advertisement */
10125 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10126 (phy->speed_cap_mask &
10127 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10128 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10129 an_10_100_val |= (1<<7);
10130 /* Enable autoneg and restart autoneg for legacy speeds */
10131 autoneg_val |= (1<<9 | 1<<12);
10132
10133 if (phy->req_duplex == DUPLEX_FULL)
10134 an_10_100_val |= (1<<8);
10135 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10136 }
10137
10138 /* set 10 speed advertisement */
10139 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10140 (phy->speed_cap_mask &
10141 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10142 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10143 an_10_100_val |= (1<<5);
10144 autoneg_val |= (1<<9 | 1<<12);
10145 if (phy->req_duplex == DUPLEX_FULL)
10146 an_10_100_val |= (1<<6);
10147 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10148 }
10149
10150 /* Only 10/100 are allowed to work in FORCE mode */
10151 if (phy->req_line_speed == SPEED_100) {
10152 autoneg_val |= (1<<13);
10153 /* Enabled AUTO-MDIX when autoneg is disabled */
10154 bnx2x_cl22_write(bp, phy,
10155 0x18,
10156 (1<<15 | 1<<9 | 7<<0));
10157 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10158 }
10159 if (phy->req_line_speed == SPEED_10) {
10160 /* Enabled AUTO-MDIX when autoneg is disabled */
10161 bnx2x_cl22_write(bp, phy,
10162 0x18,
10163 (1<<15 | 1<<9 | 7<<0));
10164 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10165 }
10166
10167 /* Check if we should turn on Auto-GrEEEn */
10168 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10169 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10170 if (params->feature_config_flags &
10171 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10172 temp = 6;
10173 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10174 } else {
10175 temp = 0;
10176 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10177 }
10178 bnx2x_cl22_write(bp, phy,
10179 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10180 bnx2x_cl22_write(bp, phy,
10181 MDIO_REG_GPHY_CL45_DATA_REG,
10182 MDIO_REG_GPHY_EEE_ADV);
10183 bnx2x_cl22_write(bp, phy,
10184 MDIO_REG_GPHY_CL45_ADDR_REG,
10185 (0x1 << 14) | MDIO_AN_DEVAD);
10186 bnx2x_cl22_write(bp, phy,
10187 MDIO_REG_GPHY_CL45_DATA_REG,
10188 temp);
10189 }
10190
10191 bnx2x_cl22_write(bp, phy,
10192 0x04,
10193 an_10_100_val | fc_val);
10194
10195 if (phy->req_duplex == DUPLEX_FULL)
10196 autoneg_val |= (1<<8);
10197
10198 bnx2x_cl22_write(bp, phy,
10199 MDIO_PMA_REG_CTRL, autoneg_val);
10200
10201 return 0;
10202 }
10203
10204 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10205 struct link_params *params, u8 mode)
10206 {
10207 struct bnx2x *bp = params->bp;
10208 DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10209 switch (mode) {
10210 case LED_MODE_FRONT_PANEL_OFF:
10211 case LED_MODE_OFF:
10212 case LED_MODE_OPER:
10213 case LED_MODE_ON:
10214 default:
10215 break;
10216 }
10217 return;
10218 }
10219
10220 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10221 struct link_params *params)
10222 {
10223 struct bnx2x *bp = params->bp;
10224 u32 cfg_pin;
10225 u8 port;
10226
10227 /*
10228 * In case of no EPIO routed to reset the GPHY, put it
10229 * in low power mode.
10230 */
10231 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10232 /*
10233 * This works with E3 only, no need to check the chip
10234 * before determining the port.
10235 */
10236 port = params->port;
10237 cfg_pin = (REG_RD(bp, params->shmem_base +
10238 offsetof(struct shmem_region,
10239 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10240 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10241 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10242
10243 /* Drive pin low to put GPHY in reset. */
10244 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10245 }
10246
10247 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10248 struct link_params *params,
10249 struct link_vars *vars)
10250 {
10251 struct bnx2x *bp = params->bp;
10252 u16 val;
10253 u8 link_up = 0;
10254 u16 legacy_status, legacy_speed;
10255
10256 /* Get speed operation status */
10257 bnx2x_cl22_read(bp, phy,
10258 0x19,
10259 &legacy_status);
10260 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10261
10262 /* Read status to clear the PHY interrupt. */
10263 bnx2x_cl22_read(bp, phy,
10264 MDIO_REG_INTR_STATUS,
10265 &val);
10266
10267 link_up = ((legacy_status & (1<<2)) == (1<<2));
10268
10269 if (link_up) {
10270 legacy_speed = (legacy_status & (7<<8));
10271 if (legacy_speed == (7<<8)) {
10272 vars->line_speed = SPEED_1000;
10273 vars->duplex = DUPLEX_FULL;
10274 } else if (legacy_speed == (6<<8)) {
10275 vars->line_speed = SPEED_1000;
10276 vars->duplex = DUPLEX_HALF;
10277 } else if (legacy_speed == (5<<8)) {
10278 vars->line_speed = SPEED_100;
10279 vars->duplex = DUPLEX_FULL;
10280 }
10281 /* Omitting 100Base-T4 for now */
10282 else if (legacy_speed == (3<<8)) {
10283 vars->line_speed = SPEED_100;
10284 vars->duplex = DUPLEX_HALF;
10285 } else if (legacy_speed == (2<<8)) {
10286 vars->line_speed = SPEED_10;
10287 vars->duplex = DUPLEX_FULL;
10288 } else if (legacy_speed == (1<<8)) {
10289 vars->line_speed = SPEED_10;
10290 vars->duplex = DUPLEX_HALF;
10291 } else /* Should not happen */
10292 vars->line_speed = 0;
10293
10294 DP(NETIF_MSG_LINK,
10295 "Link is up in %dMbps, is_duplex_full= %d\n",
10296 vars->line_speed,
10297 (vars->duplex == DUPLEX_FULL));
10298
10299 /* Check legacy speed AN resolution */
10300 bnx2x_cl22_read(bp, phy,
10301 0x01,
10302 &val);
10303 if (val & (1<<5))
10304 vars->link_status |=
10305 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10306 bnx2x_cl22_read(bp, phy,
10307 0x06,
10308 &val);
10309 if ((val & (1<<0)) == 0)
10310 vars->link_status |=
10311 LINK_STATUS_PARALLEL_DETECTION_USED;
10312
10313 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10314 vars->line_speed);
10315
10316 /* Report whether EEE is resolved. */
10317 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10318 if (val == MDIO_REG_GPHY_ID_54618SE) {
10319 if (vars->link_status &
10320 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10321 val = 0;
10322 else {
10323 bnx2x_cl22_write(bp, phy,
10324 MDIO_REG_GPHY_CL45_ADDR_REG,
10325 MDIO_AN_DEVAD);
10326 bnx2x_cl22_write(bp, phy,
10327 MDIO_REG_GPHY_CL45_DATA_REG,
10328 MDIO_REG_GPHY_EEE_RESOLVED);
10329 bnx2x_cl22_write(bp, phy,
10330 MDIO_REG_GPHY_CL45_ADDR_REG,
10331 (0x1 << 14) | MDIO_AN_DEVAD);
10332 bnx2x_cl22_read(bp, phy,
10333 MDIO_REG_GPHY_CL45_DATA_REG,
10334 &val);
10335 }
10336 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10337 }
10338
10339 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10340 }
10341 return link_up;
10342 }
10343
10344 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10345 struct link_params *params)
10346 {
10347 struct bnx2x *bp = params->bp;
10348 u16 val;
10349 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10350
10351 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10352
10353 /* Enable master/slave manual mmode and set to master */
10354 /* mii write 9 [bits set 11 12] */
10355 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10356
10357 /* forced 1G and disable autoneg */
10358 /* set val [mii read 0] */
10359 /* set val [expr $val & [bits clear 6 12 13]] */
10360 /* set val [expr $val | [bits set 6 8]] */
10361 /* mii write 0 $val */
10362 bnx2x_cl22_read(bp, phy, 0x00, &val);
10363 val &= ~((1<<6) | (1<<12) | (1<<13));
10364 val |= (1<<6) | (1<<8);
10365 bnx2x_cl22_write(bp, phy, 0x00, val);
10366
10367 /* Set external loopback and Tx using 6dB coding */
10368 /* mii write 0x18 7 */
10369 /* set val [mii read 0x18] */
10370 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10371 bnx2x_cl22_write(bp, phy, 0x18, 7);
10372 bnx2x_cl22_read(bp, phy, 0x18, &val);
10373 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10374
10375 /* This register opens the gate for the UMAC despite its name */
10376 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10377
10378 /*
10379 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10380 * length used by the MAC receive logic to check frames.
10381 */
10382 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10383 }
10384
10385 /******************************************************************/
10386 /* SFX7101 PHY SECTION */
10387 /******************************************************************/
10388 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10389 struct link_params *params)
10390 {
10391 struct bnx2x *bp = params->bp;
10392 /* SFX7101_XGXS_TEST1 */
10393 bnx2x_cl45_write(bp, phy,
10394 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10395 }
10396
10397 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10398 struct link_params *params,
10399 struct link_vars *vars)
10400 {
10401 u16 fw_ver1, fw_ver2, val;
10402 struct bnx2x *bp = params->bp;
10403 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10404
10405 /* Restore normal power mode*/
10406 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10407 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10408 /* HW reset */
10409 bnx2x_ext_phy_hw_reset(bp, params->port);
10410 bnx2x_wait_reset_complete(bp, phy, params);
10411
10412 bnx2x_cl45_write(bp, phy,
10413 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10414 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10415 bnx2x_cl45_write(bp, phy,
10416 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10417
10418 bnx2x_ext_phy_set_pause(params, phy, vars);
10419 /* Restart autoneg */
10420 bnx2x_cl45_read(bp, phy,
10421 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10422 val |= 0x200;
10423 bnx2x_cl45_write(bp, phy,
10424 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10425
10426 /* Save spirom version */
10427 bnx2x_cl45_read(bp, phy,
10428 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10429
10430 bnx2x_cl45_read(bp, phy,
10431 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10432 bnx2x_save_spirom_version(bp, params->port,
10433 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10434 return 0;
10435 }
10436
10437 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10438 struct link_params *params,
10439 struct link_vars *vars)
10440 {
10441 struct bnx2x *bp = params->bp;
10442 u8 link_up;
10443 u16 val1, val2;
10444 bnx2x_cl45_read(bp, phy,
10445 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10446 bnx2x_cl45_read(bp, phy,
10447 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10448 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10449 val2, val1);
10450 bnx2x_cl45_read(bp, phy,
10451 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10452 bnx2x_cl45_read(bp, phy,
10453 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10454 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10455 val2, val1);
10456 link_up = ((val1 & 4) == 4);
10457 /* if link is up print the AN outcome of the SFX7101 PHY */
10458 if (link_up) {
10459 bnx2x_cl45_read(bp, phy,
10460 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10461 &val2);
10462 vars->line_speed = SPEED_10000;
10463 vars->duplex = DUPLEX_FULL;
10464 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10465 val2, (val2 & (1<<14)));
10466 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10467 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10468 }
10469 return link_up;
10470 }
10471
10472 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10473 {
10474 if (*len < 5)
10475 return -EINVAL;
10476 str[0] = (spirom_ver & 0xFF);
10477 str[1] = (spirom_ver & 0xFF00) >> 8;
10478 str[2] = (spirom_ver & 0xFF0000) >> 16;
10479 str[3] = (spirom_ver & 0xFF000000) >> 24;
10480 str[4] = '\0';
10481 *len -= 5;
10482 return 0;
10483 }
10484
10485 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10486 {
10487 u16 val, cnt;
10488
10489 bnx2x_cl45_read(bp, phy,
10490 MDIO_PMA_DEVAD,
10491 MDIO_PMA_REG_7101_RESET, &val);
10492
10493 for (cnt = 0; cnt < 10; cnt++) {
10494 msleep(50);
10495 /* Writes a self-clearing reset */
10496 bnx2x_cl45_write(bp, phy,
10497 MDIO_PMA_DEVAD,
10498 MDIO_PMA_REG_7101_RESET,
10499 (val | (1<<15)));
10500 /* Wait for clear */
10501 bnx2x_cl45_read(bp, phy,
10502 MDIO_PMA_DEVAD,
10503 MDIO_PMA_REG_7101_RESET, &val);
10504
10505 if ((val & (1<<15)) == 0)
10506 break;
10507 }
10508 }
10509
10510 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10511 struct link_params *params) {
10512 /* Low power mode is controlled by GPIO 2 */
10513 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10514 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10515 /* The PHY reset is controlled by GPIO 1 */
10516 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10517 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10518 }
10519
10520 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10521 struct link_params *params, u8 mode)
10522 {
10523 u16 val = 0;
10524 struct bnx2x *bp = params->bp;
10525 switch (mode) {
10526 case LED_MODE_FRONT_PANEL_OFF:
10527 case LED_MODE_OFF:
10528 val = 2;
10529 break;
10530 case LED_MODE_ON:
10531 val = 1;
10532 break;
10533 case LED_MODE_OPER:
10534 val = 0;
10535 break;
10536 }
10537 bnx2x_cl45_write(bp, phy,
10538 MDIO_PMA_DEVAD,
10539 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10540 val);
10541 }
10542
10543 /******************************************************************/
10544 /* STATIC PHY DECLARATION */
10545 /******************************************************************/
10546
10547 static struct bnx2x_phy phy_null = {
10548 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10549 .addr = 0,
10550 .def_md_devad = 0,
10551 .flags = FLAGS_INIT_XGXS_FIRST,
10552 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10553 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10554 .mdio_ctrl = 0,
10555 .supported = 0,
10556 .media_type = ETH_PHY_NOT_PRESENT,
10557 .ver_addr = 0,
10558 .req_flow_ctrl = 0,
10559 .req_line_speed = 0,
10560 .speed_cap_mask = 0,
10561 .req_duplex = 0,
10562 .rsrv = 0,
10563 .config_init = (config_init_t)NULL,
10564 .read_status = (read_status_t)NULL,
10565 .link_reset = (link_reset_t)NULL,
10566 .config_loopback = (config_loopback_t)NULL,
10567 .format_fw_ver = (format_fw_ver_t)NULL,
10568 .hw_reset = (hw_reset_t)NULL,
10569 .set_link_led = (set_link_led_t)NULL,
10570 .phy_specific_func = (phy_specific_func_t)NULL
10571 };
10572
10573 static struct bnx2x_phy phy_serdes = {
10574 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10575 .addr = 0xff,
10576 .def_md_devad = 0,
10577 .flags = 0,
10578 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10579 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10580 .mdio_ctrl = 0,
10581 .supported = (SUPPORTED_10baseT_Half |
10582 SUPPORTED_10baseT_Full |
10583 SUPPORTED_100baseT_Half |
10584 SUPPORTED_100baseT_Full |
10585 SUPPORTED_1000baseT_Full |
10586 SUPPORTED_2500baseX_Full |
10587 SUPPORTED_TP |
10588 SUPPORTED_Autoneg |
10589 SUPPORTED_Pause |
10590 SUPPORTED_Asym_Pause),
10591 .media_type = ETH_PHY_BASE_T,
10592 .ver_addr = 0,
10593 .req_flow_ctrl = 0,
10594 .req_line_speed = 0,
10595 .speed_cap_mask = 0,
10596 .req_duplex = 0,
10597 .rsrv = 0,
10598 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10599 .read_status = (read_status_t)bnx2x_link_settings_status,
10600 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10601 .config_loopback = (config_loopback_t)NULL,
10602 .format_fw_ver = (format_fw_ver_t)NULL,
10603 .hw_reset = (hw_reset_t)NULL,
10604 .set_link_led = (set_link_led_t)NULL,
10605 .phy_specific_func = (phy_specific_func_t)NULL
10606 };
10607
10608 static struct bnx2x_phy phy_xgxs = {
10609 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10610 .addr = 0xff,
10611 .def_md_devad = 0,
10612 .flags = 0,
10613 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10614 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10615 .mdio_ctrl = 0,
10616 .supported = (SUPPORTED_10baseT_Half |
10617 SUPPORTED_10baseT_Full |
10618 SUPPORTED_100baseT_Half |
10619 SUPPORTED_100baseT_Full |
10620 SUPPORTED_1000baseT_Full |
10621 SUPPORTED_2500baseX_Full |
10622 SUPPORTED_10000baseT_Full |
10623 SUPPORTED_FIBRE |
10624 SUPPORTED_Autoneg |
10625 SUPPORTED_Pause |
10626 SUPPORTED_Asym_Pause),
10627 .media_type = ETH_PHY_CX4,
10628 .ver_addr = 0,
10629 .req_flow_ctrl = 0,
10630 .req_line_speed = 0,
10631 .speed_cap_mask = 0,
10632 .req_duplex = 0,
10633 .rsrv = 0,
10634 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10635 .read_status = (read_status_t)bnx2x_link_settings_status,
10636 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10637 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10638 .format_fw_ver = (format_fw_ver_t)NULL,
10639 .hw_reset = (hw_reset_t)NULL,
10640 .set_link_led = (set_link_led_t)NULL,
10641 .phy_specific_func = (phy_specific_func_t)NULL
10642 };
10643 static struct bnx2x_phy phy_warpcore = {
10644 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10645 .addr = 0xff,
10646 .def_md_devad = 0,
10647 .flags = (FLAGS_HW_LOCK_REQUIRED |
10648 FLAGS_TX_ERROR_CHECK),
10649 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10650 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10651 .mdio_ctrl = 0,
10652 .supported = (SUPPORTED_10baseT_Half |
10653 SUPPORTED_10baseT_Full |
10654 SUPPORTED_100baseT_Half |
10655 SUPPORTED_100baseT_Full |
10656 SUPPORTED_1000baseT_Full |
10657 SUPPORTED_10000baseT_Full |
10658 SUPPORTED_20000baseKR2_Full |
10659 SUPPORTED_20000baseMLD2_Full |
10660 SUPPORTED_FIBRE |
10661 SUPPORTED_Autoneg |
10662 SUPPORTED_Pause |
10663 SUPPORTED_Asym_Pause),
10664 .media_type = ETH_PHY_UNSPECIFIED,
10665 .ver_addr = 0,
10666 .req_flow_ctrl = 0,
10667 .req_line_speed = 0,
10668 .speed_cap_mask = 0,
10669 /* req_duplex = */0,
10670 /* rsrv = */0,
10671 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10672 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10673 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10674 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10675 .format_fw_ver = (format_fw_ver_t)NULL,
10676 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
10677 .set_link_led = (set_link_led_t)NULL,
10678 .phy_specific_func = (phy_specific_func_t)NULL
10679 };
10680
10681
10682 static struct bnx2x_phy phy_7101 = {
10683 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10684 .addr = 0xff,
10685 .def_md_devad = 0,
10686 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10687 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10688 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10689 .mdio_ctrl = 0,
10690 .supported = (SUPPORTED_10000baseT_Full |
10691 SUPPORTED_TP |
10692 SUPPORTED_Autoneg |
10693 SUPPORTED_Pause |
10694 SUPPORTED_Asym_Pause),
10695 .media_type = ETH_PHY_BASE_T,
10696 .ver_addr = 0,
10697 .req_flow_ctrl = 0,
10698 .req_line_speed = 0,
10699 .speed_cap_mask = 0,
10700 .req_duplex = 0,
10701 .rsrv = 0,
10702 .config_init = (config_init_t)bnx2x_7101_config_init,
10703 .read_status = (read_status_t)bnx2x_7101_read_status,
10704 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10705 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10706 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10707 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10708 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10709 .phy_specific_func = (phy_specific_func_t)NULL
10710 };
10711 static struct bnx2x_phy phy_8073 = {
10712 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10713 .addr = 0xff,
10714 .def_md_devad = 0,
10715 .flags = FLAGS_HW_LOCK_REQUIRED,
10716 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10717 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10718 .mdio_ctrl = 0,
10719 .supported = (SUPPORTED_10000baseT_Full |
10720 SUPPORTED_2500baseX_Full |
10721 SUPPORTED_1000baseT_Full |
10722 SUPPORTED_FIBRE |
10723 SUPPORTED_Autoneg |
10724 SUPPORTED_Pause |
10725 SUPPORTED_Asym_Pause),
10726 .media_type = ETH_PHY_KR,
10727 .ver_addr = 0,
10728 .req_flow_ctrl = 0,
10729 .req_line_speed = 0,
10730 .speed_cap_mask = 0,
10731 .req_duplex = 0,
10732 .rsrv = 0,
10733 .config_init = (config_init_t)bnx2x_8073_config_init,
10734 .read_status = (read_status_t)bnx2x_8073_read_status,
10735 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10736 .config_loopback = (config_loopback_t)NULL,
10737 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10738 .hw_reset = (hw_reset_t)NULL,
10739 .set_link_led = (set_link_led_t)NULL,
10740 .phy_specific_func = (phy_specific_func_t)NULL
10741 };
10742 static struct bnx2x_phy phy_8705 = {
10743 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10744 .addr = 0xff,
10745 .def_md_devad = 0,
10746 .flags = FLAGS_INIT_XGXS_FIRST,
10747 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10748 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10749 .mdio_ctrl = 0,
10750 .supported = (SUPPORTED_10000baseT_Full |
10751 SUPPORTED_FIBRE |
10752 SUPPORTED_Pause |
10753 SUPPORTED_Asym_Pause),
10754 .media_type = ETH_PHY_XFP_FIBER,
10755 .ver_addr = 0,
10756 .req_flow_ctrl = 0,
10757 .req_line_speed = 0,
10758 .speed_cap_mask = 0,
10759 .req_duplex = 0,
10760 .rsrv = 0,
10761 .config_init = (config_init_t)bnx2x_8705_config_init,
10762 .read_status = (read_status_t)bnx2x_8705_read_status,
10763 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10764 .config_loopback = (config_loopback_t)NULL,
10765 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
10766 .hw_reset = (hw_reset_t)NULL,
10767 .set_link_led = (set_link_led_t)NULL,
10768 .phy_specific_func = (phy_specific_func_t)NULL
10769 };
10770 static struct bnx2x_phy phy_8706 = {
10771 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10772 .addr = 0xff,
10773 .def_md_devad = 0,
10774 .flags = (FLAGS_INIT_XGXS_FIRST |
10775 FLAGS_TX_ERROR_CHECK),
10776 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10777 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10778 .mdio_ctrl = 0,
10779 .supported = (SUPPORTED_10000baseT_Full |
10780 SUPPORTED_1000baseT_Full |
10781 SUPPORTED_FIBRE |
10782 SUPPORTED_Pause |
10783 SUPPORTED_Asym_Pause),
10784 .media_type = ETH_PHY_SFP_FIBER,
10785 .ver_addr = 0,
10786 .req_flow_ctrl = 0,
10787 .req_line_speed = 0,
10788 .speed_cap_mask = 0,
10789 .req_duplex = 0,
10790 .rsrv = 0,
10791 .config_init = (config_init_t)bnx2x_8706_config_init,
10792 .read_status = (read_status_t)bnx2x_8706_read_status,
10793 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10794 .config_loopback = (config_loopback_t)NULL,
10795 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10796 .hw_reset = (hw_reset_t)NULL,
10797 .set_link_led = (set_link_led_t)NULL,
10798 .phy_specific_func = (phy_specific_func_t)NULL
10799 };
10800
10801 static struct bnx2x_phy phy_8726 = {
10802 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10803 .addr = 0xff,
10804 .def_md_devad = 0,
10805 .flags = (FLAGS_HW_LOCK_REQUIRED |
10806 FLAGS_INIT_XGXS_FIRST |
10807 FLAGS_TX_ERROR_CHECK),
10808 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10809 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10810 .mdio_ctrl = 0,
10811 .supported = (SUPPORTED_10000baseT_Full |
10812 SUPPORTED_1000baseT_Full |
10813 SUPPORTED_Autoneg |
10814 SUPPORTED_FIBRE |
10815 SUPPORTED_Pause |
10816 SUPPORTED_Asym_Pause),
10817 .media_type = ETH_PHY_NOT_PRESENT,
10818 .ver_addr = 0,
10819 .req_flow_ctrl = 0,
10820 .req_line_speed = 0,
10821 .speed_cap_mask = 0,
10822 .req_duplex = 0,
10823 .rsrv = 0,
10824 .config_init = (config_init_t)bnx2x_8726_config_init,
10825 .read_status = (read_status_t)bnx2x_8726_read_status,
10826 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
10827 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10828 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10829 .hw_reset = (hw_reset_t)NULL,
10830 .set_link_led = (set_link_led_t)NULL,
10831 .phy_specific_func = (phy_specific_func_t)NULL
10832 };
10833
10834 static struct bnx2x_phy phy_8727 = {
10835 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10836 .addr = 0xff,
10837 .def_md_devad = 0,
10838 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
10839 FLAGS_TX_ERROR_CHECK),
10840 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10841 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10842 .mdio_ctrl = 0,
10843 .supported = (SUPPORTED_10000baseT_Full |
10844 SUPPORTED_1000baseT_Full |
10845 SUPPORTED_FIBRE |
10846 SUPPORTED_Pause |
10847 SUPPORTED_Asym_Pause),
10848 .media_type = ETH_PHY_NOT_PRESENT,
10849 .ver_addr = 0,
10850 .req_flow_ctrl = 0,
10851 .req_line_speed = 0,
10852 .speed_cap_mask = 0,
10853 .req_duplex = 0,
10854 .rsrv = 0,
10855 .config_init = (config_init_t)bnx2x_8727_config_init,
10856 .read_status = (read_status_t)bnx2x_8727_read_status,
10857 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
10858 .config_loopback = (config_loopback_t)NULL,
10859 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10860 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
10861 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
10862 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10863 };
10864 static struct bnx2x_phy phy_8481 = {
10865 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10866 .addr = 0xff,
10867 .def_md_devad = 0,
10868 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10869 FLAGS_REARM_LATCH_SIGNAL,
10870 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10871 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10872 .mdio_ctrl = 0,
10873 .supported = (SUPPORTED_10baseT_Half |
10874 SUPPORTED_10baseT_Full |
10875 SUPPORTED_100baseT_Half |
10876 SUPPORTED_100baseT_Full |
10877 SUPPORTED_1000baseT_Full |
10878 SUPPORTED_10000baseT_Full |
10879 SUPPORTED_TP |
10880 SUPPORTED_Autoneg |
10881 SUPPORTED_Pause |
10882 SUPPORTED_Asym_Pause),
10883 .media_type = ETH_PHY_BASE_T,
10884 .ver_addr = 0,
10885 .req_flow_ctrl = 0,
10886 .req_line_speed = 0,
10887 .speed_cap_mask = 0,
10888 .req_duplex = 0,
10889 .rsrv = 0,
10890 .config_init = (config_init_t)bnx2x_8481_config_init,
10891 .read_status = (read_status_t)bnx2x_848xx_read_status,
10892 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
10893 .config_loopback = (config_loopback_t)NULL,
10894 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10895 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
10896 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10897 .phy_specific_func = (phy_specific_func_t)NULL
10898 };
10899
10900 static struct bnx2x_phy phy_84823 = {
10901 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10902 .addr = 0xff,
10903 .def_md_devad = 0,
10904 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10905 FLAGS_REARM_LATCH_SIGNAL,
10906 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10907 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10908 .mdio_ctrl = 0,
10909 .supported = (SUPPORTED_10baseT_Half |
10910 SUPPORTED_10baseT_Full |
10911 SUPPORTED_100baseT_Half |
10912 SUPPORTED_100baseT_Full |
10913 SUPPORTED_1000baseT_Full |
10914 SUPPORTED_10000baseT_Full |
10915 SUPPORTED_TP |
10916 SUPPORTED_Autoneg |
10917 SUPPORTED_Pause |
10918 SUPPORTED_Asym_Pause),
10919 .media_type = ETH_PHY_BASE_T,
10920 .ver_addr = 0,
10921 .req_flow_ctrl = 0,
10922 .req_line_speed = 0,
10923 .speed_cap_mask = 0,
10924 .req_duplex = 0,
10925 .rsrv = 0,
10926 .config_init = (config_init_t)bnx2x_848x3_config_init,
10927 .read_status = (read_status_t)bnx2x_848xx_read_status,
10928 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10929 .config_loopback = (config_loopback_t)NULL,
10930 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10931 .hw_reset = (hw_reset_t)NULL,
10932 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10933 .phy_specific_func = (phy_specific_func_t)NULL
10934 };
10935
10936 static struct bnx2x_phy phy_84833 = {
10937 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10938 .addr = 0xff,
10939 .def_md_devad = 0,
10940 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10941 FLAGS_REARM_LATCH_SIGNAL,
10942 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10943 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10944 .mdio_ctrl = 0,
10945 .supported = (SUPPORTED_100baseT_Half |
10946 SUPPORTED_100baseT_Full |
10947 SUPPORTED_1000baseT_Full |
10948 SUPPORTED_10000baseT_Full |
10949 SUPPORTED_TP |
10950 SUPPORTED_Autoneg |
10951 SUPPORTED_Pause |
10952 SUPPORTED_Asym_Pause),
10953 .media_type = ETH_PHY_BASE_T,
10954 .ver_addr = 0,
10955 .req_flow_ctrl = 0,
10956 .req_line_speed = 0,
10957 .speed_cap_mask = 0,
10958 .req_duplex = 0,
10959 .rsrv = 0,
10960 .config_init = (config_init_t)bnx2x_848x3_config_init,
10961 .read_status = (read_status_t)bnx2x_848xx_read_status,
10962 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10963 .config_loopback = (config_loopback_t)NULL,
10964 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10965 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10966 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10967 .phy_specific_func = (phy_specific_func_t)NULL
10968 };
10969
10970 static struct bnx2x_phy phy_54618se = {
10971 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10972 .addr = 0xff,
10973 .def_md_devad = 0,
10974 .flags = FLAGS_INIT_XGXS_FIRST,
10975 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10976 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10977 .mdio_ctrl = 0,
10978 .supported = (SUPPORTED_10baseT_Half |
10979 SUPPORTED_10baseT_Full |
10980 SUPPORTED_100baseT_Half |
10981 SUPPORTED_100baseT_Full |
10982 SUPPORTED_1000baseT_Full |
10983 SUPPORTED_TP |
10984 SUPPORTED_Autoneg |
10985 SUPPORTED_Pause |
10986 SUPPORTED_Asym_Pause),
10987 .media_type = ETH_PHY_BASE_T,
10988 .ver_addr = 0,
10989 .req_flow_ctrl = 0,
10990 .req_line_speed = 0,
10991 .speed_cap_mask = 0,
10992 /* req_duplex = */0,
10993 /* rsrv = */0,
10994 .config_init = (config_init_t)bnx2x_54618se_config_init,
10995 .read_status = (read_status_t)bnx2x_54618se_read_status,
10996 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
10997 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10998 .format_fw_ver = (format_fw_ver_t)NULL,
10999 .hw_reset = (hw_reset_t)NULL,
11000 .set_link_led = (set_link_led_t)bnx2x_54618se_set_link_led,
11001 .phy_specific_func = (phy_specific_func_t)NULL
11002 };
11003 /*****************************************************************/
11004 /* */
11005 /* Populate the phy according. Main function: bnx2x_populate_phy */
11006 /* */
11007 /*****************************************************************/
11008
11009 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11010 struct bnx2x_phy *phy, u8 port,
11011 u8 phy_index)
11012 {
11013 /* Get the 4 lanes xgxs config rx and tx */
11014 u32 rx = 0, tx = 0, i;
11015 for (i = 0; i < 2; i++) {
11016 /*
11017 * INT_PHY and EXT_PHY1 share the same value location in the
11018 * shmem. When num_phys is greater than 1, than this value
11019 * applies only to EXT_PHY1
11020 */
11021 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11022 rx = REG_RD(bp, shmem_base +
11023 offsetof(struct shmem_region,
11024 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11025
11026 tx = REG_RD(bp, shmem_base +
11027 offsetof(struct shmem_region,
11028 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11029 } else {
11030 rx = REG_RD(bp, shmem_base +
11031 offsetof(struct shmem_region,
11032 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11033
11034 tx = REG_RD(bp, shmem_base +
11035 offsetof(struct shmem_region,
11036 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11037 }
11038
11039 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11040 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11041
11042 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11043 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11044 }
11045 }
11046
11047 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11048 u8 phy_index, u8 port)
11049 {
11050 u32 ext_phy_config = 0;
11051 switch (phy_index) {
11052 case EXT_PHY1:
11053 ext_phy_config = REG_RD(bp, shmem_base +
11054 offsetof(struct shmem_region,
11055 dev_info.port_hw_config[port].external_phy_config));
11056 break;
11057 case EXT_PHY2:
11058 ext_phy_config = REG_RD(bp, shmem_base +
11059 offsetof(struct shmem_region,
11060 dev_info.port_hw_config[port].external_phy_config2));
11061 break;
11062 default:
11063 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11064 return -EINVAL;
11065 }
11066
11067 return ext_phy_config;
11068 }
11069 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11070 struct bnx2x_phy *phy)
11071 {
11072 u32 phy_addr;
11073 u32 chip_id;
11074 u32 switch_cfg = (REG_RD(bp, shmem_base +
11075 offsetof(struct shmem_region,
11076 dev_info.port_feature_config[port].link_config)) &
11077 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11078 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11079 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11080 if (USES_WARPCORE(bp)) {
11081 u32 serdes_net_if;
11082 phy_addr = REG_RD(bp,
11083 MISC_REG_WC0_CTRL_PHY_ADDR);
11084 *phy = phy_warpcore;
11085 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11086 phy->flags |= FLAGS_4_PORT_MODE;
11087 else
11088 phy->flags &= ~FLAGS_4_PORT_MODE;
11089 /* Check Dual mode */
11090 serdes_net_if = (REG_RD(bp, shmem_base +
11091 offsetof(struct shmem_region, dev_info.
11092 port_hw_config[port].default_cfg)) &
11093 PORT_HW_CFG_NET_SERDES_IF_MASK);
11094 /*
11095 * Set the appropriate supported and flags indications per
11096 * interface type of the chip
11097 */
11098 switch (serdes_net_if) {
11099 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11100 phy->supported &= (SUPPORTED_10baseT_Half |
11101 SUPPORTED_10baseT_Full |
11102 SUPPORTED_100baseT_Half |
11103 SUPPORTED_100baseT_Full |
11104 SUPPORTED_1000baseT_Full |
11105 SUPPORTED_FIBRE |
11106 SUPPORTED_Autoneg |
11107 SUPPORTED_Pause |
11108 SUPPORTED_Asym_Pause);
11109 phy->media_type = ETH_PHY_BASE_T;
11110 break;
11111 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11112 phy->media_type = ETH_PHY_XFP_FIBER;
11113 break;
11114 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11115 phy->supported &= (SUPPORTED_1000baseT_Full |
11116 SUPPORTED_10000baseT_Full |
11117 SUPPORTED_FIBRE |
11118 SUPPORTED_Pause |
11119 SUPPORTED_Asym_Pause);
11120 phy->media_type = ETH_PHY_SFP_FIBER;
11121 break;
11122 case PORT_HW_CFG_NET_SERDES_IF_KR:
11123 phy->media_type = ETH_PHY_KR;
11124 phy->supported &= (SUPPORTED_1000baseT_Full |
11125 SUPPORTED_10000baseT_Full |
11126 SUPPORTED_FIBRE |
11127 SUPPORTED_Autoneg |
11128 SUPPORTED_Pause |
11129 SUPPORTED_Asym_Pause);
11130 break;
11131 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11132 phy->media_type = ETH_PHY_KR;
11133 phy->flags |= FLAGS_WC_DUAL_MODE;
11134 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11135 SUPPORTED_FIBRE |
11136 SUPPORTED_Pause |
11137 SUPPORTED_Asym_Pause);
11138 break;
11139 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11140 phy->media_type = ETH_PHY_KR;
11141 phy->flags |= FLAGS_WC_DUAL_MODE;
11142 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11143 SUPPORTED_FIBRE |
11144 SUPPORTED_Pause |
11145 SUPPORTED_Asym_Pause);
11146 break;
11147 default:
11148 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11149 serdes_net_if);
11150 break;
11151 }
11152
11153 /*
11154 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11155 * was not set as expected. For B0, ECO will be enabled so there
11156 * won't be an issue there
11157 */
11158 if (CHIP_REV(bp) == CHIP_REV_Ax)
11159 phy->flags |= FLAGS_MDC_MDIO_WA;
11160 else
11161 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11162 } else {
11163 switch (switch_cfg) {
11164 case SWITCH_CFG_1G:
11165 phy_addr = REG_RD(bp,
11166 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11167 port * 0x10);
11168 *phy = phy_serdes;
11169 break;
11170 case SWITCH_CFG_10G:
11171 phy_addr = REG_RD(bp,
11172 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11173 port * 0x18);
11174 *phy = phy_xgxs;
11175 break;
11176 default:
11177 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11178 return -EINVAL;
11179 }
11180 }
11181 phy->addr = (u8)phy_addr;
11182 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11183 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11184 port);
11185 if (CHIP_IS_E2(bp))
11186 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11187 else
11188 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11189
11190 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11191 port, phy->addr, phy->mdio_ctrl);
11192
11193 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11194 return 0;
11195 }
11196
11197 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11198 u8 phy_index,
11199 u32 shmem_base,
11200 u32 shmem2_base,
11201 u8 port,
11202 struct bnx2x_phy *phy)
11203 {
11204 u32 ext_phy_config, phy_type, config2;
11205 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11206 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11207 phy_index, port);
11208 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11209 /* Select the phy type */
11210 switch (phy_type) {
11211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11212 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11213 *phy = phy_8073;
11214 break;
11215 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11216 *phy = phy_8705;
11217 break;
11218 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11219 *phy = phy_8706;
11220 break;
11221 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11222 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11223 *phy = phy_8726;
11224 break;
11225 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11226 /* BCM8727_NOC => BCM8727 no over current */
11227 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11228 *phy = phy_8727;
11229 phy->flags |= FLAGS_NOC;
11230 break;
11231 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11232 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11233 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11234 *phy = phy_8727;
11235 break;
11236 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11237 *phy = phy_8481;
11238 break;
11239 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11240 *phy = phy_84823;
11241 break;
11242 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11243 *phy = phy_84833;
11244 break;
11245 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11246 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11247 *phy = phy_54618se;
11248 break;
11249 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11250 *phy = phy_7101;
11251 break;
11252 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11253 *phy = phy_null;
11254 return -EINVAL;
11255 default:
11256 *phy = phy_null;
11257 return 0;
11258 }
11259
11260 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11261 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11262
11263 /*
11264 * The shmem address of the phy version is located on different
11265 * structures. In case this structure is too old, do not set
11266 * the address
11267 */
11268 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11269 dev_info.shared_hw_config.config2));
11270 if (phy_index == EXT_PHY1) {
11271 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11272 port_mb[port].ext_phy_fw_version);
11273
11274 /* Check specific mdc mdio settings */
11275 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11276 mdc_mdio_access = config2 &
11277 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11278 } else {
11279 u32 size = REG_RD(bp, shmem2_base);
11280
11281 if (size >
11282 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11283 phy->ver_addr = shmem2_base +
11284 offsetof(struct shmem2_region,
11285 ext_phy_fw_version2[port]);
11286 }
11287 /* Check specific mdc mdio settings */
11288 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11289 mdc_mdio_access = (config2 &
11290 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11291 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11292 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11293 }
11294 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11295
11296 /*
11297 * In case mdc/mdio_access of the external phy is different than the
11298 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11299 * to prevent one port interfere with another port's CL45 operations.
11300 */
11301 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11302 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11303 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11304 phy_type, port, phy_index);
11305 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11306 phy->addr, phy->mdio_ctrl);
11307 return 0;
11308 }
11309
11310 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11311 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11312 {
11313 int status = 0;
11314 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11315 if (phy_index == INT_PHY)
11316 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11317 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11318 port, phy);
11319 return status;
11320 }
11321
11322 static void bnx2x_phy_def_cfg(struct link_params *params,
11323 struct bnx2x_phy *phy,
11324 u8 phy_index)
11325 {
11326 struct bnx2x *bp = params->bp;
11327 u32 link_config;
11328 /* Populate the default phy configuration for MF mode */
11329 if (phy_index == EXT_PHY2) {
11330 link_config = REG_RD(bp, params->shmem_base +
11331 offsetof(struct shmem_region, dev_info.
11332 port_feature_config[params->port].link_config2));
11333 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11334 offsetof(struct shmem_region,
11335 dev_info.
11336 port_hw_config[params->port].speed_capability_mask2));
11337 } else {
11338 link_config = REG_RD(bp, params->shmem_base +
11339 offsetof(struct shmem_region, dev_info.
11340 port_feature_config[params->port].link_config));
11341 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11342 offsetof(struct shmem_region,
11343 dev_info.
11344 port_hw_config[params->port].speed_capability_mask));
11345 }
11346 DP(NETIF_MSG_LINK,
11347 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11348 phy_index, link_config, phy->speed_cap_mask);
11349
11350 phy->req_duplex = DUPLEX_FULL;
11351 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11352 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11353 phy->req_duplex = DUPLEX_HALF;
11354 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11355 phy->req_line_speed = SPEED_10;
11356 break;
11357 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11358 phy->req_duplex = DUPLEX_HALF;
11359 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11360 phy->req_line_speed = SPEED_100;
11361 break;
11362 case PORT_FEATURE_LINK_SPEED_1G:
11363 phy->req_line_speed = SPEED_1000;
11364 break;
11365 case PORT_FEATURE_LINK_SPEED_2_5G:
11366 phy->req_line_speed = SPEED_2500;
11367 break;
11368 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11369 phy->req_line_speed = SPEED_10000;
11370 break;
11371 default:
11372 phy->req_line_speed = SPEED_AUTO_NEG;
11373 break;
11374 }
11375
11376 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11377 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11378 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11379 break;
11380 case PORT_FEATURE_FLOW_CONTROL_TX:
11381 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11382 break;
11383 case PORT_FEATURE_FLOW_CONTROL_RX:
11384 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11385 break;
11386 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11387 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11388 break;
11389 default:
11390 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11391 break;
11392 }
11393 }
11394
11395 u32 bnx2x_phy_selection(struct link_params *params)
11396 {
11397 u32 phy_config_swapped, prio_cfg;
11398 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11399
11400 phy_config_swapped = params->multi_phy_config &
11401 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11402
11403 prio_cfg = params->multi_phy_config &
11404 PORT_HW_CFG_PHY_SELECTION_MASK;
11405
11406 if (phy_config_swapped) {
11407 switch (prio_cfg) {
11408 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11409 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11410 break;
11411 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11412 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11413 break;
11414 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11415 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11416 break;
11417 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11418 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11419 break;
11420 }
11421 } else
11422 return_cfg = prio_cfg;
11423
11424 return return_cfg;
11425 }
11426
11427
11428 int bnx2x_phy_probe(struct link_params *params)
11429 {
11430 u8 phy_index, actual_phy_idx, link_cfg_idx;
11431 u32 phy_config_swapped, sync_offset, media_types;
11432 struct bnx2x *bp = params->bp;
11433 struct bnx2x_phy *phy;
11434 params->num_phys = 0;
11435 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11436 phy_config_swapped = params->multi_phy_config &
11437 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11438
11439 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11440 phy_index++) {
11441 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11442 actual_phy_idx = phy_index;
11443 if (phy_config_swapped) {
11444 if (phy_index == EXT_PHY1)
11445 actual_phy_idx = EXT_PHY2;
11446 else if (phy_index == EXT_PHY2)
11447 actual_phy_idx = EXT_PHY1;
11448 }
11449 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11450 " actual_phy_idx %x\n", phy_config_swapped,
11451 phy_index, actual_phy_idx);
11452 phy = &params->phy[actual_phy_idx];
11453 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11454 params->shmem2_base, params->port,
11455 phy) != 0) {
11456 params->num_phys = 0;
11457 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11458 phy_index);
11459 for (phy_index = INT_PHY;
11460 phy_index < MAX_PHYS;
11461 phy_index++)
11462 *phy = phy_null;
11463 return -EINVAL;
11464 }
11465 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11466 break;
11467
11468 sync_offset = params->shmem_base +
11469 offsetof(struct shmem_region,
11470 dev_info.port_hw_config[params->port].media_type);
11471 media_types = REG_RD(bp, sync_offset);
11472
11473 /*
11474 * Update media type for non-PMF sync only for the first time
11475 * In case the media type changes afterwards, it will be updated
11476 * using the update_status function
11477 */
11478 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11479 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11480 actual_phy_idx))) == 0) {
11481 media_types |= ((phy->media_type &
11482 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11483 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11484 actual_phy_idx));
11485 }
11486 REG_WR(bp, sync_offset, media_types);
11487
11488 bnx2x_phy_def_cfg(params, phy, phy_index);
11489 params->num_phys++;
11490 }
11491
11492 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11493 return 0;
11494 }
11495
11496 void bnx2x_init_bmac_loopback(struct link_params *params,
11497 struct link_vars *vars)
11498 {
11499 struct bnx2x *bp = params->bp;
11500 vars->link_up = 1;
11501 vars->line_speed = SPEED_10000;
11502 vars->duplex = DUPLEX_FULL;
11503 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11504 vars->mac_type = MAC_TYPE_BMAC;
11505
11506 vars->phy_flags = PHY_XGXS_FLAG;
11507
11508 bnx2x_xgxs_deassert(params);
11509
11510 /* set bmac loopback */
11511 bnx2x_bmac_enable(params, vars, 1);
11512
11513 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11514 }
11515
11516 void bnx2x_init_emac_loopback(struct link_params *params,
11517 struct link_vars *vars)
11518 {
11519 struct bnx2x *bp = params->bp;
11520 vars->link_up = 1;
11521 vars->line_speed = SPEED_1000;
11522 vars->duplex = DUPLEX_FULL;
11523 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11524 vars->mac_type = MAC_TYPE_EMAC;
11525
11526 vars->phy_flags = PHY_XGXS_FLAG;
11527
11528 bnx2x_xgxs_deassert(params);
11529 /* set bmac loopback */
11530 bnx2x_emac_enable(params, vars, 1);
11531 bnx2x_emac_program(params, vars);
11532 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11533 }
11534
11535 void bnx2x_init_xmac_loopback(struct link_params *params,
11536 struct link_vars *vars)
11537 {
11538 struct bnx2x *bp = params->bp;
11539 vars->link_up = 1;
11540 if (!params->req_line_speed[0])
11541 vars->line_speed = SPEED_10000;
11542 else
11543 vars->line_speed = params->req_line_speed[0];
11544 vars->duplex = DUPLEX_FULL;
11545 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11546 vars->mac_type = MAC_TYPE_XMAC;
11547 vars->phy_flags = PHY_XGXS_FLAG;
11548 /*
11549 * Set WC to loopback mode since link is required to provide clock
11550 * to the XMAC in 20G mode
11551 */
11552 bnx2x_set_aer_mmd(params, &params->phy[0]);
11553 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11554 params->phy[INT_PHY].config_loopback(
11555 &params->phy[INT_PHY],
11556 params);
11557
11558 bnx2x_xmac_enable(params, vars, 1);
11559 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11560 }
11561
11562 void bnx2x_init_umac_loopback(struct link_params *params,
11563 struct link_vars *vars)
11564 {
11565 struct bnx2x *bp = params->bp;
11566 vars->link_up = 1;
11567 vars->line_speed = SPEED_1000;
11568 vars->duplex = DUPLEX_FULL;
11569 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11570 vars->mac_type = MAC_TYPE_UMAC;
11571 vars->phy_flags = PHY_XGXS_FLAG;
11572 bnx2x_umac_enable(params, vars, 1);
11573
11574 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11575 }
11576
11577 void bnx2x_init_xgxs_loopback(struct link_params *params,
11578 struct link_vars *vars)
11579 {
11580 struct bnx2x *bp = params->bp;
11581 vars->link_up = 1;
11582 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11583 vars->duplex = DUPLEX_FULL;
11584 if (params->req_line_speed[0] == SPEED_1000)
11585 vars->line_speed = SPEED_1000;
11586 else
11587 vars->line_speed = SPEED_10000;
11588
11589 if (!USES_WARPCORE(bp))
11590 bnx2x_xgxs_deassert(params);
11591 bnx2x_link_initialize(params, vars);
11592
11593 if (params->req_line_speed[0] == SPEED_1000) {
11594 if (USES_WARPCORE(bp))
11595 bnx2x_umac_enable(params, vars, 0);
11596 else {
11597 bnx2x_emac_program(params, vars);
11598 bnx2x_emac_enable(params, vars, 0);
11599 }
11600 } else {
11601 if (USES_WARPCORE(bp))
11602 bnx2x_xmac_enable(params, vars, 0);
11603 else
11604 bnx2x_bmac_enable(params, vars, 0);
11605 }
11606
11607 if (params->loopback_mode == LOOPBACK_XGXS) {
11608 /* set 10G XGXS loopback */
11609 params->phy[INT_PHY].config_loopback(
11610 &params->phy[INT_PHY],
11611 params);
11612
11613 } else {
11614 /* set external phy loopback */
11615 u8 phy_index;
11616 for (phy_index = EXT_PHY1;
11617 phy_index < params->num_phys; phy_index++) {
11618 if (params->phy[phy_index].config_loopback)
11619 params->phy[phy_index].config_loopback(
11620 &params->phy[phy_index],
11621 params);
11622 }
11623 }
11624 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11625
11626 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11627 }
11628
11629 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11630 {
11631 struct bnx2x *bp = params->bp;
11632 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11633 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11634 params->req_line_speed[0], params->req_flow_ctrl[0]);
11635 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11636 params->req_line_speed[1], params->req_flow_ctrl[1]);
11637 vars->link_status = 0;
11638 vars->phy_link_up = 0;
11639 vars->link_up = 0;
11640 vars->line_speed = 0;
11641 vars->duplex = DUPLEX_FULL;
11642 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11643 vars->mac_type = MAC_TYPE_NONE;
11644 vars->phy_flags = 0;
11645
11646 /* disable attentions */
11647 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11648 (NIG_MASK_XGXS0_LINK_STATUS |
11649 NIG_MASK_XGXS0_LINK10G |
11650 NIG_MASK_SERDES0_LINK_STATUS |
11651 NIG_MASK_MI_INT));
11652
11653 bnx2x_emac_init(params, vars);
11654
11655 if (params->num_phys == 0) {
11656 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11657 return -EINVAL;
11658 }
11659 set_phy_vars(params, vars);
11660
11661 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11662 switch (params->loopback_mode) {
11663 case LOOPBACK_BMAC:
11664 bnx2x_init_bmac_loopback(params, vars);
11665 break;
11666 case LOOPBACK_EMAC:
11667 bnx2x_init_emac_loopback(params, vars);
11668 break;
11669 case LOOPBACK_XMAC:
11670 bnx2x_init_xmac_loopback(params, vars);
11671 break;
11672 case LOOPBACK_UMAC:
11673 bnx2x_init_umac_loopback(params, vars);
11674 break;
11675 case LOOPBACK_XGXS:
11676 case LOOPBACK_EXT_PHY:
11677 bnx2x_init_xgxs_loopback(params, vars);
11678 break;
11679 default:
11680 if (!CHIP_IS_E3(bp)) {
11681 if (params->switch_cfg == SWITCH_CFG_10G)
11682 bnx2x_xgxs_deassert(params);
11683 else
11684 bnx2x_serdes_deassert(bp, params->port);
11685 }
11686 bnx2x_link_initialize(params, vars);
11687 msleep(30);
11688 bnx2x_link_int_enable(params);
11689 break;
11690 }
11691 return 0;
11692 }
11693
11694 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11695 u8 reset_ext_phy)
11696 {
11697 struct bnx2x *bp = params->bp;
11698 u8 phy_index, port = params->port, clear_latch_ind = 0;
11699 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11700 /* disable attentions */
11701 vars->link_status = 0;
11702 bnx2x_update_mng(params, vars->link_status);
11703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11704 (NIG_MASK_XGXS0_LINK_STATUS |
11705 NIG_MASK_XGXS0_LINK10G |
11706 NIG_MASK_SERDES0_LINK_STATUS |
11707 NIG_MASK_MI_INT));
11708
11709 /* activate nig drain */
11710 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11711
11712 /* disable nig egress interface */
11713 if (!CHIP_IS_E3(bp)) {
11714 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11715 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11716 }
11717
11718 /* Stop BigMac rx */
11719 if (!CHIP_IS_E3(bp))
11720 bnx2x_bmac_rx_disable(bp, port);
11721 else
11722 bnx2x_xmac_disable(params);
11723 /* disable emac */
11724 if (!CHIP_IS_E3(bp))
11725 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11726
11727 msleep(10);
11728 /* The PHY reset is controlled by GPIO 1
11729 * Hold it as vars low
11730 */
11731 /* clear link led */
11732 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11733
11734 if (reset_ext_phy) {
11735 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11736 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11737 phy_index++) {
11738 if (params->phy[phy_index].link_reset) {
11739 bnx2x_set_aer_mmd(params,
11740 &params->phy[phy_index]);
11741 params->phy[phy_index].link_reset(
11742 &params->phy[phy_index],
11743 params);
11744 }
11745 if (params->phy[phy_index].flags &
11746 FLAGS_REARM_LATCH_SIGNAL)
11747 clear_latch_ind = 1;
11748 }
11749 }
11750
11751 if (clear_latch_ind) {
11752 /* Clear latching indication */
11753 bnx2x_rearm_latch_signal(bp, port, 0);
11754 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11755 1 << NIG_LATCH_BC_ENABLE_MI_INT);
11756 }
11757 if (params->phy[INT_PHY].link_reset)
11758 params->phy[INT_PHY].link_reset(
11759 &params->phy[INT_PHY], params);
11760 /* reset BigMac */
11761 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11762 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11763
11764 /* disable nig ingress interface */
11765 if (!CHIP_IS_E3(bp)) {
11766 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11767 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11768 }
11769 vars->link_up = 0;
11770 vars->phy_flags = 0;
11771 return 0;
11772 }
11773
11774 /****************************************************************************/
11775 /* Common function */
11776 /****************************************************************************/
11777 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11778 u32 shmem_base_path[],
11779 u32 shmem2_base_path[], u8 phy_index,
11780 u32 chip_id)
11781 {
11782 struct bnx2x_phy phy[PORT_MAX];
11783 struct bnx2x_phy *phy_blk[PORT_MAX];
11784 u16 val;
11785 s8 port = 0;
11786 s8 port_of_path = 0;
11787 u32 swap_val, swap_override;
11788 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11789 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11790 port ^= (swap_val && swap_override);
11791 bnx2x_ext_phy_hw_reset(bp, port);
11792 /* PART1 - Reset both phys */
11793 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11794 u32 shmem_base, shmem2_base;
11795 /* In E2, same phy is using for port0 of the two paths */
11796 if (CHIP_IS_E1x(bp)) {
11797 shmem_base = shmem_base_path[0];
11798 shmem2_base = shmem2_base_path[0];
11799 port_of_path = port;
11800 } else {
11801 shmem_base = shmem_base_path[port];
11802 shmem2_base = shmem2_base_path[port];
11803 port_of_path = 0;
11804 }
11805
11806 /* Extract the ext phy address for the port */
11807 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11808 port_of_path, &phy[port]) !=
11809 0) {
11810 DP(NETIF_MSG_LINK, "populate_phy failed\n");
11811 return -EINVAL;
11812 }
11813 /* disable attentions */
11814 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11815 port_of_path*4,
11816 (NIG_MASK_XGXS0_LINK_STATUS |
11817 NIG_MASK_XGXS0_LINK10G |
11818 NIG_MASK_SERDES0_LINK_STATUS |
11819 NIG_MASK_MI_INT));
11820
11821 /* Need to take the phy out of low power mode in order
11822 to write to access its registers */
11823 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11824 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11825 port);
11826
11827 /* Reset the phy */
11828 bnx2x_cl45_write(bp, &phy[port],
11829 MDIO_PMA_DEVAD,
11830 MDIO_PMA_REG_CTRL,
11831 1<<15);
11832 }
11833
11834 /* Add delay of 150ms after reset */
11835 msleep(150);
11836
11837 if (phy[PORT_0].addr & 0x1) {
11838 phy_blk[PORT_0] = &(phy[PORT_1]);
11839 phy_blk[PORT_1] = &(phy[PORT_0]);
11840 } else {
11841 phy_blk[PORT_0] = &(phy[PORT_0]);
11842 phy_blk[PORT_1] = &(phy[PORT_1]);
11843 }
11844
11845 /* PART2 - Download firmware to both phys */
11846 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11847 if (CHIP_IS_E1x(bp))
11848 port_of_path = port;
11849 else
11850 port_of_path = 0;
11851
11852 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11853 phy_blk[port]->addr);
11854 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11855 port_of_path))
11856 return -EINVAL;
11857
11858 /* Only set bit 10 = 1 (Tx power down) */
11859 bnx2x_cl45_read(bp, phy_blk[port],
11860 MDIO_PMA_DEVAD,
11861 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11862
11863 /* Phase1 of TX_POWER_DOWN reset */
11864 bnx2x_cl45_write(bp, phy_blk[port],
11865 MDIO_PMA_DEVAD,
11866 MDIO_PMA_REG_TX_POWER_DOWN,
11867 (val | 1<<10));
11868 }
11869
11870 /*
11871 * Toggle Transmitter: Power down and then up with 600ms delay
11872 * between
11873 */
11874 msleep(600);
11875
11876 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11877 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11878 /* Phase2 of POWER_DOWN_RESET */
11879 /* Release bit 10 (Release Tx power down) */
11880 bnx2x_cl45_read(bp, phy_blk[port],
11881 MDIO_PMA_DEVAD,
11882 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11883
11884 bnx2x_cl45_write(bp, phy_blk[port],
11885 MDIO_PMA_DEVAD,
11886 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11887 msleep(15);
11888
11889 /* Read modify write the SPI-ROM version select register */
11890 bnx2x_cl45_read(bp, phy_blk[port],
11891 MDIO_PMA_DEVAD,
11892 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11893 bnx2x_cl45_write(bp, phy_blk[port],
11894 MDIO_PMA_DEVAD,
11895 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11896
11897 /* set GPIO2 back to LOW */
11898 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11899 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11900 }
11901 return 0;
11902 }
11903 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11904 u32 shmem_base_path[],
11905 u32 shmem2_base_path[], u8 phy_index,
11906 u32 chip_id)
11907 {
11908 u32 val;
11909 s8 port;
11910 struct bnx2x_phy phy;
11911 /* Use port1 because of the static port-swap */
11912 /* Enable the module detection interrupt */
11913 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11914 val |= ((1<<MISC_REGISTERS_GPIO_3)|
11915 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11916 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11917
11918 bnx2x_ext_phy_hw_reset(bp, 0);
11919 msleep(5);
11920 for (port = 0; port < PORT_MAX; port++) {
11921 u32 shmem_base, shmem2_base;
11922
11923 /* In E2, same phy is using for port0 of the two paths */
11924 if (CHIP_IS_E1x(bp)) {
11925 shmem_base = shmem_base_path[0];
11926 shmem2_base = shmem2_base_path[0];
11927 } else {
11928 shmem_base = shmem_base_path[port];
11929 shmem2_base = shmem2_base_path[port];
11930 }
11931 /* Extract the ext phy address for the port */
11932 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11933 port, &phy) !=
11934 0) {
11935 DP(NETIF_MSG_LINK, "populate phy failed\n");
11936 return -EINVAL;
11937 }
11938
11939 /* Reset phy*/
11940 bnx2x_cl45_write(bp, &phy,
11941 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11942
11943
11944 /* Set fault module detected LED on */
11945 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11946 MISC_REGISTERS_GPIO_HIGH,
11947 port);
11948 }
11949
11950 return 0;
11951 }
11952 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11953 u8 *io_gpio, u8 *io_port)
11954 {
11955
11956 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11957 offsetof(struct shmem_region,
11958 dev_info.port_hw_config[PORT_0].default_cfg));
11959 switch (phy_gpio_reset) {
11960 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11961 *io_gpio = 0;
11962 *io_port = 0;
11963 break;
11964 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11965 *io_gpio = 1;
11966 *io_port = 0;
11967 break;
11968 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11969 *io_gpio = 2;
11970 *io_port = 0;
11971 break;
11972 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11973 *io_gpio = 3;
11974 *io_port = 0;
11975 break;
11976 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11977 *io_gpio = 0;
11978 *io_port = 1;
11979 break;
11980 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11981 *io_gpio = 1;
11982 *io_port = 1;
11983 break;
11984 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11985 *io_gpio = 2;
11986 *io_port = 1;
11987 break;
11988 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11989 *io_gpio = 3;
11990 *io_port = 1;
11991 break;
11992 default:
11993 /* Don't override the io_gpio and io_port */
11994 break;
11995 }
11996 }
11997
11998 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11999 u32 shmem_base_path[],
12000 u32 shmem2_base_path[], u8 phy_index,
12001 u32 chip_id)
12002 {
12003 s8 port, reset_gpio;
12004 u32 swap_val, swap_override;
12005 struct bnx2x_phy phy[PORT_MAX];
12006 struct bnx2x_phy *phy_blk[PORT_MAX];
12007 s8 port_of_path;
12008 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12009 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12010
12011 reset_gpio = MISC_REGISTERS_GPIO_1;
12012 port = 1;
12013
12014 /*
12015 * Retrieve the reset gpio/port which control the reset.
12016 * Default is GPIO1, PORT1
12017 */
12018 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12019 (u8 *)&reset_gpio, (u8 *)&port);
12020
12021 /* Calculate the port based on port swap */
12022 port ^= (swap_val && swap_override);
12023
12024 /* Initiate PHY reset*/
12025 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12026 port);
12027 msleep(1);
12028 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12029 port);
12030
12031 msleep(5);
12032
12033 /* PART1 - Reset both phys */
12034 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12035 u32 shmem_base, shmem2_base;
12036
12037 /* In E2, same phy is using for port0 of the two paths */
12038 if (CHIP_IS_E1x(bp)) {
12039 shmem_base = shmem_base_path[0];
12040 shmem2_base = shmem2_base_path[0];
12041 port_of_path = port;
12042 } else {
12043 shmem_base = shmem_base_path[port];
12044 shmem2_base = shmem2_base_path[port];
12045 port_of_path = 0;
12046 }
12047
12048 /* Extract the ext phy address for the port */
12049 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12050 port_of_path, &phy[port]) !=
12051 0) {
12052 DP(NETIF_MSG_LINK, "populate phy failed\n");
12053 return -EINVAL;
12054 }
12055 /* disable attentions */
12056 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12057 port_of_path*4,
12058 (NIG_MASK_XGXS0_LINK_STATUS |
12059 NIG_MASK_XGXS0_LINK10G |
12060 NIG_MASK_SERDES0_LINK_STATUS |
12061 NIG_MASK_MI_INT));
12062
12063
12064 /* Reset the phy */
12065 bnx2x_cl45_write(bp, &phy[port],
12066 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12067 }
12068
12069 /* Add delay of 150ms after reset */
12070 msleep(150);
12071 if (phy[PORT_0].addr & 0x1) {
12072 phy_blk[PORT_0] = &(phy[PORT_1]);
12073 phy_blk[PORT_1] = &(phy[PORT_0]);
12074 } else {
12075 phy_blk[PORT_0] = &(phy[PORT_0]);
12076 phy_blk[PORT_1] = &(phy[PORT_1]);
12077 }
12078 /* PART2 - Download firmware to both phys */
12079 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12080 if (CHIP_IS_E1x(bp))
12081 port_of_path = port;
12082 else
12083 port_of_path = 0;
12084 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12085 phy_blk[port]->addr);
12086 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12087 port_of_path))
12088 return -EINVAL;
12089 /* Disable PHY transmitter output */
12090 bnx2x_cl45_write(bp, phy_blk[port],
12091 MDIO_PMA_DEVAD,
12092 MDIO_PMA_REG_TX_DISABLE, 1);
12093
12094 }
12095 return 0;
12096 }
12097
12098 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12099 u32 shmem2_base_path[], u8 phy_index,
12100 u32 ext_phy_type, u32 chip_id)
12101 {
12102 int rc = 0;
12103
12104 switch (ext_phy_type) {
12105 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12106 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12107 shmem2_base_path,
12108 phy_index, chip_id);
12109 break;
12110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12111 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12112 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12113 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12114 shmem2_base_path,
12115 phy_index, chip_id);
12116 break;
12117
12118 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12119 /*
12120 * GPIO1 affects both ports, so there's need to pull
12121 * it for single port alone
12122 */
12123 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12124 shmem2_base_path,
12125 phy_index, chip_id);
12126 break;
12127 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12128 /*
12129 * GPIO3's are linked, and so both need to be toggled
12130 * to obtain required 2us pulse.
12131 */
12132 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12133 break;
12134 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12135 rc = -EINVAL;
12136 break;
12137 default:
12138 DP(NETIF_MSG_LINK,
12139 "ext_phy 0x%x common init not required\n",
12140 ext_phy_type);
12141 break;
12142 }
12143
12144 if (rc != 0)
12145 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12146 " Port %d\n",
12147 0);
12148 return rc;
12149 }
12150
12151 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12152 u32 shmem2_base_path[], u32 chip_id)
12153 {
12154 int rc = 0;
12155 u32 phy_ver, val;
12156 u8 phy_index = 0;
12157 u32 ext_phy_type, ext_phy_config;
12158 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12159 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12160 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12161 if (CHIP_IS_E3(bp)) {
12162 /* Enable EPIO */
12163 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12164 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12165 }
12166 /* Check if common init was already done */
12167 phy_ver = REG_RD(bp, shmem_base_path[0] +
12168 offsetof(struct shmem_region,
12169 port_mb[PORT_0].ext_phy_fw_version));
12170 if (phy_ver) {
12171 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12172 phy_ver);
12173 return 0;
12174 }
12175
12176 /* Read the ext_phy_type for arbitrary port(0) */
12177 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12178 phy_index++) {
12179 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12180 shmem_base_path[0],
12181 phy_index, 0);
12182 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12183 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12184 shmem2_base_path,
12185 phy_index, ext_phy_type,
12186 chip_id);
12187 }
12188 return rc;
12189 }
12190
12191 static void bnx2x_check_over_curr(struct link_params *params,
12192 struct link_vars *vars)
12193 {
12194 struct bnx2x *bp = params->bp;
12195 u32 cfg_pin;
12196 u8 port = params->port;
12197 u32 pin_val;
12198
12199 cfg_pin = (REG_RD(bp, params->shmem_base +
12200 offsetof(struct shmem_region,
12201 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12202 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12203 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12204
12205 /* Ignore check if no external input PIN available */
12206 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12207 return;
12208
12209 if (!pin_val) {
12210 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12211 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12212 " been detected and the power to "
12213 "that SFP+ module has been removed"
12214 " to prevent failure of the card."
12215 " Please remove the SFP+ module and"
12216 " restart the system to clear this"
12217 " error.\n",
12218 params->port);
12219 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12220 }
12221 } else
12222 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12223 }
12224
12225 static void bnx2x_analyze_link_error(struct link_params *params,
12226 struct link_vars *vars, u32 lss_status)
12227 {
12228 struct bnx2x *bp = params->bp;
12229 /* Compare new value with previous value */
12230 u8 led_mode;
12231 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12232
12233 if ((lss_status ^ half_open_conn) == 0)
12234 return;
12235
12236 /* If values differ */
12237 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12238 half_open_conn, lss_status);
12239
12240 /*
12241 * a. Update shmem->link_status accordingly
12242 * b. Update link_vars->link_up
12243 */
12244 if (lss_status) {
12245 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12246 vars->link_status &= ~LINK_STATUS_LINK_UP;
12247 vars->link_up = 0;
12248 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12249 /*
12250 * Set LED mode to off since the PHY doesn't know about these
12251 * errors
12252 */
12253 led_mode = LED_MODE_OFF;
12254 } else {
12255 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12256 vars->link_status |= LINK_STATUS_LINK_UP;
12257 vars->link_up = 1;
12258 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12259 led_mode = LED_MODE_OPER;
12260 }
12261 /* Update the LED according to the link state */
12262 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12263
12264 /* Update link status in the shared memory */
12265 bnx2x_update_mng(params, vars->link_status);
12266
12267 /* C. Trigger General Attention */
12268 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12269 bnx2x_notify_link_changed(bp);
12270 }
12271
12272 /******************************************************************************
12273 * Description:
12274 * This function checks for half opened connection change indication.
12275 * When such change occurs, it calls the bnx2x_analyze_link_error
12276 * to check if Remote Fault is set or cleared. Reception of remote fault
12277 * status message in the MAC indicates that the peer's MAC has detected
12278 * a fault, for example, due to break in the TX side of fiber.
12279 *
12280 ******************************************************************************/
12281 static void bnx2x_check_half_open_conn(struct link_params *params,
12282 struct link_vars *vars)
12283 {
12284 struct bnx2x *bp = params->bp;
12285 u32 lss_status = 0;
12286 u32 mac_base;
12287 /* In case link status is physically up @ 10G do */
12288 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12289 return;
12290
12291 if (CHIP_IS_E3(bp) &&
12292 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12293 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12294 /* Check E3 XMAC */
12295 /*
12296 * Note that link speed cannot be queried here, since it may be
12297 * zero while link is down. In case UMAC is active, LSS will
12298 * simply not be set
12299 */
12300 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12301
12302 /* Clear stick bits (Requires rising edge) */
12303 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12304 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12305 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12306 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12307 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12308 lss_status = 1;
12309
12310 bnx2x_analyze_link_error(params, vars, lss_status);
12311 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12312 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12313 /* Check E1X / E2 BMAC */
12314 u32 lss_status_reg;
12315 u32 wb_data[2];
12316 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12317 NIG_REG_INGRESS_BMAC0_MEM;
12318 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12319 if (CHIP_IS_E2(bp))
12320 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12321 else
12322 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12323
12324 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12325 lss_status = (wb_data[0] > 0);
12326
12327 bnx2x_analyze_link_error(params, vars, lss_status);
12328 }
12329 }
12330
12331 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12332 {
12333 struct bnx2x *bp = params->bp;
12334 u16 phy_idx;
12335 if (!params) {
12336 DP(NETIF_MSG_LINK, "Uninitialized params !\n");
12337 return;
12338 }
12339
12340 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12341 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12342 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12343 bnx2x_check_half_open_conn(params, vars);
12344 break;
12345 }
12346 }
12347
12348 if (CHIP_IS_E3(bp))
12349 bnx2x_check_over_curr(params, vars);
12350 }
12351
12352 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12353 {
12354 u8 phy_index;
12355 struct bnx2x_phy phy;
12356 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12357 phy_index++) {
12358 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12359 0, &phy) != 0) {
12360 DP(NETIF_MSG_LINK, "populate phy failed\n");
12361 return 0;
12362 }
12363
12364 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12365 return 1;
12366 }
12367 return 0;
12368 }
12369
12370 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12371 u32 shmem_base,
12372 u32 shmem2_base,
12373 u8 port)
12374 {
12375 u8 phy_index, fan_failure_det_req = 0;
12376 struct bnx2x_phy phy;
12377 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12378 phy_index++) {
12379 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12380 port, &phy)
12381 != 0) {
12382 DP(NETIF_MSG_LINK, "populate phy failed\n");
12383 return 0;
12384 }
12385 fan_failure_det_req |= (phy.flags &
12386 FLAGS_FAN_FAILURE_DET_REQ);
12387 }
12388 return fan_failure_det_req;
12389 }
12390
12391 void bnx2x_hw_reset_phy(struct link_params *params)
12392 {
12393 u8 phy_index;
12394 struct bnx2x *bp = params->bp;
12395 bnx2x_update_mng(params, 0);
12396 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12397 (NIG_MASK_XGXS0_LINK_STATUS |
12398 NIG_MASK_XGXS0_LINK10G |
12399 NIG_MASK_SERDES0_LINK_STATUS |
12400 NIG_MASK_MI_INT));
12401
12402 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12403 phy_index++) {
12404 if (params->phy[phy_index].hw_reset) {
12405 params->phy[phy_index].hw_reset(
12406 &params->phy[phy_index],
12407 params);
12408 params->phy[phy_index] = phy_null;
12409 }
12410 }
12411 }
12412
12413 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12414 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12415 u8 port)
12416 {
12417 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12418 u32 val;
12419 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12420 if (CHIP_IS_E3(bp)) {
12421 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12422 shmem_base,
12423 port,
12424 &gpio_num,
12425 &gpio_port) != 0)
12426 return;
12427 } else {
12428 struct bnx2x_phy phy;
12429 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12430 phy_index++) {
12431 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12432 shmem2_base, port, &phy)
12433 != 0) {
12434 DP(NETIF_MSG_LINK, "populate phy failed\n");
12435 return;
12436 }
12437 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12438 gpio_num = MISC_REGISTERS_GPIO_3;
12439 gpio_port = port;
12440 break;
12441 }
12442 }
12443 }
12444
12445 if (gpio_num == 0xff)
12446 return;
12447
12448 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12449 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12450
12451 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12452 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12453 gpio_port ^= (swap_val && swap_override);
12454
12455 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12456 (gpio_num + (gpio_port << 2));
12457
12458 sync_offset = shmem_base +
12459 offsetof(struct shmem_region,
12460 dev_info.port_hw_config[port].aeu_int_mask);
12461 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12462
12463 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12464 gpio_num, gpio_port, vars->aeu_int_mask);
12465
12466 if (port == 0)
12467 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12468 else
12469 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12470
12471 /* Open appropriate AEU for interrupts */
12472 aeu_mask = REG_RD(bp, offset);
12473 aeu_mask |= vars->aeu_int_mask;
12474 REG_WR(bp, offset, aeu_mask);
12475
12476 /* Enable the GPIO to trigger interrupt */
12477 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12478 val |= 1 << (gpio_num + (gpio_port << 2));
12479 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12480 }
linux-next