2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/sched.h>
43 #include <linux/seq_file.h>
44 #include <linux/mii.h>
45 #include <linux/slab.h>
46 #include <linux/dmi.h>
47 #include <linux/prefetch.h>
52 #define DRV_NAME "skge"
53 #define DRV_VERSION "1.14"
55 #define DEFAULT_TX_RING_SIZE 128
56 #define DEFAULT_RX_RING_SIZE 512
57 #define MAX_TX_RING_SIZE 1024
58 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
59 #define MAX_RX_RING_SIZE 4096
60 #define RX_COPY_THRESHOLD 128
61 #define RX_BUF_SIZE 1536
62 #define PHY_RETRIES 1000
63 #define ETH_JUMBO_MTU 9000
64 #define TX_WATCHDOG (5 * HZ)
65 #define NAPI_WEIGHT 64
69 #define SKGE_EEPROM_MAGIC 0x9933aabb
72 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
73 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
74 MODULE_LICENSE("GPL");
75 MODULE_VERSION(DRV_VERSION
);
77 static const u32 default_msg
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
78 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
81 static int debug
= -1; /* defaults above */
82 module_param(debug
, int, 0);
83 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
85 static DEFINE_PCI_DEVICE_TABLE(skge_id_table
) = {
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, 0x80EB) }, /* 3Com 3C940B */
88 #ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x4300) }, /* SK-9xx */
91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4c00) }, /* D-Link DGE-530T */
94 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302) }, /* D-Link DGE-530T Rev C1 */
95 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET
, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS
, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0015 }, /* Linksys EG1032 v2 */
102 MODULE_DEVICE_TABLE(pci
, skge_id_table
);
104 static int skge_up(struct net_device
*dev
);
105 static int skge_down(struct net_device
*dev
);
106 static void skge_phy_reset(struct skge_port
*skge
);
107 static void skge_tx_clean(struct net_device
*dev
);
108 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
109 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
110 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
);
111 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
);
112 static void yukon_init(struct skge_hw
*hw
, int port
);
113 static void genesis_mac_init(struct skge_hw
*hw
, int port
);
114 static void genesis_link_up(struct skge_port
*skge
);
115 static void skge_set_multicast(struct net_device
*dev
);
117 /* Avoid conditionals by using array */
118 static const int txqaddr
[] = { Q_XA1
, Q_XA2
};
119 static const int rxqaddr
[] = { Q_R1
, Q_R2
};
120 static const u32 rxirqmask
[] = { IS_R1_F
, IS_R2_F
};
121 static const u32 txirqmask
[] = { IS_XA1_F
, IS_XA2_F
};
122 static const u32 napimask
[] = { IS_R1_F
|IS_XA1_F
, IS_R2_F
|IS_XA2_F
};
123 static const u32 portmask
[] = { IS_PORT_1
, IS_PORT_2
};
125 static inline bool is_genesis(const struct skge_hw
*hw
)
127 #ifdef CONFIG_SKGE_GENESIS
128 return hw
->chip_id
== CHIP_ID_GENESIS
;
134 static int skge_get_regs_len(struct net_device
*dev
)
140 * Returns copy of whole control register region
141 * Note: skip RAM address register because accessing it will
144 static void skge_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
147 const struct skge_port
*skge
= netdev_priv(dev
);
148 const void __iomem
*io
= skge
->hw
->regs
;
151 memset(p
, 0, regs
->len
);
152 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
154 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
,
155 regs
->len
- B3_RI_WTO_R1
);
158 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
159 static u32
wol_supported(const struct skge_hw
*hw
)
164 if (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
167 return WAKE_MAGIC
| WAKE_PHY
;
170 static void skge_wol_init(struct skge_port
*skge
)
172 struct skge_hw
*hw
= skge
->hw
;
173 int port
= skge
->port
;
176 skge_write16(hw
, B0_CTST
, CS_RST_CLR
);
177 skge_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
180 skge_write8(hw
, B0_POWER_CTRL
,
181 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_ON
| PC_VCC_OFF
);
183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
185 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
186 u32 reg
= skge_read32(hw
, B2_GP_IO
);
189 skge_write32(hw
, B2_GP_IO
, reg
);
192 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
),
194 GPC_HWCFG_M_3
| GPC_HWCFG_M_2
| GPC_HWCFG_M_1
| GPC_HWCFG_M_0
|
195 GPC_ANEG_1
| GPC_RST_SET
);
197 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
),
199 GPC_HWCFG_M_3
| GPC_HWCFG_M_2
| GPC_HWCFG_M_1
| GPC_HWCFG_M_0
|
200 GPC_ANEG_1
| GPC_RST_CLR
);
202 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
204 /* Force to 10/100 skge_reset will re-enable on resume */
205 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
206 (PHY_AN_100FULL
| PHY_AN_100HALF
|
207 PHY_AN_10FULL
| PHY_AN_10HALF
| PHY_AN_CSMA
));
209 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, 0);
210 gm_phy_write(hw
, port
, PHY_MARV_CTRL
,
211 PHY_CT_RESET
| PHY_CT_SPS_LSB
| PHY_CT_ANE
|
212 PHY_CT_RE_CFG
| PHY_CT_DUP_MD
);
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw
, port
, GM_GP_CTRL
,
217 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
218 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
220 /* Set WOL address */
221 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
222 skge
->netdev
->dev_addr
, ETH_ALEN
);
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
227 if (skge
->wol
& WAKE_PHY
)
228 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
230 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
232 if (skge
->wol
& WAKE_MAGIC
)
233 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
235 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;
237 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
238 skge_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
241 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
244 static void skge_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
246 struct skge_port
*skge
= netdev_priv(dev
);
248 wol
->supported
= wol_supported(skge
->hw
);
249 wol
->wolopts
= skge
->wol
;
252 static int skge_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
254 struct skge_port
*skge
= netdev_priv(dev
);
255 struct skge_hw
*hw
= skge
->hw
;
257 if ((wol
->wolopts
& ~wol_supported(hw
)) ||
258 !device_can_wakeup(&hw
->pdev
->dev
))
261 skge
->wol
= wol
->wolopts
;
263 device_set_wakeup_enable(&hw
->pdev
->dev
, skge
->wol
);
268 /* Determine supported/advertised modes based on hardware.
269 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
271 static u32
skge_supported_modes(const struct skge_hw
*hw
)
276 supported
= (SUPPORTED_10baseT_Half
|
277 SUPPORTED_10baseT_Full
|
278 SUPPORTED_100baseT_Half
|
279 SUPPORTED_100baseT_Full
|
280 SUPPORTED_1000baseT_Half
|
281 SUPPORTED_1000baseT_Full
|
286 supported
&= ~(SUPPORTED_10baseT_Half
|
287 SUPPORTED_10baseT_Full
|
288 SUPPORTED_100baseT_Half
|
289 SUPPORTED_100baseT_Full
);
291 else if (hw
->chip_id
== CHIP_ID_YUKON
)
292 supported
&= ~SUPPORTED_1000baseT_Half
;
294 supported
= (SUPPORTED_1000baseT_Full
|
295 SUPPORTED_1000baseT_Half
|
302 static int skge_get_settings(struct net_device
*dev
,
303 struct ethtool_cmd
*ecmd
)
305 struct skge_port
*skge
= netdev_priv(dev
);
306 struct skge_hw
*hw
= skge
->hw
;
308 ecmd
->transceiver
= XCVR_INTERNAL
;
309 ecmd
->supported
= skge_supported_modes(hw
);
312 ecmd
->port
= PORT_TP
;
313 ecmd
->phy_address
= hw
->phy_addr
;
315 ecmd
->port
= PORT_FIBRE
;
317 ecmd
->advertising
= skge
->advertising
;
318 ecmd
->autoneg
= skge
->autoneg
;
319 ethtool_cmd_speed_set(ecmd
, skge
->speed
);
320 ecmd
->duplex
= skge
->duplex
;
324 static int skge_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
326 struct skge_port
*skge
= netdev_priv(dev
);
327 const struct skge_hw
*hw
= skge
->hw
;
328 u32 supported
= skge_supported_modes(hw
);
331 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
332 ecmd
->advertising
= supported
;
337 u32 speed
= ethtool_cmd_speed(ecmd
);
341 if (ecmd
->duplex
== DUPLEX_FULL
)
342 setting
= SUPPORTED_1000baseT_Full
;
343 else if (ecmd
->duplex
== DUPLEX_HALF
)
344 setting
= SUPPORTED_1000baseT_Half
;
349 if (ecmd
->duplex
== DUPLEX_FULL
)
350 setting
= SUPPORTED_100baseT_Full
;
351 else if (ecmd
->duplex
== DUPLEX_HALF
)
352 setting
= SUPPORTED_100baseT_Half
;
358 if (ecmd
->duplex
== DUPLEX_FULL
)
359 setting
= SUPPORTED_10baseT_Full
;
360 else if (ecmd
->duplex
== DUPLEX_HALF
)
361 setting
= SUPPORTED_10baseT_Half
;
369 if ((setting
& supported
) == 0)
373 skge
->duplex
= ecmd
->duplex
;
376 skge
->autoneg
= ecmd
->autoneg
;
377 skge
->advertising
= ecmd
->advertising
;
379 if (netif_running(dev
)) {
391 static void skge_get_drvinfo(struct net_device
*dev
,
392 struct ethtool_drvinfo
*info
)
394 struct skge_port
*skge
= netdev_priv(dev
);
396 strcpy(info
->driver
, DRV_NAME
);
397 strcpy(info
->version
, DRV_VERSION
);
398 strcpy(info
->fw_version
, "N/A");
399 strcpy(info
->bus_info
, pci_name(skge
->hw
->pdev
));
402 static const struct skge_stat
{
403 char name
[ETH_GSTRING_LEN
];
407 { "tx_bytes", XM_TXO_OK_HI
, GM_TXO_OK_HI
},
408 { "rx_bytes", XM_RXO_OK_HI
, GM_RXO_OK_HI
},
410 { "tx_broadcast", XM_TXF_BC_OK
, GM_TXF_BC_OK
},
411 { "rx_broadcast", XM_RXF_BC_OK
, GM_RXF_BC_OK
},
412 { "tx_multicast", XM_TXF_MC_OK
, GM_TXF_MC_OK
},
413 { "rx_multicast", XM_RXF_MC_OK
, GM_RXF_MC_OK
},
414 { "tx_unicast", XM_TXF_UC_OK
, GM_TXF_UC_OK
},
415 { "rx_unicast", XM_RXF_UC_OK
, GM_RXF_UC_OK
},
416 { "tx_mac_pause", XM_TXF_MPAUSE
, GM_TXF_MPAUSE
},
417 { "rx_mac_pause", XM_RXF_MPAUSE
, GM_RXF_MPAUSE
},
419 { "collisions", XM_TXF_SNG_COL
, GM_TXF_SNG_COL
},
420 { "multi_collisions", XM_TXF_MUL_COL
, GM_TXF_MUL_COL
},
421 { "aborted", XM_TXF_ABO_COL
, GM_TXF_ABO_COL
},
422 { "late_collision", XM_TXF_LAT_COL
, GM_TXF_LAT_COL
},
423 { "fifo_underrun", XM_TXE_FIFO_UR
, GM_TXE_FIFO_UR
},
424 { "fifo_overflow", XM_RXE_FIFO_OV
, GM_RXE_FIFO_OV
},
426 { "rx_toolong", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
427 { "rx_jabber", XM_RXF_JAB_PKT
, GM_RXF_JAB_PKT
},
428 { "rx_runt", XM_RXE_RUNT
, GM_RXE_FRAG
},
429 { "rx_too_long", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
430 { "rx_fcs_error", XM_RXF_FCS_ERR
, GM_RXF_FCS_ERR
},
433 static int skge_get_sset_count(struct net_device
*dev
, int sset
)
437 return ARRAY_SIZE(skge_stats
);
443 static void skge_get_ethtool_stats(struct net_device
*dev
,
444 struct ethtool_stats
*stats
, u64
*data
)
446 struct skge_port
*skge
= netdev_priv(dev
);
448 if (is_genesis(skge
->hw
))
449 genesis_get_stats(skge
, data
);
451 yukon_get_stats(skge
, data
);
454 /* Use hardware MIB variables for critical path statistics and
455 * transmit feedback not reported at interrupt.
456 * Other errors are accounted for in interrupt handler.
458 static struct net_device_stats
*skge_get_stats(struct net_device
*dev
)
460 struct skge_port
*skge
= netdev_priv(dev
);
461 u64 data
[ARRAY_SIZE(skge_stats
)];
463 if (is_genesis(skge
->hw
))
464 genesis_get_stats(skge
, data
);
466 yukon_get_stats(skge
, data
);
468 dev
->stats
.tx_bytes
= data
[0];
469 dev
->stats
.rx_bytes
= data
[1];
470 dev
->stats
.tx_packets
= data
[2] + data
[4] + data
[6];
471 dev
->stats
.rx_packets
= data
[3] + data
[5] + data
[7];
472 dev
->stats
.multicast
= data
[3] + data
[5];
473 dev
->stats
.collisions
= data
[10];
474 dev
->stats
.tx_aborted_errors
= data
[12];
479 static void skge_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
485 for (i
= 0; i
< ARRAY_SIZE(skge_stats
); i
++)
486 memcpy(data
+ i
* ETH_GSTRING_LEN
,
487 skge_stats
[i
].name
, ETH_GSTRING_LEN
);
492 static void skge_get_ring_param(struct net_device
*dev
,
493 struct ethtool_ringparam
*p
)
495 struct skge_port
*skge
= netdev_priv(dev
);
497 p
->rx_max_pending
= MAX_RX_RING_SIZE
;
498 p
->tx_max_pending
= MAX_TX_RING_SIZE
;
499 p
->rx_mini_max_pending
= 0;
500 p
->rx_jumbo_max_pending
= 0;
502 p
->rx_pending
= skge
->rx_ring
.count
;
503 p
->tx_pending
= skge
->tx_ring
.count
;
504 p
->rx_mini_pending
= 0;
505 p
->rx_jumbo_pending
= 0;
508 static int skge_set_ring_param(struct net_device
*dev
,
509 struct ethtool_ringparam
*p
)
511 struct skge_port
*skge
= netdev_priv(dev
);
514 if (p
->rx_pending
== 0 || p
->rx_pending
> MAX_RX_RING_SIZE
||
515 p
->tx_pending
< TX_LOW_WATER
|| p
->tx_pending
> MAX_TX_RING_SIZE
)
518 skge
->rx_ring
.count
= p
->rx_pending
;
519 skge
->tx_ring
.count
= p
->tx_pending
;
521 if (netif_running(dev
)) {
531 static u32
skge_get_msglevel(struct net_device
*netdev
)
533 struct skge_port
*skge
= netdev_priv(netdev
);
534 return skge
->msg_enable
;
537 static void skge_set_msglevel(struct net_device
*netdev
, u32 value
)
539 struct skge_port
*skge
= netdev_priv(netdev
);
540 skge
->msg_enable
= value
;
543 static int skge_nway_reset(struct net_device
*dev
)
545 struct skge_port
*skge
= netdev_priv(dev
);
547 if (skge
->autoneg
!= AUTONEG_ENABLE
|| !netif_running(dev
))
550 skge_phy_reset(skge
);
554 static void skge_get_pauseparam(struct net_device
*dev
,
555 struct ethtool_pauseparam
*ecmd
)
557 struct skge_port
*skge
= netdev_priv(dev
);
559 ecmd
->rx_pause
= ((skge
->flow_control
== FLOW_MODE_SYMMETRIC
) ||
560 (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
));
561 ecmd
->tx_pause
= (ecmd
->rx_pause
||
562 (skge
->flow_control
== FLOW_MODE_LOC_SEND
));
564 ecmd
->autoneg
= ecmd
->rx_pause
|| ecmd
->tx_pause
;
567 static int skge_set_pauseparam(struct net_device
*dev
,
568 struct ethtool_pauseparam
*ecmd
)
570 struct skge_port
*skge
= netdev_priv(dev
);
571 struct ethtool_pauseparam old
;
574 skge_get_pauseparam(dev
, &old
);
576 if (ecmd
->autoneg
!= old
.autoneg
)
577 skge
->flow_control
= ecmd
->autoneg
? FLOW_MODE_NONE
: FLOW_MODE_SYMMETRIC
;
579 if (ecmd
->rx_pause
&& ecmd
->tx_pause
)
580 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
581 else if (ecmd
->rx_pause
&& !ecmd
->tx_pause
)
582 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
583 else if (!ecmd
->rx_pause
&& ecmd
->tx_pause
)
584 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
586 skge
->flow_control
= FLOW_MODE_NONE
;
589 if (netif_running(dev
)) {
601 /* Chip internal frequency for clock calculations */
602 static inline u32
hwkhz(const struct skge_hw
*hw
)
604 return is_genesis(hw
) ? 53125 : 78125;
607 /* Chip HZ to microseconds */
608 static inline u32
skge_clk2usec(const struct skge_hw
*hw
, u32 ticks
)
610 return (ticks
* 1000) / hwkhz(hw
);
613 /* Microseconds to chip HZ */
614 static inline u32
skge_usecs2clk(const struct skge_hw
*hw
, u32 usec
)
616 return hwkhz(hw
) * usec
/ 1000;
619 static int skge_get_coalesce(struct net_device
*dev
,
620 struct ethtool_coalesce
*ecmd
)
622 struct skge_port
*skge
= netdev_priv(dev
);
623 struct skge_hw
*hw
= skge
->hw
;
624 int port
= skge
->port
;
626 ecmd
->rx_coalesce_usecs
= 0;
627 ecmd
->tx_coalesce_usecs
= 0;
629 if (skge_read32(hw
, B2_IRQM_CTRL
) & TIM_START
) {
630 u32 delay
= skge_clk2usec(hw
, skge_read32(hw
, B2_IRQM_INI
));
631 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
633 if (msk
& rxirqmask
[port
])
634 ecmd
->rx_coalesce_usecs
= delay
;
635 if (msk
& txirqmask
[port
])
636 ecmd
->tx_coalesce_usecs
= delay
;
642 /* Note: interrupt timer is per board, but can turn on/off per port */
643 static int skge_set_coalesce(struct net_device
*dev
,
644 struct ethtool_coalesce
*ecmd
)
646 struct skge_port
*skge
= netdev_priv(dev
);
647 struct skge_hw
*hw
= skge
->hw
;
648 int port
= skge
->port
;
649 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
652 if (ecmd
->rx_coalesce_usecs
== 0)
653 msk
&= ~rxirqmask
[port
];
654 else if (ecmd
->rx_coalesce_usecs
< 25 ||
655 ecmd
->rx_coalesce_usecs
> 33333)
658 msk
|= rxirqmask
[port
];
659 delay
= ecmd
->rx_coalesce_usecs
;
662 if (ecmd
->tx_coalesce_usecs
== 0)
663 msk
&= ~txirqmask
[port
];
664 else if (ecmd
->tx_coalesce_usecs
< 25 ||
665 ecmd
->tx_coalesce_usecs
> 33333)
668 msk
|= txirqmask
[port
];
669 delay
= min(delay
, ecmd
->rx_coalesce_usecs
);
672 skge_write32(hw
, B2_IRQM_MSK
, msk
);
674 skge_write32(hw
, B2_IRQM_CTRL
, TIM_STOP
);
676 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, delay
));
677 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
682 enum led_mode
{ LED_MODE_OFF
, LED_MODE_ON
, LED_MODE_TST
};
683 static void skge_led(struct skge_port
*skge
, enum led_mode mode
)
685 struct skge_hw
*hw
= skge
->hw
;
686 int port
= skge
->port
;
688 spin_lock_bh(&hw
->phy_lock
);
689 if (is_genesis(hw
)) {
692 if (hw
->phy_type
== SK_PHY_BCOM
)
693 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_OFF
);
695 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 0);
696 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_T_OFF
);
698 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
699 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 0);
700 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_T_OFF
);
704 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_ON
);
705 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_LINKSYNC_ON
);
707 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
708 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
713 skge_write8(hw
, SK_REG(port
, RX_LED_TST
), LED_T_ON
);
714 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 100);
715 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
717 if (hw
->phy_type
== SK_PHY_BCOM
)
718 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_ON
);
720 skge_write8(hw
, SK_REG(port
, TX_LED_TST
), LED_T_ON
);
721 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 100);
722 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
729 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
730 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
731 PHY_M_LED_MO_DUP(MO_LED_OFF
) |
732 PHY_M_LED_MO_10(MO_LED_OFF
) |
733 PHY_M_LED_MO_100(MO_LED_OFF
) |
734 PHY_M_LED_MO_1000(MO_LED_OFF
) |
735 PHY_M_LED_MO_RX(MO_LED_OFF
));
738 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
,
739 PHY_M_LED_PULS_DUR(PULS_170MS
) |
740 PHY_M_LED_BLINK_RT(BLINK_84MS
) |
744 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
745 PHY_M_LED_MO_RX(MO_LED_OFF
) |
746 (skge
->speed
== SPEED_100
?
747 PHY_M_LED_MO_100(MO_LED_ON
) : 0));
750 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
751 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
752 PHY_M_LED_MO_DUP(MO_LED_ON
) |
753 PHY_M_LED_MO_10(MO_LED_ON
) |
754 PHY_M_LED_MO_100(MO_LED_ON
) |
755 PHY_M_LED_MO_1000(MO_LED_ON
) |
756 PHY_M_LED_MO_RX(MO_LED_ON
));
759 spin_unlock_bh(&hw
->phy_lock
);
762 /* blink LED's for finding board */
763 static int skge_set_phys_id(struct net_device
*dev
,
764 enum ethtool_phys_id_state state
)
766 struct skge_port
*skge
= netdev_priv(dev
);
769 case ETHTOOL_ID_ACTIVE
:
770 return 2; /* cycle on/off twice per second */
773 skge_led(skge
, LED_MODE_TST
);
777 skge_led(skge
, LED_MODE_OFF
);
780 case ETHTOOL_ID_INACTIVE
:
781 /* back to regular LED state */
782 skge_led(skge
, netif_running(dev
) ? LED_MODE_ON
: LED_MODE_OFF
);
788 static int skge_get_eeprom_len(struct net_device
*dev
)
790 struct skge_port
*skge
= netdev_priv(dev
);
793 pci_read_config_dword(skge
->hw
->pdev
, PCI_DEV_REG2
, ®2
);
794 return 1 << (((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
797 static u32
skge_vpd_read(struct pci_dev
*pdev
, int cap
, u16 offset
)
801 pci_write_config_word(pdev
, cap
+ PCI_VPD_ADDR
, offset
);
804 pci_read_config_word(pdev
, cap
+ PCI_VPD_ADDR
, &offset
);
805 } while (!(offset
& PCI_VPD_ADDR_F
));
807 pci_read_config_dword(pdev
, cap
+ PCI_VPD_DATA
, &val
);
811 static void skge_vpd_write(struct pci_dev
*pdev
, int cap
, u16 offset
, u32 val
)
813 pci_write_config_dword(pdev
, cap
+ PCI_VPD_DATA
, val
);
814 pci_write_config_word(pdev
, cap
+ PCI_VPD_ADDR
,
815 offset
| PCI_VPD_ADDR_F
);
818 pci_read_config_word(pdev
, cap
+ PCI_VPD_ADDR
, &offset
);
819 } while (offset
& PCI_VPD_ADDR_F
);
822 static int skge_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
825 struct skge_port
*skge
= netdev_priv(dev
);
826 struct pci_dev
*pdev
= skge
->hw
->pdev
;
827 int cap
= pci_find_capability(pdev
, PCI_CAP_ID_VPD
);
828 int length
= eeprom
->len
;
829 u16 offset
= eeprom
->offset
;
834 eeprom
->magic
= SKGE_EEPROM_MAGIC
;
837 u32 val
= skge_vpd_read(pdev
, cap
, offset
);
838 int n
= min_t(int, length
, sizeof(val
));
840 memcpy(data
, &val
, n
);
848 static int skge_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
851 struct skge_port
*skge
= netdev_priv(dev
);
852 struct pci_dev
*pdev
= skge
->hw
->pdev
;
853 int cap
= pci_find_capability(pdev
, PCI_CAP_ID_VPD
);
854 int length
= eeprom
->len
;
855 u16 offset
= eeprom
->offset
;
860 if (eeprom
->magic
!= SKGE_EEPROM_MAGIC
)
865 int n
= min_t(int, length
, sizeof(val
));
868 val
= skge_vpd_read(pdev
, cap
, offset
);
869 memcpy(&val
, data
, n
);
871 skge_vpd_write(pdev
, cap
, offset
, val
);
880 static const struct ethtool_ops skge_ethtool_ops
= {
881 .get_settings
= skge_get_settings
,
882 .set_settings
= skge_set_settings
,
883 .get_drvinfo
= skge_get_drvinfo
,
884 .get_regs_len
= skge_get_regs_len
,
885 .get_regs
= skge_get_regs
,
886 .get_wol
= skge_get_wol
,
887 .set_wol
= skge_set_wol
,
888 .get_msglevel
= skge_get_msglevel
,
889 .set_msglevel
= skge_set_msglevel
,
890 .nway_reset
= skge_nway_reset
,
891 .get_link
= ethtool_op_get_link
,
892 .get_eeprom_len
= skge_get_eeprom_len
,
893 .get_eeprom
= skge_get_eeprom
,
894 .set_eeprom
= skge_set_eeprom
,
895 .get_ringparam
= skge_get_ring_param
,
896 .set_ringparam
= skge_set_ring_param
,
897 .get_pauseparam
= skge_get_pauseparam
,
898 .set_pauseparam
= skge_set_pauseparam
,
899 .get_coalesce
= skge_get_coalesce
,
900 .set_coalesce
= skge_set_coalesce
,
901 .get_strings
= skge_get_strings
,
902 .set_phys_id
= skge_set_phys_id
,
903 .get_sset_count
= skge_get_sset_count
,
904 .get_ethtool_stats
= skge_get_ethtool_stats
,
908 * Allocate ring elements and chain them together
909 * One-to-one association of board descriptors with ring elements
911 static int skge_ring_alloc(struct skge_ring
*ring
, void *vaddr
, u32 base
)
913 struct skge_tx_desc
*d
;
914 struct skge_element
*e
;
917 ring
->start
= kcalloc(ring
->count
, sizeof(*e
), GFP_KERNEL
);
921 for (i
= 0, e
= ring
->start
, d
= vaddr
; i
< ring
->count
; i
++, e
++, d
++) {
923 if (i
== ring
->count
- 1) {
924 e
->next
= ring
->start
;
925 d
->next_offset
= base
;
928 d
->next_offset
= base
+ (i
+1) * sizeof(*d
);
931 ring
->to_use
= ring
->to_clean
= ring
->start
;
936 /* Allocate and setup a new buffer for receiving */
937 static void skge_rx_setup(struct skge_port
*skge
, struct skge_element
*e
,
938 struct sk_buff
*skb
, unsigned int bufsize
)
940 struct skge_rx_desc
*rd
= e
->desc
;
943 map
= pci_map_single(skge
->hw
->pdev
, skb
->data
, bufsize
,
947 rd
->dma_hi
= map
>> 32;
949 rd
->csum1_start
= ETH_HLEN
;
950 rd
->csum2_start
= ETH_HLEN
;
956 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| bufsize
;
957 dma_unmap_addr_set(e
, mapaddr
, map
);
958 dma_unmap_len_set(e
, maplen
, bufsize
);
961 /* Resume receiving using existing skb,
962 * Note: DMA address is not changed by chip.
963 * MTU not changed while receiver active.
965 static inline void skge_rx_reuse(struct skge_element
*e
, unsigned int size
)
967 struct skge_rx_desc
*rd
= e
->desc
;
970 rd
->csum2_start
= ETH_HLEN
;
974 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| size
;
978 /* Free all buffers in receive ring, assumes receiver stopped */
979 static void skge_rx_clean(struct skge_port
*skge
)
981 struct skge_hw
*hw
= skge
->hw
;
982 struct skge_ring
*ring
= &skge
->rx_ring
;
983 struct skge_element
*e
;
987 struct skge_rx_desc
*rd
= e
->desc
;
990 pci_unmap_single(hw
->pdev
,
991 dma_unmap_addr(e
, mapaddr
),
992 dma_unmap_len(e
, maplen
),
994 dev_kfree_skb(e
->skb
);
997 } while ((e
= e
->next
) != ring
->start
);
1001 /* Allocate buffers for receive ring
1002 * For receive: to_clean is next received frame.
1004 static int skge_rx_fill(struct net_device
*dev
)
1006 struct skge_port
*skge
= netdev_priv(dev
);
1007 struct skge_ring
*ring
= &skge
->rx_ring
;
1008 struct skge_element
*e
;
1012 struct sk_buff
*skb
;
1014 skb
= __netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
,
1019 skb_reserve(skb
, NET_IP_ALIGN
);
1020 skge_rx_setup(skge
, e
, skb
, skge
->rx_buf_size
);
1021 } while ((e
= e
->next
) != ring
->start
);
1023 ring
->to_clean
= ring
->start
;
1027 static const char *skge_pause(enum pause_status status
)
1030 case FLOW_STAT_NONE
:
1032 case FLOW_STAT_REM_SEND
:
1034 case FLOW_STAT_LOC_SEND
:
1036 case FLOW_STAT_SYMMETRIC
: /* Both station may send PAUSE */
1039 return "indeterminated";
1044 static void skge_link_up(struct skge_port
*skge
)
1046 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
),
1047 LED_BLK_OFF
|LED_SYNC_OFF
|LED_ON
);
1049 netif_carrier_on(skge
->netdev
);
1050 netif_wake_queue(skge
->netdev
);
1052 netif_info(skge
, link
, skge
->netdev
,
1053 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1055 skge
->duplex
== DUPLEX_FULL
? "full" : "half",
1056 skge_pause(skge
->flow_status
));
1059 static void skge_link_down(struct skge_port
*skge
)
1061 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
1062 netif_carrier_off(skge
->netdev
);
1063 netif_stop_queue(skge
->netdev
);
1065 netif_info(skge
, link
, skge
->netdev
, "Link is down\n");
1068 static void xm_link_down(struct skge_hw
*hw
, int port
)
1070 struct net_device
*dev
= hw
->dev
[port
];
1071 struct skge_port
*skge
= netdev_priv(dev
);
1073 xm_write16(hw
, port
, XM_IMSK
, XM_IMSK_DISABLE
);
1075 if (netif_carrier_ok(dev
))
1076 skge_link_down(skge
);
1079 static int __xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1083 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
1084 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
1086 if (hw
->phy_type
== SK_PHY_XMAC
)
1089 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1090 if (xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_RDY
)
1097 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
1102 static u16
xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1105 if (__xm_phy_read(hw
, port
, reg
, &v
))
1106 pr_warning("%s: phy read timed out\n", hw
->dev
[port
]->name
);
1110 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1114 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
1115 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1116 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
1123 xm_write16(hw
, port
, XM_PHY_DATA
, val
);
1124 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1125 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
1132 static void genesis_init(struct skge_hw
*hw
)
1134 /* set blink source counter */
1135 skge_write32(hw
, B2_BSC_INI
, (SK_BLK_DUR
* SK_FACT_53
) / 100);
1136 skge_write8(hw
, B2_BSC_CTRL
, BSC_START
);
1138 /* configure mac arbiter */
1139 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1141 /* configure mac arbiter timeout values */
1142 skge_write8(hw
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
1143 skge_write8(hw
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
1144 skge_write8(hw
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
1145 skge_write8(hw
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
1147 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1148 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1149 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1150 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1152 /* configure packet arbiter timeout */
1153 skge_write16(hw
, B3_PA_CTRL
, PA_RST_CLR
);
1154 skge_write16(hw
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
1155 skge_write16(hw
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
1156 skge_write16(hw
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
1157 skge_write16(hw
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
1160 static void genesis_reset(struct skge_hw
*hw
, int port
)
1162 static const u8 zero
[8] = { 0 };
1165 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
1167 /* reset the statistics module */
1168 xm_write32(hw
, port
, XM_GP_PORT
, XM_GP_RES_STAT
);
1169 xm_write16(hw
, port
, XM_IMSK
, XM_IMSK_DISABLE
);
1170 xm_write32(hw
, port
, XM_MODE
, 0); /* clear Mode Reg */
1171 xm_write16(hw
, port
, XM_TX_CMD
, 0); /* reset TX CMD Reg */
1172 xm_write16(hw
, port
, XM_RX_CMD
, 0); /* reset RX CMD Reg */
1174 /* disable Broadcom PHY IRQ */
1175 if (hw
->phy_type
== SK_PHY_BCOM
)
1176 xm_write16(hw
, port
, PHY_BCOM_INT_MASK
, 0xffff);
1178 xm_outhash(hw
, port
, XM_HSM
, zero
);
1180 /* Flush TX and RX fifo */
1181 reg
= xm_read32(hw
, port
, XM_MODE
);
1182 xm_write32(hw
, port
, XM_MODE
, reg
| XM_MD_FTF
);
1183 xm_write32(hw
, port
, XM_MODE
, reg
| XM_MD_FRF
);
1186 /* Convert mode to MII values */
1187 static const u16 phy_pause_map
[] = {
1188 [FLOW_MODE_NONE
] = 0,
1189 [FLOW_MODE_LOC_SEND
] = PHY_AN_PAUSE_ASYM
,
1190 [FLOW_MODE_SYMMETRIC
] = PHY_AN_PAUSE_CAP
,
1191 [FLOW_MODE_SYM_OR_REM
] = PHY_AN_PAUSE_CAP
| PHY_AN_PAUSE_ASYM
,
1194 /* special defines for FIBER (88E1011S only) */
1195 static const u16 fiber_pause_map
[] = {
1196 [FLOW_MODE_NONE
] = PHY_X_P_NO_PAUSE
,
1197 [FLOW_MODE_LOC_SEND
] = PHY_X_P_ASYM_MD
,
1198 [FLOW_MODE_SYMMETRIC
] = PHY_X_P_SYM_MD
,
1199 [FLOW_MODE_SYM_OR_REM
] = PHY_X_P_BOTH_MD
,
1203 /* Check status of Broadcom phy link */
1204 static void bcom_check_link(struct skge_hw
*hw
, int port
)
1206 struct net_device
*dev
= hw
->dev
[port
];
1207 struct skge_port
*skge
= netdev_priv(dev
);
1210 /* read twice because of latch */
1211 xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1212 status
= xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1214 if ((status
& PHY_ST_LSYNC
) == 0) {
1215 xm_link_down(hw
, port
);
1219 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1222 if (!(status
& PHY_ST_AN_OVER
))
1225 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1226 if (lpa
& PHY_B_AN_RF
) {
1227 netdev_notice(dev
, "remote fault\n");
1231 aux
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_STAT
);
1233 /* Check Duplex mismatch */
1234 switch (aux
& PHY_B_AS_AN_RES_MSK
) {
1235 case PHY_B_RES_1000FD
:
1236 skge
->duplex
= DUPLEX_FULL
;
1238 case PHY_B_RES_1000HD
:
1239 skge
->duplex
= DUPLEX_HALF
;
1242 netdev_notice(dev
, "duplex mismatch\n");
1246 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1247 switch (aux
& PHY_B_AS_PAUSE_MSK
) {
1248 case PHY_B_AS_PAUSE_MSK
:
1249 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1252 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1255 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1258 skge
->flow_status
= FLOW_STAT_NONE
;
1260 skge
->speed
= SPEED_1000
;
1263 if (!netif_carrier_ok(dev
))
1264 genesis_link_up(skge
);
1267 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1268 * Phy on for 100 or 10Mbit operation
1270 static void bcom_phy_init(struct skge_port
*skge
)
1272 struct skge_hw
*hw
= skge
->hw
;
1273 int port
= skge
->port
;
1275 u16 id1
, r
, ext
, ctl
;
1277 /* magic workaround patterns for Broadcom */
1278 static const struct {
1282 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1283 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1284 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1285 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1287 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1288 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1291 /* read Id from external PHY (all have the same address) */
1292 id1
= xm_phy_read(hw
, port
, PHY_XMAC_ID1
);
1294 /* Optimize MDIO transfer by suppressing preamble. */
1295 r
= xm_read16(hw
, port
, XM_MMU_CMD
);
1297 xm_write16(hw
, port
, XM_MMU_CMD
, r
);
1300 case PHY_BCOM_ID1_C0
:
1302 * Workaround BCOM Errata for the C0 type.
1303 * Write magic patterns to reserved registers.
1305 for (i
= 0; i
< ARRAY_SIZE(C0hack
); i
++)
1306 xm_phy_write(hw
, port
,
1307 C0hack
[i
].reg
, C0hack
[i
].val
);
1310 case PHY_BCOM_ID1_A1
:
1312 * Workaround BCOM Errata for the A1 type.
1313 * Write magic patterns to reserved registers.
1315 for (i
= 0; i
< ARRAY_SIZE(A1hack
); i
++)
1316 xm_phy_write(hw
, port
,
1317 A1hack
[i
].reg
, A1hack
[i
].val
);
1322 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1323 * Disable Power Management after reset.
1325 r
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
);
1326 r
|= PHY_B_AC_DIS_PM
;
1327 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
, r
);
1330 xm_read16(hw
, port
, XM_ISRC
);
1332 ext
= PHY_B_PEC_EN_LTR
; /* enable tx led */
1333 ctl
= PHY_CT_SP1000
; /* always 1000mbit */
1335 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1337 * Workaround BCOM Errata #1 for the C5 type.
1338 * 1000Base-T Link Acquisition Failure in Slave Mode
1339 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1341 u16 adv
= PHY_B_1000C_RD
;
1342 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1343 adv
|= PHY_B_1000C_AHD
;
1344 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1345 adv
|= PHY_B_1000C_AFD
;
1346 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, adv
);
1348 ctl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1350 if (skge
->duplex
== DUPLEX_FULL
)
1351 ctl
|= PHY_CT_DUP_MD
;
1352 /* Force to slave */
1353 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, PHY_B_1000C_MSE
);
1356 /* Set autonegotiation pause parameters */
1357 xm_phy_write(hw
, port
, PHY_BCOM_AUNE_ADV
,
1358 phy_pause_map
[skge
->flow_control
] | PHY_AN_CSMA
);
1360 /* Handle Jumbo frames */
1361 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
1362 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1363 PHY_B_AC_TX_TST
| PHY_B_AC_LONG_PACK
);
1365 ext
|= PHY_B_PEC_HIGH_LA
;
1369 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, ext
);
1370 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
, ctl
);
1372 /* Use link status change interrupt */
1373 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1376 static void xm_phy_init(struct skge_port
*skge
)
1378 struct skge_hw
*hw
= skge
->hw
;
1379 int port
= skge
->port
;
1382 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1383 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1384 ctrl
|= PHY_X_AN_HD
;
1385 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1386 ctrl
|= PHY_X_AN_FD
;
1388 ctrl
|= fiber_pause_map
[skge
->flow_control
];
1390 xm_phy_write(hw
, port
, PHY_XMAC_AUNE_ADV
, ctrl
);
1392 /* Restart Auto-negotiation */
1393 ctrl
= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1395 /* Set DuplexMode in Config register */
1396 if (skge
->duplex
== DUPLEX_FULL
)
1397 ctrl
|= PHY_CT_DUP_MD
;
1399 * Do NOT enable Auto-negotiation here. This would hold
1400 * the link down because no IDLEs are transmitted
1404 xm_phy_write(hw
, port
, PHY_XMAC_CTRL
, ctrl
);
1406 /* Poll PHY for status changes */
1407 mod_timer(&skge
->link_timer
, jiffies
+ LINK_HZ
);
1410 static int xm_check_link(struct net_device
*dev
)
1412 struct skge_port
*skge
= netdev_priv(dev
);
1413 struct skge_hw
*hw
= skge
->hw
;
1414 int port
= skge
->port
;
1417 /* read twice because of latch */
1418 xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1419 status
= xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1421 if ((status
& PHY_ST_LSYNC
) == 0) {
1422 xm_link_down(hw
, port
);
1426 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1429 if (!(status
& PHY_ST_AN_OVER
))
1432 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1433 if (lpa
& PHY_B_AN_RF
) {
1434 netdev_notice(dev
, "remote fault\n");
1438 res
= xm_phy_read(hw
, port
, PHY_XMAC_RES_ABI
);
1440 /* Check Duplex mismatch */
1441 switch (res
& (PHY_X_RS_HD
| PHY_X_RS_FD
)) {
1443 skge
->duplex
= DUPLEX_FULL
;
1446 skge
->duplex
= DUPLEX_HALF
;
1449 netdev_notice(dev
, "duplex mismatch\n");
1453 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1454 if ((skge
->flow_control
== FLOW_MODE_SYMMETRIC
||
1455 skge
->flow_control
== FLOW_MODE_SYM_OR_REM
) &&
1456 (lpa
& PHY_X_P_SYM_MD
))
1457 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1458 else if (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
&&
1459 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_ASYM_MD
)
1460 /* Enable PAUSE receive, disable PAUSE transmit */
1461 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1462 else if (skge
->flow_control
== FLOW_MODE_LOC_SEND
&&
1463 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_BOTH_MD
)
1464 /* Disable PAUSE receive, enable PAUSE transmit */
1465 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1467 skge
->flow_status
= FLOW_STAT_NONE
;
1469 skge
->speed
= SPEED_1000
;
1472 if (!netif_carrier_ok(dev
))
1473 genesis_link_up(skge
);
1477 /* Poll to check for link coming up.
1479 * Since internal PHY is wired to a level triggered pin, can't
1480 * get an interrupt when carrier is detected, need to poll for
1483 static void xm_link_timer(unsigned long arg
)
1485 struct skge_port
*skge
= (struct skge_port
*) arg
;
1486 struct net_device
*dev
= skge
->netdev
;
1487 struct skge_hw
*hw
= skge
->hw
;
1488 int port
= skge
->port
;
1490 unsigned long flags
;
1492 if (!netif_running(dev
))
1495 spin_lock_irqsave(&hw
->phy_lock
, flags
);
1498 * Verify that the link by checking GPIO register three times.
1499 * This pin has the signal from the link_sync pin connected to it.
1501 for (i
= 0; i
< 3; i
++) {
1502 if (xm_read16(hw
, port
, XM_GP_PORT
) & XM_GP_INP_ASS
)
1506 /* Re-enable interrupt to detect link down */
1507 if (xm_check_link(dev
)) {
1508 u16 msk
= xm_read16(hw
, port
, XM_IMSK
);
1509 msk
&= ~XM_IS_INP_ASS
;
1510 xm_write16(hw
, port
, XM_IMSK
, msk
);
1511 xm_read16(hw
, port
, XM_ISRC
);
1514 mod_timer(&skge
->link_timer
,
1515 round_jiffies(jiffies
+ LINK_HZ
));
1517 spin_unlock_irqrestore(&hw
->phy_lock
, flags
);
1520 static void genesis_mac_init(struct skge_hw
*hw
, int port
)
1522 struct net_device
*dev
= hw
->dev
[port
];
1523 struct skge_port
*skge
= netdev_priv(dev
);
1524 int jumbo
= hw
->dev
[port
]->mtu
> ETH_DATA_LEN
;
1527 static const u8 zero
[6] = { 0 };
1529 for (i
= 0; i
< 10; i
++) {
1530 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
1532 if (skge_read16(hw
, SK_REG(port
, TX_MFF_CTRL1
)) & MFF_SET_MAC_RST
)
1537 netdev_warn(dev
, "genesis reset failed\n");
1540 /* Unreset the XMAC. */
1541 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1544 * Perform additional initialization for external PHYs,
1545 * namely for the 1000baseTX cards that use the XMAC's
1548 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1549 /* Take external Phy out of reset */
1550 r
= skge_read32(hw
, B2_GP_IO
);
1552 r
|= GP_DIR_0
|GP_IO_0
;
1554 r
|= GP_DIR_2
|GP_IO_2
;
1556 skge_write32(hw
, B2_GP_IO
, r
);
1558 /* Enable GMII interface */
1559 xm_write16(hw
, port
, XM_HW_CFG
, XM_HW_GMII_MD
);
1563 switch (hw
->phy_type
) {
1568 bcom_phy_init(skge
);
1569 bcom_check_link(hw
, port
);
1572 /* Set Station Address */
1573 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
1575 /* We don't use match addresses so clear */
1576 for (i
= 1; i
< 16; i
++)
1577 xm_outaddr(hw
, port
, XM_EXM(i
), zero
);
1579 /* Clear MIB counters */
1580 xm_write16(hw
, port
, XM_STAT_CMD
,
1581 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1582 /* Clear two times according to Errata #3 */
1583 xm_write16(hw
, port
, XM_STAT_CMD
,
1584 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1586 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1587 xm_write16(hw
, port
, XM_RX_HI_WM
, 1450);
1589 /* We don't need the FCS appended to the packet. */
1590 r
= XM_RX_LENERR_OK
| XM_RX_STRIP_FCS
;
1592 r
|= XM_RX_BIG_PK_OK
;
1594 if (skge
->duplex
== DUPLEX_HALF
) {
1596 * If in manual half duplex mode the other side might be in
1597 * full duplex mode, so ignore if a carrier extension is not seen
1598 * on frames received
1600 r
|= XM_RX_DIS_CEXT
;
1602 xm_write16(hw
, port
, XM_RX_CMD
, r
);
1604 /* We want short frames padded to 60 bytes. */
1605 xm_write16(hw
, port
, XM_TX_CMD
, XM_TX_AUTO_PAD
);
1607 /* Increase threshold for jumbo frames on dual port */
1608 if (hw
->ports
> 1 && jumbo
)
1609 xm_write16(hw
, port
, XM_TX_THR
, 1020);
1611 xm_write16(hw
, port
, XM_TX_THR
, 512);
1614 * Enable the reception of all error frames. This is is
1615 * a necessary evil due to the design of the XMAC. The
1616 * XMAC's receive FIFO is only 8K in size, however jumbo
1617 * frames can be up to 9000 bytes in length. When bad
1618 * frame filtering is enabled, the XMAC's RX FIFO operates
1619 * in 'store and forward' mode. For this to work, the
1620 * entire frame has to fit into the FIFO, but that means
1621 * that jumbo frames larger than 8192 bytes will be
1622 * truncated. Disabling all bad frame filtering causes
1623 * the RX FIFO to operate in streaming mode, in which
1624 * case the XMAC will start transferring frames out of the
1625 * RX FIFO as soon as the FIFO threshold is reached.
1627 xm_write32(hw
, port
, XM_MODE
, XM_DEF_MODE
);
1631 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1632 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1633 * and 'Octets Rx OK Hi Cnt Ov'.
1635 xm_write32(hw
, port
, XM_RX_EV_MSK
, XMR_DEF_MSK
);
1638 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1639 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1640 * and 'Octets Tx OK Hi Cnt Ov'.
1642 xm_write32(hw
, port
, XM_TX_EV_MSK
, XMT_DEF_MSK
);
1644 /* Configure MAC arbiter */
1645 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1647 /* configure timeout values */
1648 skge_write8(hw
, B3_MA_TOINI_RX1
, 72);
1649 skge_write8(hw
, B3_MA_TOINI_RX2
, 72);
1650 skge_write8(hw
, B3_MA_TOINI_TX1
, 72);
1651 skge_write8(hw
, B3_MA_TOINI_TX2
, 72);
1653 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1654 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1655 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1656 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1658 /* Configure Rx MAC FIFO */
1659 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1660 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_TIM_PAT
);
1661 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1663 /* Configure Tx MAC FIFO */
1664 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1665 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1666 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1669 /* Enable frame flushing if jumbo frames used */
1670 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1672 /* enable timeout timers if normal frames */
1673 skge_write16(hw
, B3_PA_CTRL
,
1674 (port
== 0) ? PA_ENA_TO_TX1
: PA_ENA_TO_TX2
);
1678 static void genesis_stop(struct skge_port
*skge
)
1680 struct skge_hw
*hw
= skge
->hw
;
1681 int port
= skge
->port
;
1682 unsigned retries
= 1000;
1685 /* Disable Tx and Rx */
1686 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1687 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1688 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1690 genesis_reset(hw
, port
);
1692 /* Clear Tx packet arbiter timeout IRQ */
1693 skge_write16(hw
, B3_PA_CTRL
,
1694 port
== 0 ? PA_CLR_TO_TX1
: PA_CLR_TO_TX2
);
1697 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1699 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_SET_MAC_RST
);
1700 if (!(skge_read16(hw
, SK_REG(port
, TX_MFF_CTRL1
)) & MFF_SET_MAC_RST
))
1702 } while (--retries
> 0);
1704 /* For external PHYs there must be special handling */
1705 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1706 u32 reg
= skge_read32(hw
, B2_GP_IO
);
1714 skge_write32(hw
, B2_GP_IO
, reg
);
1715 skge_read32(hw
, B2_GP_IO
);
1718 xm_write16(hw
, port
, XM_MMU_CMD
,
1719 xm_read16(hw
, port
, XM_MMU_CMD
)
1720 & ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
));
1722 xm_read16(hw
, port
, XM_MMU_CMD
);
1726 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
)
1728 struct skge_hw
*hw
= skge
->hw
;
1729 int port
= skge
->port
;
1731 unsigned long timeout
= jiffies
+ HZ
;
1733 xm_write16(hw
, port
,
1734 XM_STAT_CMD
, XM_SC_SNP_TXC
| XM_SC_SNP_RXC
);
1736 /* wait for update to complete */
1737 while (xm_read16(hw
, port
, XM_STAT_CMD
)
1738 & (XM_SC_SNP_TXC
| XM_SC_SNP_RXC
)) {
1739 if (time_after(jiffies
, timeout
))
1744 /* special case for 64 bit octet counter */
1745 data
[0] = (u64
) xm_read32(hw
, port
, XM_TXO_OK_HI
) << 32
1746 | xm_read32(hw
, port
, XM_TXO_OK_LO
);
1747 data
[1] = (u64
) xm_read32(hw
, port
, XM_RXO_OK_HI
) << 32
1748 | xm_read32(hw
, port
, XM_RXO_OK_LO
);
1750 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1751 data
[i
] = xm_read32(hw
, port
, skge_stats
[i
].xmac_offset
);
1754 static void genesis_mac_intr(struct skge_hw
*hw
, int port
)
1756 struct net_device
*dev
= hw
->dev
[port
];
1757 struct skge_port
*skge
= netdev_priv(dev
);
1758 u16 status
= xm_read16(hw
, port
, XM_ISRC
);
1760 netif_printk(skge
, intr
, KERN_DEBUG
, skge
->netdev
,
1761 "mac interrupt status 0x%x\n", status
);
1763 if (hw
->phy_type
== SK_PHY_XMAC
&& (status
& XM_IS_INP_ASS
)) {
1764 xm_link_down(hw
, port
);
1765 mod_timer(&skge
->link_timer
, jiffies
+ 1);
1768 if (status
& XM_IS_TXF_UR
) {
1769 xm_write32(hw
, port
, XM_MODE
, XM_MD_FTF
);
1770 ++dev
->stats
.tx_fifo_errors
;
1774 static void genesis_link_up(struct skge_port
*skge
)
1776 struct skge_hw
*hw
= skge
->hw
;
1777 int port
= skge
->port
;
1781 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1784 * enabling pause frame reception is required for 1000BT
1785 * because the XMAC is not reset if the link is going down
1787 if (skge
->flow_status
== FLOW_STAT_NONE
||
1788 skge
->flow_status
== FLOW_STAT_LOC_SEND
)
1789 /* Disable Pause Frame Reception */
1790 cmd
|= XM_MMU_IGN_PF
;
1792 /* Enable Pause Frame Reception */
1793 cmd
&= ~XM_MMU_IGN_PF
;
1795 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1797 mode
= xm_read32(hw
, port
, XM_MODE
);
1798 if (skge
->flow_status
== FLOW_STAT_SYMMETRIC
||
1799 skge
->flow_status
== FLOW_STAT_LOC_SEND
) {
1801 * Configure Pause Frame Generation
1802 * Use internal and external Pause Frame Generation.
1803 * Sending pause frames is edge triggered.
1804 * Send a Pause frame with the maximum pause time if
1805 * internal oder external FIFO full condition occurs.
1806 * Send a zero pause time frame to re-start transmission.
1808 /* XM_PAUSE_DA = '010000C28001' (default) */
1809 /* XM_MAC_PTIME = 0xffff (maximum) */
1810 /* remember this value is defined in big endian (!) */
1811 xm_write16(hw
, port
, XM_MAC_PTIME
, 0xffff);
1813 mode
|= XM_PAUSE_MODE
;
1814 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_PAUSE
);
1817 * disable pause frame generation is required for 1000BT
1818 * because the XMAC is not reset if the link is going down
1820 /* Disable Pause Mode in Mode Register */
1821 mode
&= ~XM_PAUSE_MODE
;
1823 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_DIS_PAUSE
);
1826 xm_write32(hw
, port
, XM_MODE
, mode
);
1828 /* Turn on detection of Tx underrun */
1829 msk
= xm_read16(hw
, port
, XM_IMSK
);
1830 msk
&= ~XM_IS_TXF_UR
;
1831 xm_write16(hw
, port
, XM_IMSK
, msk
);
1833 xm_read16(hw
, port
, XM_ISRC
);
1835 /* get MMU Command Reg. */
1836 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1837 if (hw
->phy_type
!= SK_PHY_XMAC
&& skge
->duplex
== DUPLEX_FULL
)
1838 cmd
|= XM_MMU_GMII_FD
;
1841 * Workaround BCOM Errata (#10523) for all BCom Phys
1842 * Enable Power Management after link up
1844 if (hw
->phy_type
== SK_PHY_BCOM
) {
1845 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1846 xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
)
1847 & ~PHY_B_AC_DIS_PM
);
1848 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1852 xm_write16(hw
, port
, XM_MMU_CMD
,
1853 cmd
| XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1858 static inline void bcom_phy_intr(struct skge_port
*skge
)
1860 struct skge_hw
*hw
= skge
->hw
;
1861 int port
= skge
->port
;
1864 isrc
= xm_phy_read(hw
, port
, PHY_BCOM_INT_STAT
);
1865 netif_printk(skge
, intr
, KERN_DEBUG
, skge
->netdev
,
1866 "phy interrupt status 0x%x\n", isrc
);
1868 if (isrc
& PHY_B_IS_PSE
)
1869 pr_err("%s: uncorrectable pair swap error\n",
1870 hw
->dev
[port
]->name
);
1872 /* Workaround BCom Errata:
1873 * enable and disable loopback mode if "NO HCD" occurs.
1875 if (isrc
& PHY_B_IS_NO_HDCL
) {
1876 u16 ctrl
= xm_phy_read(hw
, port
, PHY_BCOM_CTRL
);
1877 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1878 ctrl
| PHY_CT_LOOP
);
1879 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1880 ctrl
& ~PHY_CT_LOOP
);
1883 if (isrc
& (PHY_B_IS_AN_PR
| PHY_B_IS_LST_CHANGE
))
1884 bcom_check_link(hw
, port
);
1888 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1892 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
1893 gma_write16(hw
, port
, GM_SMI_CTRL
,
1894 GM_SMI_CT_PHY_AD(hw
->phy_addr
) | GM_SMI_CT_REG_AD(reg
));
1895 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1898 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
1902 pr_warning("%s: phy write timeout\n", hw
->dev
[port
]->name
);
1906 static int __gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1910 gma_write16(hw
, port
, GM_SMI_CTRL
,
1911 GM_SMI_CT_PHY_AD(hw
->phy_addr
)
1912 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
1914 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1916 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
)
1922 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
1926 static u16
gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1929 if (__gm_phy_read(hw
, port
, reg
, &v
))
1930 pr_warning("%s: phy read timeout\n", hw
->dev
[port
]->name
);
1934 /* Marvell Phy Initialization */
1935 static void yukon_init(struct skge_hw
*hw
, int port
)
1937 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1938 u16 ctrl
, ct1000
, adv
;
1940 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1941 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
1943 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
1944 PHY_M_EC_MAC_S_MSK
);
1945 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
1947 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1949 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
1952 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
1953 if (skge
->autoneg
== AUTONEG_DISABLE
)
1954 ctrl
&= ~PHY_CT_ANE
;
1956 ctrl
|= PHY_CT_RESET
;
1957 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1963 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1965 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1966 ct1000
|= PHY_M_1000C_AFD
;
1967 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1968 ct1000
|= PHY_M_1000C_AHD
;
1969 if (skge
->advertising
& ADVERTISED_100baseT_Full
)
1970 adv
|= PHY_M_AN_100_FD
;
1971 if (skge
->advertising
& ADVERTISED_100baseT_Half
)
1972 adv
|= PHY_M_AN_100_HD
;
1973 if (skge
->advertising
& ADVERTISED_10baseT_Full
)
1974 adv
|= PHY_M_AN_10_FD
;
1975 if (skge
->advertising
& ADVERTISED_10baseT_Half
)
1976 adv
|= PHY_M_AN_10_HD
;
1978 /* Set Flow-control capabilities */
1979 adv
|= phy_pause_map
[skge
->flow_control
];
1981 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1982 adv
|= PHY_M_AN_1000X_AFD
;
1983 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1984 adv
|= PHY_M_AN_1000X_AHD
;
1986 adv
|= fiber_pause_map
[skge
->flow_control
];
1989 /* Restart Auto-negotiation */
1990 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1992 /* forced speed/duplex settings */
1993 ct1000
= PHY_M_1000C_MSE
;
1995 if (skge
->duplex
== DUPLEX_FULL
)
1996 ctrl
|= PHY_CT_DUP_MD
;
1998 switch (skge
->speed
) {
2000 ctrl
|= PHY_CT_SP1000
;
2003 ctrl
|= PHY_CT_SP100
;
2007 ctrl
|= PHY_CT_RESET
;
2010 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
2012 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
2013 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2015 /* Enable phy interrupt on autonegotiation complete (or link up) */
2016 if (skge
->autoneg
== AUTONEG_ENABLE
)
2017 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_MSK
);
2019 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
2022 static void yukon_reset(struct skge_hw
*hw
, int port
)
2024 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);/* disable PHY IRQs */
2025 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
2026 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
2027 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
2028 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
2030 gma_write16(hw
, port
, GM_RX_CTRL
,
2031 gma_read16(hw
, port
, GM_RX_CTRL
)
2032 | GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2035 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2036 static int is_yukon_lite_a0(struct skge_hw
*hw
)
2041 if (hw
->chip_id
!= CHIP_ID_YUKON
)
2044 reg
= skge_read32(hw
, B2_FAR
);
2045 skge_write8(hw
, B2_FAR
+ 3, 0xff);
2046 ret
= (skge_read8(hw
, B2_FAR
+ 3) != 0);
2047 skge_write32(hw
, B2_FAR
, reg
);
2051 static void yukon_mac_init(struct skge_hw
*hw
, int port
)
2053 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
2056 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
2058 /* WA code for COMA mode -- set PHY reset */
2059 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
2060 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
2061 reg
= skge_read32(hw
, B2_GP_IO
);
2062 reg
|= GP_DIR_9
| GP_IO_9
;
2063 skge_write32(hw
, B2_GP_IO
, reg
);
2067 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2068 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2070 /* WA code for COMA mode -- clear PHY reset */
2071 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
2072 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
2073 reg
= skge_read32(hw
, B2_GP_IO
);
2076 skge_write32(hw
, B2_GP_IO
, reg
);
2079 /* Set hardware config mode */
2080 reg
= GPC_INT_POL_HI
| GPC_DIS_FC
| GPC_DIS_SLEEP
|
2081 GPC_ENA_XC
| GPC_ANEG_ADV_ALL_M
| GPC_ENA_PAUSE
;
2082 reg
|= hw
->copper
? GPC_HWCFG_GMII_COP
: GPC_HWCFG_GMII_FIB
;
2084 /* Clear GMC reset */
2085 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_SET
);
2086 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_CLR
);
2087 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
| GMC_RST_CLR
);
2089 if (skge
->autoneg
== AUTONEG_DISABLE
) {
2090 reg
= GM_GPCR_AU_ALL_DIS
;
2091 gma_write16(hw
, port
, GM_GP_CTRL
,
2092 gma_read16(hw
, port
, GM_GP_CTRL
) | reg
);
2094 switch (skge
->speed
) {
2096 reg
&= ~GM_GPCR_SPEED_100
;
2097 reg
|= GM_GPCR_SPEED_1000
;
2100 reg
&= ~GM_GPCR_SPEED_1000
;
2101 reg
|= GM_GPCR_SPEED_100
;
2104 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
2108 if (skge
->duplex
== DUPLEX_FULL
)
2109 reg
|= GM_GPCR_DUP_FULL
;
2111 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
2113 switch (skge
->flow_control
) {
2114 case FLOW_MODE_NONE
:
2115 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2116 reg
|= GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
2118 case FLOW_MODE_LOC_SEND
:
2119 /* disable Rx flow-control */
2120 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
2122 case FLOW_MODE_SYMMETRIC
:
2123 case FLOW_MODE_SYM_OR_REM
:
2124 /* enable Tx & Rx flow-control */
2128 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2129 skge_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2131 yukon_init(hw
, port
);
2134 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
2135 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
2137 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
2138 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8*i
);
2139 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
2141 /* transmit control */
2142 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
2144 /* receive control reg: unicast + multicast + no FCS */
2145 gma_write16(hw
, port
, GM_RX_CTRL
,
2146 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
2148 /* transmit flow control */
2149 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
2151 /* transmit parameter */
2152 gma_write16(hw
, port
, GM_TX_PARAM
,
2153 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
2154 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
2155 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
));
2157 /* configure the Serial Mode Register */
2158 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
)
2160 | IPG_DATA_VAL(IPG_DATA_DEF
);
2162 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
2163 reg
|= GM_SMOD_JUMBO_ENA
;
2165 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
2167 /* physical address: used for pause frames */
2168 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
2169 /* virtual address for data */
2170 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
2172 /* enable interrupt mask for counter overflows */
2173 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
2174 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
2175 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
2177 /* Initialize Mac Fifo */
2179 /* Configure Rx MAC FIFO */
2180 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), RX_FF_FL_DEF_MSK
);
2181 reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
2183 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2184 if (is_yukon_lite_a0(hw
))
2185 reg
&= ~GMF_RX_F_FL_ON
;
2187 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
2188 skge_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
), reg
);
2190 * because Pause Packet Truncation in GMAC is not working
2191 * we have to increase the Flush Threshold to 64 bytes
2192 * in order to flush pause packets in Rx FIFO on Yukon-1
2194 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
2196 /* Configure Tx MAC FIFO */
2197 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
2198 skge_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
2201 /* Go into power down mode */
2202 static void yukon_suspend(struct skge_hw
*hw
, int port
)
2206 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2207 ctrl
|= PHY_M_PC_POL_R_DIS
;
2208 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
2210 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2211 ctrl
|= PHY_CT_RESET
;
2212 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2214 /* switch IEEE compatible power down mode on */
2215 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2216 ctrl
|= PHY_CT_PDOWN
;
2217 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2220 static void yukon_stop(struct skge_port
*skge
)
2222 struct skge_hw
*hw
= skge
->hw
;
2223 int port
= skge
->port
;
2225 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
2226 yukon_reset(hw
, port
);
2228 gma_write16(hw
, port
, GM_GP_CTRL
,
2229 gma_read16(hw
, port
, GM_GP_CTRL
)
2230 & ~(GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
));
2231 gma_read16(hw
, port
, GM_GP_CTRL
);
2233 yukon_suspend(hw
, port
);
2235 /* set GPHY Control reset */
2236 skge_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2237 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2240 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
)
2242 struct skge_hw
*hw
= skge
->hw
;
2243 int port
= skge
->port
;
2246 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2247 | gma_read32(hw
, port
, GM_TXO_OK_LO
);
2248 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2249 | gma_read32(hw
, port
, GM_RXO_OK_LO
);
2251 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
2252 data
[i
] = gma_read32(hw
, port
,
2253 skge_stats
[i
].gma_offset
);
2256 static void yukon_mac_intr(struct skge_hw
*hw
, int port
)
2258 struct net_device
*dev
= hw
->dev
[port
];
2259 struct skge_port
*skge
= netdev_priv(dev
);
2260 u8 status
= skge_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2262 netif_printk(skge
, intr
, KERN_DEBUG
, skge
->netdev
,
2263 "mac interrupt status 0x%x\n", status
);
2265 if (status
& GM_IS_RX_FF_OR
) {
2266 ++dev
->stats
.rx_fifo_errors
;
2267 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2270 if (status
& GM_IS_TX_FF_UR
) {
2271 ++dev
->stats
.tx_fifo_errors
;
2272 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2277 static u16
yukon_speed(const struct skge_hw
*hw
, u16 aux
)
2279 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2280 case PHY_M_PS_SPEED_1000
:
2282 case PHY_M_PS_SPEED_100
:
2289 static void yukon_link_up(struct skge_port
*skge
)
2291 struct skge_hw
*hw
= skge
->hw
;
2292 int port
= skge
->port
;
2295 /* Enable Transmit FIFO Underrun */
2296 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
2298 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2299 if (skge
->duplex
== DUPLEX_FULL
|| skge
->autoneg
== AUTONEG_ENABLE
)
2300 reg
|= GM_GPCR_DUP_FULL
;
2303 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2304 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2306 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
2310 static void yukon_link_down(struct skge_port
*skge
)
2312 struct skge_hw
*hw
= skge
->hw
;
2313 int port
= skge
->port
;
2316 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2317 ctrl
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2318 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2320 if (skge
->flow_status
== FLOW_STAT_REM_SEND
) {
2321 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2322 ctrl
|= PHY_M_AN_ASP
;
2323 /* restore Asymmetric Pause bit */
2324 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, ctrl
);
2327 skge_link_down(skge
);
2329 yukon_init(hw
, port
);
2332 static void yukon_phy_intr(struct skge_port
*skge
)
2334 struct skge_hw
*hw
= skge
->hw
;
2335 int port
= skge
->port
;
2336 const char *reason
= NULL
;
2337 u16 istatus
, phystat
;
2339 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2340 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2342 netif_printk(skge
, intr
, KERN_DEBUG
, skge
->netdev
,
2343 "phy interrupt status 0x%x 0x%x\n", istatus
, phystat
);
2345 if (istatus
& PHY_M_IS_AN_COMPL
) {
2346 if (gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
)
2348 reason
= "remote fault";
2352 if (gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
2353 reason
= "master/slave fault";
2357 if (!(phystat
& PHY_M_PS_SPDUP_RES
)) {
2358 reason
= "speed/duplex";
2362 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
)
2363 ? DUPLEX_FULL
: DUPLEX_HALF
;
2364 skge
->speed
= yukon_speed(hw
, phystat
);
2366 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2367 switch (phystat
& PHY_M_PS_PAUSE_MSK
) {
2368 case PHY_M_PS_PAUSE_MSK
:
2369 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
2371 case PHY_M_PS_RX_P_EN
:
2372 skge
->flow_status
= FLOW_STAT_REM_SEND
;
2374 case PHY_M_PS_TX_P_EN
:
2375 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
2378 skge
->flow_status
= FLOW_STAT_NONE
;
2381 if (skge
->flow_status
== FLOW_STAT_NONE
||
2382 (skge
->speed
< SPEED_1000
&& skge
->duplex
== DUPLEX_HALF
))
2383 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2385 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2386 yukon_link_up(skge
);
2390 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2391 skge
->speed
= yukon_speed(hw
, phystat
);
2393 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2394 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2395 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2396 if (phystat
& PHY_M_PS_LINK_UP
)
2397 yukon_link_up(skge
);
2399 yukon_link_down(skge
);
2403 pr_err("%s: autonegotiation failed (%s)\n", skge
->netdev
->name
, reason
);
2405 /* XXX restart autonegotiation? */
2408 static void skge_phy_reset(struct skge_port
*skge
)
2410 struct skge_hw
*hw
= skge
->hw
;
2411 int port
= skge
->port
;
2412 struct net_device
*dev
= hw
->dev
[port
];
2414 netif_stop_queue(skge
->netdev
);
2415 netif_carrier_off(skge
->netdev
);
2417 spin_lock_bh(&hw
->phy_lock
);
2418 if (is_genesis(hw
)) {
2419 genesis_reset(hw
, port
);
2420 genesis_mac_init(hw
, port
);
2422 yukon_reset(hw
, port
);
2423 yukon_init(hw
, port
);
2425 spin_unlock_bh(&hw
->phy_lock
);
2427 skge_set_multicast(dev
);
2430 /* Basic MII support */
2431 static int skge_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2433 struct mii_ioctl_data
*data
= if_mii(ifr
);
2434 struct skge_port
*skge
= netdev_priv(dev
);
2435 struct skge_hw
*hw
= skge
->hw
;
2436 int err
= -EOPNOTSUPP
;
2438 if (!netif_running(dev
))
2439 return -ENODEV
; /* Phy still in reset */
2443 data
->phy_id
= hw
->phy_addr
;
2448 spin_lock_bh(&hw
->phy_lock
);
2451 err
= __xm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2453 err
= __gm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2454 spin_unlock_bh(&hw
->phy_lock
);
2455 data
->val_out
= val
;
2460 spin_lock_bh(&hw
->phy_lock
);
2462 err
= xm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2465 err
= gm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2467 spin_unlock_bh(&hw
->phy_lock
);
2473 static void skge_ramset(struct skge_hw
*hw
, u16 q
, u32 start
, size_t len
)
2479 end
= start
+ len
- 1;
2481 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
2482 skge_write32(hw
, RB_ADDR(q
, RB_START
), start
);
2483 skge_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
2484 skge_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
2485 skge_write32(hw
, RB_ADDR(q
, RB_END
), end
);
2487 if (q
== Q_R1
|| q
== Q_R2
) {
2488 /* Set thresholds on receive queue's */
2489 skge_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
),
2491 skge_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
),
2494 /* Enable store & forward on Tx queue's because
2495 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2497 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
2500 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
2503 /* Setup Bus Memory Interface */
2504 static void skge_qset(struct skge_port
*skge
, u16 q
,
2505 const struct skge_element
*e
)
2507 struct skge_hw
*hw
= skge
->hw
;
2508 u32 watermark
= 0x600;
2509 u64 base
= skge
->dma
+ (e
->desc
- skge
->mem
);
2511 /* optimization to reduce window on 32bit/33mhz */
2512 if ((skge_read16(hw
, B0_CTST
) & (CS_BUS_CLOCK
| CS_BUS_SLOT_SZ
)) == 0)
2515 skge_write32(hw
, Q_ADDR(q
, Q_CSR
), CSR_CLR_RESET
);
2516 skge_write32(hw
, Q_ADDR(q
, Q_F
), watermark
);
2517 skge_write32(hw
, Q_ADDR(q
, Q_DA_H
), (u32
)(base
>> 32));
2518 skge_write32(hw
, Q_ADDR(q
, Q_DA_L
), (u32
)base
);
2521 static int skge_up(struct net_device
*dev
)
2523 struct skge_port
*skge
= netdev_priv(dev
);
2524 struct skge_hw
*hw
= skge
->hw
;
2525 int port
= skge
->port
;
2526 u32 chunk
, ram_addr
;
2527 size_t rx_size
, tx_size
;
2530 if (!is_valid_ether_addr(dev
->dev_addr
))
2533 netif_info(skge
, ifup
, skge
->netdev
, "enabling interface\n");
2535 if (dev
->mtu
> RX_BUF_SIZE
)
2536 skge
->rx_buf_size
= dev
->mtu
+ ETH_HLEN
;
2538 skge
->rx_buf_size
= RX_BUF_SIZE
;
2541 rx_size
= skge
->rx_ring
.count
* sizeof(struct skge_rx_desc
);
2542 tx_size
= skge
->tx_ring
.count
* sizeof(struct skge_tx_desc
);
2543 skge
->mem_size
= tx_size
+ rx_size
;
2544 skge
->mem
= pci_alloc_consistent(hw
->pdev
, skge
->mem_size
, &skge
->dma
);
2548 BUG_ON(skge
->dma
& 7);
2550 if ((u64
)skge
->dma
>> 32 != ((u64
) skge
->dma
+ skge
->mem_size
) >> 32) {
2551 dev_err(&hw
->pdev
->dev
, "pci_alloc_consistent region crosses 4G boundary\n");
2556 memset(skge
->mem
, 0, skge
->mem_size
);
2558 err
= skge_ring_alloc(&skge
->rx_ring
, skge
->mem
, skge
->dma
);
2562 err
= skge_rx_fill(dev
);
2566 err
= skge_ring_alloc(&skge
->tx_ring
, skge
->mem
+ rx_size
,
2567 skge
->dma
+ rx_size
);
2571 /* Initialize MAC */
2572 spin_lock_bh(&hw
->phy_lock
);
2574 genesis_mac_init(hw
, port
);
2576 yukon_mac_init(hw
, port
);
2577 spin_unlock_bh(&hw
->phy_lock
);
2579 /* Configure RAMbuffers - equally between ports and tx/rx */
2580 chunk
= (hw
->ram_size
- hw
->ram_offset
) / (hw
->ports
* 2);
2581 ram_addr
= hw
->ram_offset
+ 2 * chunk
* port
;
2583 skge_ramset(hw
, rxqaddr
[port
], ram_addr
, chunk
);
2584 skge_qset(skge
, rxqaddr
[port
], skge
->rx_ring
.to_clean
);
2586 BUG_ON(skge
->tx_ring
.to_use
!= skge
->tx_ring
.to_clean
);
2587 skge_ramset(hw
, txqaddr
[port
], ram_addr
+chunk
, chunk
);
2588 skge_qset(skge
, txqaddr
[port
], skge
->tx_ring
.to_use
);
2590 /* Start receiver BMU */
2592 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2593 skge_led(skge
, LED_MODE_ON
);
2595 spin_lock_irq(&hw
->hw_lock
);
2596 hw
->intr_mask
|= portmask
[port
];
2597 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2598 spin_unlock_irq(&hw
->hw_lock
);
2600 napi_enable(&skge
->napi
);
2604 skge_rx_clean(skge
);
2605 kfree(skge
->rx_ring
.start
);
2607 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2614 static void skge_rx_stop(struct skge_hw
*hw
, int port
)
2616 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_STOP
);
2617 skge_write32(hw
, RB_ADDR(port
? Q_R2
: Q_R1
, RB_CTRL
),
2618 RB_RST_SET
|RB_DIS_OP_MD
);
2619 skge_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2622 static int skge_down(struct net_device
*dev
)
2624 struct skge_port
*skge
= netdev_priv(dev
);
2625 struct skge_hw
*hw
= skge
->hw
;
2626 int port
= skge
->port
;
2628 if (skge
->mem
== NULL
)
2631 netif_info(skge
, ifdown
, skge
->netdev
, "disabling interface\n");
2633 netif_tx_disable(dev
);
2635 if (is_genesis(hw
) && hw
->phy_type
== SK_PHY_XMAC
)
2636 del_timer_sync(&skge
->link_timer
);
2638 napi_disable(&skge
->napi
);
2639 netif_carrier_off(dev
);
2641 spin_lock_irq(&hw
->hw_lock
);
2642 hw
->intr_mask
&= ~portmask
[port
];
2643 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2644 spin_unlock_irq(&hw
->hw_lock
);
2646 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
2652 /* Stop transmitter */
2653 skge_write8(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_STOP
);
2654 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2655 RB_RST_SET
|RB_DIS_OP_MD
);
2658 /* Disable Force Sync bit and Enable Alloc bit */
2659 skge_write8(hw
, SK_REG(port
, TXA_CTRL
),
2660 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2662 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2663 skge_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2664 skge_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2666 /* Reset PCI FIFO */
2667 skge_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2668 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2670 /* Reset the RAM Buffer async Tx queue */
2671 skge_write8(hw
, RB_ADDR(port
== 0 ? Q_XA1
: Q_XA2
, RB_CTRL
), RB_RST_SET
);
2673 skge_rx_stop(hw
, port
);
2675 if (is_genesis(hw
)) {
2676 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_SET
);
2677 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_SET
);
2679 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2680 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2683 skge_led(skge
, LED_MODE_OFF
);
2685 netif_tx_lock_bh(dev
);
2687 netif_tx_unlock_bh(dev
);
2689 skge_rx_clean(skge
);
2691 kfree(skge
->rx_ring
.start
);
2692 kfree(skge
->tx_ring
.start
);
2693 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2698 static inline int skge_avail(const struct skge_ring
*ring
)
2701 return ((ring
->to_clean
> ring
->to_use
) ? 0 : ring
->count
)
2702 + (ring
->to_clean
- ring
->to_use
) - 1;
2705 static netdev_tx_t
skge_xmit_frame(struct sk_buff
*skb
,
2706 struct net_device
*dev
)
2708 struct skge_port
*skge
= netdev_priv(dev
);
2709 struct skge_hw
*hw
= skge
->hw
;
2710 struct skge_element
*e
;
2711 struct skge_tx_desc
*td
;
2716 if (skb_padto(skb
, ETH_ZLEN
))
2717 return NETDEV_TX_OK
;
2719 if (unlikely(skge_avail(&skge
->tx_ring
) < skb_shinfo(skb
)->nr_frags
+ 1))
2720 return NETDEV_TX_BUSY
;
2722 e
= skge
->tx_ring
.to_use
;
2724 BUG_ON(td
->control
& BMU_OWN
);
2726 len
= skb_headlen(skb
);
2727 map
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2728 dma_unmap_addr_set(e
, mapaddr
, map
);
2729 dma_unmap_len_set(e
, maplen
, len
);
2732 td
->dma_hi
= map
>> 32;
2734 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2735 const int offset
= skb_checksum_start_offset(skb
);
2737 /* This seems backwards, but it is what the sk98lin
2738 * does. Looks like hardware is wrong?
2740 if (ipip_hdr(skb
)->protocol
== IPPROTO_UDP
&&
2741 hw
->chip_rev
== 0 && hw
->chip_id
== CHIP_ID_YUKON
)
2742 control
= BMU_TCP_CHECK
;
2744 control
= BMU_UDP_CHECK
;
2747 td
->csum_start
= offset
;
2748 td
->csum_write
= offset
+ skb
->csum_offset
;
2750 control
= BMU_CHECK
;
2752 if (!skb_shinfo(skb
)->nr_frags
) /* single buffer i.e. no fragments */
2753 control
|= BMU_EOF
| BMU_IRQ_EOF
;
2755 struct skge_tx_desc
*tf
= td
;
2757 control
|= BMU_STFWD
;
2758 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2759 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2761 map
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
2762 frag
->size
, PCI_DMA_TODEVICE
);
2767 BUG_ON(tf
->control
& BMU_OWN
);
2770 tf
->dma_hi
= (u64
) map
>> 32;
2771 dma_unmap_addr_set(e
, mapaddr
, map
);
2772 dma_unmap_len_set(e
, maplen
, frag
->size
);
2774 tf
->control
= BMU_OWN
| BMU_SW
| control
| frag
->size
;
2776 tf
->control
|= BMU_EOF
| BMU_IRQ_EOF
;
2778 /* Make sure all the descriptors written */
2780 td
->control
= BMU_OWN
| BMU_SW
| BMU_STF
| control
| len
;
2783 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2785 netif_printk(skge
, tx_queued
, KERN_DEBUG
, skge
->netdev
,
2786 "tx queued, slot %td, len %d\n",
2787 e
- skge
->tx_ring
.start
, skb
->len
);
2789 skge
->tx_ring
.to_use
= e
->next
;
2792 if (skge_avail(&skge
->tx_ring
) <= TX_LOW_WATER
) {
2793 netdev_dbg(dev
, "transmit queue full\n");
2794 netif_stop_queue(dev
);
2797 return NETDEV_TX_OK
;
2801 /* Free resources associated with this reing element */
2802 static void skge_tx_free(struct skge_port
*skge
, struct skge_element
*e
,
2805 struct pci_dev
*pdev
= skge
->hw
->pdev
;
2807 /* skb header vs. fragment */
2808 if (control
& BMU_STF
)
2809 pci_unmap_single(pdev
, dma_unmap_addr(e
, mapaddr
),
2810 dma_unmap_len(e
, maplen
),
2813 pci_unmap_page(pdev
, dma_unmap_addr(e
, mapaddr
),
2814 dma_unmap_len(e
, maplen
),
2817 if (control
& BMU_EOF
) {
2818 netif_printk(skge
, tx_done
, KERN_DEBUG
, skge
->netdev
,
2819 "tx done slot %td\n", e
- skge
->tx_ring
.start
);
2821 dev_kfree_skb(e
->skb
);
2825 /* Free all buffers in transmit ring */
2826 static void skge_tx_clean(struct net_device
*dev
)
2828 struct skge_port
*skge
= netdev_priv(dev
);
2829 struct skge_element
*e
;
2831 for (e
= skge
->tx_ring
.to_clean
; e
!= skge
->tx_ring
.to_use
; e
= e
->next
) {
2832 struct skge_tx_desc
*td
= e
->desc
;
2833 skge_tx_free(skge
, e
, td
->control
);
2837 skge
->tx_ring
.to_clean
= e
;
2840 static void skge_tx_timeout(struct net_device
*dev
)
2842 struct skge_port
*skge
= netdev_priv(dev
);
2844 netif_printk(skge
, timer
, KERN_DEBUG
, skge
->netdev
, "tx timeout\n");
2846 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_STOP
);
2848 netif_wake_queue(dev
);
2851 static int skge_change_mtu(struct net_device
*dev
, int new_mtu
)
2855 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2858 if (!netif_running(dev
)) {
2874 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2876 static void genesis_add_filter(u8 filter
[8], const u8
*addr
)
2880 crc
= ether_crc_le(ETH_ALEN
, addr
);
2882 filter
[bit
/8] |= 1 << (bit
%8);
2885 static void genesis_set_multicast(struct net_device
*dev
)
2887 struct skge_port
*skge
= netdev_priv(dev
);
2888 struct skge_hw
*hw
= skge
->hw
;
2889 int port
= skge
->port
;
2890 struct netdev_hw_addr
*ha
;
2894 mode
= xm_read32(hw
, port
, XM_MODE
);
2895 mode
|= XM_MD_ENA_HASH
;
2896 if (dev
->flags
& IFF_PROMISC
)
2897 mode
|= XM_MD_ENA_PROM
;
2899 mode
&= ~XM_MD_ENA_PROM
;
2901 if (dev
->flags
& IFF_ALLMULTI
)
2902 memset(filter
, 0xff, sizeof(filter
));
2904 memset(filter
, 0, sizeof(filter
));
2906 if (skge
->flow_status
== FLOW_STAT_REM_SEND
||
2907 skge
->flow_status
== FLOW_STAT_SYMMETRIC
)
2908 genesis_add_filter(filter
, pause_mc_addr
);
2910 netdev_for_each_mc_addr(ha
, dev
)
2911 genesis_add_filter(filter
, ha
->addr
);
2914 xm_write32(hw
, port
, XM_MODE
, mode
);
2915 xm_outhash(hw
, port
, XM_HSM
, filter
);
2918 static void yukon_add_filter(u8 filter
[8], const u8
*addr
)
2920 u32 bit
= ether_crc(ETH_ALEN
, addr
) & 0x3f;
2921 filter
[bit
/8] |= 1 << (bit
%8);
2924 static void yukon_set_multicast(struct net_device
*dev
)
2926 struct skge_port
*skge
= netdev_priv(dev
);
2927 struct skge_hw
*hw
= skge
->hw
;
2928 int port
= skge
->port
;
2929 struct netdev_hw_addr
*ha
;
2930 int rx_pause
= (skge
->flow_status
== FLOW_STAT_REM_SEND
||
2931 skge
->flow_status
== FLOW_STAT_SYMMETRIC
);
2935 memset(filter
, 0, sizeof(filter
));
2937 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2938 reg
|= GM_RXCR_UCF_ENA
;
2940 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2941 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2942 else if (dev
->flags
& IFF_ALLMULTI
) /* all multicast */
2943 memset(filter
, 0xff, sizeof(filter
));
2944 else if (netdev_mc_empty(dev
) && !rx_pause
)/* no multicast */
2945 reg
&= ~GM_RXCR_MCF_ENA
;
2947 reg
|= GM_RXCR_MCF_ENA
;
2950 yukon_add_filter(filter
, pause_mc_addr
);
2952 netdev_for_each_mc_addr(ha
, dev
)
2953 yukon_add_filter(filter
, ha
->addr
);
2957 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2958 (u16
)filter
[0] | ((u16
)filter
[1] << 8));
2959 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2960 (u16
)filter
[2] | ((u16
)filter
[3] << 8));
2961 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2962 (u16
)filter
[4] | ((u16
)filter
[5] << 8));
2963 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2964 (u16
)filter
[6] | ((u16
)filter
[7] << 8));
2966 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2969 static inline u16
phy_length(const struct skge_hw
*hw
, u32 status
)
2972 return status
>> XMR_FS_LEN_SHIFT
;
2974 return status
>> GMR_FS_LEN_SHIFT
;
2977 static inline int bad_phy_status(const struct skge_hw
*hw
, u32 status
)
2980 return (status
& (XMR_FS_ERR
| XMR_FS_2L_VLAN
)) != 0;
2982 return (status
& GMR_FS_ANY_ERR
) ||
2983 (status
& GMR_FS_RX_OK
) == 0;
2986 static void skge_set_multicast(struct net_device
*dev
)
2988 struct skge_port
*skge
= netdev_priv(dev
);
2990 if (is_genesis(skge
->hw
))
2991 genesis_set_multicast(dev
);
2993 yukon_set_multicast(dev
);
2998 /* Get receive buffer from descriptor.
2999 * Handles copy of small buffers and reallocation failures
3001 static struct sk_buff
*skge_rx_get(struct net_device
*dev
,
3002 struct skge_element
*e
,
3003 u32 control
, u32 status
, u16 csum
)
3005 struct skge_port
*skge
= netdev_priv(dev
);
3006 struct sk_buff
*skb
;
3007 u16 len
= control
& BMU_BBC
;
3009 netif_printk(skge
, rx_status
, KERN_DEBUG
, skge
->netdev
,
3010 "rx slot %td status 0x%x len %d\n",
3011 e
- skge
->rx_ring
.start
, status
, len
);
3013 if (len
> skge
->rx_buf_size
)
3016 if ((control
& (BMU_EOF
|BMU_STF
)) != (BMU_STF
|BMU_EOF
))
3019 if (bad_phy_status(skge
->hw
, status
))
3022 if (phy_length(skge
->hw
, status
) != len
)
3025 if (len
< RX_COPY_THRESHOLD
) {
3026 skb
= netdev_alloc_skb_ip_align(dev
, len
);
3030 pci_dma_sync_single_for_cpu(skge
->hw
->pdev
,
3031 dma_unmap_addr(e
, mapaddr
),
3032 len
, PCI_DMA_FROMDEVICE
);
3033 skb_copy_from_linear_data(e
->skb
, skb
->data
, len
);
3034 pci_dma_sync_single_for_device(skge
->hw
->pdev
,
3035 dma_unmap_addr(e
, mapaddr
),
3036 len
, PCI_DMA_FROMDEVICE
);
3037 skge_rx_reuse(e
, skge
->rx_buf_size
);
3039 struct sk_buff
*nskb
;
3041 nskb
= netdev_alloc_skb_ip_align(dev
, skge
->rx_buf_size
);
3045 pci_unmap_single(skge
->hw
->pdev
,
3046 dma_unmap_addr(e
, mapaddr
),
3047 dma_unmap_len(e
, maplen
),
3048 PCI_DMA_FROMDEVICE
);
3050 prefetch(skb
->data
);
3051 skge_rx_setup(skge
, e
, nskb
, skge
->rx_buf_size
);
3056 if (dev
->features
& NETIF_F_RXCSUM
) {
3058 skb
->ip_summed
= CHECKSUM_COMPLETE
;
3061 skb
->protocol
= eth_type_trans(skb
, dev
);
3066 netif_printk(skge
, rx_err
, KERN_DEBUG
, skge
->netdev
,
3067 "rx err, slot %td control 0x%x status 0x%x\n",
3068 e
- skge
->rx_ring
.start
, control
, status
);
3070 if (is_genesis(skge
->hw
)) {
3071 if (status
& (XMR_FS_RUNT
|XMR_FS_LNG_ERR
))
3072 dev
->stats
.rx_length_errors
++;
3073 if (status
& XMR_FS_FRA_ERR
)
3074 dev
->stats
.rx_frame_errors
++;
3075 if (status
& XMR_FS_FCS_ERR
)
3076 dev
->stats
.rx_crc_errors
++;
3078 if (status
& (GMR_FS_LONG_ERR
|GMR_FS_UN_SIZE
))
3079 dev
->stats
.rx_length_errors
++;
3080 if (status
& GMR_FS_FRAGMENT
)
3081 dev
->stats
.rx_frame_errors
++;
3082 if (status
& GMR_FS_CRC_ERR
)
3083 dev
->stats
.rx_crc_errors
++;
3087 skge_rx_reuse(e
, skge
->rx_buf_size
);
3091 /* Free all buffers in Tx ring which are no longer owned by device */
3092 static void skge_tx_done(struct net_device
*dev
)
3094 struct skge_port
*skge
= netdev_priv(dev
);
3095 struct skge_ring
*ring
= &skge
->tx_ring
;
3096 struct skge_element
*e
;
3098 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
3100 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
3101 u32 control
= ((const struct skge_tx_desc
*) e
->desc
)->control
;
3103 if (control
& BMU_OWN
)
3106 skge_tx_free(skge
, e
, control
);
3108 skge
->tx_ring
.to_clean
= e
;
3110 /* Can run lockless until we need to synchronize to restart queue. */
3113 if (unlikely(netif_queue_stopped(dev
) &&
3114 skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)) {
3116 if (unlikely(netif_queue_stopped(dev
) &&
3117 skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)) {
3118 netif_wake_queue(dev
);
3121 netif_tx_unlock(dev
);
3125 static int skge_poll(struct napi_struct
*napi
, int to_do
)
3127 struct skge_port
*skge
= container_of(napi
, struct skge_port
, napi
);
3128 struct net_device
*dev
= skge
->netdev
;
3129 struct skge_hw
*hw
= skge
->hw
;
3130 struct skge_ring
*ring
= &skge
->rx_ring
;
3131 struct skge_element
*e
;
3136 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
3138 for (e
= ring
->to_clean
; prefetch(e
->next
), work_done
< to_do
; e
= e
->next
) {
3139 struct skge_rx_desc
*rd
= e
->desc
;
3140 struct sk_buff
*skb
;
3144 control
= rd
->control
;
3145 if (control
& BMU_OWN
)
3148 skb
= skge_rx_get(dev
, e
, control
, rd
->status
, rd
->csum2
);
3150 napi_gro_receive(napi
, skb
);
3156 /* restart receiver */
3158 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_START
);
3160 if (work_done
< to_do
) {
3161 unsigned long flags
;
3163 napi_gro_flush(napi
);
3164 spin_lock_irqsave(&hw
->hw_lock
, flags
);
3165 __napi_complete(napi
);
3166 hw
->intr_mask
|= napimask
[skge
->port
];
3167 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3168 skge_read32(hw
, B0_IMSK
);
3169 spin_unlock_irqrestore(&hw
->hw_lock
, flags
);
3175 /* Parity errors seem to happen when Genesis is connected to a switch
3176 * with no other ports present. Heartbeat error??
3178 static void skge_mac_parity(struct skge_hw
*hw
, int port
)
3180 struct net_device
*dev
= hw
->dev
[port
];
3182 ++dev
->stats
.tx_heartbeat_errors
;
3185 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
3188 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3189 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
3190 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
3191 ? GMF_CLI_TX_FC
: GMF_CLI_TX_PE
);
3194 static void skge_mac_intr(struct skge_hw
*hw
, int port
)
3197 genesis_mac_intr(hw
, port
);
3199 yukon_mac_intr(hw
, port
);
3202 /* Handle device specific framing and timeout interrupts */
3203 static void skge_error_irq(struct skge_hw
*hw
)
3205 struct pci_dev
*pdev
= hw
->pdev
;
3206 u32 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3208 if (is_genesis(hw
)) {
3209 /* clear xmac errors */
3210 if (hwstatus
& (IS_NO_STAT_M1
|IS_NO_TIST_M1
))
3211 skge_write16(hw
, RX_MFF_CTRL1
, MFF_CLR_INSTAT
);
3212 if (hwstatus
& (IS_NO_STAT_M2
|IS_NO_TIST_M2
))
3213 skge_write16(hw
, RX_MFF_CTRL2
, MFF_CLR_INSTAT
);
3215 /* Timestamp (unused) overflow */
3216 if (hwstatus
& IS_IRQ_TIST_OV
)
3217 skge_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3220 if (hwstatus
& IS_RAM_RD_PAR
) {
3221 dev_err(&pdev
->dev
, "Ram read data parity error\n");
3222 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_RD_PERR
);
3225 if (hwstatus
& IS_RAM_WR_PAR
) {
3226 dev_err(&pdev
->dev
, "Ram write data parity error\n");
3227 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_WR_PERR
);
3230 if (hwstatus
& IS_M1_PAR_ERR
)
3231 skge_mac_parity(hw
, 0);
3233 if (hwstatus
& IS_M2_PAR_ERR
)
3234 skge_mac_parity(hw
, 1);
3236 if (hwstatus
& IS_R1_PAR_ERR
) {
3237 dev_err(&pdev
->dev
, "%s: receive queue parity error\n",
3239 skge_write32(hw
, B0_R1_CSR
, CSR_IRQ_CL_P
);
3242 if (hwstatus
& IS_R2_PAR_ERR
) {
3243 dev_err(&pdev
->dev
, "%s: receive queue parity error\n",
3245 skge_write32(hw
, B0_R2_CSR
, CSR_IRQ_CL_P
);
3248 if (hwstatus
& (IS_IRQ_MST_ERR
|IS_IRQ_STAT
)) {
3249 u16 pci_status
, pci_cmd
;
3251 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3252 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3254 dev_err(&pdev
->dev
, "PCI error cmd=%#x status=%#x\n",
3255 pci_cmd
, pci_status
);
3257 /* Write the error bits back to clear them. */
3258 pci_status
&= PCI_STATUS_ERROR_BITS
;
3259 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3260 pci_write_config_word(pdev
, PCI_COMMAND
,
3261 pci_cmd
| PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
3262 pci_write_config_word(pdev
, PCI_STATUS
, pci_status
);
3263 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3265 /* if error still set then just ignore it */
3266 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3267 if (hwstatus
& IS_IRQ_STAT
) {
3268 dev_warn(&hw
->pdev
->dev
, "unable to clear error (so ignoring them)\n");
3269 hw
->intr_mask
&= ~IS_HW_ERR
;
3275 * Interrupt from PHY are handled in tasklet (softirq)
3276 * because accessing phy registers requires spin wait which might
3277 * cause excess interrupt latency.
3279 static void skge_extirq(unsigned long arg
)
3281 struct skge_hw
*hw
= (struct skge_hw
*) arg
;
3284 for (port
= 0; port
< hw
->ports
; port
++) {
3285 struct net_device
*dev
= hw
->dev
[port
];
3287 if (netif_running(dev
)) {
3288 struct skge_port
*skge
= netdev_priv(dev
);
3290 spin_lock(&hw
->phy_lock
);
3291 if (!is_genesis(hw
))
3292 yukon_phy_intr(skge
);
3293 else if (hw
->phy_type
== SK_PHY_BCOM
)
3294 bcom_phy_intr(skge
);
3295 spin_unlock(&hw
->phy_lock
);
3299 spin_lock_irq(&hw
->hw_lock
);
3300 hw
->intr_mask
|= IS_EXT_REG
;
3301 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3302 skge_read32(hw
, B0_IMSK
);
3303 spin_unlock_irq(&hw
->hw_lock
);
3306 static irqreturn_t
skge_intr(int irq
, void *dev_id
)
3308 struct skge_hw
*hw
= dev_id
;
3312 spin_lock(&hw
->hw_lock
);
3313 /* Reading this register masks IRQ */
3314 status
= skge_read32(hw
, B0_SP_ISRC
);
3315 if (status
== 0 || status
== ~0)
3319 status
&= hw
->intr_mask
;
3320 if (status
& IS_EXT_REG
) {
3321 hw
->intr_mask
&= ~IS_EXT_REG
;
3322 tasklet_schedule(&hw
->phy_task
);
3325 if (status
& (IS_XA1_F
|IS_R1_F
)) {
3326 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3327 hw
->intr_mask
&= ~(IS_XA1_F
|IS_R1_F
);
3328 napi_schedule(&skge
->napi
);
3331 if (status
& IS_PA_TO_TX1
)
3332 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX1
);
3334 if (status
& IS_PA_TO_RX1
) {
3335 ++hw
->dev
[0]->stats
.rx_over_errors
;
3336 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX1
);
3340 if (status
& IS_MAC1
)
3341 skge_mac_intr(hw
, 0);
3344 struct skge_port
*skge
= netdev_priv(hw
->dev
[1]);
3346 if (status
& (IS_XA2_F
|IS_R2_F
)) {
3347 hw
->intr_mask
&= ~(IS_XA2_F
|IS_R2_F
);
3348 napi_schedule(&skge
->napi
);
3351 if (status
& IS_PA_TO_RX2
) {
3352 ++hw
->dev
[1]->stats
.rx_over_errors
;
3353 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX2
);
3356 if (status
& IS_PA_TO_TX2
)
3357 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX2
);
3359 if (status
& IS_MAC2
)
3360 skge_mac_intr(hw
, 1);
3363 if (status
& IS_HW_ERR
)
3366 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3367 skge_read32(hw
, B0_IMSK
);
3369 spin_unlock(&hw
->hw_lock
);
3371 return IRQ_RETVAL(handled
);
3374 #ifdef CONFIG_NET_POLL_CONTROLLER
3375 static void skge_netpoll(struct net_device
*dev
)
3377 struct skge_port
*skge
= netdev_priv(dev
);
3379 disable_irq(dev
->irq
);
3380 skge_intr(dev
->irq
, skge
->hw
);
3381 enable_irq(dev
->irq
);
3385 static int skge_set_mac_address(struct net_device
*dev
, void *p
)
3387 struct skge_port
*skge
= netdev_priv(dev
);
3388 struct skge_hw
*hw
= skge
->hw
;
3389 unsigned port
= skge
->port
;
3390 const struct sockaddr
*addr
= p
;
3393 if (!is_valid_ether_addr(addr
->sa_data
))
3394 return -EADDRNOTAVAIL
;
3396 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3398 if (!netif_running(dev
)) {
3399 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3400 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3403 spin_lock_bh(&hw
->phy_lock
);
3404 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
3405 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
& ~GM_GPCR_RX_ENA
);
3407 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3408 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3411 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
3413 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3414 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3417 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
3418 spin_unlock_bh(&hw
->phy_lock
);
3424 static const struct {
3428 { CHIP_ID_GENESIS
, "Genesis" },
3429 { CHIP_ID_YUKON
, "Yukon" },
3430 { CHIP_ID_YUKON_LITE
, "Yukon-Lite"},
3431 { CHIP_ID_YUKON_LP
, "Yukon-LP"},
3434 static const char *skge_board_name(const struct skge_hw
*hw
)
3437 static char buf
[16];
3439 for (i
= 0; i
< ARRAY_SIZE(skge_chips
); i
++)
3440 if (skge_chips
[i
].id
== hw
->chip_id
)
3441 return skge_chips
[i
].name
;
3443 snprintf(buf
, sizeof buf
, "chipid 0x%x", hw
->chip_id
);
3449 * Setup the board data structure, but don't bring up
3452 static int skge_reset(struct skge_hw
*hw
)
3455 u16 ctst
, pci_status
;
3456 u8 t8
, mac_cfg
, pmd_type
;
3459 ctst
= skge_read16(hw
, B0_CTST
);
3462 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3463 skge_write8(hw
, B0_CTST
, CS_RST_CLR
);
3465 /* clear PCI errors, if any */
3466 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3467 skge_write8(hw
, B2_TST_CTRL2
, 0);
3469 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3470 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
3471 pci_status
| PCI_STATUS_ERROR_BITS
);
3472 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3473 skge_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3475 /* restore CLK_RUN bits (for Yukon-Lite) */
3476 skge_write16(hw
, B0_CTST
,
3477 ctst
& (CS_CLK_RUN_HOT
|CS_CLK_RUN_RST
|CS_CLK_RUN_ENA
));
3479 hw
->chip_id
= skge_read8(hw
, B2_CHIP_ID
);
3480 hw
->phy_type
= skge_read8(hw
, B2_E_1
) & 0xf;
3481 pmd_type
= skge_read8(hw
, B2_PMD_TYP
);
3482 hw
->copper
= (pmd_type
== 'T' || pmd_type
== '1');
3484 switch (hw
->chip_id
) {
3485 case CHIP_ID_GENESIS
:
3486 #ifdef CONFIG_SKGE_GENESIS
3487 switch (hw
->phy_type
) {
3489 hw
->phy_addr
= PHY_ADDR_XMAC
;
3492 hw
->phy_addr
= PHY_ADDR_BCOM
;
3495 dev_err(&hw
->pdev
->dev
, "unsupported phy type 0x%x\n",
3501 dev_err(&hw
->pdev
->dev
, "Genesis chip detected but not configured\n");
3506 case CHIP_ID_YUKON_LITE
:
3507 case CHIP_ID_YUKON_LP
:
3508 if (hw
->phy_type
< SK_PHY_MARV_COPPER
&& pmd_type
!= 'S')
3511 hw
->phy_addr
= PHY_ADDR_MARV
;
3515 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3520 mac_cfg
= skge_read8(hw
, B2_MAC_CFG
);
3521 hw
->ports
= (mac_cfg
& CFG_SNG_MAC
) ? 1 : 2;
3522 hw
->chip_rev
= (mac_cfg
& CFG_CHIP_R_MSK
) >> 4;
3524 /* read the adapters RAM size */
3525 t8
= skge_read8(hw
, B2_E_0
);
3526 if (is_genesis(hw
)) {
3528 /* special case: 4 x 64k x 36, offset = 0x80000 */
3529 hw
->ram_size
= 0x100000;
3530 hw
->ram_offset
= 0x80000;
3532 hw
->ram_size
= t8
* 512;
3534 hw
->ram_size
= 0x20000;
3536 hw
->ram_size
= t8
* 4096;
3538 hw
->intr_mask
= IS_HW_ERR
;
3540 /* Use PHY IRQ for all but fiber based Genesis board */
3541 if (!(is_genesis(hw
) && hw
->phy_type
== SK_PHY_XMAC
))
3542 hw
->intr_mask
|= IS_EXT_REG
;
3547 /* switch power to VCC (WA for VAUX problem) */
3548 skge_write8(hw
, B0_POWER_CTRL
,
3549 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
3551 /* avoid boards with stuck Hardware error bits */
3552 if ((skge_read32(hw
, B0_ISRC
) & IS_HW_ERR
) &&
3553 (skge_read32(hw
, B0_HWE_ISRC
) & IS_IRQ_SENSOR
)) {
3554 dev_warn(&hw
->pdev
->dev
, "stuck hardware sensor bit\n");
3555 hw
->intr_mask
&= ~IS_HW_ERR
;
3558 /* Clear PHY COMA */
3559 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3560 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®
);
3561 reg
&= ~PCI_PHY_COMA
;
3562 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg
);
3563 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3566 for (i
= 0; i
< hw
->ports
; i
++) {
3567 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3568 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3572 /* turn off hardware timer (unused) */
3573 skge_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3574 skge_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3575 skge_write8(hw
, B0_LED
, LED_STAT_ON
);
3577 /* enable the Tx Arbiters */
3578 for (i
= 0; i
< hw
->ports
; i
++)
3579 skge_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3581 /* Initialize ram interface */
3582 skge_write16(hw
, B3_RI_CTRL
, RI_RST_CLR
);
3584 skge_write8(hw
, B3_RI_WTO_R1
, SK_RI_TO_53
);
3585 skge_write8(hw
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
3586 skge_write8(hw
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
3587 skge_write8(hw
, B3_RI_RTO_R1
, SK_RI_TO_53
);
3588 skge_write8(hw
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
3589 skge_write8(hw
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
3590 skge_write8(hw
, B3_RI_WTO_R2
, SK_RI_TO_53
);
3591 skge_write8(hw
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
3592 skge_write8(hw
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
3593 skge_write8(hw
, B3_RI_RTO_R2
, SK_RI_TO_53
);
3594 skge_write8(hw
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
3595 skge_write8(hw
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
3597 skge_write32(hw
, B0_HWE_IMSK
, IS_ERR_MSK
);
3599 /* Set interrupt moderation for Transmit only
3600 * Receive interrupts avoided by NAPI
3602 skge_write32(hw
, B2_IRQM_MSK
, IS_XA1_F
|IS_XA2_F
);
3603 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, 100));
3604 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
3606 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3608 for (i
= 0; i
< hw
->ports
; i
++) {
3610 genesis_reset(hw
, i
);
3619 #ifdef CONFIG_SKGE_DEBUG
3621 static struct dentry
*skge_debug
;
3623 static int skge_debug_show(struct seq_file
*seq
, void *v
)
3625 struct net_device
*dev
= seq
->private;
3626 const struct skge_port
*skge
= netdev_priv(dev
);
3627 const struct skge_hw
*hw
= skge
->hw
;
3628 const struct skge_element
*e
;
3630 if (!netif_running(dev
))
3633 seq_printf(seq
, "IRQ src=%x mask=%x\n", skge_read32(hw
, B0_ISRC
),
3634 skge_read32(hw
, B0_IMSK
));
3636 seq_printf(seq
, "Tx Ring: (%d)\n", skge_avail(&skge
->tx_ring
));
3637 for (e
= skge
->tx_ring
.to_clean
; e
!= skge
->tx_ring
.to_use
; e
= e
->next
) {
3638 const struct skge_tx_desc
*t
= e
->desc
;
3639 seq_printf(seq
, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3640 t
->control
, t
->dma_hi
, t
->dma_lo
, t
->status
,
3641 t
->csum_offs
, t
->csum_write
, t
->csum_start
);
3644 seq_printf(seq
, "\nRx Ring:\n");
3645 for (e
= skge
->rx_ring
.to_clean
; ; e
= e
->next
) {
3646 const struct skge_rx_desc
*r
= e
->desc
;
3648 if (r
->control
& BMU_OWN
)
3651 seq_printf(seq
, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3652 r
->control
, r
->dma_hi
, r
->dma_lo
, r
->status
,
3653 r
->timestamp
, r
->csum1
, r
->csum1_start
);
3659 static int skge_debug_open(struct inode
*inode
, struct file
*file
)
3661 return single_open(file
, skge_debug_show
, inode
->i_private
);
3664 static const struct file_operations skge_debug_fops
= {
3665 .owner
= THIS_MODULE
,
3666 .open
= skge_debug_open
,
3668 .llseek
= seq_lseek
,
3669 .release
= single_release
,
3673 * Use network device events to create/remove/rename
3674 * debugfs file entries
3676 static int skge_device_event(struct notifier_block
*unused
,
3677 unsigned long event
, void *ptr
)
3679 struct net_device
*dev
= ptr
;
3680 struct skge_port
*skge
;
3683 if (dev
->netdev_ops
->ndo_open
!= &skge_up
|| !skge_debug
)
3686 skge
= netdev_priv(dev
);
3688 case NETDEV_CHANGENAME
:
3689 if (skge
->debugfs
) {
3690 d
= debugfs_rename(skge_debug
, skge
->debugfs
,
3691 skge_debug
, dev
->name
);
3695 netdev_info(dev
, "rename failed\n");
3696 debugfs_remove(skge
->debugfs
);
3701 case NETDEV_GOING_DOWN
:
3702 if (skge
->debugfs
) {
3703 debugfs_remove(skge
->debugfs
);
3704 skge
->debugfs
= NULL
;
3709 d
= debugfs_create_file(dev
->name
, S_IRUGO
,
3712 if (!d
|| IS_ERR(d
))
3713 netdev_info(dev
, "debugfs create failed\n");
3723 static struct notifier_block skge_notifier
= {
3724 .notifier_call
= skge_device_event
,
3728 static __init
void skge_debug_init(void)
3732 ent
= debugfs_create_dir("skge", NULL
);
3733 if (!ent
|| IS_ERR(ent
)) {
3734 pr_info("debugfs create directory failed\n");
3739 register_netdevice_notifier(&skge_notifier
);
3742 static __exit
void skge_debug_cleanup(void)
3745 unregister_netdevice_notifier(&skge_notifier
);
3746 debugfs_remove(skge_debug
);
3752 #define skge_debug_init()
3753 #define skge_debug_cleanup()
3756 static const struct net_device_ops skge_netdev_ops
= {
3757 .ndo_open
= skge_up
,
3758 .ndo_stop
= skge_down
,
3759 .ndo_start_xmit
= skge_xmit_frame
,
3760 .ndo_do_ioctl
= skge_ioctl
,
3761 .ndo_get_stats
= skge_get_stats
,
3762 .ndo_tx_timeout
= skge_tx_timeout
,
3763 .ndo_change_mtu
= skge_change_mtu
,
3764 .ndo_validate_addr
= eth_validate_addr
,
3765 .ndo_set_rx_mode
= skge_set_multicast
,
3766 .ndo_set_mac_address
= skge_set_mac_address
,
3767 #ifdef CONFIG_NET_POLL_CONTROLLER
3768 .ndo_poll_controller
= skge_netpoll
,
3773 /* Initialize network device */
3774 static struct net_device
*skge_devinit(struct skge_hw
*hw
, int port
,
3777 struct skge_port
*skge
;
3778 struct net_device
*dev
= alloc_etherdev(sizeof(*skge
));
3781 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
3785 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3786 dev
->netdev_ops
= &skge_netdev_ops
;
3787 dev
->ethtool_ops
= &skge_ethtool_ops
;
3788 dev
->watchdog_timeo
= TX_WATCHDOG
;
3789 dev
->irq
= hw
->pdev
->irq
;
3792 dev
->features
|= NETIF_F_HIGHDMA
;
3794 skge
= netdev_priv(dev
);
3795 netif_napi_add(dev
, &skge
->napi
, skge_poll
, NAPI_WEIGHT
);
3798 skge
->msg_enable
= netif_msg_init(debug
, default_msg
);
3800 skge
->tx_ring
.count
= DEFAULT_TX_RING_SIZE
;
3801 skge
->rx_ring
.count
= DEFAULT_RX_RING_SIZE
;
3803 /* Auto speed and flow control */
3804 skge
->autoneg
= AUTONEG_ENABLE
;
3805 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
3808 skge
->advertising
= skge_supported_modes(hw
);
3810 if (device_can_wakeup(&hw
->pdev
->dev
)) {
3811 skge
->wol
= wol_supported(hw
) & WAKE_MAGIC
;
3812 device_set_wakeup_enable(&hw
->pdev
->dev
, skge
->wol
);
3815 hw
->dev
[port
] = dev
;
3819 /* Only used for Genesis XMAC */
3821 setup_timer(&skge
->link_timer
, xm_link_timer
, (unsigned long) skge
);
3823 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_SG
|
3825 dev
->features
|= dev
->hw_features
;
3828 /* read the mac address */
3829 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
*8, ETH_ALEN
);
3830 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3835 static void __devinit
skge_show_addr(struct net_device
*dev
)
3837 const struct skge_port
*skge
= netdev_priv(dev
);
3839 netif_info(skge
, probe
, skge
->netdev
, "addr %pM\n", dev
->dev_addr
);
3842 static int only_32bit_dma
;
3844 static int __devinit
skge_probe(struct pci_dev
*pdev
,
3845 const struct pci_device_id
*ent
)
3847 struct net_device
*dev
, *dev1
;
3849 int err
, using_dac
= 0;
3851 err
= pci_enable_device(pdev
);
3853 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3857 err
= pci_request_regions(pdev
, DRV_NAME
);
3859 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3860 goto err_out_disable_pdev
;
3863 pci_set_master(pdev
);
3865 if (!only_32bit_dma
&& !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
3867 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
3868 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
3870 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
3874 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3875 goto err_out_free_regions
;
3879 /* byte swap descriptors in hardware */
3883 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3884 reg
|= PCI_REV_DESC
;
3885 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3890 /* space for skge@pci:0000:04:00.0 */
3891 hw
= kzalloc(sizeof(*hw
) + strlen(DRV_NAME
"@pci:")
3892 + strlen(pci_name(pdev
)) + 1, GFP_KERNEL
);
3894 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3895 goto err_out_free_regions
;
3897 sprintf(hw
->irq_name
, DRV_NAME
"@pci:%s", pci_name(pdev
));
3900 spin_lock_init(&hw
->hw_lock
);
3901 spin_lock_init(&hw
->phy_lock
);
3902 tasklet_init(&hw
->phy_task
, skge_extirq
, (unsigned long) hw
);
3904 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3906 dev_err(&pdev
->dev
, "cannot map device registers\n");
3907 goto err_out_free_hw
;
3910 err
= skge_reset(hw
);
3912 goto err_out_iounmap
;
3914 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3916 (unsigned long long)pci_resource_start(pdev
, 0), pdev
->irq
,
3917 skge_board_name(hw
), hw
->chip_rev
);
3919 dev
= skge_devinit(hw
, 0, using_dac
);
3921 goto err_out_led_off
;
3923 /* Some motherboards are broken and has zero in ROM. */
3924 if (!is_valid_ether_addr(dev
->dev_addr
))
3925 dev_warn(&pdev
->dev
, "bad (zero?) ethernet address in rom\n");
3927 err
= register_netdev(dev
);
3929 dev_err(&pdev
->dev
, "cannot register net device\n");
3930 goto err_out_free_netdev
;
3933 err
= request_irq(pdev
->irq
, skge_intr
, IRQF_SHARED
, hw
->irq_name
, hw
);
3935 dev_err(&pdev
->dev
, "%s: cannot assign irq %d\n",
3936 dev
->name
, pdev
->irq
);
3937 goto err_out_unregister
;
3939 skge_show_addr(dev
);
3941 if (hw
->ports
> 1) {
3942 dev1
= skge_devinit(hw
, 1, using_dac
);
3943 if (dev1
&& register_netdev(dev1
) == 0)
3944 skge_show_addr(dev1
);
3946 /* Failure to register second port need not be fatal */
3947 dev_warn(&pdev
->dev
, "register of second port failed\n");
3954 pci_set_drvdata(pdev
, hw
);
3959 unregister_netdev(dev
);
3960 err_out_free_netdev
:
3963 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3968 err_out_free_regions
:
3969 pci_release_regions(pdev
);
3970 err_out_disable_pdev
:
3971 pci_disable_device(pdev
);
3972 pci_set_drvdata(pdev
, NULL
);
3977 static void __devexit
skge_remove(struct pci_dev
*pdev
)
3979 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3980 struct net_device
*dev0
, *dev1
;
3987 unregister_netdev(dev1
);
3989 unregister_netdev(dev0
);
3991 tasklet_disable(&hw
->phy_task
);
3993 spin_lock_irq(&hw
->hw_lock
);
3995 skge_write32(hw
, B0_IMSK
, 0);
3996 skge_read32(hw
, B0_IMSK
);
3997 spin_unlock_irq(&hw
->hw_lock
);
3999 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
4000 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
4002 free_irq(pdev
->irq
, hw
);
4003 pci_release_regions(pdev
);
4004 pci_disable_device(pdev
);
4011 pci_set_drvdata(pdev
, NULL
);
4015 static int skge_suspend(struct device
*dev
)
4017 struct pci_dev
*pdev
= to_pci_dev(dev
);
4018 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
4024 for (i
= 0; i
< hw
->ports
; i
++) {
4025 struct net_device
*dev
= hw
->dev
[i
];
4026 struct skge_port
*skge
= netdev_priv(dev
);
4028 if (netif_running(dev
))
4032 skge_wol_init(skge
);
4035 skge_write32(hw
, B0_IMSK
, 0);
4040 static int skge_resume(struct device
*dev
)
4042 struct pci_dev
*pdev
= to_pci_dev(dev
);
4043 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
4049 err
= skge_reset(hw
);
4053 for (i
= 0; i
< hw
->ports
; i
++) {
4054 struct net_device
*dev
= hw
->dev
[i
];
4056 if (netif_running(dev
)) {
4060 netdev_err(dev
, "could not up: %d\n", err
);
4070 static SIMPLE_DEV_PM_OPS(skge_pm_ops
, skge_suspend
, skge_resume
);
4071 #define SKGE_PM_OPS (&skge_pm_ops)
4075 #define SKGE_PM_OPS NULL
4078 static void skge_shutdown(struct pci_dev
*pdev
)
4080 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
4086 for (i
= 0; i
< hw
->ports
; i
++) {
4087 struct net_device
*dev
= hw
->dev
[i
];
4088 struct skge_port
*skge
= netdev_priv(dev
);
4091 skge_wol_init(skge
);
4094 pci_wake_from_d3(pdev
, device_may_wakeup(&pdev
->dev
));
4095 pci_set_power_state(pdev
, PCI_D3hot
);
4098 static struct pci_driver skge_driver
= {
4100 .id_table
= skge_id_table
,
4101 .probe
= skge_probe
,
4102 .remove
= __devexit_p(skge_remove
),
4103 .shutdown
= skge_shutdown
,
4104 .driver
.pm
= SKGE_PM_OPS
,
4107 static struct dmi_system_id skge_32bit_dma_boards
[] = {
4109 .ident
= "Gigabyte nForce boards",
4111 DMI_MATCH(DMI_BOARD_VENDOR
, "Gigabyte Technology Co"),
4112 DMI_MATCH(DMI_BOARD_NAME
, "nForce"),
4118 static int __init
skge_init_module(void)
4120 if (dmi_check_system(skge_32bit_dma_boards
))
4123 return pci_register_driver(&skge_driver
);
4126 static void __exit
skge_cleanup_module(void)
4128 pci_unregister_driver(&skge_driver
);
4129 skge_debug_cleanup();
4132 module_init(skge_init_module
);
4133 module_exit(skge_cleanup_module
);