2 /* ns83820.c by Benjamin LaHaise with contributions.
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
6 * $Revision: 1.34.2.23 $
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
11 * Mmmm, chocolate vanilla mocha...
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
63 * - fix missed txok introduced during performance
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
86 * Cameo SOHO-GA2000T SOHO-GA2500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
92 * Special thanks to SMC for providing hardware to test this driver on.
94 * Reports of success or failure would be greatly appreciated.
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/interrupt.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/sched.h>
116 #include <linux/timer.h>
117 #include <linux/if_vlan.h>
118 #include <linux/rtnetlink.h>
119 #include <linux/jiffies.h>
120 #include <linux/slab.h>
123 #include <asm/uaccess.h>
124 #include <asm/system.h>
126 #define DRV_NAME "ns83820"
128 /* Global parameters. See module_param near the bottom. */
130 static int reset_phy
= 0;
131 static int lnksts
= 0; /* CFG_LNKSTS bit polarity */
133 /* Dprintk is used for more interesting debug events */
135 #define Dprintk dprintk
138 #define RX_BUF_SIZE 1500 /* 8192 */
139 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
140 #define NS83820_VLAN_ACCEL_SUPPORT
143 /* Must not exceed ~65000. */
144 #define NR_RX_DESC 64
145 #define NR_TX_DESC 128
148 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
150 #define MIN_TX_DESC_FREE 8
152 /* register defines */
155 #define CR_TXE 0x00000001
156 #define CR_TXD 0x00000002
157 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
158 * The Receive engine skips one descriptor and moves
159 * onto the next one!! */
160 #define CR_RXE 0x00000004
161 #define CR_RXD 0x00000008
162 #define CR_TXR 0x00000010
163 #define CR_RXR 0x00000020
164 #define CR_SWI 0x00000080
165 #define CR_RST 0x00000100
167 #define PTSCR_EEBIST_FAIL 0x00000001
168 #define PTSCR_EEBIST_EN 0x00000002
169 #define PTSCR_EELOAD_EN 0x00000004
170 #define PTSCR_RBIST_FAIL 0x000001b8
171 #define PTSCR_RBIST_DONE 0x00000200
172 #define PTSCR_RBIST_EN 0x00000400
173 #define PTSCR_RBIST_RST 0x00002000
175 #define MEAR_EEDI 0x00000001
176 #define MEAR_EEDO 0x00000002
177 #define MEAR_EECLK 0x00000004
178 #define MEAR_EESEL 0x00000008
179 #define MEAR_MDIO 0x00000010
180 #define MEAR_MDDIR 0x00000020
181 #define MEAR_MDC 0x00000040
183 #define ISR_TXDESC3 0x40000000
184 #define ISR_TXDESC2 0x20000000
185 #define ISR_TXDESC1 0x10000000
186 #define ISR_TXDESC0 0x08000000
187 #define ISR_RXDESC3 0x04000000
188 #define ISR_RXDESC2 0x02000000
189 #define ISR_RXDESC1 0x01000000
190 #define ISR_RXDESC0 0x00800000
191 #define ISR_TXRCMP 0x00400000
192 #define ISR_RXRCMP 0x00200000
193 #define ISR_DPERR 0x00100000
194 #define ISR_SSERR 0x00080000
195 #define ISR_RMABT 0x00040000
196 #define ISR_RTABT 0x00020000
197 #define ISR_RXSOVR 0x00010000
198 #define ISR_HIBINT 0x00008000
199 #define ISR_PHY 0x00004000
200 #define ISR_PME 0x00002000
201 #define ISR_SWI 0x00001000
202 #define ISR_MIB 0x00000800
203 #define ISR_TXURN 0x00000400
204 #define ISR_TXIDLE 0x00000200
205 #define ISR_TXERR 0x00000100
206 #define ISR_TXDESC 0x00000080
207 #define ISR_TXOK 0x00000040
208 #define ISR_RXORN 0x00000020
209 #define ISR_RXIDLE 0x00000010
210 #define ISR_RXEARLY 0x00000008
211 #define ISR_RXERR 0x00000004
212 #define ISR_RXDESC 0x00000002
213 #define ISR_RXOK 0x00000001
215 #define TXCFG_CSI 0x80000000
216 #define TXCFG_HBI 0x40000000
217 #define TXCFG_MLB 0x20000000
218 #define TXCFG_ATP 0x10000000
219 #define TXCFG_ECRETRY 0x00800000
220 #define TXCFG_BRST_DIS 0x00080000
221 #define TXCFG_MXDMA1024 0x00000000
222 #define TXCFG_MXDMA512 0x00700000
223 #define TXCFG_MXDMA256 0x00600000
224 #define TXCFG_MXDMA128 0x00500000
225 #define TXCFG_MXDMA64 0x00400000
226 #define TXCFG_MXDMA32 0x00300000
227 #define TXCFG_MXDMA16 0x00200000
228 #define TXCFG_MXDMA8 0x00100000
230 #define CFG_LNKSTS 0x80000000
231 #define CFG_SPDSTS 0x60000000
232 #define CFG_SPDSTS1 0x40000000
233 #define CFG_SPDSTS0 0x20000000
234 #define CFG_DUPSTS 0x10000000
235 #define CFG_TBI_EN 0x01000000
236 #define CFG_MODE_1000 0x00400000
237 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
238 * Read the Phy response and then configure the MAC accordingly */
239 #define CFG_AUTO_1000 0x00200000
240 #define CFG_PINT_CTL 0x001c0000
241 #define CFG_PINT_DUPSTS 0x00100000
242 #define CFG_PINT_LNKSTS 0x00080000
243 #define CFG_PINT_SPDSTS 0x00040000
244 #define CFG_TMRTEST 0x00020000
245 #define CFG_MRM_DIS 0x00010000
246 #define CFG_MWI_DIS 0x00008000
247 #define CFG_T64ADDR 0x00004000
248 #define CFG_PCI64_DET 0x00002000
249 #define CFG_DATA64_EN 0x00001000
250 #define CFG_M64ADDR 0x00000800
251 #define CFG_PHY_RST 0x00000400
252 #define CFG_PHY_DIS 0x00000200
253 #define CFG_EXTSTS_EN 0x00000100
254 #define CFG_REQALG 0x00000080
255 #define CFG_SB 0x00000040
256 #define CFG_POW 0x00000020
257 #define CFG_EXD 0x00000010
258 #define CFG_PESEL 0x00000008
259 #define CFG_BROM_DIS 0x00000004
260 #define CFG_EXT_125 0x00000002
261 #define CFG_BEM 0x00000001
263 #define EXTSTS_UDPPKT 0x00200000
264 #define EXTSTS_TCPPKT 0x00080000
265 #define EXTSTS_IPPKT 0x00020000
266 #define EXTSTS_VPKT 0x00010000
267 #define EXTSTS_VTG_MASK 0x0000ffff
269 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
271 #define MIBC_MIBS 0x00000008
272 #define MIBC_ACLR 0x00000004
273 #define MIBC_FRZ 0x00000002
274 #define MIBC_WRN 0x00000001
276 #define PCR_PSEN (1 << 31)
277 #define PCR_PS_MCAST (1 << 30)
278 #define PCR_PS_DA (1 << 29)
279 #define PCR_STHI_8 (3 << 23)
280 #define PCR_STLO_4 (1 << 23)
281 #define PCR_FFHI_8K (3 << 21)
282 #define PCR_FFLO_4K (1 << 21)
283 #define PCR_PAUSE_CNT 0xFFFE
285 #define RXCFG_AEP 0x80000000
286 #define RXCFG_ARP 0x40000000
287 #define RXCFG_STRIPCRC 0x20000000
288 #define RXCFG_RX_FD 0x10000000
289 #define RXCFG_ALP 0x08000000
290 #define RXCFG_AIRL 0x04000000
291 #define RXCFG_MXDMA512 0x00700000
292 #define RXCFG_DRTH 0x0000003e
293 #define RXCFG_DRTH0 0x00000002
295 #define RFCR_RFEN 0x80000000
296 #define RFCR_AAB 0x40000000
297 #define RFCR_AAM 0x20000000
298 #define RFCR_AAU 0x10000000
299 #define RFCR_APM 0x08000000
300 #define RFCR_APAT 0x07800000
301 #define RFCR_APAT3 0x04000000
302 #define RFCR_APAT2 0x02000000
303 #define RFCR_APAT1 0x01000000
304 #define RFCR_APAT0 0x00800000
305 #define RFCR_AARP 0x00400000
306 #define RFCR_MHEN 0x00200000
307 #define RFCR_UHEN 0x00100000
308 #define RFCR_ULM 0x00080000
310 #define VRCR_RUDPE 0x00000080
311 #define VRCR_RTCPE 0x00000040
312 #define VRCR_RIPE 0x00000020
313 #define VRCR_IPEN 0x00000010
314 #define VRCR_DUTF 0x00000008
315 #define VRCR_DVTF 0x00000004
316 #define VRCR_VTREN 0x00000002
317 #define VRCR_VTDEN 0x00000001
319 #define VTCR_PPCHK 0x00000008
320 #define VTCR_GCHK 0x00000004
321 #define VTCR_VPPTI 0x00000002
322 #define VTCR_VGTI 0x00000001
359 #define TBICR_MR_AN_ENABLE 0x00001000
360 #define TBICR_MR_RESTART_AN 0x00000200
362 #define TBISR_MR_LINK_STATUS 0x00000020
363 #define TBISR_MR_AN_COMPLETE 0x00000004
365 #define TANAR_PS2 0x00000100
366 #define TANAR_PS1 0x00000080
367 #define TANAR_HALF_DUP 0x00000040
368 #define TANAR_FULL_DUP 0x00000020
370 #define GPIOR_GP5_OE 0x00000200
371 #define GPIOR_GP4_OE 0x00000100
372 #define GPIOR_GP3_OE 0x00000080
373 #define GPIOR_GP2_OE 0x00000040
374 #define GPIOR_GP1_OE 0x00000020
375 #define GPIOR_GP3_OUT 0x00000004
376 #define GPIOR_GP1_OUT 0x00000001
378 #define LINK_AUTONEGOTIATE 0x01
379 #define LINK_DOWN 0x02
382 #define HW_ADDR_LEN sizeof(dma_addr_t)
383 #define desc_addr_set(desc, addr) \
385 ((desc)[0] = cpu_to_le32(addr)); \
386 if (HW_ADDR_LEN == 8) \
387 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
389 #define desc_addr_get(desc) \
390 (le32_to_cpu((desc)[0]) | \
391 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
394 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
395 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
396 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
398 #define CMDSTS_OWN 0x80000000
399 #define CMDSTS_MORE 0x40000000
400 #define CMDSTS_INTR 0x20000000
401 #define CMDSTS_ERR 0x10000000
402 #define CMDSTS_OK 0x08000000
403 #define CMDSTS_RUNT 0x00200000
404 #define CMDSTS_LEN_MASK 0x0000ffff
406 #define CMDSTS_DEST_MASK 0x01800000
407 #define CMDSTS_DEST_SELF 0x00800000
408 #define CMDSTS_DEST_MULTI 0x01000000
410 #define DESC_SIZE 8 /* Should be cache line sized */
417 struct sk_buff
*skbs
[NR_RX_DESC
];
419 __le32
*next_rx_desc
;
420 u16 next_rx
, next_empty
;
423 dma_addr_t phy_descs
;
430 struct pci_dev
*pci_dev
;
431 struct net_device
*ndev
;
433 struct rx_info rx_info
;
434 struct tasklet_struct rx_tasklet
;
437 struct work_struct tq_refill
;
439 /* protects everything below. irqsave when using. */
440 spinlock_t misc_lock
;
453 volatile u16 tx_free_idx
; /* idx of free desc chain */
457 struct sk_buff
*tx_skbs
[NR_TX_DESC
];
459 char pad
[16] __attribute__((aligned(16)));
461 dma_addr_t tx_phy_descs
;
463 struct timer_list tx_watchdog
;
466 static inline struct ns83820
*PRIV(struct net_device
*dev
)
468 return netdev_priv(dev
);
471 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
473 static inline void kick_rx(struct net_device
*ndev
)
475 struct ns83820
*dev
= PRIV(ndev
);
476 dprintk("kick_rx: maybe kicking\n");
477 if (test_and_clear_bit(0, &dev
->rx_info
.idle
)) {
478 dprintk("actually kicking\n");
479 writel(dev
->rx_info
.phy_descs
+
480 (4 * DESC_SIZE
* dev
->rx_info
.next_rx
),
482 if (dev
->rx_info
.next_rx
== dev
->rx_info
.next_empty
)
483 printk(KERN_DEBUG
"%s: uh-oh: next_rx == next_empty???\n",
489 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
490 #define start_tx_okay(dev) \
491 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
495 * The hardware supports linked lists of receive descriptors for
496 * which ownership is transferred back and forth by means of an
497 * ownership bit. While the hardware does support the use of a
498 * ring for receive descriptors, we only make use of a chain in
499 * an attempt to reduce bus traffic under heavy load scenarios.
500 * This will also make bugs a bit more obvious. The current code
501 * only makes use of a single rx chain; I hope to implement
502 * priority based rx for version 1.0. Goal: even under overload
503 * conditions, still route realtime traffic with as low jitter as
506 static inline void build_rx_desc(struct ns83820
*dev
, __le32
*desc
, dma_addr_t link
, dma_addr_t buf
, u32 cmdsts
, u32 extsts
)
508 desc_addr_set(desc
+ DESC_LINK
, link
);
509 desc_addr_set(desc
+ DESC_BUFPTR
, buf
);
510 desc
[DESC_EXTSTS
] = cpu_to_le32(extsts
);
512 desc
[DESC_CMDSTS
] = cpu_to_le32(cmdsts
);
515 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
516 static inline int ns83820_add_rx_skb(struct ns83820
*dev
, struct sk_buff
*skb
)
523 next_empty
= dev
->rx_info
.next_empty
;
525 /* don't overrun last rx marker */
526 if (unlikely(nr_rx_empty(dev
) <= 2)) {
532 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
533 dev
->rx_info
.next_empty
,
534 dev
->rx_info
.nr_used
,
539 sg
= dev
->rx_info
.descs
+ (next_empty
* DESC_SIZE
);
540 BUG_ON(NULL
!= dev
->rx_info
.skbs
[next_empty
]);
541 dev
->rx_info
.skbs
[next_empty
] = skb
;
543 dev
->rx_info
.next_empty
= (next_empty
+ 1) % NR_RX_DESC
;
544 cmdsts
= REAL_RX_BUF_SIZE
| CMDSTS_INTR
;
545 buf
= pci_map_single(dev
->pci_dev
, skb
->data
,
546 REAL_RX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
547 build_rx_desc(dev
, sg
, 0, buf
, cmdsts
, 0);
548 /* update link of previous rx */
549 if (likely(next_empty
!= dev
->rx_info
.next_rx
))
550 dev
->rx_info
.descs
[((NR_RX_DESC
+ next_empty
- 1) % NR_RX_DESC
) * DESC_SIZE
] = cpu_to_le32(dev
->rx_info
.phy_descs
+ (next_empty
* DESC_SIZE
* 4));
555 static inline int rx_refill(struct net_device
*ndev
, gfp_t gfp
)
557 struct ns83820
*dev
= PRIV(ndev
);
559 unsigned long flags
= 0;
561 if (unlikely(nr_rx_empty(dev
) <= 2))
564 dprintk("rx_refill(%p)\n", ndev
);
565 if (gfp
== GFP_ATOMIC
)
566 spin_lock_irqsave(&dev
->rx_info
.lock
, flags
);
567 for (i
=0; i
<NR_RX_DESC
; i
++) {
571 /* extra 16 bytes for alignment */
572 skb
= __netdev_alloc_skb(ndev
, REAL_RX_BUF_SIZE
+16, gfp
);
576 skb_reserve(skb
, skb
->data
- PTR_ALIGN(skb
->data
, 16));
577 if (gfp
!= GFP_ATOMIC
)
578 spin_lock_irqsave(&dev
->rx_info
.lock
, flags
);
579 res
= ns83820_add_rx_skb(dev
, skb
);
580 if (gfp
!= GFP_ATOMIC
)
581 spin_unlock_irqrestore(&dev
->rx_info
.lock
, flags
);
587 if (gfp
== GFP_ATOMIC
)
588 spin_unlock_irqrestore(&dev
->rx_info
.lock
, flags
);
590 return i
? 0 : -ENOMEM
;
593 static void rx_refill_atomic(struct net_device
*ndev
)
595 rx_refill(ndev
, GFP_ATOMIC
);
599 static inline void queue_refill(struct work_struct
*work
)
601 struct ns83820
*dev
= container_of(work
, struct ns83820
, tq_refill
);
602 struct net_device
*ndev
= dev
->ndev
;
604 rx_refill(ndev
, GFP_KERNEL
);
609 static inline void clear_rx_desc(struct ns83820
*dev
, unsigned i
)
611 build_rx_desc(dev
, dev
->rx_info
.descs
+ (DESC_SIZE
* i
), 0, 0, CMDSTS_OWN
, 0);
614 static void phy_intr(struct net_device
*ndev
)
616 struct ns83820
*dev
= PRIV(ndev
);
617 static const char *speeds
[] = { "10", "100", "1000", "1000(?)", "1000F" };
619 u32 tbisr
, tanar
, tanlpar
;
620 int speed
, fullduplex
, newlinkstate
;
622 cfg
= readl(dev
->base
+ CFG
) ^ SPDSTS_POLARITY
;
624 if (dev
->CFG_cache
& CFG_TBI_EN
) {
625 /* we have an optical transceiver */
626 tbisr
= readl(dev
->base
+ TBISR
);
627 tanar
= readl(dev
->base
+ TANAR
);
628 tanlpar
= readl(dev
->base
+ TANLPAR
);
629 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
630 tbisr
, tanar
, tanlpar
);
632 if ( (fullduplex
= (tanlpar
& TANAR_FULL_DUP
) &&
633 (tanar
& TANAR_FULL_DUP
)) ) {
635 /* both of us are full duplex */
636 writel(readl(dev
->base
+ TXCFG
)
637 | TXCFG_CSI
| TXCFG_HBI
| TXCFG_ATP
,
639 writel(readl(dev
->base
+ RXCFG
) | RXCFG_RX_FD
,
641 /* Light up full duplex LED */
642 writel(readl(dev
->base
+ GPIOR
) | GPIOR_GP1_OUT
,
645 } else if (((tanlpar
& TANAR_HALF_DUP
) &&
646 (tanar
& TANAR_HALF_DUP
)) ||
647 ((tanlpar
& TANAR_FULL_DUP
) &&
648 (tanar
& TANAR_HALF_DUP
)) ||
649 ((tanlpar
& TANAR_HALF_DUP
) &&
650 (tanar
& TANAR_FULL_DUP
))) {
652 /* one or both of us are half duplex */
653 writel((readl(dev
->base
+ TXCFG
)
654 & ~(TXCFG_CSI
| TXCFG_HBI
)) | TXCFG_ATP
,
656 writel(readl(dev
->base
+ RXCFG
) & ~RXCFG_RX_FD
,
658 /* Turn off full duplex LED */
659 writel(readl(dev
->base
+ GPIOR
) & ~GPIOR_GP1_OUT
,
663 speed
= 4; /* 1000F */
666 /* we have a copper transceiver */
667 new_cfg
= dev
->CFG_cache
& ~(CFG_SB
| CFG_MODE_1000
| CFG_SPDSTS
);
669 if (cfg
& CFG_SPDSTS1
)
670 new_cfg
|= CFG_MODE_1000
;
672 new_cfg
&= ~CFG_MODE_1000
;
674 speed
= ((cfg
/ CFG_SPDSTS0
) & 3);
675 fullduplex
= (cfg
& CFG_DUPSTS
);
679 writel(readl(dev
->base
+ TXCFG
)
680 | TXCFG_CSI
| TXCFG_HBI
,
682 writel(readl(dev
->base
+ RXCFG
) | RXCFG_RX_FD
,
685 writel(readl(dev
->base
+ TXCFG
)
686 & ~(TXCFG_CSI
| TXCFG_HBI
),
688 writel(readl(dev
->base
+ RXCFG
) & ~(RXCFG_RX_FD
),
692 if ((cfg
& CFG_LNKSTS
) &&
693 ((new_cfg
^ dev
->CFG_cache
) != 0)) {
694 writel(new_cfg
, dev
->base
+ CFG
);
695 dev
->CFG_cache
= new_cfg
;
698 dev
->CFG_cache
&= ~CFG_SPDSTS
;
699 dev
->CFG_cache
|= cfg
& CFG_SPDSTS
;
702 newlinkstate
= (cfg
& CFG_LNKSTS
) ? LINK_UP
: LINK_DOWN
;
704 if (newlinkstate
& LINK_UP
&&
705 dev
->linkstate
!= newlinkstate
) {
706 netif_start_queue(ndev
);
707 netif_wake_queue(ndev
);
708 printk(KERN_INFO
"%s: link now %s mbps, %s duplex and up.\n",
711 fullduplex
? "full" : "half");
712 } else if (newlinkstate
& LINK_DOWN
&&
713 dev
->linkstate
!= newlinkstate
) {
714 netif_stop_queue(ndev
);
715 printk(KERN_INFO
"%s: link now down.\n", ndev
->name
);
718 dev
->linkstate
= newlinkstate
;
721 static int ns83820_setup_rx(struct net_device
*ndev
)
723 struct ns83820
*dev
= PRIV(ndev
);
727 dprintk("ns83820_setup_rx(%p)\n", ndev
);
729 dev
->rx_info
.idle
= 1;
730 dev
->rx_info
.next_rx
= 0;
731 dev
->rx_info
.next_rx_desc
= dev
->rx_info
.descs
;
732 dev
->rx_info
.next_empty
= 0;
734 for (i
=0; i
<NR_RX_DESC
; i
++)
735 clear_rx_desc(dev
, i
);
737 writel(0, dev
->base
+ RXDP_HI
);
738 writel(dev
->rx_info
.phy_descs
, dev
->base
+ RXDP
);
740 ret
= rx_refill(ndev
, GFP_KERNEL
);
742 dprintk("starting receiver\n");
743 /* prevent the interrupt handler from stomping on us */
744 spin_lock_irq(&dev
->rx_info
.lock
);
746 writel(0x0001, dev
->base
+ CCSR
);
747 writel(0, dev
->base
+ RFCR
);
748 writel(0x7fc00000, dev
->base
+ RFCR
);
749 writel(0xffc00000, dev
->base
+ RFCR
);
755 /* Okay, let it rip */
756 spin_lock(&dev
->misc_lock
);
757 dev
->IMR_cache
|= ISR_PHY
;
758 dev
->IMR_cache
|= ISR_RXRCMP
;
759 //dev->IMR_cache |= ISR_RXERR;
760 //dev->IMR_cache |= ISR_RXOK;
761 dev
->IMR_cache
|= ISR_RXORN
;
762 dev
->IMR_cache
|= ISR_RXSOVR
;
763 dev
->IMR_cache
|= ISR_RXDESC
;
764 dev
->IMR_cache
|= ISR_RXIDLE
;
765 dev
->IMR_cache
|= ISR_TXDESC
;
766 dev
->IMR_cache
|= ISR_TXIDLE
;
768 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
769 writel(1, dev
->base
+ IER
);
770 spin_unlock(&dev
->misc_lock
);
774 spin_unlock_irq(&dev
->rx_info
.lock
);
779 static void ns83820_cleanup_rx(struct ns83820
*dev
)
784 dprintk("ns83820_cleanup_rx(%p)\n", dev
);
786 /* disable receive interrupts */
787 spin_lock_irqsave(&dev
->misc_lock
, flags
);
788 dev
->IMR_cache
&= ~(ISR_RXOK
| ISR_RXDESC
| ISR_RXERR
| ISR_RXEARLY
| ISR_RXIDLE
);
789 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
790 spin_unlock_irqrestore(&dev
->misc_lock
, flags
);
792 /* synchronize with the interrupt handler and kill it */
794 synchronize_irq(dev
->pci_dev
->irq
);
796 /* touch the pci bus... */
797 readl(dev
->base
+ IMR
);
799 /* assumes the transmitter is already disabled and reset */
800 writel(0, dev
->base
+ RXDP_HI
);
801 writel(0, dev
->base
+ RXDP
);
803 for (i
=0; i
<NR_RX_DESC
; i
++) {
804 struct sk_buff
*skb
= dev
->rx_info
.skbs
[i
];
805 dev
->rx_info
.skbs
[i
] = NULL
;
806 clear_rx_desc(dev
, i
);
811 static void ns83820_rx_kick(struct net_device
*ndev
)
813 struct ns83820
*dev
= PRIV(ndev
);
814 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
815 if (dev
->rx_info
.up
) {
816 rx_refill_atomic(ndev
);
821 if (dev
->rx_info
.up
&& nr_rx_empty(dev
) > NR_RX_DESC
*3/4)
822 schedule_work(&dev
->tq_refill
);
825 if (dev
->rx_info
.idle
)
826 printk(KERN_DEBUG
"%s: BAD\n", ndev
->name
);
832 static void rx_irq(struct net_device
*ndev
)
834 struct ns83820
*dev
= PRIV(ndev
);
835 struct rx_info
*info
= &dev
->rx_info
;
843 dprintk("rx_irq(%p)\n", ndev
);
844 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
845 readl(dev
->base
+ RXDP
),
846 (long)(dev
->rx_info
.phy_descs
),
847 (int)dev
->rx_info
.next_rx
,
848 (dev
->rx_info
.descs
+ (DESC_SIZE
* dev
->rx_info
.next_rx
)),
849 (int)dev
->rx_info
.next_empty
,
850 (dev
->rx_info
.descs
+ (DESC_SIZE
* dev
->rx_info
.next_empty
))
853 spin_lock_irqsave(&info
->lock
, flags
);
857 dprintk("walking descs\n");
858 next_rx
= info
->next_rx
;
859 desc
= info
->next_rx_desc
;
860 while ((CMDSTS_OWN
& (cmdsts
= le32_to_cpu(desc
[DESC_CMDSTS
]))) &&
861 (cmdsts
!= CMDSTS_OWN
)) {
863 u32 extsts
= le32_to_cpu(desc
[DESC_EXTSTS
]);
864 dma_addr_t bufptr
= desc_addr_get(desc
+ DESC_BUFPTR
);
866 dprintk("cmdsts: %08x\n", cmdsts
);
867 dprintk("link: %08x\n", cpu_to_le32(desc
[DESC_LINK
]));
868 dprintk("extsts: %08x\n", extsts
);
870 skb
= info
->skbs
[next_rx
];
871 info
->skbs
[next_rx
] = NULL
;
872 info
->next_rx
= (next_rx
+ 1) % NR_RX_DESC
;
875 clear_rx_desc(dev
, next_rx
);
877 pci_unmap_single(dev
->pci_dev
, bufptr
,
878 RX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
879 len
= cmdsts
& CMDSTS_LEN_MASK
;
880 #ifdef NS83820_VLAN_ACCEL_SUPPORT
881 /* NH: As was mentioned below, this chip is kinda
882 * brain dead about vlan tag stripping. Frames
883 * that are 64 bytes with a vlan header appended
884 * like arp frames, or pings, are flagged as Runts
885 * when the tag is stripped and hardware. This
886 * also means that the OK bit in the descriptor
887 * is cleared when the frame comes in so we have
888 * to do a specific length check here to make sure
889 * the frame would have been ok, had we not stripped
892 if (likely((CMDSTS_OK
& cmdsts
) ||
893 ((cmdsts
& CMDSTS_RUNT
) && len
>= 56))) {
895 if (likely(CMDSTS_OK
& cmdsts
)) {
899 goto netdev_mangle_me_harder_failed
;
900 if (cmdsts
& CMDSTS_DEST_MULTI
)
901 ndev
->stats
.multicast
++;
902 ndev
->stats
.rx_packets
++;
903 ndev
->stats
.rx_bytes
+= len
;
904 if ((extsts
& 0x002a0000) && !(extsts
& 0x00540000)) {
905 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
907 skb_checksum_none_assert(skb
);
909 skb
->protocol
= eth_type_trans(skb
, ndev
);
910 #ifdef NS83820_VLAN_ACCEL_SUPPORT
911 if(extsts
& EXTSTS_VPKT
) {
914 tag
= ntohs(extsts
& EXTSTS_VTG_MASK
);
915 __vlan_hwaccel_put_tag(skb
, tag
);
918 rx_rc
= netif_rx(skb
);
919 if (NET_RX_DROP
== rx_rc
) {
920 netdev_mangle_me_harder_failed
:
921 ndev
->stats
.rx_dropped
++;
928 next_rx
= info
->next_rx
;
929 desc
= info
->descs
+ (DESC_SIZE
* next_rx
);
931 info
->next_rx
= next_rx
;
932 info
->next_rx_desc
= info
->descs
+ (DESC_SIZE
* next_rx
);
936 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts
);
939 spin_unlock_irqrestore(&info
->lock
, flags
);
942 static void rx_action(unsigned long _dev
)
944 struct net_device
*ndev
= (void *)_dev
;
945 struct ns83820
*dev
= PRIV(ndev
);
947 writel(ihr
, dev
->base
+ IHR
);
949 spin_lock_irq(&dev
->misc_lock
);
950 dev
->IMR_cache
|= ISR_RXDESC
;
951 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
952 spin_unlock_irq(&dev
->misc_lock
);
955 ns83820_rx_kick(ndev
);
958 /* Packet Transmit code
960 static inline void kick_tx(struct ns83820
*dev
)
962 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
963 dev
, dev
->tx_idx
, dev
->tx_free_idx
);
964 writel(CR_TXE
, dev
->base
+ CR
);
967 /* No spinlock needed on the transmit irq path as the interrupt handler is
970 static void do_tx_done(struct net_device
*ndev
)
972 struct ns83820
*dev
= PRIV(ndev
);
973 u32 cmdsts
, tx_done_idx
;
976 dprintk("do_tx_done(%p)\n", ndev
);
977 tx_done_idx
= dev
->tx_done_idx
;
978 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
980 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
981 tx_done_idx
, dev
->tx_free_idx
, le32_to_cpu(desc
[DESC_CMDSTS
]));
982 while ((tx_done_idx
!= dev
->tx_free_idx
) &&
983 !(CMDSTS_OWN
& (cmdsts
= le32_to_cpu(desc
[DESC_CMDSTS
]))) ) {
988 if (cmdsts
& CMDSTS_ERR
)
989 ndev
->stats
.tx_errors
++;
990 if (cmdsts
& CMDSTS_OK
)
991 ndev
->stats
.tx_packets
++;
992 if (cmdsts
& CMDSTS_OK
)
993 ndev
->stats
.tx_bytes
+= cmdsts
& 0xffff;
995 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
996 tx_done_idx
, dev
->tx_free_idx
, cmdsts
);
997 skb
= dev
->tx_skbs
[tx_done_idx
];
998 dev
->tx_skbs
[tx_done_idx
] = NULL
;
999 dprintk("done(%p)\n", skb
);
1001 len
= cmdsts
& CMDSTS_LEN_MASK
;
1002 addr
= desc_addr_get(desc
+ DESC_BUFPTR
);
1004 pci_unmap_single(dev
->pci_dev
,
1008 dev_kfree_skb_irq(skb
);
1009 atomic_dec(&dev
->nr_tx_skbs
);
1011 pci_unmap_page(dev
->pci_dev
,
1016 tx_done_idx
= (tx_done_idx
+ 1) % NR_TX_DESC
;
1017 dev
->tx_done_idx
= tx_done_idx
;
1018 desc
[DESC_CMDSTS
] = cpu_to_le32(0);
1020 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1023 /* Allow network stack to resume queueing packets after we've
1024 * finished transmitting at least 1/4 of the packets in the queue.
1026 if (netif_queue_stopped(ndev
) && start_tx_okay(dev
)) {
1027 dprintk("start_queue(%p)\n", ndev
);
1028 netif_start_queue(ndev
);
1029 netif_wake_queue(ndev
);
1033 static void ns83820_cleanup_tx(struct ns83820
*dev
)
1037 for (i
=0; i
<NR_TX_DESC
; i
++) {
1038 struct sk_buff
*skb
= dev
->tx_skbs
[i
];
1039 dev
->tx_skbs
[i
] = NULL
;
1041 __le32
*desc
= dev
->tx_descs
+ (i
* DESC_SIZE
);
1042 pci_unmap_single(dev
->pci_dev
,
1043 desc_addr_get(desc
+ DESC_BUFPTR
),
1044 le32_to_cpu(desc
[DESC_CMDSTS
]) & CMDSTS_LEN_MASK
,
1046 dev_kfree_skb_irq(skb
);
1047 atomic_dec(&dev
->nr_tx_skbs
);
1051 memset(dev
->tx_descs
, 0, NR_TX_DESC
* DESC_SIZE
* 4);
1054 /* transmit routine. This code relies on the network layer serializing
1055 * its calls in, but will run happily in parallel with the interrupt
1056 * handler. This code currently has provisions for fragmenting tx buffers
1057 * while trying to track down a bug in either the zero copy code or
1058 * the tx fifo (hence the MAX_FRAG_LEN).
1060 static netdev_tx_t
ns83820_hard_start_xmit(struct sk_buff
*skb
,
1061 struct net_device
*ndev
)
1063 struct ns83820
*dev
= PRIV(ndev
);
1064 u32 free_idx
, cmdsts
, extsts
;
1065 int nr_free
, nr_frags
;
1066 unsigned tx_done_idx
, last_idx
;
1072 volatile __le32
*first_desc
;
1074 dprintk("ns83820_hard_start_xmit\n");
1076 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1078 if (unlikely(dev
->CFG_cache
& CFG_LNKSTS
)) {
1079 netif_stop_queue(ndev
);
1080 if (unlikely(dev
->CFG_cache
& CFG_LNKSTS
))
1081 return NETDEV_TX_BUSY
;
1082 netif_start_queue(ndev
);
1085 last_idx
= free_idx
= dev
->tx_free_idx
;
1086 tx_done_idx
= dev
->tx_done_idx
;
1087 nr_free
= (tx_done_idx
+ NR_TX_DESC
-2 - free_idx
) % NR_TX_DESC
;
1089 if (nr_free
<= nr_frags
) {
1090 dprintk("stop_queue - not enough(%p)\n", ndev
);
1091 netif_stop_queue(ndev
);
1093 /* Check again: we may have raced with a tx done irq */
1094 if (dev
->tx_done_idx
!= tx_done_idx
) {
1095 dprintk("restart queue(%p)\n", ndev
);
1096 netif_start_queue(ndev
);
1099 return NETDEV_TX_BUSY
;
1102 if (free_idx
== dev
->tx_intr_idx
) {
1104 dev
->tx_intr_idx
= (dev
->tx_intr_idx
+ NR_TX_DESC
/4) % NR_TX_DESC
;
1107 nr_free
-= nr_frags
;
1108 if (nr_free
< MIN_TX_DESC_FREE
) {
1109 dprintk("stop_queue - last entry(%p)\n", ndev
);
1110 netif_stop_queue(ndev
);
1114 frag
= skb_shinfo(skb
)->frags
;
1118 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1119 extsts
|= EXTSTS_IPPKT
;
1120 if (IPPROTO_TCP
== ip_hdr(skb
)->protocol
)
1121 extsts
|= EXTSTS_TCPPKT
;
1122 else if (IPPROTO_UDP
== ip_hdr(skb
)->protocol
)
1123 extsts
|= EXTSTS_UDPPKT
;
1126 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1127 if(vlan_tx_tag_present(skb
)) {
1128 /* fetch the vlan tag info out of the
1129 * ancillary data if the vlan code
1130 * is using hw vlan acceleration
1132 short tag
= vlan_tx_tag_get(skb
);
1133 extsts
|= (EXTSTS_VPKT
| htons(tag
));
1139 len
-= skb
->data_len
;
1140 buf
= pci_map_single(dev
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1142 first_desc
= dev
->tx_descs
+ (free_idx
* DESC_SIZE
);
1145 volatile __le32
*desc
= dev
->tx_descs
+ (free_idx
* DESC_SIZE
);
1147 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx
, len
,
1148 (unsigned long long)buf
);
1149 last_idx
= free_idx
;
1150 free_idx
= (free_idx
+ 1) % NR_TX_DESC
;
1151 desc
[DESC_LINK
] = cpu_to_le32(dev
->tx_phy_descs
+ (free_idx
* DESC_SIZE
* 4));
1152 desc_addr_set(desc
+ DESC_BUFPTR
, buf
);
1153 desc
[DESC_EXTSTS
] = cpu_to_le32(extsts
);
1155 cmdsts
= ((nr_frags
) ? CMDSTS_MORE
: do_intr
? CMDSTS_INTR
: 0);
1156 cmdsts
|= (desc
== first_desc
) ? 0 : CMDSTS_OWN
;
1158 desc
[DESC_CMDSTS
] = cpu_to_le32(cmdsts
);
1163 buf
= pci_map_page(dev
->pci_dev
, frag
->page
,
1165 frag
->size
, PCI_DMA_TODEVICE
);
1166 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1167 (long long)buf
, (long) page_to_pfn(frag
->page
),
1173 dprintk("done pkt\n");
1175 spin_lock_irq(&dev
->tx_lock
);
1176 dev
->tx_skbs
[last_idx
] = skb
;
1177 first_desc
[DESC_CMDSTS
] |= cpu_to_le32(CMDSTS_OWN
);
1178 dev
->tx_free_idx
= free_idx
;
1179 atomic_inc(&dev
->nr_tx_skbs
);
1180 spin_unlock_irq(&dev
->tx_lock
);
1184 /* Check again: we may have raced with a tx done irq */
1185 if (stopped
&& (dev
->tx_done_idx
!= tx_done_idx
) && start_tx_okay(dev
))
1186 netif_start_queue(ndev
);
1188 return NETDEV_TX_OK
;
1191 static void ns83820_update_stats(struct ns83820
*dev
)
1193 struct net_device
*ndev
= dev
->ndev
;
1194 u8 __iomem
*base
= dev
->base
;
1196 /* the DP83820 will freeze counters, so we need to read all of them */
1197 ndev
->stats
.rx_errors
+= readl(base
+ 0x60) & 0xffff;
1198 ndev
->stats
.rx_crc_errors
+= readl(base
+ 0x64) & 0xffff;
1199 ndev
->stats
.rx_missed_errors
+= readl(base
+ 0x68) & 0xffff;
1200 ndev
->stats
.rx_frame_errors
+= readl(base
+ 0x6c) & 0xffff;
1201 /*ndev->stats.rx_symbol_errors +=*/ readl(base
+ 0x70);
1202 ndev
->stats
.rx_length_errors
+= readl(base
+ 0x74) & 0xffff;
1203 ndev
->stats
.rx_length_errors
+= readl(base
+ 0x78) & 0xffff;
1204 /*ndev->stats.rx_badopcode_errors += */ readl(base
+ 0x7c);
1205 /*ndev->stats.rx_pause_count += */ readl(base
+ 0x80);
1206 /*ndev->stats.tx_pause_count += */ readl(base
+ 0x84);
1207 ndev
->stats
.tx_carrier_errors
+= readl(base
+ 0x88) & 0xff;
1210 static struct net_device_stats
*ns83820_get_stats(struct net_device
*ndev
)
1212 struct ns83820
*dev
= PRIV(ndev
);
1214 /* somewhat overkill */
1215 spin_lock_irq(&dev
->misc_lock
);
1216 ns83820_update_stats(dev
);
1217 spin_unlock_irq(&dev
->misc_lock
);
1219 return &ndev
->stats
;
1222 /* Let ethtool retrieve info */
1223 static int ns83820_get_settings(struct net_device
*ndev
,
1224 struct ethtool_cmd
*cmd
)
1226 struct ns83820
*dev
= PRIV(ndev
);
1227 u32 cfg
, tanar
, tbicr
;
1231 * Here's the list of available ethtool commands from other drivers:
1232 * cmd->advertising =
1233 * ethtool_cmd_speed_set(cmd, ...)
1236 * cmd->phy_address =
1237 * cmd->transceiver = 0;
1239 * cmd->maxtxpkt = 0;
1240 * cmd->maxrxpkt = 0;
1243 /* read current configuration */
1244 cfg
= readl(dev
->base
+ CFG
) ^ SPDSTS_POLARITY
;
1245 tanar
= readl(dev
->base
+ TANAR
);
1246 tbicr
= readl(dev
->base
+ TBICR
);
1248 fullduplex
= (cfg
& CFG_DUPSTS
) ? 1 : 0;
1250 cmd
->supported
= SUPPORTED_Autoneg
;
1252 if (dev
->CFG_cache
& CFG_TBI_EN
) {
1253 /* we have optical interface */
1254 cmd
->supported
|= SUPPORTED_1000baseT_Half
|
1255 SUPPORTED_1000baseT_Full
|
1257 cmd
->port
= PORT_FIBRE
;
1259 /* we have copper */
1260 cmd
->supported
|= SUPPORTED_10baseT_Half
|
1261 SUPPORTED_10baseT_Full
| SUPPORTED_100baseT_Half
|
1262 SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Half
|
1263 SUPPORTED_1000baseT_Full
|
1265 cmd
->port
= PORT_MII
;
1268 cmd
->duplex
= fullduplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1269 switch (cfg
/ CFG_SPDSTS0
& 3) {
1271 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1274 ethtool_cmd_speed_set(cmd
, SPEED_100
);
1277 ethtool_cmd_speed_set(cmd
, SPEED_10
);
1280 cmd
->autoneg
= (tbicr
& TBICR_MR_AN_ENABLE
)
1281 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
1285 /* Let ethool change settings*/
1286 static int ns83820_set_settings(struct net_device
*ndev
,
1287 struct ethtool_cmd
*cmd
)
1289 struct ns83820
*dev
= PRIV(ndev
);
1291 int have_optical
= 0;
1294 /* read current configuration */
1295 cfg
= readl(dev
->base
+ CFG
) ^ SPDSTS_POLARITY
;
1296 tanar
= readl(dev
->base
+ TANAR
);
1298 if (dev
->CFG_cache
& CFG_TBI_EN
) {
1299 /* we have optical */
1301 fullduplex
= (tanar
& TANAR_FULL_DUP
);
1304 /* we have copper */
1305 fullduplex
= cfg
& CFG_DUPSTS
;
1308 spin_lock_irq(&dev
->misc_lock
);
1309 spin_lock(&dev
->tx_lock
);
1312 if (cmd
->duplex
!= fullduplex
) {
1315 if (cmd
->duplex
== DUPLEX_FULL
) {
1316 /* force full duplex */
1317 writel(readl(dev
->base
+ TXCFG
)
1318 | TXCFG_CSI
| TXCFG_HBI
| TXCFG_ATP
,
1320 writel(readl(dev
->base
+ RXCFG
) | RXCFG_RX_FD
,
1322 /* Light up full duplex LED */
1323 writel(readl(dev
->base
+ GPIOR
) | GPIOR_GP1_OUT
,
1326 /*TODO: set half duplex */
1331 /* TODO: Set duplex for copper cards */
1333 printk(KERN_INFO
"%s: Duplex set via ethtool\n",
1337 /* Set autonegotiation */
1339 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1340 /* restart auto negotiation */
1341 writel(TBICR_MR_AN_ENABLE
| TBICR_MR_RESTART_AN
,
1343 writel(TBICR_MR_AN_ENABLE
, dev
->base
+ TBICR
);
1344 dev
->linkstate
= LINK_AUTONEGOTIATE
;
1346 printk(KERN_INFO
"%s: autoneg enabled via ethtool\n",
1349 /* disable auto negotiation */
1350 writel(0x00000000, dev
->base
+ TBICR
);
1353 printk(KERN_INFO
"%s: autoneg %s via ethtool\n", ndev
->name
,
1354 cmd
->autoneg
? "ENABLED" : "DISABLED");
1358 spin_unlock(&dev
->tx_lock
);
1359 spin_unlock_irq(&dev
->misc_lock
);
1363 /* end ethtool get/set support -df */
1365 static void ns83820_get_drvinfo(struct net_device
*ndev
, struct ethtool_drvinfo
*info
)
1367 struct ns83820
*dev
= PRIV(ndev
);
1368 strcpy(info
->driver
, "ns83820");
1369 strcpy(info
->version
, VERSION
);
1370 strcpy(info
->bus_info
, pci_name(dev
->pci_dev
));
1373 static u32
ns83820_get_link(struct net_device
*ndev
)
1375 struct ns83820
*dev
= PRIV(ndev
);
1376 u32 cfg
= readl(dev
->base
+ CFG
) ^ SPDSTS_POLARITY
;
1377 return cfg
& CFG_LNKSTS
? 1 : 0;
1380 static const struct ethtool_ops ops
= {
1381 .get_settings
= ns83820_get_settings
,
1382 .set_settings
= ns83820_set_settings
,
1383 .get_drvinfo
= ns83820_get_drvinfo
,
1384 .get_link
= ns83820_get_link
1387 static inline void ns83820_disable_interrupts(struct ns83820
*dev
)
1389 writel(0, dev
->base
+ IMR
);
1390 writel(0, dev
->base
+ IER
);
1391 readl(dev
->base
+ IER
);
1394 /* this function is called in irq context from the ISR */
1395 static void ns83820_mib_isr(struct ns83820
*dev
)
1397 unsigned long flags
;
1398 spin_lock_irqsave(&dev
->misc_lock
, flags
);
1399 ns83820_update_stats(dev
);
1400 spin_unlock_irqrestore(&dev
->misc_lock
, flags
);
1403 static void ns83820_do_isr(struct net_device
*ndev
, u32 isr
);
1404 static irqreturn_t
ns83820_irq(int foo
, void *data
)
1406 struct net_device
*ndev
= data
;
1407 struct ns83820
*dev
= PRIV(ndev
);
1409 dprintk("ns83820_irq(%p)\n", ndev
);
1413 isr
= readl(dev
->base
+ ISR
);
1414 dprintk("irq: %08x\n", isr
);
1415 ns83820_do_isr(ndev
, isr
);
1419 static void ns83820_do_isr(struct net_device
*ndev
, u32 isr
)
1421 struct ns83820
*dev
= PRIV(ndev
);
1422 unsigned long flags
;
1425 if (isr
& ~(ISR_PHY
| ISR_RXDESC
| ISR_RXEARLY
| ISR_RXOK
| ISR_RXERR
| ISR_TXIDLE
| ISR_TXOK
| ISR_TXDESC
))
1426 Dprintk("odd isr? 0x%08x\n", isr
);
1429 if (ISR_RXIDLE
& isr
) {
1430 dev
->rx_info
.idle
= 1;
1431 Dprintk("oh dear, we are idle\n");
1432 ns83820_rx_kick(ndev
);
1435 if ((ISR_RXDESC
| ISR_RXOK
) & isr
) {
1436 prefetch(dev
->rx_info
.next_rx_desc
);
1438 spin_lock_irqsave(&dev
->misc_lock
, flags
);
1439 dev
->IMR_cache
&= ~(ISR_RXDESC
| ISR_RXOK
);
1440 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
1441 spin_unlock_irqrestore(&dev
->misc_lock
, flags
);
1443 tasklet_schedule(&dev
->rx_tasklet
);
1445 //writel(4, dev->base + IHR);
1448 if ((ISR_RXIDLE
| ISR_RXORN
| ISR_RXDESC
| ISR_RXOK
| ISR_RXERR
) & isr
)
1449 ns83820_rx_kick(ndev
);
1451 if (unlikely(ISR_RXSOVR
& isr
)) {
1452 //printk("overrun: rxsovr\n");
1453 ndev
->stats
.rx_fifo_errors
++;
1456 if (unlikely(ISR_RXORN
& isr
)) {
1457 //printk("overrun: rxorn\n");
1458 ndev
->stats
.rx_fifo_errors
++;
1461 if ((ISR_RXRCMP
& isr
) && dev
->rx_info
.up
)
1462 writel(CR_RXE
, dev
->base
+ CR
);
1464 if (ISR_TXIDLE
& isr
) {
1466 txdp
= readl(dev
->base
+ TXDP
);
1467 dprintk("txdp: %08x\n", txdp
);
1468 txdp
-= dev
->tx_phy_descs
;
1469 dev
->tx_idx
= txdp
/ (DESC_SIZE
* 4);
1470 if (dev
->tx_idx
>= NR_TX_DESC
) {
1471 printk(KERN_ALERT
"%s: BUG -- txdp out of range\n", ndev
->name
);
1474 /* The may have been a race between a pci originated read
1475 * and the descriptor update from the cpu. Just in case,
1476 * kick the transmitter if the hardware thinks it is on a
1477 * different descriptor than we are.
1479 if (dev
->tx_idx
!= dev
->tx_free_idx
)
1483 /* Defer tx ring processing until more than a minimum amount of
1484 * work has accumulated
1486 if ((ISR_TXDESC
| ISR_TXIDLE
| ISR_TXOK
| ISR_TXERR
) & isr
) {
1487 spin_lock_irqsave(&dev
->tx_lock
, flags
);
1489 spin_unlock_irqrestore(&dev
->tx_lock
, flags
);
1491 /* Disable TxOk if there are no outstanding tx packets.
1493 if ((dev
->tx_done_idx
== dev
->tx_free_idx
) &&
1494 (dev
->IMR_cache
& ISR_TXOK
)) {
1495 spin_lock_irqsave(&dev
->misc_lock
, flags
);
1496 dev
->IMR_cache
&= ~ISR_TXOK
;
1497 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
1498 spin_unlock_irqrestore(&dev
->misc_lock
, flags
);
1502 /* The TxIdle interrupt can come in before the transmit has
1503 * completed. Normally we reap packets off of the combination
1504 * of TxDesc and TxIdle and leave TxOk disabled (since it
1505 * occurs on every packet), but when no further irqs of this
1506 * nature are expected, we must enable TxOk.
1508 if ((ISR_TXIDLE
& isr
) && (dev
->tx_done_idx
!= dev
->tx_free_idx
)) {
1509 spin_lock_irqsave(&dev
->misc_lock
, flags
);
1510 dev
->IMR_cache
|= ISR_TXOK
;
1511 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
1512 spin_unlock_irqrestore(&dev
->misc_lock
, flags
);
1515 /* MIB interrupt: one of the statistics counters is about to overflow */
1516 if (unlikely(ISR_MIB
& isr
))
1517 ns83820_mib_isr(dev
);
1519 /* PHY: Link up/down/negotiation state change */
1520 if (unlikely(ISR_PHY
& isr
))
1523 #if 0 /* Still working on the interrupt mitigation strategy */
1525 writel(dev
->ihr
, dev
->base
+ IHR
);
1529 static void ns83820_do_reset(struct ns83820
*dev
, u32 which
)
1531 Dprintk("resetting chip...\n");
1532 writel(which
, dev
->base
+ CR
);
1535 } while (readl(dev
->base
+ CR
) & which
);
1539 static int ns83820_stop(struct net_device
*ndev
)
1541 struct ns83820
*dev
= PRIV(ndev
);
1543 /* FIXME: protect against interrupt handler? */
1544 del_timer_sync(&dev
->tx_watchdog
);
1546 ns83820_disable_interrupts(dev
);
1548 dev
->rx_info
.up
= 0;
1549 synchronize_irq(dev
->pci_dev
->irq
);
1551 ns83820_do_reset(dev
, CR_RST
);
1553 synchronize_irq(dev
->pci_dev
->irq
);
1555 spin_lock_irq(&dev
->misc_lock
);
1556 dev
->IMR_cache
&= ~(ISR_TXURN
| ISR_TXIDLE
| ISR_TXERR
| ISR_TXDESC
| ISR_TXOK
);
1557 spin_unlock_irq(&dev
->misc_lock
);
1559 ns83820_cleanup_rx(dev
);
1560 ns83820_cleanup_tx(dev
);
1565 static void ns83820_tx_timeout(struct net_device
*ndev
)
1567 struct ns83820
*dev
= PRIV(ndev
);
1570 unsigned long flags
;
1572 spin_lock_irqsave(&dev
->tx_lock
, flags
);
1574 tx_done_idx
= dev
->tx_done_idx
;
1575 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1577 printk(KERN_INFO
"%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1579 tx_done_idx
, dev
->tx_free_idx
, le32_to_cpu(desc
[DESC_CMDSTS
]));
1584 isr
= readl(dev
->base
+ ISR
);
1585 printk("irq: %08x imr: %08x\n", isr
, dev
->IMR_cache
);
1586 ns83820_do_isr(ndev
, isr
);
1592 tx_done_idx
= dev
->tx_done_idx
;
1593 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1595 printk(KERN_INFO
"%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1597 tx_done_idx
, dev
->tx_free_idx
, le32_to_cpu(desc
[DESC_CMDSTS
]));
1599 spin_unlock_irqrestore(&dev
->tx_lock
, flags
);
1602 static void ns83820_tx_watch(unsigned long data
)
1604 struct net_device
*ndev
= (void *)data
;
1605 struct ns83820
*dev
= PRIV(ndev
);
1608 printk("ns83820_tx_watch: %u %u %d\n",
1609 dev
->tx_done_idx
, dev
->tx_free_idx
, atomic_read(&dev
->nr_tx_skbs
)
1613 if (time_after(jiffies
, dev_trans_start(ndev
) + 1*HZ
) &&
1614 dev
->tx_done_idx
!= dev
->tx_free_idx
) {
1615 printk(KERN_DEBUG
"%s: ns83820_tx_watch: %u %u %d\n",
1617 dev
->tx_done_idx
, dev
->tx_free_idx
,
1618 atomic_read(&dev
->nr_tx_skbs
));
1619 ns83820_tx_timeout(ndev
);
1622 mod_timer(&dev
->tx_watchdog
, jiffies
+ 2*HZ
);
1625 static int ns83820_open(struct net_device
*ndev
)
1627 struct ns83820
*dev
= PRIV(ndev
);
1632 dprintk("ns83820_open\n");
1634 writel(0, dev
->base
+ PQCR
);
1636 ret
= ns83820_setup_rx(ndev
);
1640 memset(dev
->tx_descs
, 0, 4 * NR_TX_DESC
* DESC_SIZE
);
1641 for (i
=0; i
<NR_TX_DESC
; i
++) {
1642 dev
->tx_descs
[(i
* DESC_SIZE
) + DESC_LINK
]
1645 + ((i
+1) % NR_TX_DESC
) * DESC_SIZE
* 4);
1649 dev
->tx_done_idx
= 0;
1650 desc
= dev
->tx_phy_descs
;
1651 writel(0, dev
->base
+ TXDP_HI
);
1652 writel(desc
, dev
->base
+ TXDP
);
1654 init_timer(&dev
->tx_watchdog
);
1655 dev
->tx_watchdog
.data
= (unsigned long)ndev
;
1656 dev
->tx_watchdog
.function
= ns83820_tx_watch
;
1657 mod_timer(&dev
->tx_watchdog
, jiffies
+ 2*HZ
);
1659 netif_start_queue(ndev
); /* FIXME: wait for phy to come up */
1668 static void ns83820_getmac(struct ns83820
*dev
, u8
*mac
)
1671 for (i
=0; i
<3; i
++) {
1674 /* Read from the perfect match memory: this is loaded by
1675 * the chip from the EEPROM via the EELOAD self test.
1677 writel(i
*2, dev
->base
+ RFCR
);
1678 data
= readl(dev
->base
+ RFDR
);
1685 static int ns83820_change_mtu(struct net_device
*ndev
, int new_mtu
)
1687 if (new_mtu
> RX_BUF_SIZE
)
1689 ndev
->mtu
= new_mtu
;
1693 static void ns83820_set_multicast(struct net_device
*ndev
)
1695 struct ns83820
*dev
= PRIV(ndev
);
1696 u8 __iomem
*rfcr
= dev
->base
+ RFCR
;
1697 u32 and_mask
= 0xffffffff;
1701 if (ndev
->flags
& IFF_PROMISC
)
1702 or_mask
|= RFCR_AAU
| RFCR_AAM
;
1704 and_mask
&= ~(RFCR_AAU
| RFCR_AAM
);
1706 if (ndev
->flags
& IFF_ALLMULTI
|| netdev_mc_count(ndev
))
1707 or_mask
|= RFCR_AAM
;
1709 and_mask
&= ~RFCR_AAM
;
1711 spin_lock_irq(&dev
->misc_lock
);
1712 val
= (readl(rfcr
) & and_mask
) | or_mask
;
1713 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1714 writel(val
& ~RFCR_RFEN
, rfcr
);
1716 spin_unlock_irq(&dev
->misc_lock
);
1719 static void ns83820_run_bist(struct net_device
*ndev
, const char *name
, u32 enable
, u32 done
, u32 fail
)
1721 struct ns83820
*dev
= PRIV(ndev
);
1723 unsigned long start
;
1727 dprintk("%s: start %s\n", ndev
->name
, name
);
1731 writel(enable
, dev
->base
+ PTSCR
);
1734 status
= readl(dev
->base
+ PTSCR
);
1735 if (!(status
& enable
))
1741 if (time_after_eq(jiffies
, start
+ HZ
)) {
1745 schedule_timeout_uninterruptible(1);
1749 printk(KERN_INFO
"%s: %s failed! (0x%08x & 0x%08x)\n",
1750 ndev
->name
, name
, status
, fail
);
1752 printk(KERN_INFO
"%s: run_bist %s timed out! (%08x)\n",
1753 ndev
->name
, name
, status
);
1755 dprintk("%s: done %s in %d loops\n", ndev
->name
, name
, loops
);
1758 #ifdef PHY_CODE_IS_FINISHED
1759 static void ns83820_mii_write_bit(struct ns83820
*dev
, int bit
)
1762 dev
->MEAR_cache
&= ~MEAR_MDC
;
1763 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1764 readl(dev
->base
+ MEAR
);
1766 /* enable output, set bit */
1767 dev
->MEAR_cache
|= MEAR_MDDIR
;
1769 dev
->MEAR_cache
|= MEAR_MDIO
;
1771 dev
->MEAR_cache
&= ~MEAR_MDIO
;
1773 /* set the output bit */
1774 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1775 readl(dev
->base
+ MEAR
);
1777 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1780 /* drive MDC high causing the data bit to be latched */
1781 dev
->MEAR_cache
|= MEAR_MDC
;
1782 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1783 readl(dev
->base
+ MEAR
);
1789 static int ns83820_mii_read_bit(struct ns83820
*dev
)
1793 /* drive MDC low, disable output */
1794 dev
->MEAR_cache
&= ~MEAR_MDC
;
1795 dev
->MEAR_cache
&= ~MEAR_MDDIR
;
1796 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1797 readl(dev
->base
+ MEAR
);
1799 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1802 /* drive MDC high causing the data bit to be latched */
1803 bit
= (readl(dev
->base
+ MEAR
) & MEAR_MDIO
) ? 1 : 0;
1804 dev
->MEAR_cache
|= MEAR_MDC
;
1805 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1813 static unsigned ns83820_mii_read_reg(struct ns83820
*dev
, unsigned phy
, unsigned reg
)
1818 /* read some garbage so that we eventually sync up */
1819 for (i
=0; i
<64; i
++)
1820 ns83820_mii_read_bit(dev
);
1822 ns83820_mii_write_bit(dev
, 0); /* start */
1823 ns83820_mii_write_bit(dev
, 1);
1824 ns83820_mii_write_bit(dev
, 1); /* opcode read */
1825 ns83820_mii_write_bit(dev
, 0);
1827 /* write out the phy address: 5 bits, msb first */
1829 ns83820_mii_write_bit(dev
, phy
& (0x10 >> i
));
1831 /* write out the register address, 5 bits, msb first */
1833 ns83820_mii_write_bit(dev
, reg
& (0x10 >> i
));
1835 ns83820_mii_read_bit(dev
); /* turn around cycles */
1836 ns83820_mii_read_bit(dev
);
1838 /* read in the register data, 16 bits msb first */
1839 for (i
=0; i
<16; i
++) {
1841 data
|= ns83820_mii_read_bit(dev
);
1847 static unsigned ns83820_mii_write_reg(struct ns83820
*dev
, unsigned phy
, unsigned reg
, unsigned data
)
1851 /* read some garbage so that we eventually sync up */
1852 for (i
=0; i
<64; i
++)
1853 ns83820_mii_read_bit(dev
);
1855 ns83820_mii_write_bit(dev
, 0); /* start */
1856 ns83820_mii_write_bit(dev
, 1);
1857 ns83820_mii_write_bit(dev
, 0); /* opcode read */
1858 ns83820_mii_write_bit(dev
, 1);
1860 /* write out the phy address: 5 bits, msb first */
1862 ns83820_mii_write_bit(dev
, phy
& (0x10 >> i
));
1864 /* write out the register address, 5 bits, msb first */
1866 ns83820_mii_write_bit(dev
, reg
& (0x10 >> i
));
1868 ns83820_mii_read_bit(dev
); /* turn around cycles */
1869 ns83820_mii_read_bit(dev
);
1871 /* read in the register data, 16 bits msb first */
1872 for (i
=0; i
<16; i
++)
1873 ns83820_mii_write_bit(dev
, (data
>> (15 - i
)) & 1);
1878 static void ns83820_probe_phy(struct net_device
*ndev
)
1880 struct ns83820
*dev
= PRIV(ndev
);
1883 #define MII_PHYIDR1 0x02
1884 #define MII_PHYIDR2 0x03
1889 ns83820_mii_read_reg(dev
, 1, 0x09);
1890 ns83820_mii_write_reg(dev
, 1, 0x10, 0x0d3e);
1892 tmp
= ns83820_mii_read_reg(dev
, 1, 0x00);
1893 ns83820_mii_write_reg(dev
, 1, 0x00, tmp
| 0x8000);
1895 ns83820_mii_read_reg(dev
, 1, 0x09);
1900 for (i
=1; i
<2; i
++) {
1903 a
= ns83820_mii_read_reg(dev
, i
, MII_PHYIDR1
);
1904 b
= ns83820_mii_read_reg(dev
, i
, MII_PHYIDR2
);
1906 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1907 // ndev->name, i, a, b);
1909 for (j
=0; j
<0x16; j
+=4) {
1910 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1912 ns83820_mii_read_reg(dev
, i
, 0 + j
),
1913 ns83820_mii_read_reg(dev
, i
, 1 + j
),
1914 ns83820_mii_read_reg(dev
, i
, 2 + j
),
1915 ns83820_mii_read_reg(dev
, i
, 3 + j
)
1921 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1922 ns83820_mii_write_reg(dev
, 1, 0x16, 0x000d);
1923 ns83820_mii_write_reg(dev
, 1, 0x1e, 0x810e);
1924 a
= ns83820_mii_read_reg(dev
, 1, 0x1d);
1926 ns83820_mii_write_reg(dev
, 1, 0x16, 0x000d);
1927 ns83820_mii_write_reg(dev
, 1, 0x1e, 0x810e);
1928 b
= ns83820_mii_read_reg(dev
, 1, 0x1d);
1929 dprintk("version: 0x%04x 0x%04x\n", a
, b
);
1934 static const struct net_device_ops netdev_ops
= {
1935 .ndo_open
= ns83820_open
,
1936 .ndo_stop
= ns83820_stop
,
1937 .ndo_start_xmit
= ns83820_hard_start_xmit
,
1938 .ndo_get_stats
= ns83820_get_stats
,
1939 .ndo_change_mtu
= ns83820_change_mtu
,
1940 .ndo_set_rx_mode
= ns83820_set_multicast
,
1941 .ndo_validate_addr
= eth_validate_addr
,
1942 .ndo_set_mac_address
= eth_mac_addr
,
1943 .ndo_tx_timeout
= ns83820_tx_timeout
,
1946 static int __devinit
ns83820_init_one(struct pci_dev
*pci_dev
,
1947 const struct pci_device_id
*id
)
1949 struct net_device
*ndev
;
1950 struct ns83820
*dev
;
1955 /* See if we can set the dma mask early on; failure is fatal. */
1956 if (sizeof(dma_addr_t
) == 8 &&
1957 !pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(64))) {
1959 } else if (!pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(32))) {
1962 dev_warn(&pci_dev
->dev
, "pci_set_dma_mask failed!\n");
1966 ndev
= alloc_etherdev(sizeof(struct ns83820
));
1974 spin_lock_init(&dev
->rx_info
.lock
);
1975 spin_lock_init(&dev
->tx_lock
);
1976 spin_lock_init(&dev
->misc_lock
);
1977 dev
->pci_dev
= pci_dev
;
1979 SET_NETDEV_DEV(ndev
, &pci_dev
->dev
);
1981 INIT_WORK(&dev
->tq_refill
, queue_refill
);
1982 tasklet_init(&dev
->rx_tasklet
, rx_action
, (unsigned long)ndev
);
1984 err
= pci_enable_device(pci_dev
);
1986 dev_info(&pci_dev
->dev
, "pci_enable_dev failed: %d\n", err
);
1990 pci_set_master(pci_dev
);
1991 addr
= pci_resource_start(pci_dev
, 1);
1992 dev
->base
= ioremap_nocache(addr
, PAGE_SIZE
);
1993 dev
->tx_descs
= pci_alloc_consistent(pci_dev
,
1994 4 * DESC_SIZE
* NR_TX_DESC
, &dev
->tx_phy_descs
);
1995 dev
->rx_info
.descs
= pci_alloc_consistent(pci_dev
,
1996 4 * DESC_SIZE
* NR_RX_DESC
, &dev
->rx_info
.phy_descs
);
1998 if (!dev
->base
|| !dev
->tx_descs
|| !dev
->rx_info
.descs
)
2001 dprintk("%p: %08lx %p: %08lx\n",
2002 dev
->tx_descs
, (long)dev
->tx_phy_descs
,
2003 dev
->rx_info
.descs
, (long)dev
->rx_info
.phy_descs
);
2005 ns83820_disable_interrupts(dev
);
2009 err
= request_irq(pci_dev
->irq
, ns83820_irq
, IRQF_SHARED
,
2012 dev_info(&pci_dev
->dev
, "unable to register irq %d, err %d\n",
2018 * FIXME: we are holding rtnl_lock() over obscenely long area only
2019 * because some of the setup code uses dev->name. It's Wrong(tm) -
2020 * we should be using driver-specific names for all that stuff.
2021 * For now that will do, but we really need to come back and kill
2022 * most of the dev_alloc_name() users later.
2025 err
= dev_alloc_name(ndev
, ndev
->name
);
2027 dev_info(&pci_dev
->dev
, "unable to get netdev name: %d\n", err
);
2031 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2032 ndev
->name
, le32_to_cpu(readl(dev
->base
+ 0x22c)),
2033 pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
);
2035 ndev
->netdev_ops
= &netdev_ops
;
2036 SET_ETHTOOL_OPS(ndev
, &ops
);
2037 ndev
->watchdog_timeo
= 5 * HZ
;
2038 pci_set_drvdata(pci_dev
, ndev
);
2040 ns83820_do_reset(dev
, CR_RST
);
2042 /* Must reset the ram bist before running it */
2043 writel(PTSCR_RBIST_RST
, dev
->base
+ PTSCR
);
2044 ns83820_run_bist(ndev
, "sram bist", PTSCR_RBIST_EN
,
2045 PTSCR_RBIST_DONE
, PTSCR_RBIST_FAIL
);
2046 ns83820_run_bist(ndev
, "eeprom bist", PTSCR_EEBIST_EN
, 0,
2048 ns83820_run_bist(ndev
, "eeprom load", PTSCR_EELOAD_EN
, 0, 0);
2050 /* I love config registers */
2051 dev
->CFG_cache
= readl(dev
->base
+ CFG
);
2053 if ((dev
->CFG_cache
& CFG_PCI64_DET
)) {
2054 printk(KERN_INFO
"%s: detected 64 bit PCI data bus.\n",
2056 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2057 if (!(dev
->CFG_cache
& CFG_DATA64_EN
))
2058 printk(KERN_INFO
"%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2061 dev
->CFG_cache
&= ~(CFG_DATA64_EN
);
2063 dev
->CFG_cache
&= (CFG_TBI_EN
| CFG_MRM_DIS
| CFG_MWI_DIS
|
2064 CFG_T64ADDR
| CFG_DATA64_EN
| CFG_EXT_125
|
2066 dev
->CFG_cache
|= CFG_PINT_DUPSTS
| CFG_PINT_LNKSTS
| CFG_PINT_SPDSTS
|
2067 CFG_EXTSTS_EN
| CFG_EXD
| CFG_PESEL
;
2068 dev
->CFG_cache
|= CFG_REQALG
;
2069 dev
->CFG_cache
|= CFG_POW
;
2070 dev
->CFG_cache
|= CFG_TMRTEST
;
2072 /* When compiled with 64 bit addressing, we must always enable
2073 * the 64 bit descriptor format.
2075 if (sizeof(dma_addr_t
) == 8)
2076 dev
->CFG_cache
|= CFG_M64ADDR
;
2078 dev
->CFG_cache
|= CFG_T64ADDR
;
2080 /* Big endian mode does not seem to do what the docs suggest */
2081 dev
->CFG_cache
&= ~CFG_BEM
;
2083 /* setup optical transceiver if we have one */
2084 if (dev
->CFG_cache
& CFG_TBI_EN
) {
2085 printk(KERN_INFO
"%s: enabling optical transceiver\n",
2087 writel(readl(dev
->base
+ GPIOR
) | 0x3e8, dev
->base
+ GPIOR
);
2089 /* setup auto negotiation feature advertisement */
2090 writel(readl(dev
->base
+ TANAR
)
2091 | TANAR_HALF_DUP
| TANAR_FULL_DUP
,
2094 /* start auto negotiation */
2095 writel(TBICR_MR_AN_ENABLE
| TBICR_MR_RESTART_AN
,
2097 writel(TBICR_MR_AN_ENABLE
, dev
->base
+ TBICR
);
2098 dev
->linkstate
= LINK_AUTONEGOTIATE
;
2100 dev
->CFG_cache
|= CFG_MODE_1000
;
2103 writel(dev
->CFG_cache
, dev
->base
+ CFG
);
2104 dprintk("CFG: %08x\n", dev
->CFG_cache
);
2107 printk(KERN_INFO
"%s: resetting phy\n", ndev
->name
);
2108 writel(dev
->CFG_cache
| CFG_PHY_RST
, dev
->base
+ CFG
);
2110 writel(dev
->CFG_cache
, dev
->base
+ CFG
);
2113 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2114 * the PCI layer. FIXME.
2116 if (readl(dev
->base
+ SRR
))
2117 writel(readl(dev
->base
+0x20c) | 0xfe00, dev
->base
+ 0x20c);
2120 /* Note! The DMA burst size interacts with packet
2121 * transmission, such that the largest packet that
2122 * can be transmitted is 8192 - FLTH - burst size.
2123 * If only the transmit fifo was larger...
2125 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2126 * some DELL and COMPAQ SMP systems */
2127 writel(TXCFG_CSI
| TXCFG_HBI
| TXCFG_ATP
| TXCFG_MXDMA512
2128 | ((1600 / 32) * 0x100),
2131 /* Flush the interrupt holdoff timer */
2132 writel(0x000, dev
->base
+ IHR
);
2133 writel(0x100, dev
->base
+ IHR
);
2134 writel(0x000, dev
->base
+ IHR
);
2136 /* Set Rx to full duplex, don't accept runt, errored, long or length
2137 * range errored packets. Use 512 byte DMA.
2139 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2140 * some DELL and COMPAQ SMP systems
2141 * Turn on ALP, only we are accpeting Jumbo Packets */
2142 writel(RXCFG_AEP
| RXCFG_ARP
| RXCFG_AIRL
| RXCFG_RX_FD
2145 | (RXCFG_MXDMA512
) | 0, dev
->base
+ RXCFG
);
2147 /* Disable priority queueing */
2148 writel(0, dev
->base
+ PQCR
);
2150 /* Enable IP checksum validation and detetion of VLAN headers.
2151 * Note: do not set the reject options as at least the 0x102
2152 * revision of the chip does not properly accept IP fragments
2155 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2156 * the MAC it calculates the packetsize AFTER stripping the VLAN
2157 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2158 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2159 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2160 * it discrards it!. These guys......
2161 * also turn on tag stripping if hardware acceleration is enabled
2163 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2164 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2166 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2168 writel(VRCR_INIT_VALUE
, dev
->base
+ VRCR
);
2170 /* Enable per-packet TCP/UDP/IP checksumming
2171 * and per packet vlan tag insertion if
2172 * vlan hardware acceleration is enabled
2174 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2175 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2177 #define VTCR_INIT_VALUE VTCR_PPCHK
2179 writel(VTCR_INIT_VALUE
, dev
->base
+ VTCR
);
2181 /* Ramit : Enable async and sync pause frames */
2182 /* writel(0, dev->base + PCR); */
2183 writel((PCR_PS_MCAST
| PCR_PS_DA
| PCR_PSEN
| PCR_FFLO_4K
|
2184 PCR_FFHI_8K
| PCR_STLO_4
| PCR_STHI_8
| PCR_PAUSE_CNT
),
2187 /* Disable Wake On Lan */
2188 writel(0, dev
->base
+ WCSR
);
2190 ns83820_getmac(dev
, ndev
->dev_addr
);
2192 /* Yes, we support dumb IP checksum on transmit */
2193 ndev
->features
|= NETIF_F_SG
;
2194 ndev
->features
|= NETIF_F_IP_CSUM
;
2196 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2197 /* We also support hardware vlan acceleration */
2198 ndev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2202 printk(KERN_INFO
"%s: using 64 bit addressing.\n",
2204 ndev
->features
|= NETIF_F_HIGHDMA
;
2207 printk(KERN_INFO
"%s: ns83820 v" VERSION
": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2209 (unsigned)readl(dev
->base
+ SRR
) >> 8,
2210 (unsigned)readl(dev
->base
+ SRR
) & 0xff,
2211 ndev
->dev_addr
, addr
, pci_dev
->irq
,
2212 (ndev
->features
& NETIF_F_HIGHDMA
) ? "h,sg" : "sg"
2215 #ifdef PHY_CODE_IS_FINISHED
2216 ns83820_probe_phy(ndev
);
2219 err
= register_netdevice(ndev
);
2221 printk(KERN_INFO
"ns83820: unable to register netdev: %d\n", err
);
2229 ns83820_disable_interrupts(dev
); /* paranoia */
2232 free_irq(pci_dev
->irq
, ndev
);
2236 pci_free_consistent(pci_dev
, 4 * DESC_SIZE
* NR_TX_DESC
, dev
->tx_descs
, dev
->tx_phy_descs
);
2237 pci_free_consistent(pci_dev
, 4 * DESC_SIZE
* NR_RX_DESC
, dev
->rx_info
.descs
, dev
->rx_info
.phy_descs
);
2238 pci_disable_device(pci_dev
);
2241 pci_set_drvdata(pci_dev
, NULL
);
2246 static void __devexit
ns83820_remove_one(struct pci_dev
*pci_dev
)
2248 struct net_device
*ndev
= pci_get_drvdata(pci_dev
);
2249 struct ns83820
*dev
= PRIV(ndev
); /* ok even if NULL */
2251 if (!ndev
) /* paranoia */
2254 ns83820_disable_interrupts(dev
); /* paranoia */
2256 unregister_netdev(ndev
);
2257 free_irq(dev
->pci_dev
->irq
, ndev
);
2259 pci_free_consistent(dev
->pci_dev
, 4 * DESC_SIZE
* NR_TX_DESC
,
2260 dev
->tx_descs
, dev
->tx_phy_descs
);
2261 pci_free_consistent(dev
->pci_dev
, 4 * DESC_SIZE
* NR_RX_DESC
,
2262 dev
->rx_info
.descs
, dev
->rx_info
.phy_descs
);
2263 pci_disable_device(dev
->pci_dev
);
2265 pci_set_drvdata(pci_dev
, NULL
);
2268 static DEFINE_PCI_DEVICE_TABLE(ns83820_pci_tbl
) = {
2269 { 0x100b, 0x0022, PCI_ANY_ID
, PCI_ANY_ID
, 0, .driver_data
= 0, },
2273 static struct pci_driver driver
= {
2275 .id_table
= ns83820_pci_tbl
,
2276 .probe
= ns83820_init_one
,
2277 .remove
= __devexit_p(ns83820_remove_one
),
2278 #if 0 /* FIXME: implement */
2285 static int __init
ns83820_init(void)
2287 printk(KERN_INFO
"ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2288 return pci_register_driver(&driver
);
2291 static void __exit
ns83820_exit(void)
2293 pci_unregister_driver(&driver
);
2296 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2297 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2298 MODULE_LICENSE("GPL");
2300 MODULE_DEVICE_TABLE(pci
, ns83820_pci_tbl
);
2302 module_param(lnksts
, int, 0);
2303 MODULE_PARM_DESC(lnksts
, "Polarity of LNKSTS bit");
2305 module_param(ihr
, int, 0);
2306 MODULE_PARM_DESC(ihr
, "Time in 100 us increments to delay interrupts (range 0-127)");
2308 module_param(reset_phy
, int, 0);
2309 MODULE_PARM_DESC(reset_phy
, "Set to 1 to reset the PHY on startup");
2311 module_init(ns83820_init
);
2312 module_exit(ns83820_exit
);